Apparatus and method for digital pre-distortion of power amplifiers

Abstract

In one embodiment, an apparatus includes a baseband processor to generate a baseband signal and a digital pre-distortion (DPD) circuit to pre-distort the baseband signal with compensation information obtained from a lookup table. The lookup table may have a plurality of entries, each entry to store a predistortion value, the lookup table to be addressed based on a target output power level of the baseband signal. The apparatus may also include a converter to convert the pre-distorted baseband signal to an analog signal and radio frequency (RF) circuitry including a mixer to up-convert the analog signal to a pre-distorted RF signal, and a power amplifier to amplify the pre-distorted RF signal.

Description

Devices and methods for digital predistortion in power amplifiers Background Technology

[0001] Some wireless transceivers have radio frequency (RF) power amplifiers (PAs) that can operate in multiple frequency bands, such as 2.4 GHz and 5 GHz. Ideally, these PAs are linear amplifiers used to amplify and transmit RF signals. However, at high power levels, PAs may soft-clip due to limited amplifier margins, resulting in nonlinearity. This soft clipping is a nonlinear function that degrades performance. Soft clipping can modify the amplitude and phase of the envelope of the PA output signal. One technique to reduce this nonlinearity is to perform digital compensation at the baseband frequency by predistorting the baseband signal, essentially creating an inverse function of the PA. Current implementations of digital predistortion (DPD) can incur significant computation time, which can affect the ability to fully implement DPD when transmitting high-speed signals. Summary of the Invention

[0002] In one aspect, an apparatus includes: a baseband processor for generating a baseband signal; a digital predistortion (DPD) circuit for predistorting the baseband signal using compensation information obtained from a lookup table, the lookup table having multiple entries, each entry storing a predistortion value, the lookup table being addressed based on a target output power level of the baseband signal; a converter for converting the predistorted baseband signal into an analog signal; and a radio frequency (RF) circuit system. The RF circuit system may include: a mixer for upconverting the analog signal into a predistorted RF signal; and a power amplifier (PA) for amplifying the predistorted RF signal.

[0003] In various implementations, each of the multiple entries in the lookup table stores compensation information, including either a complex attenuation value or a complex gain value.

[0004] In its implementation, the device also includes an address generator circuit for generating an address based on a target output power level. The address generator circuit generates an address comprising the sum of a first portion and a second portion. The address generation circuit generates the first portion based on a first comparison of the target output power level with a first value; and generates the second portion based on a second comparison of the result of the operation between the target output power level and the first portion with a second value.

[0005] In its implementation, the device further includes at least one counter for maintaining a count of samples of the baseband signal having a target output power level exceeding at least one threshold. The device may also include control circuitry for controlling the gain level of the transmission circuitry system of the RF circuitry, at least partially based on the count. The device may also include a loopback circuit coupled to the output of the PA for generating a digital signal corresponding to the amplified RF signal.

[0006] In the implementation, the loopback circuit also includes an alignment circuit for receiving the digital signal and the predistorted baseband signal and aligning the predistorted baseband signal with the digital signal. In the implementation, the alignment circuit includes: an integer alignment circuit; a fractional alignment circuit; and a gain / phase alignment circuit. The alignment circuit may include at least one correlator, and each of the integer alignment circuit, fractional alignment circuit, and gain / phase alignment circuit shares at least one correlator.

[0007] In the implementation, each of the multiple entries is associated with a target output power level that is logarithmically spaced from adjacent entries.

[0008] In implementation, the DPD circuit needs to further predistort the baseband signal to compensate for the memory effect of the PA.

[0009] In another aspect, a method includes: calculating, in a digital predistortion circuit of a transmitter, an input power of an input sample of a packet to be amplified and output from a PA of the transmitter; determining a target output power of the input sample based on the input power; generating an address based on the target output power and accessing an entry in a lookup table using the address, the entry including a complex attenuation value of the PA associated with the target output power; predistorting the input sample using the complex attenuation value of the PA; upconverting the predistorted input sample to an RF signal corresponding to the input sample; and amplifying the RF signal via the PA to output an amplified RF signal.

[0010] In implementation, generating the address includes: determining a first part of the address according to a first decoding; determining a second part of the address according to a second decoding; and combining the first part and the second part to generate the address.

[0011] In its implementation, the method further includes accessing a second entry in the lookup table using the address, wherein the second entry is adjacent to the first entry. The method may also include: determining an interpolated complex PA attenuation value based on the complex PA attenuation value of the entry and a second complex PA attenuation value of the second entry; and pre-distorting the input sample using the interpolated complex PA attenuation value.

[0012] In another aspect, a method includes: calculating an attenuation value for a sample pair, the sample pair including an input sample to a PA of a transceiver and an output sample from the PA, the output sample being aligned with the input sample; calculating an output power level of the PA based at least in part on the input sample; generating a PA attenuation value based at least in part on the calculated attenuation value; and storing the PA attenuation value in an entry in a memory associated with the output power level.

[0013] In implementation, generating the PA attenuation value involves combining the calculated attenuation value with a stored attenuation value in an entry stored in memory. The method may also include aligning input samples with output samples. Aligning the input signal with the output signal includes: aligning the input samples with the output samples integer; aligning the input samples with the output samples partially; and aligning the input samples with the output samples in at least one of gain or phase.

[0014] In implementation, the method includes: updating a plurality of entries in the memory during the transmission of a first packet from the transceiver; and accessing one or more of the updated entries in the memory to provide digital predistortion to one or more samples of a second packet to be transmitted from the transceiver.

[0015] In its implementation, the method also includes calculating the attenuation value, calculating the output power level, and generating the PA attenuation value when the change in at least one environmental metric of the transceiver exceeds a threshold. Attached Figure Description

[0016] Figure 1 is a high-level block diagram of a wireless transmitter according to an embodiment.

[0017] Figure 2 is a high-level block diagram of a digital predistortion system according to an embodiment.

[0018] Figure 3 is a graphical illustration of input power and output power.

[0019] Figure 4 is a block diagram of the address generation circuit and lookup table according to an embodiment.

[0020] Figure 5 is another block diagram of a digital predistortion system according to an embodiment, illustrating further details of the loopback path.

[0021] Figure 6A is a block diagram of the fractional delay calculation circuit according to an embodiment.

[0022] Figure 6B is a block diagram of a fractional delay calculation circuit according to another embodiment.

[0023] Figure 7A is a block diagram of the Farrow filter according to an embodiment.

[0024] Figure 7B is a block diagram of a Farrow filter according to another embodiment.

[0025] Figure 8 is a block diagram of the lookup table according to an embodiment.

[0026] Figure 9 is a flowchart of a method according to an embodiment for generating a lookup table.

[0027] Figure 10 is a flowchart of a method for predistorting a transmitted signal using a lookup table according to another embodiment.

[0028] Figure 11 is a block diagram of a representative integrated circuit according to an embodiment.

[0029] Figure 12 is a high-level diagram of the network according to an embodiment. Detailed Implementation

[0030] In various embodiments, the power amplifier can be digitally compensated to pre-distort the baseband signal before it is up-converted to RF levels. As described above, this compensation is performed to reduce the nonlinearity effects of the PA. The embodiments provide a lookup table (LUT)-based solution for performing DPD compensation. As will be described herein, the LUT can be addressed via an addressing scheme based on an identifier of the PA's target output power level, by directly accessing specific entries in the LUT instead of performing a search of the LUT to find the entry, reducing complexity and latency.

[0031] PA linearity can degrade the error vector magnitude (EVM) and lead to transmission mask violations due to memoryless nonlinearity. However, at wider channel bandwidths (e.g., 80 MHz), PA memory effects can also impact performance. These memory effects may result from internal capacitance within the PA and the slow response time of the voltage regulator-based power supply used for the PA. In such embodiments, a hybrid compensation approach can be implemented, employing both LUT-based DPD and further compensation for memory effects using filter functions and / or memory polynomials. In such a hybrid implementation, most of the PA DPD correction is achieved by a LUT modeling the PA characteristics, and memory effects are compensated by a finite impulse response (FIR) filter or small memory polynomial operating in conjunction with the LUT function.

[0032] Referring now to FIG1, a high-level block diagram of a wireless transmitter according to an embodiment is shown. As shown in FIG1, a portion of device 100 is illustrated. In various embodiments, device 100 can be any type of wireless device, ranging from small Internet of Things (IoT) devices to larger wireless devices such as smartphones, access points, tablet computers, etc. In the high-level simplified diagram shown in FIG1, the transmission portion of wireless device 100 is illustrated. As shown, baseband processor 110 performs digital operations on the information to be transmitted and provides it to another circuit system for conversion into analog form and further upconversion to RF level within RF circuitry 150, which further processes the RF signals and amplifies them to output a transmitted RF signal transmitted via antenna 170.

[0033] As shown, incoming data received from additional circuitry (such as the core or other processing circuitry) of the baseband processor is provided to modulator 112. Modulator 112 can generate various forms of modulation, such as phase shift keying (PSK), quadrature amplitude modulation (QAM), orthogonal frequency division modulation (OFDM), and many other techniques known in the art. Additional operations can be performed here. For example, the modulated data can be further transformed to the time domain after frequency domain processing. The resulting signal can then be filtered and interpolated in filter / interpolator 114. The resulting signal, in complex format, is then provided to DPD circuit 115.

[0034] In various embodiments, the DPD circuit 115 includes a lookup table (LUT) configured as described herein. Based on the power level of the input signal, a corresponding target output power level can be determined. This target output power level can then be used to generate an address. This address is then used to access a given entry within the LUT to obtain compensation data. The DPD circuit 115 then operates to apply this compensation data to the input signal. The resulting predistorted signal (still in complex form) is provided to the interpolator 118.

[0035] From there, the interpolated signal is converted to analog form in a digital-to-analog converter (DAC) and can be further filtered in one or more low-pass filters (LPFs) (box 130). The resulting analog signal, still in complex form and containing pre-distorted sample information, is provided to a complex mixer 155, which up-converts the signal to the desired RF level (e.g., 2.4 or 5 GHz). The RF signal is then amplified in a PA 160 before being transmitted via antenna 170. Although shown at this high level in the embodiment of Figure 1, many variations and alternatives are possible.

[0036] Although not shown in Figure 1, digital circuitry may exist after the DPD circuit 115 to correct I / Q mismatch and DC offset in the analog / RF path to reduce LO feedthrough. For the 5 GHz band, the DPD circuit 115 operates at a sampling rate of 160 megasamples per second (MSP), the I / Q DAC operates at 160 Mbps, and the LPF has a nominal corner frequency of approximately 20 MHz. In one or more implementations, the LUT (and FIR filters or memory polynomials, when using a hybrid approach) can be implemented in dedicated register transfer stage (RTL) hardware.

[0037] In this embodiment, calibration data stored in the LUT and FIR filter coefficients can be determined during the calibration phase. Such calibration can be performed during manufacturing operations (e.g., as part of production testing (PTE)) and may be performed again when the integrated circuit, including the transceiver, is incorporated into the wireless device. Further calibration can be performed dynamically in the field. For example, dynamic calibration can be performed in the field during normal operation as environmental conditions change.

[0038] DPD calibration can be performed by looping the transmit (TX) signal back to the transceiver's receiver signal processing path. This loopback fills the LUT with baseband equivalents of the PA input and output signals (e.g., complex I and Q signals). For a given PA output (or input) power, the complex PA attenuation (or gain) is stored in the LUT. The coefficients (or memory polynomials) of the FIR filter can be determined using a least mean square (LMS) adaptive method or a block method to minimize the mean square error (MSE).

[0039] Referring now to Figure 2, a high-level block diagram of a DPD system according to an embodiment is shown during transmission and calibration. In the embodiment, while packets are being transmitted, the DPD parameters remain constant throughout the TX signal processing path to avoid unwanted transients in the TX signal. Since the PA typically exhibits compression at high power levels, the DPD produces expansion, resulting in a linear overall response. When TX packets are transmitted, the RX path loops back to the downconverted PA output signal. The equivalent PA input signal (at the output of the replication filter) and the PA output signal are stored in memory. This data is processed, for example, via firmware with an optional hardware accelerator, which generates compensation data to fill into the LUT. This updated compensation data can then be used to perform compensation for future packets. For a hybrid approach, the firmware also determines the coefficients of the FIR filter (or, more generally, the memory polynomial).

[0040] As shown in Figure 2, device 200 includes digital gain circuitry 205. In an embodiment, digital gain circuitry 205 receives incoming data and provides a variable digital gain to the input samples before they are provided to DPD circuitry 210. As described above, DPD circuitry 210 pre-distorts the samples using compensation data stored in a lookup table. The pre-distorted samples are then converted to analog form in DAC 215 (which can be implemented using a complex (I and Q) DAC) and filtered in LPF 220. The resulting filtered signal is then up-converted to an RF signal in complex mixer 225. The signal level can then be adjusted in variable gain amplifier (VGA) 230 and amplified via PA 240 for transmission. The signal level can also be adjusted using digital gain circuitry.

[0041] Referring again to Figure 2, a loopback path circuitry exists that allows the amplified RF signal to be processed for the purpose of performing DPD calibration as described herein. Therefore, as shown, the output of PA 240 is coupled to attenuator circuitry 254 and applied to the input of complex mixer 255, bypassing LNA 250. Attenuator 254 can be a passive circuit consisting of resistors, capacitors, inductors, or a combination of all three. Depending on the implementation, most of the remaining loopback path circuitry can be a combined transmitter and receiver (transceiver) receiver signal processing path. In other cases, at least a portion of the loopback circuitry can be implemented using a dedicated circuitry.

[0042] As shown, attenuator 254 is coupled to complex mixer 255, which downconverts the RF signal to a lower frequency. Filtering and digitization are performed in LPF 260 and ADC 265, respectively. Therefore, the digitized signal corresponding to the PA output signal is provided to the DPD calibration circuit along with the pre-distortion signal output from DPD circuit 210. More specifically, this signal is filtered in copy transfer LPF 245. As will be further described herein, prior to the actual calibration performed between these input and output signals, an alignment process is performed so that a given input sample can be processed along with its corresponding output sample.

[0043] In an embodiment, the replica filter 245 for the 5.0 GHz band can be implemented as a second-order 32 MHz Butterworth LPF with cascaded first-order filters having 26 MHz poles. The replica has a sampling rate of 160 MSps and is implemented as a hardware-based digital filter.

[0044] In this embodiment, the ADC 265 and DAC 215 can each be configured with 11 bits and a sampling rate of 160 MHz. To achieve maximum SNR via the loopback path, both can operate near their maximum levels.

[0045] PA characteristics (e.g., compression) can vary depending on PA configuration (e.g., the number of slices selected), PA load impedance (up to VSWR=3, at any angle), temperature, power supply voltage, number of channels, etc. In some cases, calibration can be performed dynamically at a predetermined frequency. Alternatively, calibration can occur when a given parameter (such as those discussed above) varies beyond a given threshold.

[0046] At PTE, calibration can be performed at room temperature against a nominal load (50 ohms), against 2.4 GHz and 5 GHz PAs, and under nominal supply. In various implementations, one or more channels can be calibrated in each frequency band. The resulting calibration data can be stored, for example, in the transceiver's non-volatile memory (NVM).

[0047] A given wireless device, coupled with a transceiver that has the nominally stored compensation data, can have an antenna design different from 50 ohms, even under nominal conditions, and therefore the manufacturer of the wireless device can re-perform the calibration routine to calibrate the PA with a specific antenna. The result of such calibration can be stored in the NVM, and in some cases, such as when NVM storage is limited, this calibration data can overwrite the original calibration data.

[0048] In the field, when TX is first powered on and begins transmission, initial calibration values ​​from the NVM are used. During this first transmission, the TX packet specifications (EVM, TX mask) may or may not be met, thus enabling loopback paths and calibration. A new set of calibration values ​​(LUTs and coefficients) dynamically determined in the field can then be used on future TX packets. As mentioned above, this updated calibration can be stored in the NVM for future use. Further PA calibration can be performed for temperature variations, the potential number of channels, and also based on time intervals. The time interval requirement can be based on capturing VSWR variations based on the customer application. For example, if the wireless device is implemented in a router or meter, VSWR variations should be relatively infrequent. In contrast, wireless devices used in wearable devices may change rapidly as individuals move. The above criteria are open-loop measures.

[0049] In one embodiment, one or more quality monitors can be configured in the loopback path to periodically evaluate EVM (or SNR or any other relevant metric) to determine whether calibration should occur. Referring to Table 1 below, example criteria for triggering calibration according to an embodiment are shown. As illustrated, in this embodiment, calibration can be triggered in response to changes in environmental metrics or parameters exceeding a threshold level.

[0050] Table 1 Ideally, the calibration performed during the TX packet via the loopback path is completed using updated compensation values ​​before transmitting the next TX packet, ensuring that the EVM and TX mask of the next packet will meet specifications. Therefore, the calibration performed during packet k results in updated compensation data stored in a lookup table, which can be used for compensation in subsequent packet k+1. However, in some implementations, the computation for creating the LUT is large, and therefore, the update may not be applied until a later packet (e.g., packet k+3). In such cases, one or more of the thresholds in Table 1 can be reduced so as not to violate the device EVM or TX mask. Note that calibration does not require the entire TX packet before processing can occur, and the entire packet is not required to populate the LUT or convergence coefficients.

[0051] If implementation incurs more calibration time, preventing updated values ​​from being ready, the transmitter can continue transmitting using previous calibration values ​​(although this may risk violating EVM or TX masks). In other cases, calibration may be performed more frequently than specified in Table 1, and / or, in the presence of a quality monitor, recalibration may be performed before the PA exceeds specifications.

[0052] To enable the PA to produce the desired output power for a given input power, the DPD process increases the amplitude of the input signal, achieving the desired output power even with soft clipping. In various embodiments, to reduce the search time within the lookup table, the PA transfer characteristics are adapted such that the desired output power is the input signal multiplied by the ideal gain (typically 1.0), and the input DPD is found.

[0053] This transfer characteristic is illustrated in the diagram 300 of Figure 3, where the target output power of the PA is plotted on the x-axis and the input DPD is plotted on the y-axis. As shown in Figure 3, the idealized transfer function 310 illustrates the linear response of the PA, while curve 320 illustrates the actual transfer response. Therefore, to achieve the target PA output power level, DPD compensation is provided to the input signal, thereby increasing its amplitude.

[0054] Using this arrangement, the address generation circuitry can be configured to map the PA output (or input) power to addresses within the LUT. Therefore, the LUT can be configured to have multiple entries (rows) indexed by the PA output (or input power).

[0055] Since the LUT and associated DPD circuitry are used to acquire the I / Q input signals and calculate predistorted I / Q output samples at a rate of 160 MSps, the hardware does not have time to search for the correct data line to use. Therefore, addressing of the LUT line can be performed as a deterministic function of the PA output (or input) power.

[0056] In this embodiment, the address generation circuitry for the LUT is configured to generate an address for accessing the LUT using a step size in the target output power. In this embodiment, the LUT may have the following characteristics: an output power range of approximately 0-40 dB; and a uniform step size across the entire range, where the coarse step size is approximately 3.0103 dB and the fine step size is 3.0103 dB / 8 (= 0.3762875 dB). Using this LUT configuration, the address generation circuitry can be configured to perform two-step RAM address decoding to generate an address for accessing the LUT.

[0057] In an embodiment, the LUT can be constructed as a 2-column matrix, where a given row is accessed using a generated address based on the target output power of the PA for a given sample. Column 1 contains the real part of the PA attenuation, and column 2 contains the imaginary part of the PA attenuation for a given power level. Thus, the rows of the matrix capture different output amplitudes and corresponding complex PA attenuations. In a particular implementation, the rows are designed such that input power increments can be stepped in steps of 3.01 / 8 = 0.376 dB, for example, in the range of 30-40 dB. In one or more implementations, the address of a row corresponds to the desired output power of the PA, and the contents of the row include the PA attenuation at that power level. Using PA attenuation instead of gain simplifies calculations (e.g., when applying a DPD at 160 MSps on the TX side). In one or more implementations, the LUT can have rows storing attenuation values ​​spaced logarithmically rather than nonlinearly (e.g., each entry can be spaced in decibel steps).

[0058] Referring now to Table 2, the lower portion of LUT address decoding based on the relative output power of PA is shown.

[0059] Table 2 As shown in Table 2, the first row represents the minimum output power of the PA (0dB), corresponding to the coarse address 0x0 and the fine address 0x0. Although the PA output power in the first column of Table 2 is shown in dB, it is never actually calculated in decibels. The coarse address is designed to allow shifting instead of multiplication (or division).

[0060] During address generation, the target output power is first calculated by summing the squares of the real and imaginary parts of the PA input sample and then multiplying by the magnitude of the ideal linear gain (which would be 1.0 for a normalized LUT). This target output power is compared with a first threshold in a digital comparator to generate a coarse power level and a corresponding coarse address bit for the RAM address. This coarse power level is then divided by an integer value (e.g., 1, 2, 4, etc.) to produce a fine power level. The fine address is then determined by comparing this fine power level with a second threshold in another digital comparator.

[0061] The final RAM address is generated by summing the coarse and fine addresses. For flexibility, the coarse and fine thresholds of the address comparator can be programmed using hardware registers.

[0062] Referring now to FIG4, a block diagram of an address generation circuit and a LUT according to an embodiment is shown. As shown in FIG4, device 400 includes an address generation circuit system and an LUT 470, as well as an associated control circuit system. As illustrated, the incoming complex signal (X) is received. R +X I The input power value is then calculated (as a sum of squares). This input power value is provided to gain circuit 405, which provides the nominal gain level to obtain the target output power (Y). 2 R +Y 2 I Therefore, in the gain circuit 405, the input power is calculated and scaled by the nominal attenuation of the LUT 470, and in the embodiment where the LUT 470 is normalized to 1.0, multiplication is not required to determine the target output power of the PA.

[0063] The target output power is decoded by the two-step address decoding circuit shown in Figure 4 to locate the complex attenuation of PA at that output power level. As shown, the target output power level is provided to a first comparator 415, which is implemented as a coarse power comparator, and compares the target output power level with a first threshold obtained from a first threshold storage device 410 (e.g., a register, which may be a programmable value set by firmware). Therefore, the output of comparator 415 may be an integer coarse power level. As shown, this coarse power level is provided to a calculation circuit 420, which divides the target output power by the coarse power level. Via a first adder 430, the coarse power level is transformed into a first part of the address, namely the coarse address.

[0064] As further illustrated, the divided value output from computing circuitry 420 is provided to a second comparator 435, which is implemented as a fine relative power comparator. This comparator compares the divided output power level with a second threshold obtained from a second threshold memory 425 (e.g., a register, which may be a programmable value set by firmware). Therefore, comparator 435 outputs a fine power level. The resulting fine address is added to a coarse address in adder 440 to generate an address for selecting a given entry within LUT 470. In embodiments, LUT 470 may be implemented as a small dedicated RAM or using individual flip-flops (FFs).

[0065] As shown in Figure 4 at a high level, LUT 470 includes multiple entries 475, each containing a PA attenuation value, i.e., a complex value. In an embodiment, this complex value can be four bytes wide, with two bytes for the real component and two bytes for the imaginary component, each byte stored in a column (e.g., a field) of a given row (e.g., an entry). Although shown as having a range of approximately 40 dB, other ranges are possible. Similarly, in implementations where LUT 470 is configured to store the complex attenuation of the PA rather than its complex gain, the amount of computation can be reduced.

[0066] As further shown, the address is also provided to a plurality of counters 450, 455, each of which increments by a given count value if the address (as described above, indicating a given target output power level) exceeds a threshold. In various implementations, these thresholds can be programmed by firmware. These counts are then provided to backoff control circuitry 460, which can control the gain of the transmit path. Backoff can be applied as a gain variation in the digital domain, baseband analog domain, or RF domain. For example, when the count exceeds one or more given thresholds, the gain can be reduced to avoid PA compression. Although shown at this high level in the embodiment of Figure 4, many variations and alternatives are possible.

[0067] Referring to Table 3, the operations performed according to the embodiments (with or without interpolation) to calculate the DPD adjustment value for a given input sample at transmission time are shown. Typically, based on the target output power, an address is determined and used to access a given attenuation value, which is then multiplied by the complex input signal to obtain the LUT-based DPD input sample. If the LUT has fine resolution in the PA output power, the algorithm used to generate the DPD is sufficient. However, if the memory size limits the LUT resolution (in rows), inter-row interpolation can be used to determine the complex attenuation of the PA, all of which are shown in Table 3.

[0068] Table 3 In an ideal world, a LUT could be constructed using all the samples present in the transmission packet; however, there is not enough memory in the loopback path to store and compute all the data. In this embodiment, instead of the entire packet, the maximum number of PA input and output samples can be limited to approximately 1024 samples. With such a limited dataset, the probability of sampling the maximum peak amplitude is quite low. The maximum 12 dB peak to RMS of an OFDM signal occurs with only a probability of 1e-6, so with 1024 samples, it will be missed most of the time.

[0069] Note that during LUT construction, an additional column can be included that maintains a count of how many samples were used to create a PA attenuation for a given output power level. Having this additional count information allows for the calculation of a weighted average of two LUTs to generate a new LUT based on more data points. For a maximum of 1024 samples used for LUT construction, using multiple LUTs and a weighted average provides an LUT that more accurately simulates the PA compression characteristics within several iterations. The compression characteristics can be modeled using complex numbers in Cartesian or polar coordinates (e.g., AM-AM and AM-PM formats).

[0070] In various embodiments, for power levels below the saturation power level (Psat), the DPD can only linearize the PA characteristics. If the target output power is equal to or exceeds Psat (or another standard, such as the 2dB compression point), an alarm can be issued to the system so that the transmission power level can be reduced in subsequent packets.

[0071] In an embodiment, during packet transmission, counter 450 increments whenever the TX power exceeds the 2dB compression point of the PA. Before the next packet transmission, the counter is read and can be used to determine whether and how the PA power should be adjusted based on how many times the 2dB compression point has been exceeded. The determination of backoff also considers the modulation and coding scheme (MCS) level, as lower MCS levels can tolerate more compression. In one or more implementations, a second counter 455 and a corresponding second threshold can be used to track even higher compression levels (e.g., a 3dB compression point). Since the LUT RAM address corresponds to the PA output power, each time the TX signal accesses a RAM address above a 2dB (3dB) compression point, the counter(s) simply increments, as that address directly corresponds to the PA output power.

[0072] The appropriate threshold can be determined based on the LUT construction, as each row of the LUT corresponds to the attenuation (or gain) of the PA at that output power level. The firmware can read through the LUT and find at what RAM address the PA attenuation exceeds 1dB, 2dB, or 3dB. The firmware then programs that address into one or more RAM threshold comparator circuits. Note that different MCS levels can select different thresholds at which the delivered power is reduced. Typically, Psat will vary with VSWR, temperature, and power supply voltage level, so the LUT address threshold will be updated as a new LUT is created.

[0073] Referring now to Figure 5, another block diagram of a DPD system according to an embodiment is shown, illustrating further details of the loopback path. As described above, calibration is performed periodically by looping the transmitted signal back through the received path. Generally, Figure 5 illustrates the same circuitry as that shown in Figure 2, and uses the same reference numerals (albeit the “500” series) to that extent.

[0074] Calibration uses the baseband equivalents of the PA input and output to update the DPD settings. Ideally, the output of the digitally replicated TX filter 545 is identical to the complex output of the analog TX filter 520, and therefore identical to the baseband equivalent of the PA input. On the receiver side, the complex output of the ADC 565 is the baseband equivalent of the PA output.

[0075] In some implementations, the calibration process is primarily firmware-based, but in other cases, certain hardware accelerators can be used. The main functions during calibration are: (i) time alignment; (ii) complex gain scaling; (iii) LUT population; and (iv) coefficient convergence enhanced by hybrid DPD. All four steps are performed whenever the loopback path is activated, even if time alignment can remain unchanged.

[0076] In one or more embodiments, complex samples of the PA input and output can be stored in RAM and then used to determine the compensation value. In one embodiment, 1024 samples can be obtained for both the input and output data. Since the transmission packets have far more than 1024 samples, certain portions of the packets can be identified to obtain the optimal samples. More specifically, for DPD calibration, samples from the middle or end of the packets during the data field portion can be used, as these samples may have the highest peak-to-root mean square ratio.

[0077] Before adjusting any DPD parameters, the transmit and receive signals are precisely aligned in time. The goal is to make the real (imaginary) parts of the PA transmission characteristics as close as possible to match, with the nominal gain being approximately 1.0. In the embodiment, alignment is performed in three stages: (1) integer time alignment; (2) fractional time alignment; and (3) gain / phase alignment.

[0078] As further shown in Figure 5, the alignment circuit 570 is configured to align samples between the input and output power paths, enabling the DPD calibration circuit 580 to operate on these corresponding samples. As illustrated, the alignment circuit 570 comprises a three-stage alignment circuit system, including an integer alignment circuit 572, a fractional alignment circuit 574, and a gain / phase correction circuit 576. In one or more embodiments, a single hardware correlator implementation can be used by these different circuits in a serial time to perform alignment, thereby aligning the input and output samples.

[0079] The first stage of alignment uses the correlation between the PA input and output to align the signal to the nearest sample boundary. For a rate of 160 MSps, the time alignment resolution will be 6.25 nanoseconds. In different implementations, as few as 128 samples may be sufficient, and at least 256 samples are preferred.

[0080] In this embodiment, integer-time alignment can be achieved using both fixed and variable delays. Specifically, a fixed delay exists in the loopback path, which can be determined from simulations or laboratory evaluations. A correlation, as shown in Equations 1 and 2, is used to find the integer-variable alignment. Specifically, Equation 1 is as follows: And Equation 2 is as follows: using maximize.

[0081] In equations 1 and 2, S R and S T These are the receiving (PA output) and transmitting (PA input) samples, respectively. In this embodiment, the search for alignment is estimated within a predefined window (e.g., + / - 20 samples). An optional parameter β can be used to nominally equalize the signal amplitude before alignment to a lower dynamic range requirement.

[0082] To optimize DPD calibration, finer time alignment than 6.25 nanoseconds resolution is required. To achieve near-infinite resolution time alignment, the Farrow filter method is used. The Farrow filter is an FIR filter with unity gain and linear phase (i.e., fixed delay) in the passband. The coefficients are modified to change the delay while maintaining unity gain.

[0083] A constant delay can be inserted into the path corresponding to the PA input signal, and a fractional variable delay can be placed in the loopback PA output path. In an embodiment, the variable delay path can be implemented using two Farrow filters (one real and one imaginary) whose delay can vary with the parameter μ. Depending on the implementation, μ can vary between -0.5 and +0.5 of the sampling period. A fixed delay path corresponds to a Farrow filter where μ=0, but reduces the amount of computation (or hardware) by utilizing the basic FIR structure.

[0084] Referring now to FIG. 6A, a block diagram of a fractional delay calculation circuit according to an embodiment is shown. In FIG. 6A, device 600 includes a fractional delay circuit 620 disposed between an integer alignment circuit 610 and a gain / phase alignment circuit 630. In the high-level view shown in FIG. 6A, the integer alignment circuit 610, which can search for approximately + / - 20 samples, provides the circuit 620 with corresponding integer-aligned transmit and receive samples (S). T and S R As illustrated, the fractional delay circuit 620 includes a pair of fixed-delay finite impulse response (FIR) filters 622 (implemented for processing real signals) and 624 (implemented for processing imaginary samples), with parameter μ=0. Conversely, the loopback signal (i.e., the received sample) is provided to corresponding Farrow filters 626 and 628 (which operate on the real and imaginary parts of these complex samples, respectively). As shown, these filters have varying delays, which in this embodiment can vary from -0.5 to 0.5 (e.g., 6.25 nanoseconds) of the sampling period. The resulting fractionally aligned samples are then provided to the gain / phase alignment circuit 630.

[0085] Integer alignment is first performed by measuring the sample correlation at the input of the Farrow filter. Fractional alignment is then performed by measuring the correlation at the output of the Farrow filter and selecting μ that maximizes the correlation.

[0086] In another embodiment, the FIR filter with a fixed delay (implemented as μ=0 in FIG. 6A) can be eliminated to save computation. Referring now to FIG. 6B, a block diagram of a fractional delay calculation circuit according to another embodiment is shown. In this arrangement, a fixed number of sample delays are included, which are close to the Farrow filter delay where μ=0.

[0087] As shown in Figure 6B, circuit 600' has a fixed delay portion of fractional alignment circuit 620, which uses a fixed number of delay elements (i.e., delay elements 621) for both the real and virtual paths. 1-n and 623 1-n This can be achieved by […]. In other respects, circuit 600' can be implemented in the same way as circuit 600 discussed above.

[0088] Then, correlation measurements of both integer and fractional alignment are performed at the output of the fractional alignment circuit 600'. In the implementation, the procedure is as follows: (1) set µ=0; (2) measure the integer alignment at the output of the Farrow filter and find the optimal integer delay to be inserted based on the correlation measurement; and (3) vary μ from -0.5 to +0.5 to determine the optimal fractional delay.

[0089] The variable-delay Farrow filter can be constructed with various topologies, but it implements the same basic equation as shown in Equation 3: In Equation 3, y is the filter output, x is the filter input, and c x These are the filter coefficients. Now referring to Figure 7A, a single real FIR filter with a single coefficient vector is shown, which is recalculated when a different fractional delay value is needed. In Figure 7B, the Farrow filter is implemented using sub-filters, each with its own constant coefficient vector.

[0090] Therefore, as shown in Figure 7A, the first filter implementation 700 is implemented using a single real filter 710. In Figure 7B, circuit 750 includes multiple sub-filters 760. 0-3 As shown, sub-filter 760 1-3 The output is via multiplier 770 1-3 Adder 780 1-3 Multiply and / or add the μ values ​​to each other and their corresponding μ values. Although shown at this high level in the embodiment of Figure 7B, many variations and alternatives are possible.

[0091] There are many possible coefficient vectors to implement a Farrow filter. The number of sub-filters can be modified, and the number of taps in each sub-filter can be changed. In the implementation, finite-width coefficients can be used in a Farrow filter, where the total coefficient width is 12 bits (1 sign, 1 integer, and 10 fractions).

[0092] In gain / phase alignment, the input and output of the PA are analyzed to determine the complex gain until the amplitude and phase of the input and output signals are nominally matched. These alignments correlate approximately equal amplitude and equal phase signals, and the LUT is automatically normalized to have a 1.0 attenuation in the linear region of the PA.

[0093] In one embodiment, an iterative complex LMS adaptive method can be used. In another embodiment, the gain G that minimizes the mean squared error (MSE) between blocks of N x() and y() samples can be calculated. Such a calculation can be performed according to Equation 4. The number of real number multiplications and additions is based on the number of samples. In the implementation, approximately 128 samples can be used, or equivalently, 768 integer multiplications.

[0094] After alignment, the transmitted and loopback data are time-aligned, phase-aligned, and amplitude-equalized. The next step in the calibration process is to calculate the complex attenuation of the PA for each PA output sample. In this embodiment, the process is as follows: 1. Take the time-aligned PA input and output samples and calculate the complex attenuation of the PA. (Attenuation = PA input / PA output).

[0095] 2. Calculate the PA output power of this sample.

[0096] 3. Locate the "bin" (i.e., the corresponding row) in the LUT that corresponds to the PA's output power. Average the new complex attenuation with any previous attenuations in that "bin". Note that a weighted sum is used because the attenuations in that row may have already been averaged over many samples.

[0097] 4. Obtain the next input / output sample pair and repeat steps 1-3.

[0098] 5. After all samples have been used, a. if any behavior corresponding to higher output power is empty, extrapolate the attenuation: i. copy the attenuation value from the last highest power measurement to the higher bins where there is no data; or ii. if the attenuation of the last few occupied bins is increasing, extrapolate the unfilled bins linearly at the same rate of attenuation increase.

[0099] b. If any intermediate row has no data, the interpolation is derived from the decay of adjacent rows.

[0100] c. For very low power signals, to eliminate noise attenuation calculations, use the same attenuation level for the lowest 10 dB (e.g., lowest 25%) of the row. (The lowest power row can also be eliminated from RAM).

[0101] 6. Finally, to smooth the data across PA output power, a 5-line moving average filter can be used across PA attenuation stored in the LUT.

[0102] When the LUT is built, an additional column can be used to store the number of samples used to create the average PA attenuation of that PA output power.

[0103] Referring now to FIG8, a block diagram of a LUT according to an embodiment is shown. As shown, LUT 800 includes a plurality of entries 810 0-n Each entry has multiple fields (812). 1-3 Note that this third entry (column) can be eliminated when used for future groupings and when placed in high-speed memory along the TX path.

[0104] As illustrated, the addresses of rows in LUT 800 are generated by circuitry that maps the target output power of the PA to the corresponding row. In each entry 810, a given complex attenuation value for the PA can be obtained, with separate two-byte values ​​for the real and imaginary parts. Although shown in Figure 8 in a specific range (i.e., 20 dB to -20 dB), additional or different maximum and minimum target output power levels may be used in other implementations.

[0105] In the implementation, to simplify the hardware and firmware requirements for LUT construction: (1) for the time alignment of PA input and output signals, only 256 samples from the group center are used; (2) the time alignment makes the PA input conjugate with the PA output and calculates abs()^2 for each alignment test until the maximum correlation is found; (3) for LUT construction, only 1024 samples from the group center are used (after alignment has been performed); (4) the Farrow filter step size is limited to, for example, 0.125T (T / 8, where T is the sampling period); (5) the word width can be limited to 2 bytes (with one sign bit, 0 integer bits and 10 fraction bits).

[0106] Referring now to Figure 9, a flowchart of a method according to an embodiment is shown. More specifically, method 900 is a method for generating PA attenuation values ​​when filling a lookup table for use in performing predistortion as described herein. Note that method 900 can be performed at various times, including during PTE (i.e., production testing), when incorporating an IC having a transceiver as described herein into a wireless device, and / or dynamically in the field during normal operation. In embodiments, method 900 can be performed by a separate hardware circuit system and / or in combination with firmware and / or software.

[0107] As illustrated, method 900 begins by aligning samples of the input and output signals (box 910). These samples of the input and output signals correspond to the input to the PA (received after baseband processing) and the output of the PA, as fed via a loopback path, as described herein. Once a pair of samples is aligned, control is passed to box 920, where an attenuation value for the PA is calculated based on these samples (box 920). In an embodiment, the attenuation value can be calculated by dividing the input of the PA by the output of the PA.

[0108] Next, at box 930, the PA output power level for the sample pair is calculated. In an embodiment, the output power can be calculated by summing the individual squares of the real and imaginary components of the output signal sample. At box 940, an entry in memory associated with the output power level can be identified. As described above, the target output power level can be used to generate an address for accessing the memory.

[0109] Then, at box 950, the PA attenuation value can be generated at least in part based on the calculated PA attenuation value. That is, the current PA attenuation value can be stored based on whether an attenuation value already exists in the accessed entry (when no previously stored value exists). Conversely, when a previously stored value exists, the current attenuation value can be combined with the stored value, for example, via an averaging operation. Note that in some cases, a weighted summation can be performed based on the number of samples. In any case, the determined PA attenuation value is then stored in the identified entry at box 960.

[0110] Referring again to Figure 9, at diamond 970, it is determined whether any further samples need to be analyzed. If so, control is transferred back to box 910 as described above. Otherwise, lookup table filling (box 980) can be accomplished by filling a table, for example, stored in memory, with updated entries. Depending on when this method is performed, the table can be stored in the NVM, which may include in the predistortion circuitry or in another location such as RAM. Although shown at this high level in the embodiment of Figure 9, many variations and alternatives are possible.

[0111] Referring now to Figure 10, a flowchart of a method according to another embodiment is shown. More specifically, method 1000 is a method for pre-distorting a signal using attenuation values ​​stored in a lookup table as described herein before amplification in the PA. In embodiments, method 1000 may be performed by a separate hardware circuit system and / or in combination with firmware and / or software.

[0112] As shown, method 1000 begins by calculating the input power of a sample of the input signal (block 1010). This input signal is a complex baseband signal that may include message content generated in another part of the baseband processor. Next, at block 1020, based on the input power, a target output power for the sample used for the PA can be determined. Based on this target output power, at block 1030, an address for accessing the LUT can be generated. As discussed above in various embodiments, a two-step address generation process can be performed.

[0113] Referring again to Figure 10, next at box 1040, an entry in the LUT can be accessed using an address. This entry includes a complex PA attenuation value. This attenuation value is used at box 1050 to pre-distort the input signal sample. In this embodiment, the attenuation value, along with any ideal gain value (which can be set to a nominal value of 1.0), is multiplied by the input signal. Subsequently, at box 1060, the resulting pre-distorted signal sample is converted to analog form and up-converted to RF level. Finally, at box 1070, the RF signal (including the pre-distortion) is amplified in the PA. Although shown at this high level, many variations and alternatives are possible.

[0114] Referring now to Figure 11, a block diagram of a representative integrated circuit 1100 is shown, which includes DPD circuitry having LUTs generated and used as described herein. In the embodiment shown in Figure 11, integrated circuit 1100 may be, for example, a multi-mode wireless transceiver that can operate according to one or more wireless protocols or other devices that can be used in various use cases. In one or more embodiments, the circuitry of integrated circuit 1100 shown in Figure 11 may be implemented on a single semiconductor die or on separate dies of additional IP blocks required for wireless communication, MCU computing, external flash memory, and / or performing various functionalities.

[0115] Integrated circuit 1100 may be included in a range of devices, but for the purposes of discussion, it may be incorporated into an IoT device. In the illustrated embodiment, integrated circuit 1100 includes a memory system 1110, which in embodiments may include volatile memory (such as RAM) and non-volatile memory (such as flash memory). Flash memory is a non-transitory storage medium that can store instructions and data. In an embodiment, the storage device may store LUT 11051, which has entries including, for example, compensation information generated during PTE. Flash memory is a non-transitory storage medium that may also store instructions that, when executed, cause the DPD circuitry system to perform dynamic updates to one or more LUTs, as described herein. As further shown, memory 1110 includes LUT 11052, which may be stored in RAM and may include entries filled from flash memory and / or entries dynamically generated and updated in the field as described herein. Integrated circuit 1100 may also include a memory controller 1190.

[0116] The memory system 1110 is coupled via a bus 1150 to one or more digital cores 1120. The digital cores 1120 may include one or more cores and / or microcontrollers that act as processing units of an integrated circuit and can execute IoT terminal device applications to control the circuitry of IoT devices. Furthermore, the digital cores 1120 may be coupled to a clock generator 1130, which may provide one or more phase-locked loops or other clock generator circuitry to generate various clocks for use by the IC's circuitry.

[0117] As further illustrated, IC 1100 also includes a power circuitry system 1140. Depending on the specific implementation, additional circuitry systems may be present to provide various functionalities and interaction with external devices. Such circuitry systems may include an interface circuitry system 1160, which provides a digital communication interface with additional circuitry systems, such as another IC that may be coupled to IC 1100 via link 1195. IC 1100 may also include a security circuitry system 1170 for implementing wireless security technologies.

[0118] Additionally, as shown in Figure 11, a transceiver circuit system 1180 can be provided to transmit and receive wireless signals, for example, according to one or more of local or wide-area wireless communication schemes such as Matter, Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. It is understood that, although shown in this high-level view, many variations and alternatives are possible.

[0119] ICs such as those described herein can be implemented in a variety of different devices as described above. Referring now to Figure 12, a high-level simplified diagram of a network according to an embodiment is shown. As shown in Figure 12, network 1200 includes various devices, including IoT devices that can use LUTs generated and updated as described herein to perform digital predistortion of baseband signals to compensate for distortion of the PA. It is understood that network 1200 includes other devices such as access points and remote service providers.

[0120] In the embodiment of FIG12, the wireless mesh network 1205 exists, for example, in a network having multiple wireless devices 1210. 0-n In the building. As shown, a wireless device 1210, which may be an IoT or other wireless device, is coupled to an access point 1230, which in turn communicates with a remote service provider 1260 via a wide area network 1250 (e.g., the Internet). It is understood that although shown at this high level in the embodiment of Figure 12, many variations and alternatives are possible.

[0121] While this disclosure has been described with respect to a limited number of embodiments, many modifications and variations will be appreciated by those skilled in the art upon which this disclosure is made. The appended claims are intended to cover all such modifications and variations.

Claims

1. An apparatus comprising: Baseband processor, which is used to generate baseband signals; A digital predistortion (DPD) circuit is used to predistort the baseband signal using compensation information obtained from a lookup table, the lookup table having multiple entries, each entry storing a predistortion value, the lookup table being addressed based on the target output power level of the baseband signal; A converter for converting the predistorted baseband signal into an analog signal; A radio frequency (RF) circuit system, comprising: a mixer for up-converting the analog signal into a predistorted RF signal; and a power amplifier (PA) for amplifying the predistorted RF signal.

2. The device according to claim 1, wherein, Each of the plurality of entries in the lookup table is used to store the compensation information, including complex attenuation values.

3. The device according to claim 1, wherein, Each of the plurality of entries in the lookup table is used to store the compensation information, including complex gain values.

4. The device according to claim 1 further includes an address generator circuit for generating the address based on the target output power level.

5. The device according to claim 4, wherein, The address generator circuit is used to generate an address comprising a first part and a second part, wherein the address generation circuit is used to: generate the first part based on a first comparison of the target output power level with a first value; and generate the second part based on a second comparison of the operation result between the target output power level and the first part with a second value.

6. The device of claim 1, further comprising at least one counter for maintaining a count of samples of the baseband signal having a target output power level exceeding at least one threshold.

7. The device of claim 6 further includes a control circuit for controlling the gain level of the transmission circuitry of the RF circuitry, at least in part based on the count.

8. The device of claim 1 further includes a loopback circuit coupled to the output of the PA, the loopback circuit being used to generate a digital signal corresponding to the amplified RF signal.

9. The device according to claim 8, wherein, The loopback circuit further includes an alignment circuit, which is used to receive the digital signal and the predistorted baseband signal and align the predistorted baseband signal with the digital signal.

10. The device according to claim 9, wherein, The alignment circuit includes: an integer alignment circuit; a fractional alignment circuit; and a gain / phase alignment circuit.

11. The device according to claim 10, wherein, The alignment circuit includes at least one correlator, and each of the integer alignment circuit, the fractional alignment circuit, and the gain / phase alignment circuit is used to share the at least one correlator.

12. The device according to claim 1, wherein, Each of the plurality of entries is associated with the target output power level that is logarithmically spaced from adjacent entries.

13. The device according to claim 1, wherein, The DPD circuit is used to further predistort the baseband signal to compensate for the memory effect of the PA.

14. A method comprising: The input power of the input samples of the group to be amplified and output from the power amplifier (PA) of the transmitter is calculated in the digital predistortion circuit of the transmitter; The target output power of the input sample is determined based on the input power; an address is generated based on the target output power and an entry in a lookup table is accessed using the address, the entry including a complex attenuation value of the PA associated with the target output power; the input sample is predistorted using the complex attenuation value of the PA; the predistorted input sample is up-converted to a radio frequency (RF) signal corresponding to the input sample; and the RF signal is amplified via the PA to output an amplified RF signal.

15. The method of claim 14, wherein, Generating the address includes: determining a first part of the address based on a first decoding; determining a second part of the address based on a second decoding; and combining the first part and the second part to generate the address.

16. The method of claim 14, further comprising: Use the address to access the second entry in the lookup table, wherein the second entry is adjacent to the first entry.

17. The method of claim 14, further comprising: The interpolated complex PA attenuation value is determined based on the complex PA attenuation value of the first entry and the second complex PA attenuation value of the second entry; The input sample is pre-distorted using the interpolated complex attenuation value of PA.

18. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 14-17.

19. An apparatus comprising: The component is used to calculate the attenuation value of a sample pair, the sample pair including an input sample to a power amplifier (PA) of the transceiver and an output sample from the PA, the output sample being aligned with the input sample; A component for calculating the output power level of the PA based at least in part on the input samples; Components used to generate PA attenuation values ​​based at least in part on the calculated attenuation values; And components for storing the PA attenuation value in an entry in memory, the entry being associated with the output power level.

20. The device according to claim 19, wherein, The component used to generate the PA attenuation value is used to combine the calculated attenuation value with the attenuation value stored in the entry stored in the memory.

21. The apparatus of claim 19, further comprising a component for aligning the input sample with the output sample.

22. The device according to claim 21, wherein, The components for aligning the input signal with the output signal include: components for aligning the input sample with the output sample integer; components for aligning the input sample with the output sample partially; and components for aligning the input sample with the output sample in at least one of gain or phase.

23. The apparatus of claim 19, further comprising: Components for updating multiple entries in the memory during the transmission of a first packet from the transceiver; And one or more of the multiple entries used to access the memory for updates to provide digital predistortion components to one or more samples of a second packet to be transmitted from the transceiver.

24. The device of claim 19, further comprising components for calculating the attenuation value, components for calculating the output power level, and components for generating the PA attenuation value when a change in at least one environmental metric of the transceiver exceeds a threshold.

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