Test circuit and method for delay circuit, register setup time and hold time
By simplifying the delay circuit structure, high-precision register setup and hold time testing can be achieved with only two delay chains and one register under test, solving the problems of low testing accuracy and large area occupation in the existing technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QINGXIN SEMICON TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-01-19
- Publication Date
- 2026-07-10
AI Technical Summary
In the existing technology, the setup and hold time test circuits for registers require a large number of parallel delay chains, which occupy a large chip area and have manufacturing errors, resulting in low test accuracy.
A delay circuit is used, including a selector, a series delay unit, a NAND gate and an inverter. By controlling the operating mode of the delay unit and the selector, the setup time and hold time can be tested with only two delay chains and one register under test, thus reducing the number of delay chains and registers.
It achieves high-precision register setup and hold time testing, reduces input transmission time error and output load error, and saves chip area.
Smart Images
Figure CN121966524B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of register technology, and in particular to a delay circuit, a test circuit and method for register setup time and hold time. Background Technology
[0002] Register setup time and hold time are two core timing parameters in sequential circuits. They determine whether the register can stably sample the input signal and are key indicators for chip timing analysis (STA). Setup time refers to the minimum time the register's input signal must remain stable before the arrival of the clock's effective edge. Essentially, it ensures that the register's input signal has sufficient time to propagate to the internal latch structure and complete level stabilization. Hold time refers to the minimum time the register's input signal must remain stable after the arrival of the clock's effective edge. Essentially, it ensures that the register's internal latch state is not disturbed by subsequent changes in the input signal after the clock edge is triggered.
[0003] To verify whether sequential circuits can operate stably and reliably, and to provide key information for chip design, mass production, and system integration, it is necessary to test the setup and hold times of registers. Figure 1 and Figure 2 The diagrams show schematic representations of test circuits for register setup time and hold time in the prior art. For example... Figure 1 As shown, the setup time test circuit includes multiple registers (DFF). The first register's data input (D) is connected to a delay chain, while the clock input (CK) is not connected. The second register has no delay chain connected to either its data input or clock input. The third register has a delay chain connected to its clock input, but no data input. The fourth register branch and subsequent branches all have delay chains connected to their clock inputs, but no data inputs, with the delay chain lengths gradually increasing. Each delay chain consists of buffers with known cell delays connected in series. This circuit controls the delay time of the input data and clock for each register through a series of parallel delay chains. It identifies the branch where the register output first flips; the delay time corresponding to this branch is the maximum setup time. This branch and subsequent branches with longer delay chains meet the setup requirements and thus flip. The branch preceding this branch, the critical branch where the register output has not yet flipped, corresponds to the minimum setup time. This branch and subsequent branches with shorter delay chains maintain their previous output state because the setup requirement is not met. Figure 2As shown, the hold time test circuit also includes multiple registers. The clock input of the first register is connected to a delay chain, while the data input is not. Neither the clock nor data input of the second register is connected to a delay chain. The data input of the third register is connected to a delay chain, while the clock input is not. The fourth register branch and subsequent branches all have data inputs connected to delay chains, but no clock input, with the delay chain lengths gradually increasing. This circuit controls the delay time of the input data and clock for each register through a series of parallel delay chains. It finds the branch where the register output first flips; the delay time corresponding to this branch is the maximum hold time. This branch and subsequent branches with longer delay chains satisfy the hold requirement and thus flip. The delay time of the branch preceding this branch—the critical branch where the register output has not yet flipped—corresponds to the minimum hold time. This branch and its preceding branches with shorter delay chains do not satisfy the hold requirement and remain unchanged from the previous output state.
[0004] It can be seen that existing test circuits require a large number of parallel delay chains to ensure accuracy, thus necessitating a large number of registers and buffers, resulting in a large footprint. Furthermore, due to the different positions and routing of branches in the actual layout, manufacturing errors are inherent. Moreover, it is impossible to guarantee that the input slew time of each delay chain and the output loading conditions of the register under test are consistent, leading to potential discrepancies between the test results and actual values. Summary of the Invention
[0005] To address some or all of the limitations of existing technologies, and in order to simplify the test circuit structure for register setup and hold times and improve test accuracy, the first aspect of this invention provides a delay circuit, comprising:
[0006] The first selector has its first data input terminal D0 connected to the first enable signal;
[0007] A number of time delay units connected in series are connected to the output of the first selector;
[0008] The NAND gate has its first input connected to the last stage delay unit and its second input connected to the second enable signal.
[0009] A second selector, whose selection control terminal is connected to the output terminal of the NAND gate, has its first data input terminal D0 and second data input terminal D1 connected through a first inverter, and its output terminal connected to the second data input terminal D1 of the first selector through a second inverter; and
[0010] The third inverter is connected to the output of the second selector and is used to output the output signal of the delay circuit.
[0011] Furthermore, the delay unit includes a third selector, wherein the first data input terminal D0 of the third selector is connected to the input signal, and the second data input terminal D1 is connected to the input signal through a buffer.
[0012] Based on the delay circuit described above, a second aspect of the present invention provides a test circuit for register setup time and hold time, comprising:
[0013] An input buffer whose input is connected to the test vector;
[0014] A data delay circuit, employing the delay circuit described above, has its input connected to the output of the input buffer, and its output connected to the data input of the register under test; and
[0015] The clock delay circuit adopts the delay circuit described above, and its input terminal is connected to the output terminal of the input buffer, and its output terminal is connected to the clock terminal of the register under test.
[0016] Furthermore, the test circuit also includes:
[0017] The frequency divider and counting circuit is located between the data delay circuit and the data input terminal of the register, and between the clock delay circuit and the clock terminal of the register.
[0018] Based on the test circuit described above, a third aspect of the present invention provides a method for testing register setup time and hold time, comprising:
[0019] By controlling the data delay circuit and clock delay circuit in the test circuit, the critical control signal value when the register under test flips is determined;
[0020] The delays of the data delay circuit and the clock delay circuit are determined based on the critical control signal value; and
[0021] The setup time and / or hold time of the register under test are determined based on the delay of the data delay circuit and the clock delay circuit.
[0022] Furthermore, determining the critical control signal value when the register under test flips includes:
[0023] During setup testing, the data delay circuit and clock delay circuit are controlled to ensure that the clock transmission delay is greater than the data transmission delay. Then, the delay difference between the data delay circuit and clock delay circuit is gradually reduced. The control signal values of the clock delay circuit and data delay circuit at the first register output flip are recorded; these are the critical control signal values at the flip of the register under test.
[0024] During the hold time test, the data delay circuit and clock delay circuit are controlled to make the data transmission delay greater than the clock transmission delay. Then, the delay difference between the data delay circuit and clock delay circuit is gradually reduced, and the control signal values of the data delay circuit and clock delay circuit at the first flip of the register output are recorded. These control signal values are the critical control signal values when the register under test flips.
[0025] Furthermore, determining the delay of the data delay circuit and the clock delay circuit based on the critical control signal value includes:
[0026] The clock delay circuit is set to the critical control signal value and the clock delay circuit is set to oscillation mode. After a specified time, the output value of the clock delay circuit is recorded, and the delay of the clock delay circuit is determined based on the output value.
[0027] The data delay circuit is set to the critical control signal value and set to oscillation mode. After a specified time, the output value of the data delay circuit is recorded, and the delay of the data delay circuit is determined based on the output value.
[0028] Furthermore, the testing method also includes:
[0029] During setup testing, before determining the critical control signal value for the register under test toggling, the data delay circuit and clock delay circuit are controlled to ensure that the clock transmission delay is less than the data transmission delay, thus triggering a register toggle.
[0030] When testing the hold time, before determining the critical control signal value when the register under test flips, the data delay circuit and clock delay circuit are controlled to make the clock transmission delay greater than the data transmission delay, and the register is triggered to flip once.
[0031] The present invention provides a test circuit and method for delay circuits, register setup time and hold time. It only requires two delay chains and one register under test to simultaneously measure the setup time and hold time of the register. It not only has no manufacturing error and occupies a small area, but also has small input transmission time error and zero output load error, thus achieving higher test accuracy. Attached Figure Description
[0032] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.
[0033] Figure 1 A schematic diagram of the structure of a test circuit for register setup time in the prior art is shown;
[0034] Figure 2 A schematic diagram of the structure of a test circuit for the hold time of a register in the prior art is shown;
[0035] Figure 3 This diagram illustrates the structure of a delay circuit according to an embodiment of the present invention.
[0036] Figure 4 This diagram illustrates the structure of a delay unit according to an embodiment of the present invention.
[0037] Figure 5 This diagram illustrates a structural schematic of a test circuit for register setup and hold times according to an embodiment of the present invention; and
[0038] Figure 6 The diagram shows a flowchart illustrating a method for testing register setup time and hold time according to an embodiment of the present invention. Detailed Implementation
[0039] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
[0040] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.
[0041] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.
[0042] To simplify the structure of test circuits for register setup and hold times, save chip area, and improve test accuracy, this invention provides a delay circuit and its corresponding control method, which is applied to the testing of register setup and hold times. This allows setup and hold time testing to be achieved using only two delay chains and one register under test. Due to the small number of delay chains and registers used, input transmission time errors and output load errors can also be effectively reduced, thus improving test accuracy.
[0043] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.
[0044] Figure 3 A schematic diagram of a delay circuit according to an embodiment of the present invention is shown. Figure 3 As shown, a delay circuit includes several series-connected delay units 301, a first selector 302, a second selector 303, a NAND gate 304, and multiple inverters 305. By controlling each delay unit 301, the desired delay duration can be obtained. Simultaneously, the operating mode of the delay circuit can be controlled by the first selector 302, the second selector 303, the NAND gate 304, and the multiple inverters 305, thereby meeting different requirements. In one embodiment of the invention, the delay circuit includes two operating modes: an input mode and an oscillation mode. In the input mode, the delay circuit is controlled by an external enable signal. In the oscillation mode, the output of the delay unit after specific logic processing is used as the control signal.
[0045] To achieve the above functions, such as Figure 3 As shown, in one embodiment of the present invention, the first data input terminal D0 of the first selector 302 is connected to the first enable signal and the external enable signal SH_EN, and the second data input terminal D1 is connected to the output of the delay unit 301 through several logic devices, so that when the selection signal SH_LOOP_SEL is 0, the first selector 302 outputs the first enable signal SH_EN, and when the selection signal SH_LOOP_SEL is 1, the delay circuit is in oscillation mode.
[0046] like Figure 3As shown, the first input of the NAND gate 304 is connected to the output of the last stage delay unit 301, and the second input is connected to the second enable signal SH_OSC_EN. Its output serves as the selection signal for the second selector 303. The first data input D0 of the second selector 303 is connected to the edge selection signal EDGE_SW, and the second data input D1 is connected to the edge selection signal EDGE_SW via a first inverter. The output is connected to the second data input D1 of the first selector 302 via a second inverter. Therefore, when the selection signal SH_LOOP_SEL of the first selector 302 is set to 1 and the second enable signal SH_OSC_EN is set to 1, the delay circuit enters oscillation mode.
[0047] At the same time, such as Figure 3 As shown, the output terminal of the second selector 303 is also connected to a third inverter, and the output signal of the third inverter is the output signal OSC_OUT of the delay circuit.
[0048] Figure 4 A schematic diagram of a delay unit according to an embodiment of the present invention is shown. Figure 4 As shown, the delay unit includes a selector 401 and a buffer 402. The first data input terminal D0 of the selector 401 is connected to the input signal IN, and the second data input terminal D1 is connected to the input signal IN through the buffer 402. Based on Figure 3 As can be seen, in the embodiments of the present invention, the input signal IN of the first-stage delay unit is the output signal of the first selector 302, and the input signals IN of the remaining delay units are the output OUT of the previous stage delay unit. By controlling the selection signal SEL of the selector 401, it is possible to control whether a buffer is connected in the circuit, and thus control whether the delay unit generates a delay. After connecting multiple delay units in series, the corresponding delay time can be obtained by inputting the control signal DLY_SEL as needed.
[0049] As mentioned above, the delay circuit can be used in the test circuit for the setup time and hold time of the register. By controlling the working mode of the delay circuit and the output of each delay unit through specific steps and methods, the setup time and hold time of the register can be obtained.
[0050] Figure 5 This diagram illustrates the structure of a test circuit for register setup and hold times according to an embodiment of the present invention. Figure 5As shown, a test circuit for register setup and hold times includes two delay circuits as described above. One delay circuit, 501, serves as a data delay circuit and is connected to the data input terminal D of the register under test (001). The other delay circuit, 502, serves as a clock delay circuit and is connected to the clock terminal CK of the register under test (001). The delay circuits also include an input buffer 503, whose input terminal is connected to the test vector, and whose output terminal is connected to the input terminals of the delay circuits 501 and 502. The type of register under test is not limited.
[0051] To adapt to different test accuracy requirements, in one embodiment of the present invention, a frequency divider and a counting circuit can be further connected between the delay circuits 501 and 502 and the data input terminal and clock terminal of the register under test, so as to control the accuracy of the delay time output by the delay circuit, and thus control the test accuracy of the final setup time and hold time.
[0052] Based on the test circuit described above, the setup time and hold time of the register can be tested. Specifically, the critical control signal value when the register under test flips can be determined by controlling the specific delay time of the data delay circuit and the clock delay circuit in the test circuit. Then, the delay of the data delay circuit and the clock delay circuit is determined based on the critical control signal value. Finally, the setup time and / or hold time of the register under test are determined based on the delay of the data delay circuit and the clock delay circuit.
[0053] Figure 6 This diagram illustrates a flowchart of a method for testing register setup time and hold time according to an embodiment of the present invention. Figure 6 As shown, a method for testing register setup time and hold time includes:
[0054] First, in step 601, the initial delay time is set. The delay time of the data delay circuit and the clock delay circuit is controlled by setting the values of the control signals D_DLY_SEL and CK_DLY_SEL. When testing the hold time, initially, the data transmission delay should be much greater than the clock transmission delay. For example, the control signal D_DLY_SEL of the data delay circuit can be set to all 1s, meaning all delay units of the data delay circuit will be delayed. Conversely, the low-order bit of the control signal CK_DLY_SEL of the clock delay circuit can be set to 1, and the high-order bit to 0, meaning only some delay units of the clock delay circuit will be delayed. Conversely, during test setup, the initial clock transmission delay must be significantly greater than the data transmission delay. For example, the control signal CK_DLY_SEL for the delay circuit can be set to all 1s, meaning all delay units in the delay circuit will be delayed. Conversely, the low-order bit of the control signal D_DLY_SEL for the data delay circuit can be set to 1, and the high-order bit to 0, meaning only some delay units in the data delay circuit will be delayed. In one embodiment of the invention, to ensure the register under test is in a stable output state at the start of the test, a register toggle can be triggered first. Specifically, when testing the hold time, the register needs to be in a stable state that meets the hold requirement at the start of the test. Therefore, the control signal D_DLY_SEL of the data delay circuit can be set to all 0s, and the low bit of the control signal CK_DLY_SEL of the clock delay circuit can be set to 1 and the high bit to 0, so that the data arrives at the register input much before the clock. At this time, the register does not meet the hold requirement, so the first enable signal of the delay circuit generates a valid edge, i.e., a trigger signal, and the register output is state 1. At the start of the test, CK_DLY_SEL is kept unchanged, while D_DLY_SEL is set to all 1s, which can meet the hold requirement. The register output will undergo a flip, and the register output will be state 2. This flip confirms that the register under test is in a stable output state that meets the hold requirement at the start of the test. Similarly, when testing setup time, the clock needs to arrive at the register input much before the data, so that the register does not meet the setup requirements. Then, a trigger signal is given. At the start of the test, D_DLY_SEL is kept unchanged, while CK_DLY_SEL is set to all 1s. The register can meet the setup requirements, and the register output flips once, thus ensuring that the register is in a stable output state that meets the setup requirements when the test starts.
[0055] Subsequently, if the test holds for a certain time, the data delay circuit is controlled to gradually reduce the data transmission delay. The control signal values of the data delay circuit and clock delay circuit at the first toggle of the register output are recorded, thus obtaining the critical control signal value when the register under test toggles. If the test sets up for a certain time, the clock delay circuit is controlled to gradually reduce the clock transmission delay. The control signal values of the data delay circuit and clock delay circuit at the first toggle of the register output are recorded, thus obtaining the critical control signal value when the register under test toggles. Specifically, this includes:
[0056] Next, in step 602, the delay difference between the two delay circuits is reduced. If the hold time is being tested, the value of the control signal of the clock delay circuit can be kept unchanged, but the control signal of at least one delay unit in the data delay circuit can be changed from 1 to 0 to reduce the delay of the data delay unit. Similarly, if the setup time is being tested, the value of the control signal of the data delay circuit can be kept unchanged, but the control signal of at least one delay unit in the clock delay circuit can be changed from 1 to 0 to reduce the delay of the clock delay unit. The specific number of delay units reduced and / or increased can be determined according to the required test accuracy and the total number of delay units. In one embodiment of the present invention, for ease of operation, this is achieved by shifting the control signal D_DLY_SEL of the data delay circuit or the control signal CK_DLY_SEL of the clock delay circuit by a specified number of bits, for example, by shifting it to the right by a specified number of bits to change its highest specified bit data from 1 to 0, etc.
[0057] Next, in step 603, it is determined whether the register output has toggled. The output of the register under test is checked, and it is determined whether it has toggled. If it has not toggled, the process returns to step 602 to further reduce the delay difference between the two delay circuits. If it has toggled, the process proceeds to step 604 to record the current control signal value. The delay difference value reduced each time can be the same or different; for ease of calculation and control accuracy, it is preferable that the delay difference value reduced each time is the same.
[0058] In step 604, record the current control signal value. Record the control signals of the data delay circuit and clock delay circuit when the register output flips as the critical control signal value; and
[0059] Finally, in step 605, the setup time or hold time is determined. Based on the recorded critical control signal value, the data delay circuit and clock delay circuit are controlled to determine their delays, and the setup time or hold time of the register is determined based on the delay. Specifically, in one embodiment of the present invention, the delay is determined by controlling the data delay circuit and clock delay circuit to enter an oscillation mode and controlling the data delay circuit and clock delay circuit with the critical control signal value. Specifically, the clock delay circuit is set to the critical control signal value and set to oscillation mode. After a specified duration, the output value of the clock delay circuit is recorded, and the delay of the clock delay circuit is determined based on the output value. Then, the data delay circuit is set to the critical control signal value and set to oscillation mode. After a specified duration, the output value of the data delay circuit is recorded, and the delay of the data delay circuit is determined based on the output value. In one embodiment of the present invention, the specified duration is 200 nanoseconds. In one embodiment of the present invention, the difference between the final data delay and the clock delay is the setup time or hold time. In another embodiment of the present invention, the upper limit of the data delay or clock delay can be further determined based on the control signal value of the previous state of the register output flip, thereby obtaining the maximum value of the setup time or hold time.
[0060] To facilitate understanding, the following example demonstrates the steps for testing based on the aforementioned test circuit, using the rising edge-triggered D register's hold-rise time as an example:
[0061] First, set the delay circuit to input mode, with the initial values for each signal as follows:
[0062] CK_EDGE_SW=0, D_EDGE_SW=0, CK_SH_LOOP_SEL=0, D_SH_LOOP_SEL=0, CK_SH_OSC_EN=1, D_SH_OSC_EN=1. In this mode, the first enable signal SH_EN reaches the output OSC_OUT of the delay circuit after passing through a delay unit. Therefore, by controlling the length of the delay unit through the D_DLY_SEL and CK_DLY_SEL signals, the time difference between data and clock arriving at the register input can be controlled.
[0063] Next, as mentioned earlier, to ensure that the register is in a stable output state when hold0, the register needs to be set to 1 first, and the data needs to arrive at the register input much before the clock. Specifically, CK_DLY_SEL=00000fffff, D_DLY_SEL=0000000000, SH_EN jumps from 0 to 1 to generate a trigger rising edge, and the register outputs Q=1 (denoted as state1).
[0064] Next, keeping CK_DLY_SEL = 00000fffff unchanged, the following loop is executed: D_DLY_SEL shifts from ffffffffff -> 7fffffffff -> 3fffffffff -> … -> 0000000001 -> 0000000000, shifting right by 0 to ensure the data transmission delay is much greater than the clock transmission delay. Then, the data transmission delay is gradually reduced, and SH_EN shifts from 0 to 1. At the beginning of the test, the data arrives at the register input much later than the clock, and the register outputs Q = 0 (denoted as state2; Q changing from state1 to state2, i.e., a jump from 1 to 0, indicates the register is in a stable hold0 state). Until a certain test, Q jumps from 0 to 1, indicating that hold0 has failed. At this point, D_DLY_SEL is recorded, assuming D_DLY_SEL = 000003ffff, and CK_DLY_SEL = 00000fffff remains unchanged.
[0065] Next, set the delay circuit to oscillation mode and test the delay time. First, test the clock delay circuit, giving it an initial state T1:
[0066] CK_DLY_SEL=00000fffff, CK_SH_LOOP_SEL=1, CK_SH_OSC_EN=0, CK_EDGE_SW=1. To ensure initial stability, set CK_SH_OSC_EN=1 and adjust the delay circuit to oscillation mode T2. It is recommended that T2 and T1 be spaced 10ns apart. After a sufficiently long time, such as 200ns, record the output CK_OSC_OUT of the delay circuit. Then, the delay time of the clock transmission path CK_delay=Period(CK_OSC_OUT) / 2.
[0067] Next, similarly, for the test data delay circuit, first give the delay circuit an initial state T1:
[0068] D_DLY_SEL=000003ffff, which is the recorded critical value. D_SH_LOOP_SEL=1, D_SH_OSC_EN=0, D_EDGE_SW=1. To ensure initial stability, set D_SH_OSC_EN=1 and adjust the delay circuit to oscillation mode T2. It is recommended that T2 and T1 be spaced 10ns apart. After a sufficiently long time, such as 200ns, record the output D_OSC_OUT of the delay circuit. Then, the delay time of the data transmission path D_delay_min=Period(D_OSC_OUT) / 2.
[0069] Next, measure the previous state, i.e., the critical value before hold0 expires. D_DLY_SEL is taken as the value before 000003ffff: 000007ffff. D_SH_LOOP_SEL=1, D_SH_OSC_EN=0, D_EDGE_SW=1. To ensure the initial state is stable, set D_SH_OSC_EN=1 and adjust the delay circuit to oscillation mode T2. It is recommended that T2 and T1 be spaced 10ns apart. After a sufficiently long time, such as 200ns, record the delay circuit output D_OSC_OUT. Then, the data transmission path delay time D_delay_max=Period(D_OSC_OUT) / 2; and...
[0070] Finally, the test is complete, and hold_rise_time is calculated using the following formula:
[0071] hold_rise_time_max=D_delay_max - CK_delay
[0072] hold_rise_time_min=D_delay_min - CK_delay.
[0073] It should be understood that, as mentioned above, the initial value of CK_DLY_SEL and the changes in D_DLY_SEL each time are not limited to the methods described above. The initial value and step can be set according to actual needs. Furthermore, the testing methods for falling edge hold time, setup time, etc., as well as the testing of other types of registers, can be performed with reference to the above description. Only the corresponding control signal values need to be adjusted appropriately according to the time to be tested and / or the register type. For example, to test hold_rise_time, the rising edge signal of the data needs to arrive at the register input later than the rising edge signal of the clock, and then the time difference between the two is gradually reduced to find the critical point where hold0 fails. To test falling edge hold time, the falling edge signal of the data needs to arrive at the register input later than the falling edge signal of the clock, and then the time difference between the two is gradually reduced to find the critical point where hold1 fails. To test setup time, the valid edge signal of the data needs to arrive at the register input earlier than the valid edge signal of the clock, and then the time difference between the two is gradually reduced to find the critical point. The specific settings of the control signal values will not be elaborated again.
[0074] As described above, the test method only requires two delay chains and one register under test. The test circuit structure can be used to test the setup time of the register and the hold time. It occupies a small area, has high measurement accuracy, and is controllable.
[0075] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.
Claims
1. A delay circuit, characterized in that, include: A first selector, wherein a first data input terminal is connected to a first enable signal, the first enable signal being configured as the input signal of the delay circuit in input mode; A number of time delay units connected in series are connected to the output of the first selector; The NAND gate has its first input connected to the output of the last stage delay unit and its second input connected to the second enable signal. The second selector has its selection control terminal connected to the output terminal of the NAND gate, its first data input terminal and second data input terminal connected through a first inverter, and its output terminal connected to the second data input terminal of the first selector through a second inverter. as well as A third inverter is connected to the output of the second selector and is configured to output the output signal of the delay circuit.
2. The delay circuit as described in claim 1, characterized in that, The delay unit includes a third selector, wherein the first data input terminal of the third selector is connected to the input signal, and the second data input terminal is connected to the input signal through a buffer.
3. A test circuit for register setup time and hold time, characterized in that, include: An input buffer whose input is connected to the test vector; A data delay circuit, employing the delay circuit described in claim 1 or 2, wherein its input terminal is connected to the output terminal of the input buffer, and its output terminal is connected to the data input terminal of the register under test; and The clock delay circuit adopts the delay circuit as described in claim 1 or 2, and its input terminal is connected to the output terminal of the input buffer, and its output terminal is connected to the clock terminal of the register under test.
4. The test circuit as described in claim 3, characterized in that, Also includes: The frequency divider and counting circuit is located between the data delay circuit and the data input terminal of the register, and between the clock delay circuit and the clock terminal of the register.
5. A method for testing register setup time and hold time, characterized in that, The test circuit described in claim 3 is used to test the register setup time and hold time, and includes: By controlling the data delay circuit and clock delay circuit in the test circuit, the critical control signal value when the register under test flips is determined; The delays of the data delay circuit and the clock delay circuit are determined based on the critical control signal value; and The setup time and / or hold time of the register under test are determined based on the delay of the data delay circuit and the clock delay circuit.
6. The test method as described in claim 5, characterized in that, The critical control signal values for determining when the register under test flips include: During setup testing, the data delay circuit and clock delay circuit are controlled to ensure that the clock transmission delay is greater than the data transmission delay. Then, the delay difference between the data delay circuit and clock delay circuit is gradually reduced. The control signal values of the clock delay circuit and data delay circuit at the first register output flip are recorded; these are the critical control signal values at the flip of the register under test. During the hold time test, the data delay circuit and clock delay circuit are controlled to make the data transmission delay greater than the clock transmission delay. Then, the delay difference between the data delay circuit and clock delay circuit is gradually reduced, and the control signal values of the data delay circuit and clock delay circuit at the first flip of the register output are recorded. These control signal values are the critical control signal values when the register under test flips.
7. The test method as described in claim 5, characterized in that, The delay of the data delay circuit and the clock delay circuit is determined based on the critical control signal value, including: The clock delay circuit is set to the critical control signal value and set to oscillation mode. After a specified duration, the output value of the clock delay circuit is recorded, and the delay of the clock delay circuit is determined based on the output value; and The data delay circuit is set to the critical control signal value and set to oscillation mode. After a specified time, the output value of the data delay circuit is recorded, and the delay of the data delay circuit is determined based on the output value.
8. The test method as described in claim 5, characterized in that, Also includes: During setup testing, before determining the critical control signal value for the register under test toggling, the data delay circuit and clock delay circuit are controlled to ensure that the clock transmission delay is less than the data transmission delay, thus triggering a register toggle. When testing the hold time, before determining the critical control signal value when the register under test flips, the data delay circuit and clock delay circuit are controlled to make the clock transmission delay greater than the data transmission delay, and the register is triggered to flip once.