Data caching device

Abstract

The invention discloses a data caching device, and belongs to the technical field of data caching. The invention aims to solve the problems of data loss, high delay and low resource utilization rate in a multi-port and burst data stream scene caused by fixed bandwidth allocation and static memory management of the existing cache device. Therefore, the device comprises a self-allocation dynamic flow control module which selects an arbiter to detect a port by circularly inputting the highest bit of data, and dynamically allocates bandwidth according to the real-time working intensity of the port to realize flow balance; and the improved consistent Hash memory space management module adopts a two-stage Hash ring structure with three-stage permission of'child node-main node-main storage 'to realize dynamic allocation and instant recovery by package of the memory space. The method is implemented in the FPGA and supports 16 parallel ports, the bandwidth of each port is 16 Gbps, and the high efficiency and reliability of water pump axial force detection data caching are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of data caching technology, and in particular to a data caching device for high-concurrency, bursty data streams. Background Technology

[0002] In transmission systems, multi-sensor data is input in parallel through multiple ports, requiring real-time buffering and processing. Existing data buffering devices mostly employ fixed bandwidth allocation or simple buffering strategies, which cannot cope with situations such as multi-port parallel read / write, rapid increases in data flow, and space requirement coordination, resulting in data loss, high latency, or low resource utilization. Traditional buffering devices lack flexible flow control mechanisms, failing to dynamically adjust bandwidth based on the actual operating status of each port; memory management strategies are inefficient, making it difficult to achieve efficient space utilization and rapid space reclamation. FPGAs, as programmable logic devices, are suitable for implementing high-performance data buffers, but existing FPGA buffer designs have significant shortcomings in dynamic resource allocation. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of this invention is to provide a data caching device that achieves efficient and reliable multi-port data caching in an FPGA through self-allocation dynamic flow control and improved consistent hash memory management.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A data caching device, comprising: The self-allocation dynamic flow control module connects to a multi-port data input interface and is used to dynamically allocate transmission bandwidth based on the working intensity of each port to achieve traffic balancing for out-of-order and bursty data packets. The improved consistent hash memory space management module is connected to the self-allocated dynamic flow control module and uses a two-level hash ring structure to realize dynamic memory space allocation and reclamation. The architecture is implemented using an FPGA, integrating the above modules into the FPGA chip.

[0005] Furthermore, the improved consistent hash memory space management module is connected to the self-allocated dynamic flow control module, and in terms of hardware configuration, it integrates a hash mapping engine, a multi-level node status table, a dynamic linked list controller, and a physical SRAM array pre-divided into multiple fixed-size storage micro-blocks. The hash mapping engine first locks the master node and child node registers in the first-level and second-level hash ring state tables according to the port number and priority of the input data. When a child node requests storage, the dynamic linked list controller extracts the address of a free micro-block from the global free block index pool, writes it to the tail pointer field of the current block, and concatenates the storage space in the form of a hardware linked list. The limit counter in the node state table controls the maximum number of micro-blocks concatenated in a single queue to support a maximum space of 4Mbit. If the space of the current node is exhausted, the controller borrows a free micro-block from the adjacent master node according to the clockwise logic of the hash ring, and immediately clears the pointer after the data is read, pushing the micro-block back to the free pool to achieve real-time reclamation per packet. It supports a maximum of 4Mbit of dynamic shared cache space per queue.

[0006] Furthermore, the self-allocation dynamic flow control module adopts a four-stage pipeline architecture in terms of timing and is physically divided into three parts: an input channel unit, a flow arbitration unit, and an output channel unit. The input channel distributes the input data from the source port to the subsequent flow arbiter through a pipeline; the flow arbiter allocates the flow of the input data by selecting the arbiter using the most significant bit in a loop; the output channel unit realizes the automatic reassembly of out-of-order data through a hardware-level 'label-address mapping' mechanism, solving the problem of accurate location of out-of-order data. The self-allocated dynamic flow control module parses and processes control frames through the input channel, and quickly parses the flow load by simplifying the data packet structure.

[0007] Furthermore, the system clock is set to 200MHz, employing a time-division multiplexing (TDM) polling mechanism. The traffic arbitrator internally contains a 16-bit status register corresponding to 16 physical ports. Within one working cycle (defined as 16 system clock cycles), the arbitrator sequentially scans the request lines of the 16 ports via a state machine (FSM). If a port has a request and is authorized, data is immediately latched on that clock edge; otherwise, it is skipped. This single-cycle, single-port polling design ensures that all 16 ports have an independent data transmission window within a complete 16-clock cycle, thus achieving full port coverage.

[0008] Furthermore, the data packet structure includes a control frame containing destination port, priority, and length information.

[0009] Furthermore, the improved consistent hashing memory space management module adopts a three-level storage permission structure of "child node-master node-main storage". Child nodes correspond to port priorities and form an 8-node two-level hash ring; master nodes correspond to ports and form a 16-node one-level hash ring; the main storage is physical SRAM space, including 32 data SRAM blocks with a total capacity of 8Mbit. When data is written, after finding the target child node through the above two-level mapping, the module immediately checks the SRAM block status in the mapping table of that child node. If the current SRAM block is not full, the data is written directly; if the block is full, the control logic triggers the loop overflow mechanism, searches for free SRAM blocks under the adjacent master node clockwise along the first-level hash ring, and updates the address mapping table to establish a temporary borrowing relationship, thereby realizing dynamic space allocation across ports.

[0010] When data enters from any port, it first searches for a storage location in the secondary hash ring. When the secondary hash ring is full, it backtracks to the primary hash ring and then searches for a location in the secondary hash ring of the next port in a clockwise direction.

[0011] Furthermore, the FPGA implementation architecture is based on the ZYNQ 7000 series FPGA chip (such as XC7Z035) and implemented using the Verilog hardware description language. FPGA resources include 275K on-chip logic units, 171900 lookup tables, 343800 flip-flops, 17.6Mb of block RAM, and 900 multipliers. The system master clock can reach over 200MHz through synthesis constraints, and it supports 16-port parallel read / write.

[0012] The technical solution adopted in this invention has the following beneficial effects: 1. Through a self-allocated dynamic flow control module, priority and load information from requests on each port are extracted in real time. A mask is dynamically generated to skip idle ports and prioritize high-load ports. This, combined with the 'serial number-address' hardware mapping mechanism of the output channel, enables the physical reassembly of out-of-order data. This ensures that the system can effectively handle sudden data flows and minimizes time slot waste.

[0013] 2. By using an improved consistent hashing algorithm, a three-level storage permission structure of "child node-master node-master storage" is formed, which significantly reduces the complexity of dynamic space allocation arbitration, thereby improving system stability while reducing system resource overhead. 3. Achieve a single-queue dynamic space of up to 4Mbit, maximizing space utilization while ensuring data transmission; 4. Implemented in FPGA, utilizing hardware parallelism, it supports 16 parallel ports working, with each port having a maximum data transmission bandwidth of 16Gbps, meeting the real-time requirements of data transmission. Attached Figure Description

[0014] Figure 1 The system architecture diagram of the data caching device provided by the present invention; Figure 2 The flowchart of the self-allocation dynamic flow control module provided by the present invention; Figure 3A schematic diagram of the improved consistent hashing memory space management provided by the present invention; Figure 4 This is a schematic diagram of the internal structure of the virtual channel group provided by the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0016] like Figure 1 As shown, this invention provides a data caching device, mainly comprising a multi-port data input interface, a self-allocated dynamic flow control module, and an improved consistent hash memory space management module. The multi-port data input interface receives data packets from sensors, each data packet including a control frame and a data frame. A control frame decoder parses the control frame, extracting destination port, priority, and length information. A data distributor encodes the data packets based on the control frame information to determine the transmission path.

[0017] The self-allocated dynamic flow control module is implemented through virtual channel groups, employing a four-stage pipeline architecture. The specific correspondence between this pipeline process and the physical hardware modules is as follows: The input channel unit performs the first two stages of the pipeline, "receiving data" and "parsing encoding." It first parallelizes and buffers the serial data from the source port, then extracts the destination port and priority information from the control frame using an internal frame parser. The flow arbitration unit performs the third stage of the pipeline, "channel concatenation," controlling the crossbar switch matrix to establish a physical data path from the input to the destination storage based on the parsed information. The flow arbitration unit and the output channel unit collaborate to perform the fourth stage of the pipeline, "arbitration transmission." The flow arbitration unit uses a cyclic most significant bit selector (CMSB) arbitrator to generate a dynamic mask to allocate bandwidth to each port and sends a transmission enable signal to the output channel. This architecture ensures that while continuously maintaining the transmission channel, it completes one round of polling for all working ports within one working cycle (16 system clock cycles), guaranteeing data transmission from all ports.

[0018] The improved consistent hashing memory space management module employs a two-level hash ring structure. For example... Figure 3 As shown, the system supports simultaneous read and write operations on 16 ports. Each port is designated as a primary storage device, forming a 16-node primary hash ring. The eight priority levels of each port form an 8-node secondary hash ring. When data enters from any port, it first searches for a storage location in the secondary hash ring. If the secondary hash ring is full, it falls back to the primary hash ring. Space allocation is managed through a hash ring index table, supporting real-time reclamation per packet.

[0019] like Figure 4As shown, the internal structure of the virtual channel group includes an input channel, a traffic arbitrator, and an output channel. The input channel distributes data to the corresponding arbitrator module through a pipelined design; the traffic arbitrator handles all concurrent requests and transmits data to the transmission port in real time according to a dynamic transmission right replacement strategy; the output channel accurately locates the relationship between data and data packets through the encoding of the current data and control signals.

[0020] In practice, the entire device is implemented in an FPGA chip, utilizing on-chip logic units, lookup tables, flip-flops, and block RAM resources. The system main clock is constrained to over 200MHz, supporting 16-port parallel operation with a bandwidth of up to 16Gbps per port and a maximum of 4Mbit for a single-queue dynamic shared cache space.

[0021] In practical implementation, this device can be built based on Xilinx Zynq-7000 series FPGA chips (such as XC7Z035), with the system clock constrained to 200MHz, and utilizes on-chip logic and block RAM resources to work together. When the sensor connected to port 03 acquires an instantaneous peak value of "4500N" (corresponding to binary payload 0x1194), its interface will generate a data packet with a header control frame of 0x3200_0008 (indicating destination port ID=3, high priority, length 8 bytes). The input channel latches and parses the frame in the first clock cycle, and the CMSB algorithm of the traffic arbitrator identifies the high-priority request and issues an authorization signal in the second clock cycle. Subsequently, the improved consistent hashing module intervenes in the third clock cycle, locates "master node-3" in the first-level hash ring based on the port ID, and locks "child node-A" in the second-level hash ring based on the priority. After checking, the physical SRAM block-12 bound to it is still free (current write pointer 0x0C00_0020). Finally, in the fourth clock cycle, the data payload 0x1194 is directly written to this physical address, realizing zero-latency efficient caching of burst data.

[0022] This invention innovatively integrates a "three-level permission, two-level hash ring" memory management architecture with a "self-allocation dynamic flow control" mechanism, solving resource bottlenecks in multi-port high-concurrency scenarios. It applies distributed consistent hashing theory to FPGA hardware caching, achieving deep integration of port priority and memory allocation through a "child node-master node-main storage" structure. This supports dynamic overflow rollback and instant reclamation per packet, completely eliminating the arbitration bottleneck of traditional linked list management. Combined with a circular highest-bit selection arbitrator, it ensures real-time load balancing across 16 16Gbps ports at a 650MHz clock frequency, achieving zero-loss, high-efficiency caching for massive bursts of data.

[0023] This invention improves data caching efficiency and system reliability through efficient flow control and memory management.

Claims

1. A data caching device, characterized in that... include: The self-allocation dynamic flow control module connects to a multi-port data input interface and is used to dynamically allocate transmission bandwidth based on the working intensity of each port to achieve traffic balancing for out-of-order and bursty data packets. The improved consistent hash memory space management module is connected to the self-allocated dynamic flow control module and uses a two-level hash ring structure to realize dynamic memory space allocation and reclamation. The architecture is implemented using an FPGA, integrating the above modules into the FPGA chip.

2. The data caching device according to claim 1, characterized in that... The improved consistent hash memory space management module is connected to the self-allocated dynamic flow control module, and in terms of hardware configuration, it integrates a hash mapping engine, a multi-level node status table, a dynamic linked list controller, and a physical SRAM array pre-divided into multiple fixed-size storage micro-blocks. The hash mapping engine first locks the master node and child node registers in the first-level and second-level hash ring state tables according to the port number and priority of the input data. When a child node requests storage, the dynamic linked list controller extracts the address of a free micro-block from the global free block index pool, writes it to the tail pointer field of the current block, and connects the storage space in the form of a hardware linked list. The limit counter in the node state table controls the maximum number of micro-blocks connected in a single queue to support a maximum space of 4Mbit. If the space of the current node is exhausted, the controller borrows a free micro-block from the adjacent master node according to the clockwise logic of the hash ring, and immediately clears the pointer after the data is read and pushes the micro-block back to the free pool, realizing real-time reclamation per packet. It supports a maximum dynamic shared cache space of 4Mbit for a single queue.

3. The data caching device according to claim 1, characterized in that... The self-allocation dynamic flow control module adopts a four-stage pipeline architecture in terms of timing and is physically divided into three parts: an input channel unit, a flow arbitration unit, and an output channel unit. The input channel distributes the input data from the source port to the subsequent flow arbiter through a pipeline; the flow arbiter allocates the flow of the input data by selecting the arbiter using the most significant bit in a loop; the output channel unit realizes the automatic reassembly of out-of-order data through a hardware-level 'label-address mapping' mechanism, solving the problem of accurate location of out-of-order data. The self-allocated dynamic flow control module parses and processes control frames through the input channel, and quickly parses the flow load by simplifying the data packet structure.

4. The data caching device according to claim 1, characterized in that... The system clock is set to 200MHz and uses a time-division multiplexing polling mechanism. The traffic arbitrator contains a 16-bit status register corresponding to 16 physical ports. In one working cycle, the arbitrator scans the request lines of the 16 ports sequentially through the state machine. If a port has a request and is authorized, the data is immediately latched on the clock edge; otherwise, it is skipped. This single-cycle, single-port polling design ensures that all 16 ports have an independent data transmission window within the complete 16 clock cycles, thereby achieving full port coverage.

5. The data caching device according to claim 1, characterized in that... The data packet structure includes a control frame containing destination port, priority, and length information.

6. The data caching device according to claim 1, characterized in that... The improved consistent hash memory space management module adopts a three-level storage permission structure of "child node-master node-main storage"; the child nodes correspond to the port priority and form an 8-node two-level hash ring; the master nodes correspond to the ports and form a 16-node one-level hash ring; the main storage is physical SRAM space, including 32 data SRAM blocks with a total capacity of 8Mbit. When data is written, after finding the target child node through the above two-level mapping, the module immediately checks the SRAM block status in the mapping table of that child node; if the current SRAM block is not full, the data is written directly. If the block is full, the control logic triggers the loop overflow mechanism, searches for free SRAM blocks under the adjacent master node clockwise along the first-level hash ring, and updates the address mapping table to establish a temporary borrowing relationship, thereby realizing dynamic space allocation across ports. When data enters from any port, it first searches for a storage location in the secondary hash ring. When the secondary hash ring is full, it backtracks to the primary hash ring and then searches for a location in the secondary hash ring of the next port in a clockwise direction.

7. The data caching device according to claim 1, characterized in that... The FPGA implementation architecture is based on the ZYNQ7000 series FPGA chip and implemented using the Verilog hardware description language. The FPGA resources include 275K on-chip logic units, 171900 lookup tables, 343800 flip-flops, 17.6Mb of block RAM, and 900 multipliers. The system master clock can reach more than 200MHz through synthesis constraints and supports 16-port parallel read and write.

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