Memory cell of SONOS memory and manufacturing method thereof
By designing a select transistor and four gate-structured memory transistors in the SONOS memory, the problem of large area in traditional SONOS memory was solved, achieving improved storage density and cost savings.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional SONOS memory has a large storage cell area and low storage density.
A SONOS memory cell design is adopted, which includes a select transistor and four memory transistors evenly distributed on both sides of the select transistor. The four memory transistors are distributed in a gate structure and are fabricated by a self-aligned process to form the gate and isolation layer of the memory transistors.
It significantly reduces the area of storage cells, increases storage density, and improves the uniformity of storage tubes, while saving on manufacturing costs.
Smart Images
Figure CN121968591A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a SONOS memory cell and its manufacturing method. Background Technology
[0002] Non-volatile memory (NVM) is an essential storage device in computers, playing a crucial role in storing the processed information. Among NVMs, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory is widely used due to its advantages such as low operating voltage, high reliability, simple process, and low manufacturing cost. Traditional SONOS memory cells consist of a SONOS transistor and a select transistor, resulting in a relatively large cell area. Summary of the Invention
[0003] The purpose of this invention is to provide a storage cell for a SONOS memory and a method for manufacturing the same. The storage cell includes a select transistor and four storage transistors evenly distributed on both sides of the select transistor. The four storage transistors are distributed on both sides of the select transistor in a grid structure, which can significantly reduce the storage area and increase the storage density.
[0004] To achieve the above objectives, the present invention provides a storage unit for a SONOS memory, the storage unit comprising:
[0005] Substrate and storage tube trap located on said substrate;
[0006] The memory gate and the select gate are located on the memory tube well;
[0007] The gate of the memory transistor includes a first gate, a second gate, a third gate, and a fourth gate. The first gate and the second gate are located in a groove in the storage medium layer. An isolation layer is formed between the first gate and the second gate. Isolation oxide layers are formed on both sides of the groove. A sidewall is formed on one side of the isolation oxide layer of the first gate. The select gate is located on one side of the isolation oxide layer of the second gate.
[0008] Similar to the arrangement of the first gate and the second gate of the memory transistor, the third gate and the fourth gate of the memory transistor are symmetrically distributed on the other side of the gate of the select transistor;
[0009] The threshold voltage adjustment region of the storage tube is located below the surface of the storage tube trap and is positioned below the storage medium layer and the isolation oxide layer.
[0010] The lightly doped source / drain regions are located below the surface of the memory trap, below the isolation layer and the sidewalls; and,
[0011] The source / drain region is located below the surface of the storage tube and is positioned between the two storage cells.
[0012] Optionally, a gate oxide layer is also included, located between the select gate, the isolation oxide layer, the sidewall, and the substrate.
[0013] Optionally, the lightly doped source / drain regions located under the isolation layer isolate the threshold voltage adjustment region of the memory transistor.
[0014] Optionally, the first gate and the second gate of the memory transistor are symmetrically distributed about the isolation layer.
[0015] Optionally, the storage medium layer is an ONO structure.
[0016] Accordingly, the present invention also provides a method for manufacturing a storage cell of a SONOS memory, comprising:
[0017] A substrate is provided for memory trap implantation, and a gate oxide layer and a first polysilicon layer are formed on the surface of the substrate.
[0018] The first polysilicon layer is etched, and a threshold voltage adjustment injection is performed to form a threshold voltage adjustment region for the memory tube below the surface of the memory tube well in the etched area of the first polysilicon layer.
[0019] An isolation oxide layer is formed on the surface of the substrate, the isolation oxide layer covering the first polysilicon layer and the gate oxide layer;
[0020] Self-aligned etching of the isolation oxide layer and the gate oxide layer until the substrate is exposed;
[0021] A storage medium layer is formed on the surface of the substrate, the storage medium layer covering the first polysilicon layer, the sidewalls of the isolation oxide layer and the exposed substrate, and two upward-facing grooves of the storage medium layer are formed on the surface of the substrate.
[0022] A second polysilicon layer is formed on the storage medium layer;
[0023] The second polysilicon layer is self-aligned and etched to form the gate of the memory transistor. The gate of the memory transistor includes a first gate, a second gate, a third gate, and a fourth gate. The first gate, the second gate, the third gate, and the fourth gate are uniformly distributed in the two grooves of the storage medium layer. A gate gap exposing the storage medium layer is formed between the first gate and the second gate, and between the third gate and the fourth gate.
[0024] Etch the storage dielectric layer and the first polysilicon layer outside the isolation oxide layer corresponding to the first gate and the fourth gate of the memory transistor, and form a select gate between the second gate and the third gate of the memory transistor;
[0025] Lightly doped source / drain implantation is performed to form a lightly doped source / drain region beneath the surface of the memory well in the etched region of the memory dielectric layer and the first polysilicon layer; and...
[0026] A sidewall is formed on one side of the isolation oxide layer of the first gate and the fourth gate of the memory transistor, and source / drain injection is performed using the sidewall as a mask to form a source / drain region.
[0027] Optionally, while forming the sidewall, the sidewall material simultaneously fills the gate gap of the memory cell to form an isolation layer.
[0028] Optionally, the lightly doped source / drain regions are located below the isolation layer and the sidewalls.
[0029] Optionally, it also includes: removing part of the storage medium layer after forming the source / drain region to expose the select transistor gate.
[0030] Optionally, the storage medium layer has an ONO structure and a thickness of 90 Å-160 Å.
[0031] Optionally, the thickness of the gate oxide layer is 60 Å-120 Å, and the thickness of the first polycrystalline silicon layer is 600 Å-2000 Å.
[0032] Optionally, the thickness of the insulating oxide layer is 60 Å-300 Å.
[0033] Optionally, the thickness of the second polycrystalline silicon layer is 500 Å-1000 Å.
[0034] In summary, this invention provides a storage cell for a SONOS memory and a method for manufacturing the same. The storage cell includes a select transistor and four storage transistors evenly distributed on both sides of the select transistor. The four storage transistors are arranged in a grid-like structure on both sides of the select transistor, which can significantly reduce the storage area and increase the storage density. Furthermore, in the method for manufacturing the storage cell, the four storage transistors are fabricated using a self-aligned process, which can improve the uniformity of the storage transistors and save on manufacturing costs. Attached Figure Description
[0035] Figure 1 A schematic flowchart illustrating the manufacturing method of a storage cell of a SONOS memory provided in an embodiment of the present invention;
[0036] Figures 2 to 11 This is a schematic diagram of the structure of each step in the manufacturing method of the storage cell of the SONOS memory provided in an embodiment of the present invention.
[0037] The reference numerals in the attached figures are explained as follows:
[0038] 1-Substrate; 2-Memory tube trap; 3-Gate oxide layer; 4'-First polysilicon layer; 4-Selector gate; 5-Memory tube threshold voltage adjustment region; 6-Isolation oxide layer; 7-Memory dielectric layer; 8'-Second polysilicon layer; 8-Memory tube gate; 9-Source / drain lightly doped region; 10-Sidewall; 11-Source / drain region; 12-Groove of the storage dielectric layer; 13-Memory tube gate gap; 14-Photoresist layer; 15-Isolation layer. Detailed Implementation
[0039] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.
[0040] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.
[0041] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.
[0042] The present invention also provides a storage unit for a SONOS memory, such as... Figure 11 As shown, the storage unit includes:
[0043] Substrate 1 and storage tube 2 located on the substrate;
[0044] The storage tube gate 8 and the select tube gate 4 are located on the storage tube trap 2;
[0045] The gate of the memory transistor 8 includes a first gate 81, a second gate 82, a third gate 83, and a fourth gate 84. The first gate 81 and the second gate 82 are located in the groove of the storage medium layer 7. An isolation layer 15 is formed between the first gate 81 and the second gate 82. Isolation oxide layers 6 are formed on both sides of the groove of the storage medium layer 7. A sidewall 10 is formed on one side of the isolation oxide layer 6 of the first gate 81.
[0046] The selector gate 4 is located on one side of the isolation oxide layer 6 of the second gate 82 of the memory tube;
[0047] Similar to the arrangement of the first gate 81 and the second gate 82 of the memory tube, the third gate 83 and the fourth gate 84 of the memory tube are symmetrically distributed on the other side of the select tube gate 4;
[0048] The storage tube threshold voltage adjustment region 5 is located below the surface of the storage tube trap 2, and is positioned below the storage medium layer 7 and the isolation oxide layer 6;
[0049] The lightly doped source / drain regions 9 are located below the surface of the storage trap 2, below the isolation layer 15 and the sidewall 10; and,
[0050] The source / drain region 11 is located below the surface of the storage trap 2 and is positioned between the two storage cells.
[0051] Furthermore, the SONOS memory cell also includes a gate oxide layer 3, located between the select transistor gate 4, the isolation oxide layer 6, the sidewall 10, and the substrate 1.
[0052] Furthermore, the first gate 81 and the second gate 82 of the storage tube are symmetrically distributed about the isolation layer 15.
[0053] Furthermore, the lightly doped source / drain regions 9 located under the isolation layer 15 isolate the threshold voltage adjustment region 5 of the memory tube.
[0054] Furthermore, the storage medium layer 7 is an ONO structure and serves as an ONO charge storage layer.
[0055] In the SONOS memory cell provided by this invention, the four gates of the storage transistor gate 8 are symmetrically distributed on both sides of the select transistor gate 4. That is, the memory cell includes one select transistor and four storage transistors evenly distributed on both sides of the select transistor. Compared with the traditional SONOS memory cell consisting of one storage transistor and one select transistor, the SONOS memory cell provided by this invention has four storage transistors distributed in a gate-splitting structure on both sides of the select transistor, which can significantly reduce the storage area and increase the storage density.
[0056] The present invention also provides a method for manufacturing a storage cell of a SONOS memory. Figure 1 A method for manufacturing a storage cell of a SONOS memory, as provided in an embodiment of the present invention, is as follows: Figure 1 As shown, the manufacturing method of the storage cell of the SONOS memory provided in this embodiment includes the following steps:
[0057] Step S01: Provide a substrate, perform memory trap implantation, and form a gate oxide layer and a first polysilicon layer on the surface of the substrate;
[0058] Step S02: Etch the first polysilicon layer and perform threshold voltage adjustment injection of the memory tube to form a threshold voltage adjustment region of the memory tube below the surface of the memory tube well in the etched area of the first polysilicon layer.
[0059] Step S03: An isolation oxide layer is formed on the surface of the substrate, the isolation oxide layer covering the first polysilicon layer and the gate oxide layer;
[0060] Step S04: Self-aligned etching of the isolation oxide layer and the gate oxide layer until the substrate is exposed;
[0061] Step S05: A storage medium layer is formed on the surface of the substrate, the storage medium layer covering the first polysilicon layer, the sidewall of the isolation oxide layer and the exposed substrate, and two upward-facing grooves of the storage medium layer are formed on the surface of the substrate.
[0062] Step S06: Form a second polysilicon layer on the storage medium layer;
[0063] Step S07: Self-aligned etching of the second polysilicon layer to form the gate of the memory transistor. The gate of the memory transistor includes a first gate, a second gate, a third gate, and a fourth gate. The first gate, the second gate, the third gate, and the fourth gate are uniformly distributed in the grooves of the two memory dielectric layers. A gate gap exposing the memory dielectric layer is formed between the first gate and the second gate, and between the third gate and the fourth gate.
[0064] Step S08: Etch the storage dielectric layer and the first polysilicon layer outside the isolation oxide layer corresponding to the first gate and the fourth gate of the memory transistor, and form a select gate between the second gate and the third gate of the memory transistor;
[0065] Step S09: Perform source / drain light doping implantation to form a source / drain light doped region below the surface of the memory well in the etched region of the memory dielectric layer and the first polysilicon layer; and,
[0066] Step S10: A sidewall is formed on one side of the isolation oxide layer of the first gate and the fourth gate of the memory transistor, and source / drain injection is performed using the sidewall as a mask to form a source / drain region.
[0067] Figures 2 to 11 This is a schematic diagram illustrating the structural steps of a method for manufacturing a storage cell of a SONOS memory according to an embodiment of the present invention. Please refer to... Figure 1 As shown, and in combination Figures 2 to 11 This invention provides a detailed description of the manufacturing method of the storage cell of the SONOS memory provided by the present invention. Figures 2 to 11 The diagram illustrates the manufacturing process of two adjacent memory cells as an example.
[0068] First, refer to Figure 2 As shown, in step S01, a substrate 1 is provided, and a memory trap 2 is implanted, forming a gate oxide layer 3 and a first polysilicon layer 4' on the surface of the substrate 1. The gate oxide layer 3 is a select transistor oxide layer, and the first polysilicon layer 4' is a select transistor polysilicon layer. The thickness of the gate oxide layer 3 is 60 Å-120 Å, and the thickness of the first polysilicon layer 4' is 600 Å-2000 Å.
[0069] The substrate 1 can be single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC), or it can be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 1 is only used as an example of a silicon substrate, and this is just an example. The present invention is not limited thereto.
[0070] Next, refer to Figure 3 As shown, in step S02, the first polysilicon layer 4' is etched, and a threshold voltage adjustment injection of the memory tube is performed to form a threshold voltage adjustment region 5 below the surface of the memory tube well 2 in the etched area of the first polysilicon layer 4'.
[0071] Next, refer to Figure 4 and Figure 5 As shown, steps S03 and S04 are performed to form an isolation oxide layer 6 on the surface of the substrate 1. The isolation oxide layer 6 covers the first polysilicon layer 4' and the gate oxide layer 3. Then, the isolation oxide layer 6 and the gate oxide layer 3 are self-aligned and etched until the substrate 1 is exposed. For example, dry etching and wet etching can be used to etch the isolation oxide layer 6 and the gate oxide layer 3 to expose the threshold voltage adjustment region 5 of the memory transistor, preparing for the subsequent formation of the gate of the memory transistor. The thickness of the isolation oxide layer 6 is 60 Å-300 Å.
[0072] Next, refer to Figure 6 As shown, in step S05, a storage dielectric layer 7 is formed on the surface of the substrate 1. The storage dielectric layer 7 covers the sidewalls of the first polysilicon layer 4, the isolation oxide layer 6, and the exposed substrate 1. Two upward-facing grooves 12 of the storage dielectric layer 7 are formed on the surface of the substrate 1. The storage dielectric layer 7 is an ONO charge storage layer, employing an ONO stacked structure. The thickness of the storage dielectric layer 7 is 90 Å - 160 Å, such as 120 Å or 140 Å.
[0073] Next, refer to Figure 7 and Figure 8As shown, steps S06 and S07 are performed to form a second polysilicon layer 8' on the storage medium layer 7. The second polysilicon layer 8' is then self-aligned and etched to form a memory gate 8. The memory gate 8 includes a first gate 81, a second gate 82, a third gate 83, and a fourth gate 84. The first gate 81, the second gate 82, the third gate 83, and the fourth gate 84 are uniformly distributed within the grooves 12 of the two storage medium layers 7. Gate gaps 13 exposing the storage medium layer 7 are formed between the first gate 81 and the second gate 82, and between the third gate 83 and the fourth gate 84. The second polysilicon layer 8' is a memory polysilicon layer, and its thickness determines the channel length of the memory. The thickness of the second polysilicon layer 8' is 500 Å-1000 Å, for example, 600 Å or 800 Å.
[0074] Next, refer to Figure 9 As shown, in step S08, the storage medium layer 7 and the first polysilicon layer 4' on the outside of the isolation oxide layer 6 corresponding to the first gate 81 and the fourth gate 84 of the storage tube are etched, and the select gate 4 is formed between the second gate 82 and the third gate 83 of the storage tube.
[0075] In steps S04 and S07 above, the etching of the isolation oxide layer 6, the gate oxide layer 3 and the second polysilicon layer 8' adopts a self-aligned process, which can improve the uniformity of the memory tube and save on process production costs.
[0076] Unlike the self-aligned etching process in steps S04 and S07 above, in this step, the redundant storage medium layer 7 and the first polysilicon layer 4' are etched using a photomask. Specifically, a photoresist layer 14 is formed on the substrate 1, and the photoresist layer 14 is patterned so that the patterned photoresist layer 14 covers the select transistor and storage transistor regions in the memory cell. Then, using the patterned photoresist layer 14 as a mask, the storage medium layer 7 and the first polysilicon layer 4' outside the isolation oxide layer 6 are etched to define the memory cell region.
[0077] Next, refer to Figure 10 As shown, step S09 is performed to implant lightly doped source and drain regions, forming lightly doped source and drain regions 9 below the surface of the storage tube trap in the etched region of the storage medium layer 7 and the first polysilicon layer 4'.
[0078] Next, refer to Figure 11As shown, in step S10, a sidewall 10 is formed on one side of the isolation oxide layer 6 of the first gate 81 and the fourth gate 84 of the memory transistor, and source / drain implantation is performed using the sidewall 10 as a mask to form a source / drain region 11. It should be noted that, simultaneously with the formation of the sidewall 10, the sidewall material filling the sidewall also fills the gate gap 13 of the memory transistor to form an isolation layer 15, isolating the gate of the memory transistor. Correspondingly, the lightly doped source / drain region 9 is located below the isolation layer 15 and the sidewall 10, and the lightly doped source / drain region 9 located under the isolation layer 15 isolates the threshold voltage adjustment region 5 of the memory transistor.
[0079] In other embodiments of the present invention, the method for manufacturing the storage cell of the SONOS memory further includes removing a portion of the storage medium layer 7 after forming the source-drain region 11 to expose the select transistor gate 4.
[0080] In summary, this invention provides a memory cell for a SONOS memory and a method for manufacturing the same. The memory cell includes a select transistor and four memory transistors evenly distributed on both sides of the select transistor. The four memory transistors are distributed in a grid-like structure on both sides of the select transistor, which can significantly reduce the storage area and increase the storage density. Furthermore, in the method for manufacturing the memory cell, the four memory transistors are fabricated using a self-aligned process, which can improve the uniformity of the memory transistors and save on manufacturing costs.
[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A storage cell of a SONOS memory, characterized in that, The storage unit includes: Substrate and storage tube trap located on said substrate; The memory gate and the select gate are located on the memory tube well; The gate of the memory transistor includes a first gate, a second gate, a third gate, and a fourth gate. The first gate and the second gate are located in a groove in the storage medium layer. An isolation layer is formed between the first gate and the second gate. Isolation oxide layers are formed on both sides of the groove. A sidewall is formed on one side of the isolation oxide layer of the first gate. The select gate is located on one side of the isolation oxide layer of the second gate. Similar to the arrangement of the first gate and the second gate of the memory transistor, the third gate and the fourth gate of the memory transistor are symmetrically distributed on the other side of the gate of the select transistor; The threshold voltage adjustment region of the storage tube is located below the surface of the storage tube trap and is positioned below the storage medium layer and the isolation oxide layer. The lightly doped source / drain regions are located below the surface of the memory trap, below the isolation layer and the sidewalls; and, The source / drain region is located below the surface of the storage tube and is positioned between the two storage cells.
2. The storage unit of the SONOS memory according to claim 1, characterized in that, It also includes a gate oxide layer located between the selector gate, the isolation oxide layer, the sidewall, and the substrate.
3. The storage unit of the SONOS memory according to claim 1, characterized in that, The lightly doped source / drain regions located beneath the isolation layer isolate the threshold voltage adjustment region of the memory transistor.
4. The storage unit of the SONOS memory according to claim 1, characterized in that, The first gate and the second gate of the memory transistor are symmetrically distributed about the isolation layer.
5. The storage unit of the SONOS memory according to claim 1, characterized in that, The storage medium layer has an ONO structure.
6. A method for manufacturing a storage cell of a SONOS memory, characterized in that, include: A substrate is provided for memory trap implantation, and a gate oxide layer and a first polysilicon layer are formed on the surface of the substrate. The first polysilicon layer is etched, and a threshold voltage adjustment injection is performed to form a threshold voltage adjustment region for the memory tube below the surface of the memory tube well in the etched area of the first polysilicon layer. An isolation oxide layer is formed on the surface of the substrate, the isolation oxide layer covering the first polysilicon layer and the gate oxide layer; Self-aligned etching of the isolation oxide layer and the gate oxide layer until the substrate is exposed; A storage medium layer is formed on the surface of the substrate, the storage medium layer covering the first polysilicon layer, the sidewalls of the isolation oxide layer and the exposed substrate, and two upward-facing grooves of the storage medium layer are formed on the surface of the substrate. A second polysilicon layer is formed on the storage medium layer; The second polysilicon layer is self-aligned and etched to form the gate of the memory transistor. The gate of the memory transistor includes a first gate, a second gate, a third gate, and a fourth gate. The first gate, the second gate, the third gate, and the fourth gate are uniformly distributed in the grooves of the two memory dielectric layers. A gate gap exposing the memory dielectric layer is formed between the first gate and the second gate, and between the third gate and the fourth gate. Etch the storage dielectric layer and the first polysilicon layer outside the isolation oxide layer corresponding to the first gate and the fourth gate of the memory transistor, and form a select gate between the second gate and the third gate of the memory transistor; Lightly doped source and drain regions are formed below the surface of the memory tube well in the etched region of the memory dielectric layer and the first polysilicon layer by performing source and drain light doping implantation. as well as, A sidewall is formed on one side of the isolation oxide layer of the first gate and the fourth gate of the memory transistor, and source / drain injection is performed using the sidewall as a mask to form a source / drain region.
7. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, While forming the sidewalls, the sidewall material simultaneously fills the gate gaps of the memory cells to form an isolation layer.
8. The method for manufacturing a storage cell of the SONOS memory according to claim 7, characterized in that, The lightly doped source / drain regions are located below the isolation layer and the sidewalls.
9. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, Also includes: After forming the source / drain region, part of the storage medium layer is removed to expose the gate of the select transistor.
10. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, The storage medium layer has an ONO structure and a thickness of 90 Å-160 Å.
11. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, The thickness of the gate oxide layer is 60 Å-120 Å, and the thickness of the first polycrystalline silicon layer is 600 Å-2000 Å.
12. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, The thickness of the isolation oxide layer is 60 Å-300 Å.
13. The method for manufacturing a storage cell of the SONOS memory according to claim 6, characterized in that, The thickness of the second polycrystalline silicon layer is 500 Å-1000 Å.