Three-dimensional stacked RRAM memory and preparation method thereof

Abstract

The invention provides a three-dimensional stacked RRAM memory and a preparation method thereof, and the preparation method of the three-dimensional stacked RRAM memory comprises the steps: providing a layout of an RRAM memory wafer, the layout being in an axial symmetry layout along a Y direction; preparing a set of mask plate according to the layout, wherein the pattern of the mask plate is in axial symmetry along the Y direction; a plurality of RRAM storage wafers are prepared by using the same set of mask, all the RRAM storage wafers have the same chip arrangement, and the bonding surfaces of the RRAM storage wafers have the same bonding structure; preparing a logic wafer; respectively carrying out back thinning on the RRAM storage wafer and the logic wafer, and manufacturing through silicon vias; and stacking and bonding the plurality of RRAM storage wafers along the thickness direction of the logic wafer. The layout symmetrical along the Y axis is adopted, so that the mask can be repeatedly used, and the design times are reduced; and with the same bonding structure, the bonding precision is improved.

Description

A three-dimensional stacked RRAM memory and its fabrication method Technical Field

[0001] This invention relates to the field of three-dimensional stacked RRAM memory, and more specifically, to a three-dimensional stacked RRAM memory and its fabrication method. Background Technology

[0002] In the field of very large-scale integrated circuits (VLSI), traditional two-dimensional (2D) integration technology is no longer sufficient to meet the application requirements of high-performance, high-density storage. Three-dimensional (3D) stacking technology, with its vertical interconnect characteristics, can multiply the number of transistors and integration density per unit area, while shortening the global interconnect length, increasing interconnect speed, and reducing signal latency and power consumption. Among these technologies, hybrid bonding technology, which can simultaneously achieve high-density electrical interconnects and robust mechanical connections, has become a core process for realizing high-performance 2.5D / 3D packaging. Hybrid bonding allows thousands of micron-sized metal pads on two wafer surfaces to be directly bonded to the dielectric layer, achieving interconnect density and bandwidth far exceeding traditional bump technology, laying the foundation for advanced architectures such as high-bandwidth memory and in-memory computing.

[0003] Resistive random access memory (RRAM), as a non-volatile memory, boasts advantages such as simple structure, high operating speed, low power consumption, and good compatibility with CMOS processes, demonstrating great potential in embedded storage, in-memory computing, and other fields. However, the storage density of traditional two-dimensional RRAM arrays depends on semiconductor fabrication processes. As processes continue to shrink, the maximum theoretical storage density is gradually reaching its limit, failing to meet the ever-growing storage demands of modern data centers. Furthermore, the deposition or annealing of RRAM functional layers often requires high temperatures, which can easily damage the underlying CMOS transistors and interconnect structures.

[0004] In existing technologies, some solutions have attempted to improve memory density through three-dimensional stacking. However, this involves stacking chips layer by layer using microbumps and under-bump metal interconnects. Reducing the spacing between interconnects is difficult, limiting the interconnect density per unit chip area. Furthermore, additional temporary bonding and wafer removal steps are required, increasing cost and cycle time. In addition, multi-layer stacking processes are complex, requiring the use of different masks multiple times, resulting in high fabrication costs and long cycles. Moreover, process compatibility and thermal budget management remain significant challenges when integrating logic and multi-layer memory. Summary of the Invention

[0005] In view of the complex fabrication of RRAM memory in the prior art described above, this application provides a three-dimensional stacked RRAM memory and its fabrication method, which simplifies the design process, reduces the design of photomasks, and streamlines the process steps.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a three-dimensional stacked RRAM memory, comprising:

[0007] A layout of an RRAM memory wafer is provided, the layout being arranged in an axisymmetric manner along the Y direction;

[0008] A set of photomasks is prepared based on the layout, wherein the pattern of the photomasks is axially symmetrical along the Y direction;

[0009] Using the same set of photomasks, multiple RRAM memory wafers are fabricated. All RRAM memory wafers have the same chip arrangement and the same bonding structure on the bonding surface of the RRAM memory wafers.

[0010] Fabricate a logic wafer;

[0011] The RRAM memory wafer and the logic wafer are respectively thinned on the back side and through-silicon vias are fabricated.

[0012] Multiple RRAM storage wafers are stacked and bonded along the thickness direction of the logic wafer.

[0013] Optionally, the chips of the RRAM storage wafer are arranged symmetrically along the Y direction; the bonding structures on the bonding surface of the logic wafer are arranged symmetrically along the Y direction.

[0014] Optionally, the bonding structure includes: a dielectric layer covering the wafer bonding surface, and a metal bonding layer located within the dielectric layer.

[0015] Optionally, the through-silicon via is disposed corresponding to the metal bonding layer within the bonding structure.

[0016] Optionally, the bonding structure on the logic wafer bonding surface is the same as the bonding structure on the RRAM storage wafer bonding surface.

[0017] Optionally, the bonding method includes hybrid bonding, which includes face-to-face bonding and face-to-back bonding.

[0018] Optionally, bonding multiple RRAM memory wafers face-to-back along the thickness direction of the logic wafer includes the following steps:

[0019] S61: Bond the front side of the first RRAM storage wafer to the front side of the logic wafer;

[0020] S62: Thin the back side of the first RRAM memory wafer, create through-silicon vias in the first RRAM memory wafer, and form a bonding structure on the back side;

[0021] S63: Bond the front side of the second RRAM memory wafer to the back side of the first RRAM memory wafer;

[0022] S64: Thin the back side of the second RRAM memory wafer, create through-silicon vias in the second RRAM memory wafer, and form a back-side bonding structure on the back side;

[0023] S65: Repeat steps S63-S64 sequentially to bond the front side of the i-th RRAM storage wafer to the back side of the (i-1)-th RRAM storage wafer, and process the back side of the i-th RRAM storage wafer; where i ≥ 3.

[0024] Optionally, bonding a plurality of the RRAM storage wafers along the thickness direction of the logic wafer includes the following steps:

[0025] S61': Bond the front side of the first RRAM storage wafer to the front side of the logic wafer;

[0026] S62': Thin the back side of the first RRAM memory wafer, create through-silicon vias in the first RRAM memory wafer, and form a bonding structure on the back side;

[0027] S63': Provides multiple dual-wafer stacks, which form a dual-wafer stack by bonding two RRAM memory wafers face to face;

[0028] S64': Thin the back side of one of the memory wafers in the dual-wafer stack, fabricate through-silicon vias in the memory wafer, and form a bonding structure on the back side;

[0029] S65': The dual-wafer stack is bonded to the back side of the uppermost RRAM storage wafer in the stacked structure through the processed surface;

[0030] S66: Repeat steps S63-S65 until the preset number of stacking layers is reached.

[0031] This application also provides a three-dimensional stacked RRAM memory, including:

[0032] Logic wafers;

[0033] Multiple RRAM storage wafers are stacked vertically on top of the logic wafer;

[0034] The plurality of RRAM memory wafers have the same physical layout, which includes at least: chip arrangement, test circuit arrangement and bonding structure;

[0035] A through-silicon via (TSV) is located within the RRAM storage wafer, and the TSV is directly electrically connected to the metal bonding layer within the bonding structure.

[0036] Optionally, the bonding structure is arranged in an axisymmetric manner about the Y direction.

[0037] As described above, the three-dimensional stacked RRAM memory, its fabrication method, and display device provided by the present invention have at least the following beneficial technical effects:

[0038] In the three-dimensional stacked RRAM memory of this invention, the light-emitting epitaxial structure includes blue and green epitaxial structures stacked vertically, and red epitaxial structures arranged at intervals with the green epitaxial structures. This arrangement of the epitaxial structures allows for the separate transfer and bonding of the red, blue, and green epitaxial structures, reducing the difficulty of epitaxial structure transfer, improving transfer yield, and enhancing product reliability. Each epitaxial structure has an individually controlled electrode structure, enabling independent control of each color chip and achieving full color gamut display.

[0039] In addition, the thickness of the red, blue and green epitaxial structures in the above epitaxial structure is less than 2 μm and the maximum side length is less than 10 μm. Therefore, the three-dimensional stacked RRAM memory of the present invention can also meet the requirements of a small-size three-dimensional stacked RRAM memory. Attached Figure Description

[0040] Figure 1 shows a flowchart of the fabrication method of the three-dimensional stacked RRAM memory provided in Embodiment 1 of the present invention.

[0041] Figure 2 shows a schematic diagram of the structure of the RRAM memory wafer layout provided in Example 1.

[0042] Figure 3 shows a schematic diagram of a three-dimensional stacked RRAM memory structure with back-to-back bonding.

[0043] Figure 4 shows a schematic diagram of the dual-wafer stack structure provided in Example 1.

[0044] Figure 5 shows a schematic diagram of another three-dimensional stacked RRAM memory structure provided in this application.

[0045] Figure reference numerals: 10, chip; 20, test circuit; 30, test chip; 1, bonding structure; 2, redistribution layer; 3, carrier board. Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0048] Example 1

[0049] This embodiment provides a method for fabricating a three-dimensional stacked RRAM memory. As shown in Figure 1, the flowchart of the three-dimensional stacked RRAM memory fabrication method of this embodiment includes the following steps: S1: Setting the layout of the RRAM memory wafer, the layout is symmetrically arranged along the Y direction; S2: Fabricating a mask according to the layout, the pattern of the mask is symmetrically arranged along the Y direction; S3: Using the same mask, fabricating multiple RRAM memory wafers, all RRAM memory wafers have the same chip arrangement, and the bonding surface of the RRAM memory wafers has the same bonding structure; S4: Fabricating a logic wafer; S5: Performing back-side thinning on the RRAM memory wafer and the logic wafer respectively, and fabricating through-silicon vias; S6: Three-dimensionally stacking and bonding the logic wafer with the multiple RRAM memory wafers.

[0050] Step S1: Set the layout of the RRAM storage wafer, with the layout arranged symmetrically along the Y-axis; as shown in Figure 2, it is a schematic diagram of the structure of the RRAM storage wafer layout provided in this embodiment; this layout is for illustration only, with the layout width direction as the X-axis and the direction perpendicular to the X-axis in the layout plane as the Y-axis, the layout is arranged symmetrically along the Y-axis. The layout includes multiple chips 10, multiple through-silicon vias within the chips 10, multiple test lines 20, and multiple test chips 30, etc. The multiple chips 10 are arranged in a matrix, and the number of rows and columns of the matrix is ​​set according to the storage capacity requirements; among them, the internal RRAM storage cell array, read / write control circuit and external interface pins of the chips 10 located on the axis of symmetry are all designed symmetrically along the Y-axis to ensure the symmetry of the chip's own functional layout; the chips 10 located on both sides of the axis of symmetry are symmetrically arranged about the Y-axis. In this embodiment, each chip 10 contains 4 TSVs, and the 4 TSVs are arranged symmetrically along the Y direction within the chip 10; the test lines 20 are distributed in the dicing channels between adjacent chips 10; in this embodiment, 4 test chips are set on a wafer, symmetrically arranged in pairs at two corners; the test chip 30 integrates a test probe interface, a signal amplification circuit and a data transmission module, and its functions include TSV continuity testing after wafer fabrication, bonding structure integrity testing, and overall electrical performance testing after stacking.

[0051] Step S2: Prepare a mask based on the layout, the pattern of which is axially symmetrical along the Y direction; based on the provided axially symmetrical RRAM layout, prepare a mask using photolithography, the pattern of which is completely identical to the layout and axially symmetrical along the Y direction. Due to the axially symmetrical design of the layout, this application only needs to prepare one mask to achieve batch preparation of all RRAM memory wafers, eliminating the need to design multiple masks for different wafers, thus reducing the design and preparation costs of the masks. Simultaneously, the axially symmetrical pattern of the mask ensures that the key structures on the wafer maintain strict symmetry after each exposure, providing process assurance for precise alignment during subsequent stacking.

[0052] Step S3: Using the same set of photomasks, multiple RRAM memory wafers are fabricated. All RRAM memory wafers have the same chip layout and the same bonding structure on their bonding surfaces. Specifically, using the same set of photomasks, multiple RRAM memory wafers are sequentially fabricated on multiple semiconductor substrates through conventional manufacturing processes including thin film deposition, photolithography, ion implantation, etching, and chemical mechanical planarization. The multiple RRAM memory wafers are physically consistent, including identical chip layout and bonding structure, and are axially symmetrical about the Y direction. Specifically, the bonding structure includes a dielectric layer covering the wafer bonding surface and a metal bonding layer located within the dielectric layer. Generally, the number of RRAM memory wafers is selected according to actual storage requirements; this embodiment uses 8 RRAM memory wafers as an example.

[0053] Step S4: Fabricate a logic wafer; specifically, the front side of the logic wafer integrates control circuitry, including an address decoder, read / write driver circuitry, input / output interfaces, and control logic. The fabrication process of the logic wafer is a conventional technique in the field, and specific details can be found in existing technologies, which will not be elaborated here.

[0054] Optionally, a bonding structure is formed on the front side of the logic wafer to facilitate bonding with the first RRAM memory wafer and achieve electrical connection. Optionally, the bonding structure on the front side of the logic wafer is designed to be symmetrical about the Y-axis. Optionally, the bonding structure on the front side of the logic wafer is the same as the bonding structure on the bonding surface of the RRAM memory wafer.

[0055] Step S5: Perform back-side thinning on the RRAM memory wafer and logic wafer respectively, and fabricate through-silicon vias (TSVs). Specifically, the TSVs fall within the projection plane of the bonding metal layer within the bonding structure to ensure direct electrical connection between the TSV bonding metal layer and the bonding metal layer.

[0056] Step S6: Stack and bond the logic wafer with multiple RRAM memory wafers in three dimensions.

[0057] Specifically, the bonding methods include face-to-back sequential bonding and face-to-face stacking after face-to-face combination. In this embodiment, eight RRAM memory wafers are used as an example for illustration.

[0058] Specifically, the back-to-back sequential bonding includes: Step S61: Connecting the front side of the first RRAM memory wafer to the front side of the logic wafer using a hybrid bonding method; Step S62: Thinning the back side of the bonded first RRAM memory wafer, forming through-silicon vias (TSVs) within the first RRAM memory wafer, and forming a bonding structure on the back side; wherein the layout of the bonding structure on the back side is symmetrical about the Y-axis to the bonding structure on the front side, and the two are electrically connected through the TSVs; Step S63: Providing a second RRAM memory wafer, and hybrid bonding the front side of the second RRAM memory wafer to the back side of the first RRAM memory wafer; Step S64: Thinning the back side of the bonded second RRAM memory wafer, and forming TSVs and bonding structures; then repeating steps S63-S64: sequentially providing the i-th RRAM memory wafer, i≥3; bonding the front side of the i-th RRAM memory wafer to the back side of the (i-1)-th RRAM memory wafer; bonding the i-th RRAM memory wafer to the back side of the (i-1)-th RRAM memory wafer; The back side of the RRAM memory wafer is thinned to form a bonding structure, and a through-silicon via (TSV) is formed within the i-th RRAM memory wafer, until all preset layers are stacked. Figure 3 shows a schematic diagram of a three-dimensional stacked RRAM memory structure with back-to-back bonding; in the entire three-dimensional stacked structure, the front side of the RRAM wafer faces the logic wafer.

[0059] After face-to-face assembly, face-to-back stacking includes the following steps: Step S61: Connect the front side of the first RRAM storage wafer RRAM1 to the front side of the logic wafer using a hybrid bonding method; Step S62: Thin the back side of the first RRAM storage wafer, form a through-silicon via (TSV) within the first RRAM storage wafer, and form a bonding structure on the back side; Step S63: Provide multiple dual-wafer stacks, and bond two RRAM storage wafers face-to-face to form a dual-wafer stack; Step S64: Thin the back side of one of the storage wafers in the dual-wafer stack, fabricate a TSV within the storage wafer, and form a bonding structure 1 on the back side;

[0060] Specifically, as shown in Figure 4, this embodiment provides a schematic diagram of a dual-wafer stack structure. Taking the second RRAM storage wafer RRAM2 and the third RRAM storage wafer RRAM3 as examples, the back side of the third RRAM storage wafer RRAM3 is temporarily bonded to the carrier 3, and a bonding structure 1 is formed on the front side of the second RRAM storage wafer RRAM2 and the third RRAM storage wafer RRAM3. The second RRAM storage wafer RRAM2 and the third RRAM storage wafer RRAM3 are bonded together by a hybrid bonding method to form a dual-wafer stack.

[0061] The back side of the second RRAM memory wafer RRAM2, which is away from the carrier 3 in the dual-wafer stack, is thinned, and the process parameters are the same as those for the back side thinning of the first RRAM memory wafer RRAM1. A TSV (Transient Voltage Slab) penetrating its thickness is etched from the back side of the second RRAM memory wafer RRAM2, and the TSV is electrically connected to the bonding structure 1 on the front side of the second RRAM memory wafer. The bonding structure 1 (symmetrical about the Y-axis with the front bonding structure 1) is fabricated on the thinned back side of the second RRAM memory wafer. Optionally, the back side of the third RRAM memory wafer (the side temporarily bonded to the carrier 3) is not thinned, TSV fabricated, or bonding structure formed. Optionally, a redistribution layer 2 is formed between the back side bonding structure 1 and the TSV of the second RRAM memory wafer. The redistribution layer 2 is electrically connected to the TSV to optimize the current transmission path.

[0062] Step S65': Bond the dual-wafer stack of the second RRAM memory wafer and the third RRAM memory wafer to the back side of the first RRAM memory wafer, specifically, the back side of the second RRAM memory wafer is bonded to the back side of the first RRAM memory wafer; invert the dual-wafer stack shown in Figure 4 and bond it to the back side of the topmost RRAM memory wafer of the stacked structure.

[0063] Step S66': Provide the i-th RRAM storage wafer and the (i+1)-th RRAM storage wafer stack in sequence, where i is greater than or equal to 3; repeat steps S63'-S65' to complete the face-to-face combination, and then the back-to-back stacked stack, as shown in Figure 5, which is a schematic diagram of the three-dimensional stacked structure formed by back-to-back bonding after face-to-face combination provided in this embodiment.

[0064] The stacked structures shown in Figure 3 and Figure 5 differ in that the stacked structure in Figure 3, due to the perfect correspondence and alignment of the bonding surfaces (front side of the upper layer and back side of the lower layer) of the two wafers, can achieve interconnection solely through TSVs and the bonding structure, eliminating the need for an additional back-side redistribution layer (RDL). In the stacked structure shown in Figure 5, at the "back-to-back bonding" interface, both back sides require TSVs to connect to their respective front-side circuitry. To achieve specific interconnections or signal routing, a redistribution layer (RDL) is typically required on at least one back side to complete the necessary electrical connection network.

[0065] The fabrication method of the three-dimensional stacked RRAM memory provided in this embodiment includes a layout of the entire RRAM memory wafer, which at least includes chip circuits, test structures, and bonding structures. All of these adopt a design symmetrical along the Y-axis. Key markers for photolithography alignment and process monitoring can be reused within the layout, reducing the number of mask designs. Furthermore, all RRAM memory wafers use the exact same bonding surface layout. Therefore, only the design and verification of a single bonding interface needs to be completed, and the results can be reused in all RRAM layers of the stack. This avoids the workload of designing and optimizing interconnect structures independently for each layer, simplifying process steps, reducing costs, and improving efficiency. In addition, the axially symmetrical bonding structure can improve the alignment accuracy of bonding, reduce alignment deviations, and improve the reliability and stability of the stacked structure.

[0066] Example 2

[0067] This embodiment provides a three-dimensional stacked RRAM memory, including: a logic wafer; multiple RRAM memory wafers, stacked vertically on top of the logic wafer; wherein the multiple RRAM memory wafers have the same physical layout, the physical layout including at least: chip arrangement, test circuit arrangement, and bonding structure; through-silicon vias (TSVs) located within the RRAM memory wafers, the TSVs being directly electrically connected to a metal layer within the bonding structure. The bonding structure is symmetrical about the Y-axis.

[0068] As shown in Figure 3, the three-dimensional stacked RRAM memory includes a logic wafer and multiple RRAM memory wafers stacked vertically on it (the figure shows an 8-layer example). All RRAM memory wafers have the same physical layout. Specifically, the memory chip cells on each RRAM memory wafer are arranged in the same regular matrix; the circuitry and test chips used for process monitoring and testing are positioned identically on the wafer; the bonding surfaces for interlayer connections on each RRAM memory wafer have the same layout; in particular, the pattern of the bonding structure is symmetrical about the Y direction.

[0069] Specifically, in the stacked structure, each RRAM memory wafer contains through-silicon vias (TSVs). These TSVs vertically penetrate the wafer, with their upper ends electrically connected to the metal bonding layer within the bonding structure, and their lower ends connected to the corresponding bonding structure of the adjacent lower wafer, thus forming a vertical electrical interconnect network spanning multiple layers. Because the bonding structures of the upper and lower wafers are aligned, efficient interconnection can be achieved without introducing an additional back-side redistribution layer, significantly simplifying the structure. Particularly, in the face-to-back sequential bonding structure shown in Figure 3, the front sides of all RRAM memory wafers face the bottom logic wafer.

[0070] Figure 5 shows a schematic diagram of another type of three-dimensional stacked RRAM memory, namely a face-to-face bonding and back-to-back bonding stacked structure. In this structure, every two RRAM memory wafers are first bonded face-to-face to form a bi-wafer stack structure, and then these combined units are stacked back-to-back. This structure generally allows for more flexible interconnect design, but may require the introduction of a redistribution layer on the back side of the combined units to handle complex signal routing and power distribution.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a three-dimensional stacked RRAM memory, characterized in that, include: S1: Provide a layout of an RRAM storage wafer, the layout being axially symmetrical along the Y direction; S2: Prepare a set of photomasks according to the layout, wherein the pattern of the photomasks is axially symmetrical along the Y direction; S3: Use the same set of photomasks to prepare multiple RRAM memory wafers, wherein all the RRAM memory wafers have the same chip arrangement and the same bonding structure on the bonding surface of the RRAM memory wafers; S4: Prepare a logic wafer; S5: Thin the back side of the RRAM memory wafer and the logic wafer respectively, and fabricate through-silicon vias; S6: Stack and bond multiple RRAM memory wafers along the thickness direction of the logic wafer.

2. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, The RRAM storage wafer has its chip arrangement symmetrically distributed along the Y direction; the bonding structure on the bonding surface of the logic wafer is symmetrically arranged along the Y direction.

3. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, The bonding structure includes: a dielectric layer covering the bonding surface of the wafer, and a metal bonding layer located within the dielectric layer.

4. The method for fabricating a three-dimensional stacked RRAM memory according to claim 3, characterized in that, The through-silicon vias are disposed corresponding to the metal bonding layers within the bonding structure.

5. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, The bonding structure on the logic wafer bonding surface is the same as the bonding structure on the RRAM storage wafer bonding surface.

6. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, The bonding method includes hybrid bonding, which includes face-to-face bonding and face-to-back bonding.

7. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, The method of bonding multiple RRAM memory wafers face-to-back along the thickness direction of the logic wafer includes the following steps: S61: bonding the front side of a first RRAM memory wafer to the front side of the logic wafer; S62: thinning the back side of the first RRAM memory wafer, forming through-silicon vias (TSVs) within the first RRAM memory wafer, and forming a bonding structure on the back side; S63: bonding the front side of a second RRAM memory wafer to the back side of the first RRAM memory wafer; S64: thinning the back side of the second RRAM memory wafer, forming TSVs within the second RRAM memory wafer, and forming a back-side bonding structure on the back side; S65: repeating steps S63-S64 sequentially, bonding the front side of the i-th RRAM memory wafer to the back side of the (i-1)-th RRAM memory wafer, and processing the back side of the i-th RRAM memory wafer; wherein, i ≥ 3.

8. The method for fabricating a three-dimensional stacked RRAM memory according to claim 1, characterized in that, Bonding multiple RRAM memory wafers along the thickness direction of the logic wafer includes the following steps: S61': Bonding the front side of the first RRAM memory wafer to the front side of the logic wafer; S62': Thinning the back side of the first RRAM memory wafer, creating through-silicon vias (TSVs) within the first RRAM memory wafer, and forming a bonding structure on the back side; S63': Providing multiple dual-wafer stacks, forming dual-wafer stacks by bonding two RRAM memory wafers face-to-face; S64': Thinning the back side of one memory wafer in the dual-wafer stack, creating TSVs within the memory wafer, and forming a bonding structure on the back side; S65': Bonding the dual-wafer stack to the back side of the uppermost RRAM memory wafer in the stacked structure through the processed surface; S66': Repeating steps S63'-S65' until a preset number of stacked layers is reached.

9. A three-dimensional stacked RRAM memory, characterized in that, include: Logic wafers; Multiple RRAM memory wafers are stacked vertically on top of the logic wafer; wherein the multiple RRAM memory wafers have the same physical layout, the physical layout including at least: chip arrangement, test circuit arrangement and bonding structure; through silicon vias are located in the RRAM memory wafers, and the through silicon vias are directly electrically connected to the metal bonding layer in the bonding structure.

10. The three-dimensional stacked RRAM memory according to claim 9, characterized in that, The bonding structure is axially symmetric about the Y direction.

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