Super junction power device and method of manufacturing the same

Abstract

This application relates to the field of semiconductor technology and discloses a superjunction power device and its fabrication method, comprising: providing a substrate and forming a first epitaxial layer on the substrate; forming a plurality of deep trenches on the first epitaxial layer and filling the deep trenches with a second epitaxial layer having a different doping type than the first epitaxial layer; forming shallow trenches on each deep trench relative to the sidewalls of the deep trenches, the sidewall profile of the shallow trenches coinciding with the interface between the first and second epitaxial layers; forming a trench gate structure on the shallow trenches; performing self-aligned ion implantation and annealing push-well between adjacent deep trenches on the first epitaxial layer to form a body region and a source region located above the body region; forming contact hole regions on the first epitaxial layer respectively connected to one side of the source region and the second epitaxial layer in the deep trenches; forming a source metal layer covering the contact hole regions on the first epitaxial layer, and forming a drain region on the substrate back gold. This application improves device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a superjunction power device and its fabrication method. Background Technology

[0002] Superjunction power devices, with their unique charge balancing mechanism, can simultaneously achieve low on-resistance and high breakdown voltage. They typically employ multiple epitaxial processes to form alternating P-pillar and N-pillar regions, which deplete each other through a lateral electric field in the off-state, thus allowing for higher doping concentrations and reducing on-resistance. As power devices continue to evolve towards higher power density and lower losses, further miniaturizing the cell pitch to reduce on-resistance per unit area has become a research hotspot. In related technologies, superjunction MOSFETs mostly employ trench gate structures, which limits the cell size to further miniaturization due to the gate structure, hindering the reduction of on-resistance and impacting device performance improvement. Summary of the Invention

[0003] In view of this, this application provides a superjunction power device and its fabrication method to solve the aforementioned technical problems.

[0004] In a first aspect, embodiments of this application disclose a method for fabricating a superjunction power device, comprising:

[0005] A substrate is provided on which a first epitaxial layer of the same doping type is formed;

[0006] A plurality of deep trenches are formed on the first epitaxial layer, and the deep trenches are filled with a second epitaxial layer with a different doping type than the first epitaxial layer;

[0007] Shallow trenches are formed on each of the deep trenches relative to the sidewalls of the deep trenches, the sidewall profile of the shallow trenches coincides with the interface between the first epitaxial layer and the second epitaxial layer, and a trench gate structure is formed on the shallow trenches.

[0008] Self-aligned ion implantation and annealing push-well are performed between adjacent deep trenches on the first epitaxial layer to form a body region and a source region located above the body region and close to the trench gate structure.

[0009] Contact hole regions are formed on the first epitaxial layer, respectively connected to one side of the source region and the second epitaxial layer in the deep trench;

[0010] A source metal layer covering the contact hole region is formed on the first epitaxial layer, and a drain region is formed on the substrate back gold.

[0011] In one possible example, forming a plurality of deep trenches on the first epitaxial layer includes:

[0012] Selective deep trench etching is performed under the mask and barrier layer on the first epitaxial layer to obtain the deep trench with the first trench depth.

[0013] In one possible example, the depth of the first trench is less than the thickness of the first epitaxial layer, and the trench inclination angle of the deep trench is in the range of 0-10°.

[0014] In one possible example, forming shallow trenches relative to the sidewalls of the deep trenches on each of the deep trenches includes:

[0015] Selective shallow trench etching is performed under the mask and barrier layer on the first epitaxial layer to obtain the shallow trench embedded in the second epitaxial layer in the deep trench.

[0016] In one possible example, the shallow trench has a second trench depth that is less than the first trench depth, and the trench inclination angle of the shallow trench is the same as that of the deep trench.

[0017] In one possible example, forming a trench grid structure on the shallow trench includes:

[0018] A thick oxide layer is formed in the shallow trench, and the thick oxide layer at the bottom of the shallow trench is retained by etching back to obtain the TBO layer;

[0019] After a sacrificial oxide layer is formed in the shallow trench, the sacrificial oxide layer is removed.

[0020] After forming a gate dielectric layer in the shallow trench, gate polysilicon is deposited into the shallow trench.

[0021] In one possible example, forming contact hole regions on the first epitaxial layer that are respectively connected to one side of the source region and the second epitaxial layer within the deep trench includes:

[0022] An isolation dielectric layer is formed on the first epitaxial layer to isolate the trench gate structure;

[0023] Two first contact holes are etched between adjacent deep trenches and a second contact hole is etched between adjacent trench gate structures on the deep trenches through a mask opening on the isolation dielectric layer. The two first contact holes are respectively connected to one side of each source region in the body region, and the second contact hole is connected to the second epitaxial layer.

[0024] The first and second contact holes are injected with ions of the same type as those in the body region and then annealed to push the trap.

[0025] An alloy layer is deposited in the first contact hole and the second contact hole.

[0026] In one possible example, the depth of the first contact hole and the second contact hole is greater than the source region junction depth, and the etching tilt angle of the first contact hole and the second contact hole is less than 20°.

[0027] Secondly, embodiments of this application disclose a superjunction power device, fabricated by the superjunction power device fabrication method described in any of the above embodiments, comprising:

[0028] Substrate, wherein a first epitaxial layer is disposed on the substrate;

[0029] A deep trench, wherein a plurality of the deep trenches are disposed on the first epitaxial layer, and a second epitaxial layer is disposed within the deep trenches;

[0030] A shallow trench, wherein a trench grid structure is provided in the shallow trench, and the shallow trench is located opposite to the sidewall of each of the deep trenches, and the outline of one sidewall of the shallow trench coincides with the interface between the first epitaxial layer and the second epitaxial layer.

[0031] The body region and the source region are disposed between adjacent deep trenches on the first epitaxial layer, and the source region is connected above the body region;

[0032] The contact hole region is disposed on the first epitaxial layer and is respectively connected to one side of the source region and the second epitaxial layer in the deep trench;

[0033] A source metal layer is disposed on the first epitaxial layer and covers the contact hole area;

[0034] The drain region is located on the side of the substrate away from the first epitaxial layer.

[0035] In one possible example, the contact hole region on the first epitaxial layer includes a first contact hole and a second contact hole; the two first contact holes are located between adjacent deep trenches and are respectively connected to one side of each source region in the body region, and the second contact holes are located between adjacent trench gate structures on the deep trenches and are connected to the second epitaxial layer.

[0036] In summary, compared with the prior art, this application discloses a superjunction power device and its fabrication method, comprising: providing a substrate and forming a first epitaxial layer with the same doping type on the substrate; forming a plurality of deep trenches on the first epitaxial layer and filling the deep trenches with a second epitaxial layer with a different doping type than the first epitaxial layer; forming a shallow trench on each deep trench relative to the sidewall of the deep trench, wherein the contour of one sidewall of the shallow trench coincides with the interface between the first epitaxial layer and the second epitaxial layer; and forming a trench gate structure on the shallow trench; performing self-aligned ion implantation and annealing push-well between adjacent deep trenches on the first epitaxial layer to form a body region and a source region located above the body region and close to the trench gate structure; forming contact hole regions on the first epitaxial layer respectively connected to one side of the source region and the second epitaxial layer in the deep trench; forming a source metal layer covering the contact hole regions on the first epitaxial layer, and forming a drain region on the substrate back gold, i.e., improving device performance through the above configuration. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of the superjunction power device fabrication method according to an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the first step structure for generating a superjunction power device according to an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the second step structure for generating a superjunction power device according to an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the third step in generating a superjunction power device according to an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the fourth step in generating a superjunction power device according to an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of the fifth step in generating a superjunction power device according to an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the sixth step in generating a superjunction power device according to an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the seventh step in generating a superjunction power device according to an embodiment of this application. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the claims.

[0047] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0048] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0049] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0050] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0052] Please refer to Figure 1The superjunction power device fabrication method of this application includes providing a substrate, forming a first epitaxial layer with the same doping type on the substrate, forming a plurality of deep trenches on the first epitaxial layer, and filling the deep trenches with a second epitaxial layer with a different doping type than the first epitaxial layer, forming a shallow trench on each deep trench relative to the sidewall of the deep trench, the sidewall profile of the shallow trench coinciding with the interface between the first epitaxial layer and the second epitaxial layer, forming a trench gate structure on the shallow trench, performing self-aligned ion implantation and annealing between adjacent deep trenches on the first epitaxial layer to form a body region and a source region located above the body region and close to the trench gate structure, forming contact hole regions on the first epitaxial layer respectively connected to one side of the source region and the second epitaxial layer in the deep trench, forming a source metal layer covering the contact hole regions on the first epitaxial layer, and forming a drain region on the substrate back gold.

[0053] Thus, the first and second epitaxial layers with different doping types construct the pillar region PN junction of the superjunction power device. By forming a shallow trench in the second epitaxial layer with a deep trench and aligning one sidewall of the shallow trench with the interface (PN junction interface) of the first and second epitaxial layers, the trench gate structure is directly embedded in the second epitaxial layer with a deep trench (if the first epitaxial layer is N-type doped, the trench gate structure is directly embedded in the P pillar region of the deep trench). This allows for further miniaturization of the device cell size, thereby effectively reducing the on-resistance per unit area and improving device performance.

[0054] Furthermore, the contact hole regions are respectively connected to one side of the source region and the second epitaxial layer in the deep trench. This "dual contact hole" design diverts the source-gate channel, increases the effective area of ​​the body region, and improves the discharge path of the body region current, thereby significantly improving the avalanche tolerance of the device.

[0055] Continue to combine Figures 2 to 8 The fabrication method of this application embodiment will be described in detail below with reference to the structural schematic diagram of the superjunction power device. Specifically, the fabrication method of the superjunction power device includes:

[0056] S101, a substrate 1 is provided, and a first epitaxial layer 11 of the same doping type is formed on the substrate 1.

[0057] In the specific implementation process, refer to Figure 2The substrate 1 can be formed from materials such as single-crystal silicon, polycrystalline silicon, amorphous silicon, or doped silicon. The substrate 1 can also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure. It can also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, P atoms can be implanted into single-crystal silicon to form an N-type conductive semiconductor substrate, or B atoms can be implanted into single-crystal silicon to form a P-type conductive semiconductor substrate, so as to improve the selectivity of materials and adaptability to actual production environments.

[0058] Preferably, in this embodiment, the substrate 1 is implanted with P atoms to form an N-type conductive semiconductor substrate, that is, the substrate 1 is an N+ doped substrate, and the first epitaxial layer 11 is an N- doped epitaxial layer.

[0059] In one example, the first epitaxial layer 11 can be divided into several cell regions to include a large number of repeating basic units of a semiconductor superjunction power device.

[0060] In one example, a buried layer and a first epitaxial layer 11 are formed sequentially on a substrate 1, and the functional layers of the semiconductor superjunction power device can be formed on the first epitaxial layer 11.

[0061] Preferably, the thickness of the first epitaxial layer 11 is greater than 2 μm.

[0062] S102, a plurality of deep trenches 2 are formed on the first epitaxial layer 11, and the deep trenches 2 are filled with a second epitaxial layer 21 with a different doping type than the first epitaxial layer 11.

[0063] In this step, refer to Figure 2 and Figure 3 Several deep trenches 2 are formed on the first epitaxial layer 11, including selective deep trench etching under the mask and barrier layer on the first epitaxial layer 11, to obtain the depth of the first trench (e.g., Figure 2 Deep trench 2 (identified by H1).

[0064] In one example, a barrier layer (e.g., a silicon dioxide or silicon nitride hard mask layer) is prepared on the surface of the first epitaxial layer 11, and a photoresist layer is coated on the barrier layer. Subsequently, the photoresist layer is exposed and developed using a mask to transfer the pattern of the deep trench 2 to the photoresist layer. Using the patterned photoresist layer as a mask, the barrier layer is etched to further transfer the pattern to the barrier layer, forming a hard mask pattern. Then, the photoresist layer is removed, and the first epitaxial layer 11 is selectively etched into deep trenches using the hard mask pattern as a mask.

[0065] Preferably, during the etching process, the etching depth can be controlled within a preset first trench depth range by controlling the etching time and process parameters, thereby forming a deep trench 2 with a high aspect ratio in the first epitaxial layer 11.

[0066] After the deep trench 2 is formed, a second epitaxial layer 21 (e.g., a P-type epitaxial layer) with the opposite doping type to the first epitaxial layer 11 is filled in the deep trench 2. The filling process can be selective epitaxial growth or CVD trench filling process, and planarization treatment (e.g., CMP) is performed after filling to remove excess filling material on the surface of the first epitaxial layer 11, forming a superjunction structure with alternating P-pillar and N-pillar regions.

[0067] Preferably, if the substrate 1 is an N+ doped substrate and the first epitaxial layer 11 is an N- doped epitaxial layer, then the second epitaxial layer 21 is a P- doped epitaxial layer, i.e., the P-pillar region of the deep trench 2.

[0068] Furthermore, the depth of the first trench is less than the thickness of the first epitaxial layer 11. In other words, the deep trench 2 does not completely penetrate the first epitaxial layer 11, but terminates inside the first epitaxial layer 11. The purpose of this design is to retain a certain thickness of N-type epitaxial material at the bottom of the deep trench 2, so that there is always an N-type drift region between the subsequently formed P-pillar region and the bottom N+ substrate, avoiding the P-type filling material from directly contacting the high-concentration substrate and causing leakage or breakdown voltage failure, thereby ensuring the breakdown voltage characteristics of the device.

[0069] And the sidewalls of the deep trench 2 have an inclined angle relative to the horizontal surface of the substrate 1 or the first epitaxial layer 11 (e.g., Figure 2 If we identify a), then the trench tilt angle of the deep trench 2 is in the range of 0-10°. Specifically, during selective deep trench etching, by adjusting parameters such as the ratio of etching to passivation gas, chamber pressure, and bias power, the sidewalls of the etched trench can be made to have a slightly tilted shape (i.e., wider at the top and narrower at the bottom). The trench tilt angle range is 0-10°, which can optimize the filling quality of the second epitaxial layer 21 in the deep trench 2. The slightly tilted sidewalls of the deep trench 2 can also mitigate the sharp corner effect at the bottom of the trench, avoid local electric field concentration caused by abrupt changes in geometry, and thus improve the breakdown stability of the device.

[0070] Preferably, the groove inclination angle of the deep groove 2 is 6°.

[0071] Preferably, the trench width of the deep trench 2, i.e. the width of the P-pillar region, is configured to be greater than 0.3 μm. It should be noted that the "trench width" here refers to the horizontal distance between the opposite sidewalls of the deep trench 2 in the direction parallel to the surface of the substrate 1. Since the sidewalls of the deep trench 2 may have a certain tilt angle, the trench width can refer to the width at the top opening of the trench, or it can refer to the width of the trench body in the middle or bottom. In the superjunction power device, the P-pillar region and the adjacent N-pillar region (i.e., the part of the first epitaxial layer 11 located between adjacent deep trenches 2) need to meet the charge balance condition, that is, the total amount of P-type doping is matched with the total amount of N-type doping. Under the premise of meeting the charge balance, this embodiment optimizes the width of the P-pillar region to reduce the resistance contribution caused by the JFET effect, thereby further reducing the on-resistance of the device and improving the device performance.

[0072] S103, shallow trenches 3 are formed on each deep trench 2, located opposite to the sidewalls of the deep trench 2. The profile of one sidewall of the shallow trench 3 coincides with the interface between the first epitaxial layer 11 and the second epitaxial layer 21. A trench grid structure 4 is formed on the shallow trench 3.

[0073] In this embodiment, after the deep trench 2 is filled with a P-pillar region (i.e., the second epitaxial layer 21) and planarized, the shallow trench 3 formation process continues.

[0074] For details, please refer to Figure 4 and Figure 5 A barrier layer (such as a silicon oxide or silicon nitride hard mask layer) is prepared above the first epitaxial layer 11, the second epitaxial layer 21 and the deep trench 2, and the pattern of the shallow trench 3 is defined by photolithography. As an optional implementation, the shallow trench 3 is configured to be formed in each deep trench 2 and located relative to the sidewall of the deep trench 2.

[0075] That is, a shallow trench 3 is formed on each deep trench 2 relative to the sidewall of the deep trench 2, including selectively etching the shallow trench 3 under the mask and the barrier layer on the first epitaxial layer 11 to obtain a shallow trench 3 embedded in the second epitaxial layer 21 in the deep trench 2.

[0076] Among them, the shallow trench 3 has a second trench depth (e.g. Figure 4 (Identified H2), the second trench depth is less than the first trench depth, ensuring that the trench gate structure formed in the subsequent shallow trench 3 is completely contained in the upper region of the deep trench 2, avoiding the bottom of the trench gate structure from penetrating below the bottom of the deep trench 2 or touching the N-type drift region, thereby preventing the risk of breakdown caused by punch-through or electric field concentration between the gate and the drain region.

[0077] And the sidewalls of the shallow trench 3 have an inclined angle relative to the horizontal surface of the substrate 1 or the first epitaxial layer 11 (e.g., Figure 4If we identify b), then the trench tilt angle of shallow trench 3 is the same as that of deep trench 2. That is to say, during the etching process of shallow trench 3, a process formula similar to that of deep trench 2 is used (e.g., the same etching gas ratio, chamber pressure and bias power), so that the sidewall of shallow trench 3 also has a taper angle that is basically the same as that of deep trench 2 (e.g., controlled within the range of 0-10°). This is to facilitate the better embedding of the subsequent trench gate structure into the second epitaxial layer 21 of deep trench 2, so that the dielectric layer and polysilicon of the subsequent trench gate structure can be uniformly covered and filled in the trench, avoiding local stress concentration or filling voids caused by abrupt angle changes.

[0078] Preferably, the second trench depth of the shallow trench 3 is in the range of 0.5-2um, so as to balance the contribution of channel resistance and JFET resistance, avoid excessive increase in channel resistance due to excessive trench depth, and thus maintain a low on-resistance while reducing cell size.

[0079] Therefore, the contour of one sidewall of the shallow trench 3 coincides with the interface of the first epitaxial layer 11 and the second epitaxial layer 21, so that the trench gate formed subsequently can simultaneously generate electric field coupling with the P-pillar region (second epitaxial layer 21) and the N-pillar region (first epitaxial layer 11), thereby optimizing the charge distribution in the channel region. At the same time, it is convenient to form a trench gate structure embedded in the deep trench 2. Since the trench gate structure is directly formed in the shallow trench 3 on the deep trench 2, and one sidewall of the shallow trench 3 coincides with the PN junction interface, the gate no longer needs to occupy the lateral space of the adjacent N-pillar region. Compared with the gate layout method in the traditional structure, this embodiment significantly saves the functional area layout area, thereby enabling more cells to be integrated in a unit area, effectively reducing the cell size. The reduction in cell size means that the cell density can be increased and the number of current paths can be increased in the same chip area. At the same time, since the trench gate structure is embedded above the P-pillar region, the current path between the channel region and the P-pillar region is more direct, which is beneficial to reduce the channel resistance and the additional resistance caused by the JFET effect, and improve the device performance.

[0080] In one example, a trench grid structure 4 is formed on the shallow trench 3, specifically including:

[0081] I. A thick oxide layer is formed in the shallow trench 3, and the thick oxide layer at the bottom of the shallow trench 3 is retained by the etch back to obtain the TBO layer 31.

[0082] Specifically, a thick oxide layer is deposited or formed in the shallow trench 3 using high-density plasma chemical vapor deposition to ensure that the thick oxide layer can fill the internal space of the shallow trench 3 without voids. Then, the thick oxide layer is etched back. By controlling the etch-back time and etching selectivity, the thick oxide layer above the shallow trench 3 and part of the thick oxide layer on the trench sidewall are gradually removed until the sidewall of the upper part of the shallow trench 3 is exposed. When the etching stops, only a certain thickness of thick oxide layer is left at the bottom of the shallow trench 3, thereby forming the TBO layer 31.

[0083] It should be noted that the thickness of the TBO layer 31 is greater than the thickness of the gate dielectric layer formed subsequently, so as to mitigate the edge electric field intensity at the bottom of the trench gate when the device is turned off, avoid breakdown or reliability degradation caused by electric field concentration, and thus improve the hot carrier injection effect of the device.

[0084] II. After the sacrificial oxide layer is formed in the shallow trench 3, the sacrificial oxide layer is removed.

[0085] Specifically, after forming the TBO layer 31, the device undergoes sacrificial oxidation treatment. The device is placed in a high-temperature oxidizing atmosphere to grow a thin sacrificial oxide layer (not shown in the figure). This sacrificial oxide layer covers the exposed sidewalls of the shallow trench 3 and the surface of the TBO layer 31. The purpose of sacrificial oxidation is to remove the lattice damage layer and residual contaminants caused by the previous etching process on the surface of the trench sidewalls and to repair the silicon surface condition. Subsequently, the sacrificial oxide layer can be completely removed using a hydrofluoric acid-based solution. At this point, the sidewalls of the shallow trench 3 expose an atomically flat and clean silicon surface, providing a good interface for the subsequent growth of a high-quality gate dielectric layer.

[0086] III. After forming the gate dielectric layer 32 in the shallow trench 3, the gate polysilicon 33 is deposited into the shallow trench 3.

[0087] Specifically, a gate dielectric layer 32 is formed on the inner wall of the clean shallow trench 3. As an optional implementation, a gate dielectric layer 32 is grown on the sidewall of the shallow trench 3 and the surface of the TBO layer 31 using a thermal oxidation process. The thickness of the gate dielectric layer 32 can be controlled between 100 Å and 1000 Å. Alternatively, silicon nitride or other high-k dielectric materials can be deposited as the gate dielectric layer 32 using a chemical vapor deposition process.

[0088] After forming the gate dielectric layer 32, the gate conductive material is filled. Specifically, a low-pressure chemical vapor deposition process can be used to deposit doped polysilicon on the device surface. The polysilicon fully fills the internal space of the shallow trench 3. Then, the excess polysilicon outside the shallow trench 3 is removed by chemical mechanical polishing (CMP) or etch-back process, so that the gate polysilicon 33 is only retained inside the shallow trench 3, and its top is basically flush with the surface of the first epitaxial layer 11, forming a planarized structure.

[0089] Thus, a complete trench gate structure 4 is formed, which is composed of a bottom TBO layer 31, a sidewall gate dielectric layer 32, and an internally filled gate polysilicon 33.

[0090] S104, self-aligned ion implantation and annealing push-well are performed between adjacent deep trenches 2 on the first epitaxial layer 11 to form a body region 5 and a source region 6 located above the body region 5 and close to the trench gate structure 4.

[0091] In this step, refer to Figure 6 The self-aligned ion implantation technology is adopted, which does not require additional definition of photoresist pattern. It directly utilizes the blocking effect of the trench gate structure 4 on the implanted ions, preferably allowing P-type doped ions to be selectively implanted into the surface region of the first epitaxial layer 11 between adjacent deep trenches 2. Due to the presence of the trench gate structure 4, ions cannot penetrate the gate polysilicon 33 and the gate dielectric layer 32, thereby achieving self-alignment of the implantation region, that is, the body region 5 is formed in the region between adjacent trench gate structures 4.

[0092] After implantation, a high-temperature annealing process is performed. The annealing temperature can be controlled between 900℃ and 1150℃, and the annealing time varies from 30 seconds to several hours. During the annealing process, the implanted P-type impurities diffuse into the interior of the first epitaxial layer 11 to form a P-type body region with a certain depth and lateral distribution.

[0093] Next, the implantation process of source region 6 is carried out. The mask blocking implantation method is used to define the specific location of source region 6. Specifically, a photoresist layer is coated on the device surface, and an implantation window is opened above the body region 5 between adjacent trench gate structures 4 through photolithography. This window is close to the sidewall of the trench gate structure 4. Subsequently, N-type doping ions are preferably performed through the implantation window. The resulting source region 6 is located on the upper surface layer of the body region 5 and is adjacent to the sidewall of the trench gate structure 4.

[0094] After implantation, the photoresist layer is removed and a second annealing process is performed (which can be combined with the annealing of the body region 5, or a rapid thermal annealing can be performed separately). After annealing, the doped impurities in the source region 6 are activated and a heavily doped region with a certain junction depth is formed. The junction depth of the source region 6 should be less than the junction depth of the body region 5, and the source region 6 should be in direct contact with the sidewall of the trench gate structure 4 so as to facilitate subsequent contact hole connection.

[0095] S105, a contact hole region 7 is formed on the first epitaxial layer 11, which is respectively connected to one side of the source region 6 and the second epitaxial layer 21 in the deep trench 2.

[0096] In this step, refer to Figure 7 and Figure 8Contact hole regions 7 are formed on the first epitaxial layer 11, respectively connected to one side of the source region 6 and the second epitaxial layer 21 in the deep trench 2, so as to realize the electrical connection between the source region 6 and the P-pillar region (i.e. the second epitaxial layer 21) and the subsequent source metal.

[0097] Specifically, the contact hole region 7 includes:

[0098] First, an isolation dielectric layer 12 for the isolation trench gate structure 4 is formed on the first epitaxial layer 11. That is, an isolation dielectric layer 12 is deposited on the surface of the device with the completed gate structure. The isolation dielectric layer 12 covers the top of the trench gate structure 4 and the surface of the first epitaxial layer 11, and is used to electrically isolate the gate polysilicon 33 from the subsequently formed source metal. As an optional implementation, the isolation dielectric layer 12 can be a silicon dioxide layer formed by high-density plasma chemical vapor deposition process, or an oxide layer deposited by tetraethyl orthosilicate (TEOS) source, and chemical mechanical polishing or etch-back process can be performed as needed to obtain a planarized surface.

[0099] Preferably, the isolation dielectric layer 12 may include a two-layer structure, namely a pure silicon dioxide layer and a silicon dioxide layer doped with phosphorus and boron on its surface, and the isolation dielectric layer 12 is planarized by high-temperature reflow after deposition.

[0100] Secondly, a contact hole pattern is defined on the isolation dielectric layer 12 by photolithography and etched to form a contact hole region 7. The contact hole region 7 in this embodiment includes a first contact hole 71 and a second contact hole 72. That is, two first contact holes 71 located between adjacent deep trenches 2 and two second contact holes 72 located between adjacent trench gate structures 4 on the deep trenches 2 are obtained by making holes in the isolation dielectric layer 12 through a mask. The two first contact holes 71 are respectively connected to one side of each source region 6 in the body region 5, and the second contact hole 72 is connected to the second epitaxial layer 21.

[0101] Additionally, the first contact hole 71 and the second contact hole 72 are injected with ions of the same type as those in the body region 5 and then annealed to push the trap.

[0102] Then, an alloy layer 73 is deposited in the first contact hole 71 and the second contact hole 72, wherein the deposition material of the alloy layer 73 includes, but is not limited to, Ti / TiN / W.

[0103] This results in a "dual contact hole" structure design (i.e., each cell region contains two first contact holes 71 connecting the source region and a second contact hole 72 connecting the P-pillar region), which is beneficial for shunting the source current, increasing the effective lead-out area of ​​the body region 5, and thus improving the avalanche withstand capability of the device.

[0104] The depth of the first contact hole 71 and the second contact hole 72 is greater than the junction depth of the source region 6. This ensures that the first contact hole 71 can penetrate the source region 6 and enter the body region 5 below, creating conditions for subsequent body region contact injection, while ensuring that the second contact hole 72 can reliably expose the surface of the P-pillar region.

[0105] The etching tilt angle of the first contact hole 71 and the second contact hole 72 is less than 20°. The tilt angle mentioned here refers to the angle between the sidewall of the contact hole and the vertical direction. Controlling it within a small angle range is beneficial for the conformal coverage of the subsequent alloy layer 73 and avoids metal filling voids caused by excessively steep sidewalls.

[0106] S106, a source metal layer 8 covering the contact hole region 7 is formed on the first epitaxial layer 11, and a drain region 9 is formed on the back gold of the substrate 1.

[0107] In this step, the deposition material of the source metal layer 8 includes AlCu or AlSiCu, etc., so as to form a good ohmic contact with the alloy layer 73.

[0108] In one example, a passivation protection layer 81 is formed on the source metal layer 8 to isolate and protect the source metal layer 8, and a source / gate window is opened based on the passivation protection layer 81, and / or, a PI protection layer is formed on the source metal layer 8.

[0109] The passivation protection layer 81 may include a silicon nitride layer and a silicon oxide layer.

[0110] The drain region 9 is formed by back gold deposition on the substrate 1, which may include thinning the bottom surface of the substrate 1, wherein the thinning thickness includes 30-200um, and then depositing a metal layer on the bottom surface of the substrate 1 to form the drain region 9.

[0111] Preferably, the thickness is reduced to 150 μm.

[0112] The superjunction power device fabrication method provided in this application involves etching deep trenches 2 in the first N-type epitaxial layer 11 and filling them with a second P-type epitaxial layer 21 to form a superjunction structure. Based on this, shallow trenches 3 are formed within the P-pillar region of each deep trench 2, with one sidewall of the shallow trench 3 precisely aligned with the PN junction interface. This allows the trench gate structure 4 to be directly embedded within the P-pillar region. This design significantly saves gate space, resulting in a substantial reduction in cell size, an increase in the number of cells integrated per unit area, and a more direct current path. This effectively reduces channel resistance and the additional resistance caused by the JFET effect, achieving a reduction in the on-resistance per unit area of ​​the device. Simultaneously, by forming a "double contact hole" structure (i.e., two...) on the first epitaxial layer 11, connecting to one side of the source region 6 and the second epitaxial layer 21 within the deep trench 2 respectively... The first contact hole 71 and the second contact hole 72 effectively shunt the source current, increase the lead-out area of ​​the body region 5, and improve the discharge path of the body region current, thereby significantly improving the avalanche withstand capability of the device. In addition, during the formation of the trench gate structure 4 in the shallow trench 3, by depositing a thick oxide layer and etching back to retain only the TBO layer 31 at the bottom, the edge electric field intensity at the bottom of the trench gate is effectively mitigated, avoiding the breakdown risk and hot carrier injection effect caused by electric field concentration, and significantly improving the reliability and breakdown stability of the device. The above innovations do not require additional photomask layers or complex equipment, have good process compatibility and mass production feasibility, and ultimately achieve synergistic optimization of on-resistance, avalanche withstand capability and gate reliability while maintaining a high breakdown voltage, greatly improving the overall performance and market competitiveness of the device.

[0113] This application also discloses a superjunction power device, which is prepared by the superjunction power device fabrication method of any of the above embodiments, with reference to... Figure 8 The superjunction power device includes: a substrate 1, on which a first epitaxial layer 11 is disposed; deep trenches 2, a plurality of deep trenches 2 disposed on the first epitaxial layer 11, and a second epitaxial layer 21 disposed within the deep trenches 2; shallow trenches 3, in which trench gate structures 4 are disposed, and the shallow trenches 3 are located opposite each sidewall of the deep trenches 2, and the outline of one sidewall of the shallow trenches 3 coincides with the interface between the first epitaxial layer 11 and the second epitaxial layer 21; a body region 5 and a source region 6, disposed between adjacent deep trenches 2 on the first epitaxial layer 11, and the source region 6 is connected to the body region 5; a contact hole region 7, disposed on the first epitaxial layer 11, and respectively connected to one side of the source region 6 and the second epitaxial layer 21 within the deep trenches 2; a source metal layer 8, disposed on the first epitaxial layer 11 and covering the contact hole region 7; and a drain region 9, disposed on the side of the substrate 1 away from the first epitaxial layer 11.

[0114] In one example, the contact hole region 7 on the first epitaxial layer 11 includes a first contact hole 71 and a second contact hole 72; the two first contact holes 71 are located between adjacent deep trenches 2 and are respectively connected to one side of each source region 6 in the body region 5, and the second contact holes 72 are located between adjacent trench gate structures 4 on the deep trenches 2 and are connected to the second epitaxial layer 21.

[0115] For other working principles and processes of the superjunction power device in this embodiment, please refer to the description of the superjunction power device fabrication method in the foregoing embodiment, which will not be repeated here.

[0116] The superjunction power device and its fabrication method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. It should be noted that the descriptions of each embodiment in this application have different focuses, and parts not described in detail or in a certain embodiment can be referred to the relevant descriptions of other embodiments.

[0117] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. The technical features of the technical solution of this application can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are also included within the patent protection scope of this application, as long as the combination of these technical features does not contradict each other.

Claims

1. A method for fabricating a superjunction power device, characterized in that, include: A substrate is provided on which a first epitaxial layer of the same doping type is formed; A plurality of deep trenches are formed on the first epitaxial layer, and the deep trenches are filled with a second epitaxial layer with a different doping type than the first epitaxial layer; Shallow trenches are formed on each of the deep trenches relative to the sidewalls of the deep trenches, the sidewall profile of the shallow trenches coincides with the interface between the first epitaxial layer and the second epitaxial layer, and a trench gate structure is formed on the shallow trenches. Self-aligned ion implantation and annealing push-well are performed between adjacent deep trenches on the first epitaxial layer to form a body region and a source region located above the body region and close to the trench gate structure. Contact hole regions are formed on the first epitaxial layer, respectively connected to one side of the source region and the second epitaxial layer in the deep trench; A source metal layer covering the contact hole region is formed on the first epitaxial layer, and a drain region is formed on the substrate back gold.

2. The method for fabricating a superjunction power device as described in claim 1, characterized in that, The formation of a plurality of deep trenches on the first epitaxial layer includes: Selective deep trench etching is performed under the mask and barrier layer on the first epitaxial layer to obtain the deep trench with the first trench depth.

3. The method for fabricating a superjunction power device as described in claim 2, characterized in that, The depth of the first trench is less than the thickness of the first epitaxial layer, and the trench inclination angle of the deep trench is in the range of 0-10°.

4. The method for fabricating a superjunction power device as described in claim 2, characterized in that, The step of forming shallow trenches relative to the sidewalls of the deep trenches in each of the deep trenches includes: Selective shallow trench etching is performed under the mask and barrier layer on the first epitaxial layer to obtain the shallow trench embedded in the second epitaxial layer in the deep trench.

5. The method for fabricating a superjunction power device as described in claim 4, characterized in that, The shallow trench has a second trench depth, which is less than the first trench depth, and the trench inclination angle of the shallow trench is the same as that of the deep trench.

6. The method for fabricating a superjunction power device as described in claim 1, characterized in that, The formation of a trench grid structure on the shallow trench includes: A thick oxide layer is formed in the shallow trench, and the thick oxide layer at the bottom of the shallow trench is retained by etching back to obtain the TBO layer; After a sacrificial oxide layer is formed in the shallow trench, the sacrificial oxide layer is removed. After forming a gate dielectric layer in the shallow trench, gate polysilicon is deposited into the shallow trench.

7. The method for fabricating a superjunction power device as described in claim 1, characterized in that, The step of forming contact hole regions on the first epitaxial layer that are respectively connected to one side of the source region and the second epitaxial layer in the deep trench includes: An isolation dielectric layer is formed on the first epitaxial layer to isolate the trench gate structure; Two first contact holes are etched between adjacent deep trenches and a second contact hole is etched between adjacent trench gate structures on the deep trenches through a mask opening on the isolation dielectric layer. The two first contact holes are respectively connected to one side of each source region in the body region, and the second contact hole is connected to the second epitaxial layer. The first and second contact holes are injected with ions of the same type as those in the body region and then annealed to push the trap. An alloy layer is deposited in the first contact hole and the second contact hole.

8. The method for fabricating a superjunction power device as described in claim 7, characterized in that, The depth of the first contact hole and the second contact hole is greater than the source region junction depth, and the etching tilt angle of the first contact hole and the second contact hole is less than 20°.

9. A superjunction power device, fabricated by the superjunction power device fabrication method according to any one of claims 1 to 8, characterized in that, include: Substrate, wherein a first epitaxial layer is disposed on the substrate; A deep trench, wherein a plurality of the deep trenches are disposed on the first epitaxial layer, and a second epitaxial layer is disposed within the deep trenches; A shallow trench, wherein a trench grid structure is provided in the shallow trench, and the shallow trench is located opposite to the sidewall of each of the deep trenches, and the outline of one sidewall of the shallow trench coincides with the interface between the first epitaxial layer and the second epitaxial layer. The body region and the source region are disposed between adjacent deep trenches on the first epitaxial layer, and the source region is connected above the body region; The contact hole region is disposed on the first epitaxial layer and is respectively connected to one side of the source region and the second epitaxial layer in the deep trench; A source metal layer is disposed on the first epitaxial layer and covers the contact hole area; The drain region is located on the side of the substrate away from the first epitaxial layer.

10. The superjunction power device as described in claim 9, characterized in that, The contact hole region on the first epitaxial layer includes a first contact hole and a second contact hole; the two first contact holes are located between adjacent deep trenches and are respectively connected to one side of each source region in the body region; the second contact hole is located between adjacent trench gate structures on the deep trench and is connected to the second epitaxial layer.

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