SiC HEMT device structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a SiC HEMT device structure and a preparation method thereof. The SiC HEMT device structure comprises a 4H-SiC substrate, a silicon carbide layer and a silicon carbide layer, the 3C / 4H-SiC heterostructure layer is arranged on the 4H-SiC substrate, and the 3C / 4H-SiC heterostructure layer is formed by bonding a 4H-SiC barrier layer and a 3C-SiC channel layer which are sequentially stacked on the 4H-SiC substrate; the source electrode, the gate electrode and the drain electrode are horizontally arranged above the 3C / 4H-SiC heterostructure layer, the source electrode and the drain electrode are respectively in ohmic connection with the 3C / 4H-SiC heterostructure layer, and the gate electrode is in Schottky contact with the 3C / 4H-SiC heterostructure layer; the SiO2 passivation layers are arranged between the source electrode and the gate electrode and between the gate electrode and the drain electrode, and the SiO2 passivation layers are arranged on the 3C / 4H-SiC heterostructure layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a SiC HEMT device structure and its fabrication method. Background Technology

[0002] HEMT (High Electron Mobility Transistor) is a field-effect transistor based on a heterojunction structure. Its core operating principle relies on the high mobility of the two-dimensional electron gas (2DEG) at the heterojunction interface. Heterojunctions are typically composed of two semiconductor materials with similar lattices but significantly different band structures (such as AlGaN / GaN or AlGaAs / GaAs). Due to bandgap effects, a quantum potential well forms at the interface, generating a high density of undoped polarization charges through spontaneous polarization (the material's intrinsic dipole moment) and piezoelectric polarization (strain-induced polarization). These charges are localized within the potential well, forming a high concentration (>10¹³ cm⁻¹). - ²), a two-dimensional electron gas with high mobility (>2000 cm² / V·s). Unlike traditional MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), where electrons are confined by scattering from ionized impurities, electrons in a two-dimensional electron gas are restricted to a narrow region of approximately 10 nm at the heterojunction interface, physically isolated from the doping atoms of the parent material. This significantly reduces the scattering probability, increasing electron mobility to 5-10 times that of traditional silicon-based devices. This characteristic enables HEMTs to achieve a breakthrough combination of high-frequency (above GHz) and high-power (kW-level) performance. The current control mechanism of HEMT devices is achieved through gate voltage regulation. When a gate voltage is applied, the Schottky barrier or the electric field beneath the insulating layer controls the electron concentration in the two-dimensional electron gas channel, thereby controlling the conduction current between the source and drain. This fast response characteristic based on electric field regulation makes it an ideal choice for high-frequency switching, RF amplification, and high-efficiency power conversion.

[0003] Currently, while SiC (silicon carbide) devices perform excellently in high-temperature, high-voltage, and high-power applications, their high-frequency performance still needs improvement. Although GaN HEMTs (gallium nitride high electron mobility transistors) exhibit superior performance in high-frequency applications, their stability under high-temperature conditions is far inferior to that of SiC devices. AlGaN / GaN heterojunction HEMTs rely on the high concentration of 2DEGs formed at the heterojunction interface to achieve high-efficiency operation. However, the interdiffusion of elements due to differences in chemical composition on both sides of the heterojunction, as well as the large number of interface states caused by lattice constant mismatch, severely affect the overall performance of HEMT devices.

[0004] Most mainstream HEMT devices currently available employ GaN / AlGaN heterojunction structures, utilizing techniques such as grooved gates, multilayer heterojunctions, T-gates, and floating field plates. Innovations are made in device structure and fabrication processes, increasing performance by enhancing structural complexity. Some HEMT devices also utilize novel heterojunction structures such as AlN / Ga2O3 (aluminum nitride / gallium oxide).

[0005] In the design of traditional GaN HEMT devices, to alleviate the lattice mismatch problem at the heterojunction interface and the short-channel effect, a combination of AlN insertion layer and back barrier structure is usually adopted, that is, to construct a five-layer heterojunction stack structure of AlGaN / AlN / GaN / AlN / GaN (from top to bottom: barrier layer / space insertion layer / channel layer / back barrier layer / buffer layer). However, this introduces the following problems: Increased process complexity: Epitaxial growth of multilayer heterojunctions requires precise control of the thickness and interface quality of each layer. For example, the thickness of the AlN space insertion layer needs to be controlled to 1 nm, which greatly increases the difficulty and cost of MOCVD (metal-organic chemical vapor deposition) process.

[0006] The problem of interdiffusion of elements has not been solved: AlN insertion layers can only alleviate lattice mismatch, but the problem of interdiffusion of elements on both sides of the heterojunction still exists. Under high temperature operation or long-term bias stress, Al atoms diffuse into the GaN channel, resulting in the decay of 2DEG concentration.

[0007] Thermal expansion coefficient mismatch: Although the back barrier layer can enhance the confinement of 2DEG, the thermal expansion coefficients of AlN (4.2×10-6 / ℃ at 20℃~800℃) and GaN (17.5×10-6 / ℃ at 50℃~1000℃) are too different, and the device is prone to interface cracks during thermal cycling. Summary of the Invention

[0008] The purpose of this invention is to provide a SiC HEMT device structure to solve the problems of heterojunction interface lattice mismatch and short-channel effect in existing GaN HEMT devices, as well as element interdiffusion and thermal expansion coefficient mismatch.

[0009] To address the aforementioned problems, this invention proposes a SiC HEMT device structure, and the technical solution adopted is as follows: A SiC HEMT device structure, comprising: 4H-SiC substrate; The 3C / 4H-SiC heterostructure layer on the 4H-SiC substrate is formed by bonding a 4H-SiC barrier layer and a 3C-SiC channel layer sequentially stacked on the 4H-SiC substrate. The source electrode, gate electrode, and drain electrode are located horizontally above the 3C / 4H-SiC heterostructure layer, and the source electrode and drain electrode are ohmically connected to the 3C / 4H-SiC heterostructure layer, respectively, and the gate electrode is in Schottky contact with the 3C / 4H-SiC heterostructure layer. A SiO2 passivation layer is provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode. The SiO2 passivation layer is disposed on the 3C / 4H-SiC heterostructure layer, and the source electrode, the gate electrode and the drain electrode are spaced apart.

[0010] Furthermore, a two-dimensional electron gas channel is formed at the heterojunction interface of the 3C / 4H-SiC heterostructure layer, the two-dimensional electron gas channel contains two-dimensional electron gas, and the two-dimensional electron gas channel is connected to the source electrode and the drain electrode.

[0011] Furthermore, the bonding surface of the 3C-SiC channel layer is a (111) crystal plane, and the bonding surface of the 4H-SiC is a (000) crystal plane. Crystal facets.

[0012] Furthermore, the 4H-SiC barrier layer is epitaxially grown on the C-plane of the 4H-SiC substrate, and the thickness of the 4H-SiC barrier layer is 0.02-2 μm, with a doping concentration of high purity up to 10. 19 cm -3 .

[0013] Furthermore, the thickness of the 3C-SiC channel layer is 10-60 nm, and the doping concentration is high purity up to 10. 18 cm -3 The 4H-SiC substrate is a high-purity semi-insulator.

[0014] Furthermore, the SiO2 passivation layer is epitaxially grown from the surface of the 3C-SiC channel layer, and the thickness of the SiO2 passivation layer is consistent with the height of the source electrode, gate electrode, and drain electrode.

[0015] Furthermore, an insulating dielectric layer is disposed between the gate electrode and the 3C-SiC channel layer, and the width of the insulating dielectric layer is the same as the width of the gate electrode, and the thickness of the insulating dielectric layer is less than the thickness of the SiO2 passivation layer.

[0016] This invention also proposes a method for fabricating a SiC HEMT device structure, the technical solution of which is as follows: A method for fabricating a SiC HEMT device structure, comprising the following steps: S1, a 3C / 4H-SiC heterostructure layer is formed on a 4H-SiC substrate; S2, a source electrode and a drain electrode that are in ohmic contact with the 3C / 4H-SiC heterostructure layer are formed on the 3C / 4H-SiC heterostructure layer, and a gate electrode that is in Schottky contact with the 3C / 4H-SiC heterostructure layer is formed on the 3C / 4H-SiC heterostructure layer. S3, a SiO2 passivation layer is formed between the source electrode and the gate electrode and between the gate electrode and the drain electrode. The SiO2 passivation layer is disposed on the 3C / 4H-SiC heterostructure layer, and the source electrode, the gate electrode and the drain electrode are spaced apart.

[0017] Further, the formation of the 3C / 4H-SiC heterostructure layer on the 4H-SiC substrate includes: A 4H-SiC barrier layer is epitaxially grown on a 4H-SiC substrate, and a 3C-SiC channel layer is grown on a silicon substrate. The 4H-SiC barrier layer is bonded to the 3C-SiC thin film channel layer to form a 3C / 4H-SiC heterostructure layer.

[0018] Further, the formation of source and drain electrodes in ohmic contact with the 3C / 4H-SiC heterostructure layer, and gate electrode in Schottky contact with the 3C / 4H-SiC heterostructure layer, on the 3C / 4H-SiC heterostructure layer, includes: Alloy films were deposited on a 3C / 4H-SiC heterostructure layer using photolithography and electron beam evaporation processes, followed by high-temperature annealing, to obtain ohmic contact source and drain electrodes and Schottky contact gate electrodes.

[0019] Compared with the prior art, this application has the following beneficial effects: This invention is an improved version. It utilizes the excellent thermal conductivity of SiC and the spontaneous polarization effect of 4H-SiC, along with a novel 3C / 4H-SiC heterostructure layer composed of different crystal forms of the same elements. This reduces lattice mismatch and short-channel effects at the heterojunction interface with a simpler structure, while avoiding inter-element diffusion and thermal expansion coefficient mismatch problems. The result is a SiC HEMT device with excellent interface properties suitable for high-temperature, high-frequency applications. Compared to traditional HEMT device structures, it has the following advantages: With a simpler device structure, this invention achieves the same function with only a three-layer structure of 3C-SiC / 4H-SiC / 4H-SiC, compared to the AlGaN / AlN / GaN / AlN / GaN multilayer heterojunction structure of traditional GaN HEMT devices.

[0020] With smaller lattice mismatches, 3C-SiC has a cubic crystal system and 4H-Si has a hexagonal crystal system. As the same crystal material, the lattice mismatch between their bonding contact surfaces is negligible.

[0021] The lower coefficient of thermal expansion mismatch: 3C-SiC has an average coefficient of thermal expansion of 4.45 × 10⁻⁶ at 20℃-1000℃. -6 The average coefficient of thermal expansion of 4H-SiC in the range of 20℃-1000℃ is 4.4×10⁻⁶℃. -6 / ℃. Compared to AlN and GaN, the thermal expansion coefficients of 3C-SiC and 4H-SiC are closer, and the contact interface state will not easily deteriorate with temperature changes.

[0022] Higher high-temperature reliability: GaN has a thermal conductivity of 1.3 W / cm·K, while SiC has a thermal conductivity of 4.5 W / cm·K. Therefore, SiC HEMTs are more suitable for high-temperature environments than GaN HEMTs.

[0023] No diffusion of interface elements. Compared with traditional GaN HEMT devices, the 3C / 4H-SiC heterojunction in this invention has identical elements (both Si and C) on both sides of the interface, resulting in no diffusion contamination on both sides of the heterojunction interface and improving the reliability of the device.

[0024] A two-dimensional electron gas channel is formed at the heterojunction interface of the 3C / 4H-SiC heterostructure layer. This channel contains two-dimensional electron gas and is connected to both the source and drain electrodes. The 3C / 4H-SiC heterostructure layer excites the two-dimensional electron gas at the heterojunction interface, forming the two-dimensional electron gas channel connecting the source and drain electrodes. Due to the different band structures of 3C-SiC and 4H-SiC, an electron potential well is formed on one side of the 3C-SiC channel layer at the heterojunction interface, allowing the two-dimensional electron gas to move only in one direction. Simultaneously, electrons doped into the 4H-SiC barrier layer also flow into the potential well, further increasing the concentration of the two-dimensional electron gas at the interface.

[0025] The bonding surface of the 3C-SiC channel layer is the (111) crystal plane, and the bonding surface of the 4H-SiC is the (000) crystal plane. The two bonding planes are in contact and bonded, further reducing lattice mismatch.

[0026] The thickness of the 3C-SiC channel layer is 10-60 nm, and the doping concentration is high purity up to 10%. 18 cm -3 The 4H-SiC substrate is a high-purity semi-insulator. The high-purity semi-insulator nature of the 4H-SiC substrate effectively prevents vertical leakage (leakage from the channel layer to the substrate).

[0027] An insulating dielectric layer is disposed between the gate electrode and the 3C-SiC channel layer, and the width of the insulating dielectric layer is the same as the width of the gate electrode, while the thickness of the insulating dielectric layer is less than the thickness of the SiO2 passivation layer. The insulating dielectric layer can effectively prevent leakage current from the gate electrode, enabling the device to operate normally even when the gate voltage is positive. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the SiC HEMT device structure of the present invention; Figure 2 This is a diagram showing the conduction band structure and electron distribution of the SiC HEMT device structure of the present invention; Figure 3 This is a device transfer characteristic diagram of the SiC HEMT device structure of the present invention; Figure 4 This is a diagram showing the device output characteristics of the SiC HEMT device structure of the present invention; Figure 5 This is a diagram of the SiC HEMT device structure with an oxide layer in this invention. Figure 6 This is a diagram showing the device transfer characteristics with an oxide layer in the SiC HEMT device structure of the present invention; In the figure, 1 is the 4H-SiC substrate, 2 is the 4H-SiC barrier layer, 3 is the 3C-SiC channel layer, 4 is the source electrode, 5 is the gate electrode, 6 is the drain electrode, 7 is the SiO2 passivation layer, and 8 is the oxide layer. Detailed Implementation

[0029] As cited in the background section, existing GaN HEMT devices are prone to heterojunction interface lattice mismatch and short-channel effects, as well as elemental interdiffusion and thermal expansion coefficient mismatch. Therefore, this invention provides a SiC HEMT device structure comprising: a 4H-SiC substrate, which prevents leakage in the vertical direction of the device (leakage from the 3C-SiC channel layer to the 4H-SiC substrate); a 3C / 4H-SiC heterostructure layer on the 4H-SiC substrate, wherein the 3C / 4H-SiC heterostructure layer is formed by bonding a 4H-SiC barrier layer and a 3C-SiC channel layer sequentially stacked on the 4H-SiC substrate; wherein the 4H-SiC barrier layer is the main providing layer for the two-dimensional electron gas, through which the 4H-SiC... A two-dimensional electron gas is formed at the junction interface of the 3C / 4H-SiC heterostructure layer through spontaneous polarization and doping. The 3C-SiC channel layer is a conductive layer, and the potential well formed by the 3C / 4H-SiC heterostructure layer confines electrons from the 4H-SiC barrier layer within a nanometer-thickness, preventing electrons from flowing vertically and transforming them into a two-dimensional electron gas. Simultaneously, the interface quality of the 3C / 4H-SiC heterostructure layer is better, with higher electron mobility and fewer defects, due to the bonding between the 4H-SiC barrier layer and the 3C-SiC channel layer. A source electrode, gate electrode, and drain electrode are positioned horizontally above the 3C / 4H-SiC heterostructure layer, with the source and drain electrodes ohmically connected to the 3C / 4H-SiC heterostructure layer, and the gate electrode in a Schottky contact with the 3C / 4H-SiC heterostructure layer. The electron concentration in the channel layer is controlled by applying a negative voltage to deplete the electrons below the gate. A SiO2 passivation layer is disposed between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, on the 3C / 4H-SiC heterostructure layer, such that the source electrode, gate electrode, and drain electrode are spaced apart. The SiO2 passivation layer suppresses surface states and traps on the upper surface of the 3C-SiC channel layer, and also acts as a physical barrier to prevent external elements from contacting the 3C-SiC channel layer. The SiC HEMT device of this application is less prone to heterojunction interface lattice mismatch and short-channel effects, and also avoids elemental interdiffusion and thermal expansion coefficient mismatch.

[0030] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Specific embodiment 1 of the SiC HEMT device structure of the present invention: In this embodiment, as Figure 1 As shown, the SiC HEMT device structure includes a 4H-SiC substrate 1 and a 3C / 4H-SiC heterostructure layer on the 4H-SiC substrate 1. The 3C / 4H-SiC heterostructure layer is formed by bonding a 4H-SiC barrier layer 2 and a 3C-SiC channel layer 3 sequentially stacked on the 4H-SiC substrate 1. Specifically, the SiC HEMT device structure, from bottom to top, consists of a 4H-SiC substrate 1, a 4H-SiC barrier layer 2, and a 3C-SiC channel layer 3. Here, an inverted HEMT device structure is used, with the 4H-SiC barrier layer 2 placed in the lower layer and the 3C-SiC channel layer 3 placed in the upper layer. A source electrode 4, a gate electrode 5, and a drain electrode 6 are positioned horizontally above the 3C / 4H-SiC heterostructure layer. The source electrode 4 and the drain electrode 6 are ohmically connected to the 3C / 4H-SiC heterostructure layer, and the gate electrode 5 is in Schottky contact with the 3C / 4H-SiC heterostructure layer. A SiO2 passivation layer 7 is disposed on the 3C / 4H-SiC heterostructure layer between the source electrode 4 and the gate electrode 5, and between the gate electrode 5 and the drain electrode 6. The SiO2 passivation layer 7 is disposed on the 3C / 4H-SiC heterostructure layer, and the source electrode 4, the gate electrode 5, and the drain electrode 6 are spaced apart, i.e., the source electrode 4, the gate electrode 5, and the drain electrode 6 do not contact each other.

[0033] Specifically, the average coefficient of thermal expansion of 3C-SiC is 4.45 × 10⁻⁶ °C between 20 °C and 1000 °C. -6 The average coefficient of thermal expansion of 4H-SiC in the range of 20℃-1000℃ is 4.4×10⁻⁶℃. -6 / ℃; 3C-SiC has a cubic crystal system, and 4H-SiC has a hexagonal crystal system. The bonding plane of the 3C-SiC channel layer 3 is the (111) crystal plane, and the bonding plane of 4H-SiC is the (000) crystal plane. (111) crystal plane and (000) crystal plane When crystal planes are in contact, as materials of the same crystal, the lattice mismatch between the contact surfaces is negligible.

[0034] In this embodiment, a two-dimensional electron gas channel is formed at the heterojunction interface of the 3C / 4H-SiC heterostructure layer. The two-dimensional electron gas channel contains a two-dimensional electron gas and is connected to the source electrode 4 and the drain electrode 6. The 3C / 4H-SiC heterostructure layer is formed by utilizing the spontaneous polarization effect of 4H-SiC, and a two-dimensional electron gas 2DEG is excited at the heterojunction interface of the 3C / 4H-SiC heterostructure layer, forming a two-dimensional electron gas conductive channel connecting the source electrode 4 and the drain electrode 6.

[0035] Specific embodiment 2 of the SiC HEMT device structure of the present invention: Based on the above-described technical concept of the present invention, or based on the specific embodiments of the present invention described above, another embodiment is provided below.

[0036] In this embodiment, as Figure 1 As shown, the 4H-SiC barrier layer 2 is epitaxially grown on the C-plane of the 4H-SiC substrate 1, and the thickness of the 4H-SiC barrier layer 2 is 0.02-2 μm, with a doping concentration of high purity up to 10. 19 cm -3 The thickness of the 3C-SiC channel layer 3 is 10-60 nm, and the doping concentration is high purity up to 10. 18 cm -3 Here, the performance parameters of the device, such as threshold voltage, transconductance, cutoff frequency, and breakdown voltage, can be changed by altering the doping concentration and thickness of the 4H-SiC barrier layer 2 or the 3C-SiC channel layer 3.

[0037] Among them, the 4H-SiC substrate 1 is a high-purity semi-insulating 4H-SiC substrate. The SiO2 passivation layer 7 is epitaxially grown from the surface of the 3C-SiC channel layer 3, and the thickness of the SiO2 passivation layer 7 is consistent with the height of the source electrode 4, the gate electrode 5 and the drain electrode 6.

[0038] Specifically, the specific parameters of the SiC HEMT device structure are set as shown in Table 1 below: Table 1 Specific parameters of SiC HEMT device structure

[0039] Based on the specific parameters of the SiC HEMT device structure described above, due to the different band structures of 3C-SiC and 4H-SiC, an electron potential well will form on the 3C-SiC channel layer 3 side of the heterojunction interface of the 3C / 4H-SiC heterostructure layer, where the two-dimensional electron gas (2DEG) can only move in one direction. Simultaneously, electrons doped into the 4H-SiC barrier layer 2 will also flow into the electron potential well, further increasing the concentration of the two-dimensional electron gas at the interface. The final band structure and electron distribution are as follows: Figure 2 As shown, there is a distinct two-dimensional electron gas channel and an extremely high two-dimensional electron gas concentration (>1×10⁻⁶) at the heterojunction interface of the heterostructure layer (Distance=2.2μm). 20 cm -3 ).

[0040] The operating mode of the SiC HEMT device structure corresponding to this embodiment is: When no bias voltage is applied, a high concentration of two-dimensional electron gas (2DEG) exists in the channel of the 3C / 4H-SiC heterostructure layer. When the SiC HEMT device is operating, a negative voltage is applied to the gate electrode 5, a positive voltage is applied to the drain electrode 6, and the source electrode 4 is grounded.

[0041] Where: when the gate-source voltage (V gs Less than the threshold voltage (V) th When the electrons in the two-dimensional electron gas channel are pinched off, no current flows, and the SiC HEMT device is in the off state. When the gate-source voltage is V gs Greater than the threshold voltage V th And drain-source voltage (V ds When the voltage is small, the electric field strength of the two-dimensional electron gas channel is low; as the drain-source voltage V increases... ds As V increases, the drain-source current increases with V ds The increase is approximately linear, and the SiC HEMT device is in a linear state. When the gate-source voltage is V gs Greater than the threshold voltage V th And the drain-source voltage V ds When the voltage is large, the pinch-off point of the two-dimensional electron gas channel moves towards the source electrode 4, forming a depletion region between the two-dimensional electron gas channel and the drain region. At this time, the drift velocity of electrons in the depletion region reaches the saturation velocity and no longer changes with the electric field. The output current also no longer changes with the voltage, and the SiC HEMT device is in a saturated state. Based on this, the transfer and output characteristics of the SiC HEMT device are as follows: Figure 3 , Figure 4 As shown.

[0042] In other embodiments, the thickness of the SiO2 passivation layer 7 may not be consistent with the heights of the source electrode 4, the gate electrode 5, and the drain electrode 6.

[0043] Specific embodiment 3 of the SiC HEMT device structure of the present invention: Based on the above-described technical concept of the present invention, or based on the specific embodiments of the present invention described above, another embodiment is provided below.

[0044] In this embodiment, as Figure 5 As shown, an insulating dielectric layer is disposed between the gate electrode 5 and the 3C-SiC channel layer 3, and the width of the insulating dielectric layer is the same as the width of the gate electrode 5, while the thickness of the insulating dielectric layer is less than the thickness of the SiO2 passivation layer 7. The insulating dielectric layer is an oxide layer 8. The oxide layer 8 prevents leakage current from the gate electrode 5, allowing the device to operate normally even when the gate voltage is positive, but it will correspondingly reduce the threshold voltage. Its transfer characteristic curve is shown in the figure. Figure 6 As shown.

[0045] Specific embodiment 1 of the method for fabricating the SiC HEMT device structure of the present invention: The fabrication method of SiC HEMT device structure includes the following steps: S1, a 3C / 4H-SiC heterostructure layer is formed on a 4H-SiC substrate 1; S2, a source electrode 4 and a drain electrode 6 that are in ohmic contact with the 3C / 4H-SiC heterostructure layer are formed on the 3C / 4H-SiC heterostructure layer, and a gate electrode 5 that is in Schottky contact with the 3C / 4H-SiC heterostructure layer is formed on the 3C / 4H-SiC heterostructure layer. S3, a SiO2 passivation layer 7 is formed between the source electrode 4 and the gate electrode 5 and between the gate electrode 5 and the drain electrode 6. The SiO2 passivation layer 7 is disposed on the 3C / 4H-SiC heterostructure layer, and the source electrode 4, the gate electrode 5 and the drain electrode 6 are spaced apart.

[0046] The formation of a 3C / 4H-SiC heterostructure layer on a 4H-SiC substrate 1 includes: epitaxially growing a 4H-SiC barrier layer 2 on the 4H-SiC substrate 1, and growing a 3C-SiC channel layer 3 on a silicon substrate; the 4H-SiC barrier layer 2 and the 3C-SiC channel layer 3 are bonded to form the 3C / 4H-SiC heterostructure layer.

[0047] A source electrode 4 and a drain electrode 6 that are in ohmic contact with the 3C / 4H-SiC heterostructure layer are formed on the 3C / 4H-SiC heterostructure layer, and a gate electrode 5 that is in Schottky contact with the 3C / 4H-SiC heterostructure layer is formed on the 3C / 4H-SiC heterostructure layer. This includes: depositing an alloy thin film on the 3C / 4H-SiC heterostructure layer by photolithography and electron beam evaporation processes, followed by high-temperature annealing, to obtain the ohmic contact source electrode 4 and drain electrode 6 and the Schottky contact gate electrode 5.

[0048] Specifically, the fabrication method of the SiC HEMT device structure includes the following steps: Step 1: Take a double-sided polished high-purity semi-insulating 4H-SiC substrate 1, and epitaxially grow a doping concentration of 10 on the C-plane of the 4H-SiC substrate 1. 17 The 4H-SiC barrier layer 2 was formed and chemical mechanical polishing (CMP) was performed to reduce the surface states and reduce the thickness of the 4H-SiC barrier layer 2 to 200 nm. Step 2: Take a silicon substrate, grow a 3C-SiC thin film on the silicon substrate, and perform CMP to reduce its surface states; Step 3: The 4H-SiC barrier layer 2 obtained in Step 1 is brought into contact with the 3C-SiC thin film obtained in Step 2 and bonded to obtain a 3C / 4H-SiC heterostructure layer. Step 4: Remove the silicon substrate on top of the 3C / 4H-SiC heterostructure layer using CMP and reduce the thickness of the 3C-SiC channel layer 3 to 20nm; Step 5: Deposit an alloy thin film using photolithography and electron beam evaporation processes, and perform high-temperature annealing to obtain the ohmic contact source electrode 4 and drain electrode 6; Step 6: Deposit an alloy thin film using photolithography and electron beam evaporation processes, and perform high-temperature annealing to obtain the Schottky contact gate electrode 5; Step 7: Grow a SiO2 passivation layer 7 on the surface of the 3C-SiC channel layer 3.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. The scope of patent protection of the present invention shall be determined by the claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention shall also be included within the scope of protection of the present invention.

Claims

1. A SiC HEMT device structure, characterized in that, include: 4H-SiC substrate (1); The 3C / 4H-SiC heterostructure layer on the 4H-SiC substrate (1) is formed by bonding a 4H-SiC barrier layer (2) and a 3C-SiC channel layer (3) sequentially stacked on the 4H-SiC substrate (1). The source electrode (4), gate electrode (5) and drain electrode (6) are located horizontally above the 3C / 4H-SiC heterostructure layer, and the source electrode (4) and drain electrode (6) are ohmically connected to the 3C / 4H-SiC heterostructure layer, and the gate electrode (5) is in Schottky contact with the 3C / 4H-SiC heterostructure layer. A SiO2 passivation layer (7) is disposed on a 3C / 4H-SiC heterostructure layer between the source electrode (4) and the gate electrode (5) and between the gate electrode (5) and the drain electrode (6), and the source electrode (4), the gate electrode (5) and the drain electrode (6) are spaced apart.

2. The SiC HEMT device structure according to claim 1, characterized in that, A two-dimensional electron gas channel is formed at the heterojunction interface of the 3C / 4H-SiC heterostructure layer. The two-dimensional electron gas channel contains two-dimensional electron gas and is connected to the source electrode (4) and the drain electrode (6).

3. The SiC HEMT device structure according to claim 1, characterized in that, The bonding surface of the 3C-SiC channel layer (3) is the (111) crystal plane, and the bonding surface of the 4H-SiC is the (000) crystal plane. Crystal facets.

4. The SiC HEMT device structure according to claim 1, characterized in that, The 4H-SiC barrier layer (2) is epitaxially grown on the C-plane of the 4H-SiC substrate (1), and the thickness of the 4H-SiC barrier layer (2) is 0.02-2 μm, with a doping concentration of high purity up to 10. 19 cm -3 .

5. The SiC HEMT device structure according to claim 1, characterized in that, The thickness of the 3C-SiC channel layer (3) is 10-60 nm, and the doping concentration is high purity up to 10. 18 cm -3 The 4H-SiC substrate is a high-purity semi-insulator.

6. The SiC HEMT device structure according to claim 1, characterized in that, The SiO2 passivation layer (7) is epitaxially grown from the surface of the 3C-SiC channel layer (3), and the thickness of the SiO2 passivation layer (7) is consistent with the height of the source electrode (4), the gate electrode (5) and the drain electrode (6).

7. The SiC HEMT device structure according to claim 1, characterized in that, An insulating dielectric layer is provided between the gate electrode (5) and the 3C-SiC channel layer (3), and the width of the insulating dielectric layer is the same as the width of the gate electrode (5), and the thickness of the insulating dielectric layer is less than the thickness of the SiO2 passivation layer (7).

8. A method for fabricating a SiC HEMT device structure, characterized in that, The fabrication of the SiC HEMT device structure as described in any one of claims 1-7 includes the following steps: S1, a 3C / 4H-SiC heterostructure layer is formed on a 4H-SiC substrate (1); S2, a source electrode (4) and a drain electrode (6) that are in ohmic contact with the 3C / 4H-SiC heterostructure layer are formed on the 3C / 4H-SiC heterostructure layer, and a gate electrode (5) that is in Schottky contact with the 3C / 4H-SiC heterostructure layer is formed on the 3C / 4H-SiC heterostructure layer. S3, a SiO2 passivation layer (7) is formed between the source electrode (4) and the gate electrode (5) and between the gate electrode (5) and the drain electrode (6). The SiO2 passivation layer (7) is disposed on the 3C / 4H-SiC heterostructure layer, and the source electrode (4), the gate electrode (5) and the drain electrode (6) are spaced apart.

9. The method for fabricating the SiC HEMT device structure according to claim 8, characterized in that, The formation of a 3C / 4H-SiC heterostructure layer on a 4H-SiC substrate (1) includes: A 4H-SiC barrier layer (2) is epitaxially grown on a 4H-SiC substrate (1), and a 3C-SiC channel layer (3) is grown on a silicon substrate. The 4H-SiC barrier layer (2) is bonded to the 3C-SiC thin film channel layer to form a 3C / 4H-SiC heterostructure layer.

10. The method for fabricating the SiC HEMT device structure according to claim 9, characterized in that, The source electrode (4) and drain electrode (6) formed on the 3C / 4H-SiC heterostructure layer in ohmic contact with the 3C / 4H-SiC heterostructure layer, and the gate electrode (5) in Schottky contact with the 3C / 4H-SiC heterostructure layer, include: Alloy films were deposited on the 3C / 4H-SiC heterostructure layer by photolithography and electron beam evaporation, followed by high-temperature annealing to obtain the ohmic contact source electrode (4) and drain electrode (6) and the Schottky contact gate electrode (5).

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