Two-dimensional extensible germanium hole quantum bit array device and preparation method thereof

Abstract

The invention provides a two-dimensional extensible germanium hole quantum bit array device and a preparation method thereof. The device comprises a germanium-silicon heterojunction substrate which comprises a germanium quantum well layer, a silicon-germanium barrier layer and a silicon cover layer from bottom to top; the plurality of source-drain ohmic contact regions penetrate through the silicon cover layer and the silicon-germanium barrier layer and form ohmic contact with the germanium quantum well layer; the multiple gate dielectric layers are arranged on the upper surface of the silicon cover layer; the quantum dot control region is located above the multiple gate dielectric layers and comprises multiple layers of quantum dot electrodes, and the multiple layers of quantum dot electrodes comprise a guide gate electrode, a shielding gate electrode, a barrier gate electrode and a plunger gate electrode; the multiple layers of quantum dot electrodes are stacked and arranged in a periodic mode and are electrically isolated from one another through the gate dielectric layer; and the plurality of peripheral connection electrodes and the plurality of peripheral electrodes are electrically connected with the corresponding quantum dot electrodes. The quantum dot gates of the device are independent and controllable, nearest neighbor coupling can be flexibly adjusted, and the device has good two-dimensional expansibility and CMOS process compatibility.

Description

Two-dimensional scalable germanium hole qubit array device and its fabrication method Technical Field

[0001] This invention belongs to the field of quantum computing, specifically relating to a two-dimensional scalable germanium hole qubit array device and its fabrication method. Background Technology

[0002] Quantum computing, a novel information processing method following the laws of quantum mechanics, utilizes the physical properties of superposition and entanglement in its core qubits, exhibiting computing power far exceeding that of classical computers for specific problems. A key challenge in realizing practical quantum computing lies in constructing qubit arrays with a sufficient number of qubits that can maintain coherence over long periods. Among various qubit implementation schemes, semiconductor quantum dot systems are considered one of the important pathways to practical quantum computing due to their small feature size, compatibility with modern semiconductor manufacturing processes, and potential for large-scale expansion.

[0003] In the material systems of semiconductor quantum computing, quantum well structures (such as germanium-silicon (Ge / SiGe) heterojunctions) are an important platform for constructing high-performance qubits. This structure, composed of semiconductor layers of specific compositions, effectively confines the longitudinal movement of charge carriers (electrons or holes). Among numerous materials, germanium (Ge)-based materials exhibit unique advantages: germanium holes possess relatively light effective mass, are valley-free degeneracy, have a large and tunable g-factor, and inherently strong spin-orbit coupling. These properties enable germanium hole-based spin qubits, compared to Si / SiGe heterojunction-based electron spin qubits, to not only achieve rapid manipulation through fully electronic control but also possess a longer coherent lifetime. Furthermore, the Ge / SiGe material system is highly compatible with mainstream silicon-based microelectronic processes, providing a promising technological path for constructing large-scale quantum processors.

[0004] To realize quantum computing with practical applications, large-scale two-dimensional scaling of qubits is essential. The capability of a quantum computing system is directly influenced by the number of qubits and their controllability. However, current quantum dot scaling technologies face significant challenges. Existing schemes are mostly based on one-dimensional linear arrays or shared-gate structures. One-dimensional arrays can only scale the number of qubits in a single direction, limiting their scalability and making it difficult to achieve complex quantum entanglement network connections. While shared-gate qubit arrays can scale in a two-dimensional plane, they cannot independently and precisely control the electrochemical potential of each quantum dot, nor can they independently adjust the tunneling coupling strength between nearest-neighbor qubits, which poses difficulties for high-fidelity qubit manipulation. Therefore, developing a quantum dot array structure with good scalability in a two-dimensional plane, supporting independently controllable gates and flexibly adjusting nearest-neighbor couplings has become a key requirement for promoting the development of semiconductor quantum computing. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention aims to provide a two-dimensional scalable germanium hole qubit array device and its fabrication method, which at least partially solves the technical problems of the two-dimensional arrangement limitation of qubit arrays and the inability to support independent controllable gates in the prior art.

[0006] This invention provides a two-dimensional scalable germanium hole qubit array device, comprising: a germanium-silicon heterojunction substrate, including a germanium quantum well layer, a silicon-germanium barrier layer, and a silicon capping layer arranged sequentially from bottom to top; multiple source-drain ohmic contact regions, which penetrate the silicon capping layer and the silicon-germanium barrier layer and form ohmic contacts with the germanium quantum well layer; a multilayer gate dielectric layer disposed on the upper surface of the silicon capping layer; a quantum dot control region located above the multilayer gate dielectric layer, including multiple quantum dot electrodes, each of which includes: a guiding gate electrode for forming an electron pool and connecting the source / drain to the quantum dot; a multilayer shielding gate electrode for shielding the electric field interference generated by the upper gate; a multilayer barrier gate electrode for adjusting the electron tunneling coupling strength between adjacent quantum dots; and a multilayer plunger gate electrode for controlling the electrochemical potential of the quantum dot; wherein the multilayer quantum dot electrodes are stacked in a periodic manner and electrically isolated from each other by the multilayer gate dielectric layer; and multiple peripheral connection electrodes and multiple peripheral leads, corresponding one-to-one with the quantum dot electrodes in the quantum dot control region, with each peripheral connection electrode connected to the corresponding quantum dot electrode via a peripheral lead.

[0007] According to an embodiment of the present invention, from a top view, the quantum dot control region is divided into a core region, a fan-out region, and an interconnection region; wherein, the core region is located in the central region and includes multiple qubits and multiple charge-sensing quantum dots; the fan-out region surrounds the core region and is used to initially disperse and lead out the densely arranged quantum dot electrodes; the interconnection region is located in the outer region of the fan-out region and is used to further expand the lead spacing of the quantum dot electrodes to adapt to the peripheral connection electrodes.

[0008] According to an embodiment of the present invention, in the core region, odd-numbered rows of qubits and even-numbered rows of qubits are alternately arranged in the column direction; and a barrier gate electrode is provided between every two adjacent layers of plunger gate electrodes.

[0009] According to an embodiment of the present invention, in the core region and the fan-out region, a shielding gate electrode is provided between any two adjacent barrier gate electrodes, and the shielding gate electrode is connected to the reference potential.

[0010] According to an embodiment of the present invention, in the fan-out region, the density of quantum dot electrode leads gradually decreases from the core region to the interconnect region, and the lead spacing gradually increases, achieving a smooth transition from high-density arrangement to peripheral connection.

[0011] Another aspect of the present invention provides a method for fabricating a two-dimensional scalable germanium hole qubit array device, comprising: providing a germanium-silicon heterojunction substrate, the germanium-silicon heterojunction substrate comprising a germanium quantum well layer, a silicon-germanium barrier layer and a silicon capping layer arranged sequentially from bottom to top; forming a plurality of source-drain ohmic contact regions on the germanium-silicon heterojunction substrate, the source-drain ohmic contact regions penetrating the silicon capping layer and the silicon-germanium barrier layer and forming ohmic contacts with the germanium quantum well layer; alternately forming a gate dielectric layer and quantum dot electrodes on the upper surface of the silicon capping layer to obtain a stacked structure comprising multiple gate dielectric layers and multiple quantum dot electrodes, the multiple quantum dot electrodes comprising a guide gate electrode, a shielding gate electrode, a barrier gate electrode and a plunger gate electrode, and the multiple quantum dot electrodes are stacked in a periodic manner and electrically isolated from each other by the multiple gate dielectric layers; forming a plurality of peripheral connection electrodes and a plurality of peripheral leads, each peripheral connection electrode being electrically connected to the corresponding quantum dot electrode through the peripheral lead.

[0012] According to an embodiment of the present invention, a germanium-silicon heterojunction substrate is provided, comprising: providing a silicon substrate; forming a silicon buffer layer on the silicon substrate; forming a germanium buffer layer on the silicon buffer layer; forming a silicon-germanium buffer layer with a germanium concentration gradient on the germanium buffer layer; forming a silicon-germanium relaxation buffer layer with constant concentration and uniform strain relaxation on the silicon-germanium buffer layer; forming a strained germanium quantum well layer on the silicon-germanium relaxation buffer layer; forming a silicon-germanium barrier layer on the germanium quantum well layer; and forming a silicon capping layer on the silicon-germanium barrier layer.

[0013] According to embodiments of the present invention, forming multiple source-drain ohmic contact regions on a germanium-silicon heterojunction substrate includes: forming a first oxide insulating layer on a silicon capping layer; removing the first oxide insulating layer from the active region of the germanium-silicon heterojunction substrate to expose a portion of the silicon capping layer; forming a second oxide insulating layer in a portion of the exposed silicon capping layer; and forming multiple source-drain ohmic contact regions through the second oxide insulating layer, including any of the following schemes: Scheme 1: selectively removing a portion of the second oxide insulating layer to expose a window for the source-drain contact region; depositing a metal electrode within the window and performing an annealing treatment to allow the metal to diffuse into the germanium quantum well layer, thereby forming the source-drain ohmic contact region; Scheme 2: defining the source-drain region by P-type ion implantation and performing annealing activation; selectively removing the second oxide insulating layer to expose a window for the source and drain contact regions, thereby forming the source-drain ohmic contact region.

[0014] According to an embodiment of the present invention, alternatingly forming a gate dielectric layer and quantum dot electrodes on the upper surface of a silicon capping layer includes: forming a first gate dielectric layer on the silicon capping layer; forming a patterned guiding gate electrode on the first gate dielectric layer; forming a second gate dielectric layer on the guiding gate electrode; forming a first row of quantum dot electrodes and a last row of quantum dot electrodes on the second gate dielectric layer; sequentially forming a plurality of intermediate gate dielectric layers and corresponding quantum dot electrode layers, wherein each formed quantum dot electrode layer includes a symmetrically distributed nth row of quantum dot electrodes and a pi-nth row of quantum dot electrodes, where n is an integer greater than 1; and finally forming three consecutive rows of quantum dot electrodes in the central region; wherein the quantum dot electrodes include electrodes for controlling computational quantum dots and electrodes for controlling charge-sensing quantum dots.

[0015] According to an embodiment of the present invention, forming a plurality of peripheral connection electrodes and peripheral leads includes: forming a plurality of contact windows in the uppermost gate dielectric layer to expose the connection ends of each quantum dot electrode; forming a plurality of contact windows in the peripheral region of the source-drain ohmic contact region to expose the connection ends of the source-drain ohmic contact region; evaporating and patterning metal to form a plurality of peripheral connection electrodes and a plurality of peripheral leads, wherein the peripheral leads electrically connect the exposed quantum dot electrode connection ends to the corresponding peripheral connection electrodes, and simultaneously electrically connect the source-drain ohmic contact region to the corresponding peripheral connection electrodes.

[0016] As described above, the two-dimensional scalable germanium hole qubit array device and its fabrication method of the present invention have at least the following beneficial effects:

[0017] 1. This array supports scaling in a two-dimensional plane, enabling the number of qubits to be increased to the hundreds.

[0018] 2. Each quantum bit in the array is equipped with an independent gate control electrode, which can precisely control the electrochemical potential of each quantum bit and the coupling strength between it and its nearest neighbor quantum bit.

[0019] 3. The semiconductor manufacturing process used in this invention is compatible with the current mature CMOS technology, laying the foundation for future large-scale production.

[0020] Other advantages and beneficial effects of the present invention will be partly apparent in the following description and partly manifested through specific embodiments of the present invention. Attached Figure Description

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings. It should be noted that in the drawings, multiple similar components (e.g., peripheral leads) may be labeled with only one exemplary number, merely for clarity of illustration and should not be construed as a limitation on the number of components. Wherein:

[0022] Figure 1 is a cross-sectional schematic diagram of the germanium-silicon heterojunction substrate 10 according to an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of the planar layout of a two-dimensional scalable germanium hole qubit array device 100 according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the planar layout of the quantum dot control region 200 according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of the planar layout of the core area 400 and the fan-out area 300 in an embodiment of the present invention;

[0026] Figure 5 is a schematic diagram of the core area 400 planar layout according to an embodiment of the present invention;

[0027] Figure 6 is a flowchart of the fabrication method of a two-dimensional scalable germanium hole qubit array device according to an embodiment of the present invention;

[0028] Figures 7 to 22 are schematic diagrams illustrating various stages of the fabrication process of the two-dimensional scalable germanium hole qubit array device according to an embodiment of the present invention. Detailed Implementation

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. The drawings are not necessarily drawn to scale. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this disclosure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0031] This invention proposes a device with a two-dimensional scalable germanium hole qubit array and its fabrication method. This device and its fabrication method combine good two-dimensional scalability with CMOS process compatibility, providing a feasible integration path for the large-scale production of semiconductor qubits.

[0032] It should be noted that the fan-out paths and wiring methods described in the following embodiments are only for more intuitive explanation of how the two-dimensional scalable germanium hole qubit array of the present invention supports fan-out functionality, and are not intended to limit the present invention. Any fan-out achieved based on the structure disclosed in the present invention by adjusting the wiring layer, changing the routing, adding vias, etc., as long as it utilizes the technical advantages brought by the structure of the present invention, falls within the scope of the present invention.

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0034] Referring to Figure 1, a germanium-silicon heterojunction substrate 10 is provided, comprising a silicon (Si) substrate 11, a germanium (Ge) buffer layer 12, and a silicon-germanium (Si) layer stacked sequentially from bottom to top. 1-x Ge x The structure comprises a buffer layer 13, a silicon-germanium (SiGe) relaxation buffer layer 14, a germanium (Ge) quantum well layer 15, a silicon-germanium (SiGe) barrier layer 16, and a silicon (Si) capping layer 17. A Si buffer layer (not shown) is epitaxially deposited on the Si substrate 11. In some embodiments, the SiGe buffer layer 13 may be several micrometers thick; the SiGe relaxation buffer layer 14 may be a Si... 0.2 Ge 0.8 The relaxation buffer layer can be approximately several hundred nanometers thick; the Ge quantum well layer 15 is a strained Ge quantum well, with a thickness of approximately 15 nanometers; the SiGe barrier layer 16 can be Si 0.2 Ge 0.8 The barrier layer is approximately 50 nanometers thick; the Si capping layer 17 can be approximately 1 nanometer thick.

[0035] Referring to Figure 2, from a top view, the two-dimensional scalable germanium hole qubit array device 100 (hereinafter referred to as device 100) includes a leakage isolation layer 101, an active region 102, a source-drain ohmic contact region 103, a peripheral connecting electrode 104, a peripheral lead 105, and a quantum dot control region 200.

[0036] In this embodiment, the leakage isolation layer 101 and the active region 102 are formed in different areas above the Si capping layer 17. There are six source-drain ohmic contact regions 103, each extending from the leakage isolation layer 101 to the quantum dot control region 200. The outer ends of the source-drain ohmic contact regions 103 are covered with rectangular protective electrodes, the material of which can be the same as the peripheral connection electrodes 104. As an example, there are 132 peripheral connection electrodes 104, but for the sake of simplicity, only one is shown in the figure. The peripheral connection electrodes 104 can be rectangular in shape, with most of their area located above the leakage isolation layer 101 and a small portion located within the active region 102, used to connect the peripheral leads 105. There are 132 peripheral leads 105, each corresponding to one of the peripheral connection electrodes 104, extending from the peripheral connection electrodes 104 to the quantum dot control region 200. For the sake of simplicity, only one is shown in the figure. The quantum dot control region 200 is located at the center of the active region 102 and contains multiple layers of quantum dot electrodes. As an example, the device 100 of this embodiment includes 43 quantum dots, of which 39 are qubits for computation and 4 are charge-sensing quantum dots for detection.

[0037] Referring to Figures 3 and 4, from a top view, the quantum dot control region 200 can be divided into a core region 400, a fan-out region 300, and an interconnect region 301. The core region 400, located at the very center, integrates a quantum bit array, containing multiple quantum bits and multiple charge-sensing quantum dots. For example, the diameter of the central region of the quantum bits can be 100-200 nm, and the diameter of the central region of the charge-sensing quantum dots can be 130-260 nm. Outside these central regions, the width of the quantum dot electrodes 302 can be 10-30 nm. The fan-out region 300 surrounds the core region 400 and is used for initial dispersion and routing of the densely packed gate electrodes. The interconnect region 301, located at the outermost edge, is used to further increase the gate spacing to accommodate the connection of the peripheral leads. For example, the width of the quantum dot electrodes 302 within the interconnect region 301 can gradually increase from 10-30 nm at the center to 1 μm at the outer edge.

[0038] In the core region 400, odd-numbered rows of qubits are alternately arranged with even-numbered rows in the column direction; and a barrier gate electrode is provided between every two adjacent plunger gate electrodes. In both the core region 400 and the fan-out region 300, a shielding gate electrode is provided between any two adjacent barrier gate electrodes; this shielding gate electrode is typically grounded. The quantum dot electrodes are configured to enable electrical fan-out connections from the core region to the interconnect region. Specifically, in the fan-out region 300, the density of the quantum dot electrode leads gradually decreases from the core region 400 to the interconnect region 301, while the lead spacing gradually increases, achieving a smooth transition from high-density arrangement to peripheral connections.

[0039] As shown in Figure 3, within the interconnect region 301, there are 132 quantum dot electrodes 302 corresponding to peripheral leads 105. The peripheral ends of the quantum dot electrodes 302 are connected to the peripheral leads 105 through vias 106, which total 132 vias 106. For the sake of simplicity, only one quantum dot electrode 302 and one via 106 are shown as an example in the figure.

[0040] Referring to Figures 3, 4, and 5, the quantum dot electrode 302 can be a lead gate (LG), a screen gate (SG), a barrier gate (BG), or a plunger gate (PG). The lead gate (LG) is used to form an electron pool and connect the source / drain to the quantum dot. The screen gate (SG) is used to shield against electric field interference generated by the upper gate. The barrier gate (BG) is used to adjust the electron tunneling coupling strength between adjacent quantum dots. The plunger gate (PG) is used to modulate the electrochemical potential of the quantum dot. These multilayer quantum dot electrodes are stacked in a periodic manner and electrically isolated from each other by multiple gate dielectric layers.

[0041] As an example, all quantum dot electrodes 302 in this embodiment include 6 guiding gate electrodes LG, 3 shielding gate electrodes SG, 80 barrier gate electrodes BG, and 43 plunger gate electrodes PG. The overlap region between the guiding gate electrode LG and the center end of the source-drain ohmic contact region 103 is approximately 5 μm. 2 For the sake of simplicity, Figure 3 only shows the three guide gate electrodes LG and the source-drain ohmic contact regions 103 as examples.

[0042] Please refer to Figure 4. In the planar layout diagram of the core region 400 and fan-out region 300 of the quantum dot control region 200, all quantum dot electrodes 302 are superimposed. The dashed lines in the figure only indicate the regional division between the core region 400 and the fan-out region 300, and do not represent any physical structure. As an optional implementation, the fan-out routing can be designed as shown in Figure 4, and the width of the quantum dot electrodes 302 within the fan-out region 300 can be maintained at 10-30 nm. For the sake of simplicity, only the leads of the three shielding gate electrodes SG are illustrated in the figure. Of course, the above method is only an example and not the only one. Based on the structure of this invention, those skilled in the art can flexibly adopt other fan-out schemes.

[0043] Please refer to Figure 5. To more intuitively illustrate the overall distribution and spatial relationship of the gate structure, Figure 5 presents the gates formed in each step in a superimposed manner. It is understood that this presentation is merely illustrative for ease of understanding and is not a limitation on the actual stacked structure. The specific formation process, sequence, and detailed structure of each gate will be explained in detail later in conjunction with the fabrication flowchart and various example stages in manufacturing (as shown in Figures 6-22). The dashed lines in the figure only represent the regional division of the core region 400, charge-inducing quantum dots 401, and qubits 402, without any physical structure. As an example, the core region 400 integrates a qubit array, containing 39 qubits 402 and four charge-inducing quantum dots 401 distributed around it. The diameter of the central region of the qubits 402 (i.e., the circular portion at the center end of the plunger gate electrode PG) can be 100-200 nm, and the diameter of the central region of the charge-inducing quantum dots 401 can be 130-260 nm. For the sake of simplicity, only the quantum dot electrode 302 of a charge-inducing quantum dot 401 and the quantum dot electrode 302 of a quantum bit 402 are shown in the figure.

[0044] In this embodiment, the charge-sensing quantum dot 401 includes two guiding gate electrodes LG, two barrier gate electrodes BG, and one plunger gate electrode PG, while the quantum bit 402 includes four barrier gate electrodes BG and one plunger gate electrode PG. The two charge-sensing quantum dots 401 on the left share the same guiding gate electrode LG, and similarly, the two charge-sensing quantum dots 401 on the right share a single guiding gate electrode LG. A shielding gate electrode SG separates any two adjacent barrier gate electrodes BG, and the shielding gate electrode SG is connected to a reference potential, such as ground. For simplicity, only one shielding gate electrode SG is illustrated in the figure.

[0045] As shown in Figures 6 to 22, a method 600 for fabricating a two-dimensional scalable germanium hole qubit array device and planar diagrams of each stage of the fabrication process are provided, which can be used to fabricate the device 100 of the above embodiment. The fabrication method 600 may include steps S610 to S640.

[0046] In step S610, a germanium-silicon heterojunction substrate 10 is provided. For example, an undoped Ge / SiGe heterostructure can be grown on an intrinsic Si(001) substrate using molecular beam epitaxy (MBE) to obtain a high-quality germanium-silicon heterojunction substrate 10. In some embodiments, step S610 may include steps 611 to 618.

[0047] Step 611: Provide silicon substrate 11. For example, clean the Si(001) substrate using a standard RCA process and perform high-temperature deoxidation to obtain an atomically flat surface.

[0048] Step 612: Form a Si buffer layer on the Si substrate 11. For example, an intrinsic Si buffer layer is grown on the Si substrate 11 by homoepitaxial growth.

[0049] Step 613: Form a Ge buffer layer 12 on the Si buffer layer. For example, a pure Ge buffer layer is grown epitaxially to alleviate the lattice mismatch stress between Si and Ge.

[0050] Step 614: Form Si with a germanium concentration gradient on Ge buffer layer 12 1-x Ge x Buffer layer 13. In some embodiments, the grown Si 1-x Ge x In the buffer layer, x gradually decreases from 1 to a real number between 0.7 and 0.8, and the thickness can be a few micrometers.

[0051] Step 615: In Si 1-x Ge x A SiGe relaxation buffer layer 14 with constant concentration and uniform strain relaxation is formed on the buffer layer 13. For example, in Si 1-x Ge x Si with constant concentration and uniform strain relaxation is grown on buffer layer 13 0.2 Ge 0.8 The buffer layer serves as a virtual substrate for SiGe. The uniformly strain-relaxed SiGe buffer layer is composed of Si. 1-y Ge y y is a real number between 0.7 and 0.8, and is related to Si in step 614. 1-x Ge x The maximum values ​​of x in buffer layer 13 are equal.

[0052] Step 616: Form a strained Ge quantum well layer 15 on the SiGe relaxation buffer layer 14. The thickness of the Ge quantum well layer 15 can be approximately tens of nanometers.

[0053] Step 617: Form a SiGe barrier layer 16 on the Ge quantum well layer 15. The composition of the SiGe barrier layer is the same as that of the uniformly strain-relaxed SiGe buffer layer. For example, Si is grown on the Ge quantum well layer 15. 0.2 Ge 0.8 Barrier layer. The SiGe barrier layer 16 has a thickness of approximately tens of nanometers, which can be adjusted as needed.

[0054] Step 618: Form a Si capping layer 17 on the SiGe barrier layer 16. The thickness of the Si capping layer is about a few nanometers, for example, it can be set to about 1 nanometer, thus completing the fabrication of the Ge / SiGe heterojunction substrate.

[0055] In step S620, a plurality of source-drain ohmic contact regions 103 are formed on the germanium-silicon heterojunction substrate 10. For example, the source-drain ohmic contact regions 103 of the gate-controlled quantum dot device can be fabricated on the Ge / SiGe heterostructure using optical lithography during the microfabrication stage. In some embodiments, step S620 may include steps 621 to 624 as follows.

[0056] Step 621: Form a first oxide insulating layer on the silicon capping layer 17. For example, the substrate can be ultrasonically cleaned with a standard organic solvent to remove contaminants from the surface of the germanium-silicon heterojunction substrate 10. Then, a SiO2 insulating layer with a thickness of 200-300 nm can be deposited on the substrate by ICP-VD as a leakage isolation layer 101 for the gate electrode to avoid the formation of a leakage channel between the peripheral connection electrode and the substrate during bonding.

[0057] Step 622: Remove the first oxide insulating layer of the active region of the germanium-silicon heterojunction substrate 10 to expose a portion of the silicon capping layer 17. For example, using photoresist as a mask, wet etching with BOE is used to remove the SiO2 insulating layer L1 of the active region.

[0058] Step 623: Form a second oxide insulating layer in a portion of the exposed silicon capping layer 17. For example, deposit a SiO2 insulating layer L2 with a thickness of approximately tens of nanometers on the substrate by ICP-VD as a gate dielectric layer and to protect the initial sample surface from contamination by subsequent process steps.

[0059] Step 624: Form multiple source-drain ohmic contact regions through the second oxide insulating layer. There are two possible solutions:

[0060] Option 1:

[0061] First, a portion of the second oxide insulating layer is selectively removed to expose the windows of the source / drain contact regions. For example, using photoresist as a mask, the SiO2 insulating layer L2 is selectively etched using BOE to expose the windows of the source and drain contact electrodes. Next, patterned metal electrodes are deposited within the windows of the source and drain contact electrodes and annealed to allow the target metal to diffuse into the silicon capping layer 17, the silicon-germanium barrier layer 16, and the germanium quantum well layer 15, resulting in the source / drain ohmic contact region 103. For example, a 50–60 nm thick Pt electrode can be deposited by electron beam evaporation and then stripped to form a patterned Pt electrode in the windows of the source and drain contact electrodes. This electrode is then annealed at 300–400 °C for 1–2 hours in a nitrogen atmosphere to allow the Pt to diffuse into the germanium quantum well layer 15, approximately a few nanometers below, to form the source / drain ohmic contact region 103.

[0062] Option 2:

[0063] First, using photoresist as a mask, the source and drain regions are defined by P-type ion implantation and then activated by annealing. Next, using photoresist as a mask, the oxide insulating layer L2 is selectively etched to expose the windows of the source and drain contact regions, thereby forming multiple source and drain ohmic contact regions.

[0064] In step S630, gate dielectric layers and quantum dot electrodes 302 are alternately formed on the upper surface of the silicon capping layer 17 to obtain a stacked structure containing multiple gate dielectric layers and multiple quantum dot electrodes. For example, a high-k stacked gate dielectric is first prepared, and then a two-dimensional scalable germanium hole qubit array is prepared on the high-k stacked gate dielectric using electron beam lithography in the nanofabrication stage to achieve nanoscale electrode patterning. In this embodiment, step S630 corresponds to the process nodes shown in Figures 7-22, and may specifically include steps 631 to 636.

[0065] Step 631: Form the first gate dielectric layer on the silicon capping layer 17. For example, a high-k gate dielectric layer O1 can be deposited by ALD. The material can be a high-k dielectric such as Al2O3, HfO2, or ZrO2, with a thickness of approximately tens of nanometers. Figure 7 is a schematic cross-sectional view of the device after step 631, showing the stacked gate dielectric layer structure, including: a multi-layer epitaxial structure from bottom to top, including a strained Ge quantum well layer 15, Si... 0.2 Ge 0.8 Barrier layer 16 and Si capping layer 17; source / drain ohmic contact region 103 formed after annealing, which is made of PtSiGe alloy, sequentially penetrating Si capping layer 17 and Si... 0.2 Ge 0.8 A barrier layer 16 extends downward into the strained Ge quantum well layer 15 by at least 5 nm; a SiO2 insulating layer L1 serves as a leakage isolation layer. The SiO2 insulating layer L2 and the Al2O3 gate dielectric layer O1 form a stacked gate dielectric layer.

[0066] Step 632: Form a patterned guide gate electrode LG on the first gate dielectric layer. This step can, for example, correspond to step subset S1.0, to complete the structural state shown in FIG8.

[0067] Step 633: Form a second gate dielectric layer on the pilot gate electrode LG.

[0068] Step 634: Form the first row of quantum dot electrodes and the last row of quantum dot electrodes on the second gate dielectric layer. This step can, for example, correspond to step subset S1.1 to complete the structure shown in Figures 9-14.

[0069] Step 635: Sequentially form multiple intermediate gate dielectric layers and corresponding quantum dot electrode layers, wherein each formed quantum dot electrode layer contains symmetrically distributed quantum dot electrodes in the nth row and the nth row from the end, where n is an integer greater than 1. This step can, for example, correspond to step subset S1.2, to complete the structure shown in Figures 15-18.

[0070] Step 636: Form three consecutive rows of quantum dot electrodes in the central region. This step can, for example, correspond to step subset S1.3, to complete the structure shown in Figures 19-22. The quantum dot electrodes include electrodes for controlling computational quantum dots and electrodes for controlling charge-sensing quantum dots.

[0071] In one specific embodiment, step S630 may include a subset of the following steps S1.0 to S1.3. This embodiment fabricates an array structure comprising 7 rows of qubits and 4 charge-inducing quantum dots. It should be noted that this embodiment is merely illustrative and not restrictive. Those skilled in the art can adjust the number of rows and quantities of qubits according to actual needs without departing from the scope of protection of this invention.

[0072] Subset of steps S1.0: Subset of steps for preparing the guiding gate electrode;

[0073] Subset of steps S1.1: Subset of steps for preparing the qubit electrodes in row 1 (and row 7);

[0074] Subset of steps S1.2: Subset of steps for preparing the qubit electrodes in row 2 (and row 6);

[0075] Subset of steps S1.3: Subset of steps for preparing the qubit electrodes in rows 3, 4, and 5.

[0076] The quantum dot electrode 302 is made of Au / Ti, with a lower Ti layer approximately 3–5 nm thick and an upper Au layer approximately 30–60 nm thick, for a total electrode thickness of 30–60 nm. In the step subset, a high-k gate dielectric layer used to isolate different electrodes is deposited via ALD. This layer is made of Al₂O₃ and has a thickness of approximately a few nanometers, numbered sequentially according to the deposition order as O₂, O₃, ..., O₁₁.

[0077] Due to the symmetry of the qubit array (except for the central region), the qubit electrodes for rows 1 and 7 are completed in one step, and the qubit electrodes for rows 2 and 6 are completed in one step. Since the qubits in the central region of the array require special design, step subset S1.3 is used to prepare the qubit electrodes for rows 3, 4, and 5 in the center.

[0078] The subset of steps S1.0 includes the following steps:

[0079] Patterned guide gate electrodes LG were fabricated on a high-k gate dielectric layer O1 by electron beam exposure, metal evaporation, and lift-off. Figure 8 shows a schematic diagram of the planar layout of the guide gate electrodes LG within the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent any physical structure. There are a total of 6 guide gate electrodes LG; for the sake of simplicity, only 3 guide gate electrodes LG are illustrated in Figure 8.

[0080] The subset of steps S1.1 includes the following steps:

[0081] Step 1: Grow a high-k gate dielectric layer O2 on the substrate;

[0082] Step 2: A patterned shielding gate electrode SG1 is fabricated on the high-k gate dielectric layer O2 by electron beam exposure, metal evaporation, and lift-off. Figure 9 shows a schematic diagram of the planar layout of the guiding gate electrode LG and the shielding gate electrode SG1 within the core region 400. The dashed lines in the figure only indicate the regional division of the core region 400 and do not represent any solid structure. The shielding gate electrode SG1 completely covers the fan-out region 300.

[0083] Step 3: Grow a high-k gate dielectric layer O3 on the substrate;

[0084] Step 4: Using electron beam resist as a mask, selectively etch the high-k gate dielectric layer O3 in the core region. Figure 10 shows a schematic diagram of the relative positions of the etched region E1 on the high-k gate dielectric layer O3 and the shielding gate electrode SG1 in the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent the physical structure.

[0085] Step 5: Patterned barrier gate electrodes BG1 are fabricated on the high-k gate dielectric layers O2 and O3 by electron beam exposure, metal evaporation, and lift-off. Figure 11 is a schematic diagram of the planar layout of the guiding gate electrode LG, the shielding gate electrode SG1, and the barrier gate electrode BG1 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent any physical structure. There are a total of 32 barrier gate electrodes BG1. For the sake of simplicity, only 4 barrier gate electrodes BG1 are illustrated in the figure.

[0086] Step 6: Grow a high-k gate dielectric layer O4 on the substrate. Figure 12 shows a schematic cross-sectional view of the quantum dot device taken along section AA in Figure 11 after step 6 of subset S1.1 is completed (the cross-sectional position is shown as line AA in Figure 11). To highlight the key layer structure, some components are omitted in the figure; since the structure is symmetrically distributed in the plane perpendicular to line AA, only half of it is shown in the cross-sectional view. The illustrated structure includes the following layers (from bottom to top): a stacked gate dielectric consisting of a SiO2 insulating layer L2 and an Al2O3 gate dielectric layer O1; an Al2O3 gate dielectric layer O2; a shielding gate SG1; an Al2O3 gate dielectric layer O3; a barrier gate BG1; and an Al2O3 gate dielectric layer O4.

[0087] Step 7: Patterned plunger gate electrodes PG1 are fabricated on the high-k gate dielectric layer O4 by electron beam exposure, metal evaporation, and stripping. Figure 13 is a schematic diagram of the planar layout of the guiding gate electrode LG, shielding gate electrode SG1, barrier gate electrode BG1, and plunger gate electrode PG1 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent the actual structure. There are a total of 16 plunger gate electrodes PG1; for the sake of simplicity, only 4 plunger gate electrodes PG1 are shown as examples in the figure. Within the core region 400 and the fan-out region 300, the leads (non-circular parts) of the plunger gate electrodes PG1 are all shielded by the shielding gate electrode SG1 to prevent their leads from interfering with the electric field of the conductive channel below. Figure 14 shows a schematic cross-sectional view of the quantum dot device taken along section BB in Figure 13 after step 7 of subset S1.1 is completed (the cross-sectional position is shown along line BB in Figure 13). To highlight the key layer structure, some components are omitted in the figure; given that the structure is symmetrically distributed in the plane perpendicular to line BB, only half of it is shown. The illustrated structure includes the following layers (from bottom to top): a stacked gate dielectric consisting of a SiO2 insulating layer L2 and an Al2O3 gate dielectric layer O1; an Al2O3 gate dielectric layer O2; a shielding gate SG1; an Al2O3 gate dielectric layer O3; a barrier gate BG1; an Al2O3 gate dielectric layer O4; and a plunger gate PG1.

[0088] The subset of steps S1.2 includes the following steps:

[0089] Step 1: Grow a high-k gate dielectric layer O5 on the substrate;

[0090] Step 2: A patterned shielding gate electrode SG2 is fabricated on the high-k gate dielectric layer O5 by electron beam exposure, metal evaporation, and stripping. Figure 15 shows a schematic diagram of the planar layout of the barrier gate electrode BG1 and the shielding gate electrode SG2 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent the actual structure. The shielding gate electrode SG2 covers the barrier gate electrode BG1 and the plunger gate electrode PG1 of all qubits, and its structure completely shields the entire fan-out region 300.

[0091] Step 3: Grow a high-k gate dielectric layer O6 on the substrate;

[0092] Step 4: Using electron beam resist as a mask, selectively etch the high-k gate dielectric layers O4, O5, and O6 in the reserved qubit regions within the core region. Figure 16 shows a schematic diagram of the relative positions of the etched region E2 on the high-k gate dielectric layer O6 and the shielding gate electrode SG2 in the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent the physical structure.

[0093] Step 5: Patterned barrier gate electrodes BG2 are fabricated on the high-k gate dielectric layers O2 and O6 by electron beam exposure, metal evaporation, and lift-off. Figure 17 is a schematic diagram of the planar layout of the shielding gate electrode SG2 and barrier gate electrode BG2 within the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent any physical structure. There are a total of 24 barrier gate electrodes BG2. For the sake of simplicity, only two barrier gate electrodes BG2 are shown as examples in the figure.

[0094] Step 6: Grow a high-k gate dielectric layer O7 on the substrate;

[0095] Step 7: Patterned plunger gate electrodes PG2 are fabricated on the high-k gate dielectric layer O7 by electron beam exposure, metal evaporation, and stripping. Figure 18 is a schematic diagram of the planar layout of the shielding gate electrode SG2, barrier gate electrode BG2, and plunger gate electrode PG2 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent the actual structure. There are a total of 10 plunger gate electrodes PG2; for the sake of simplicity, only two plunger gate electrodes PG2 are shown as examples in the figure. Within the core region 400 and the fan-out region 300, the leads (non-circular parts) of the plunger gate electrodes PG2 are all shielded by the shielding gate electrode SG2 to prevent their leads from interfering with the electric field of the conductive channel below.

[0096] The subset of steps S1.3 includes the following steps:

[0097] Step 1: Grow a high-k gate dielectric layer O8 on the substrate;

[0098] Step 2: Patterned shielding gate electrode SG3 is fabricated on the high-k gate dielectric layer O8 by electron beam exposure, metal evaporation, and lift-off. Figure 19 shows a schematic diagram of the planar layout of barrier gate electrode BG2 and shielding gate electrode SG3 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent the physical structure. The shielding gate electrode SG3 covers the barrier gate electrode BG2 and the plunger gate electrode PG2 of all qubits, and its structure completely shields the entire fan-out region 300.

[0099] Step 3: Grow a high-k gate dielectric layer O9 on the substrate;

[0100] Step 4: Using electron beam resist as a mask, selectively etch the high-k gate dielectric layers O7, O8, and O9 in the reserved qubit regions within the core region. Figure 20 shows a schematic diagram of the relative positions of the etched region E3 on the high-k gate dielectric layer O9 and the shielding gate electrode SG3 in the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent the physical structure.

[0101] Step 5: Patterned barrier gate electrodes BG3 are fabricated on the high-k gate dielectric layers O2 and O9 by electron beam exposure, metal evaporation, and lift-off. Figure 21 is a schematic diagram of the planar layout of the shielding gate electrode SG3 and barrier gate electrode BG3 within the core region 400. The dashed lines in the figure only indicate the region division of the core region 400 and do not represent the actual structure. There are a total of 24 barrier gate electrodes BG3. For the sake of simplicity, only two barrier gate electrodes BG3 are shown as examples in the figure.

[0102] Step 6: Grow a high-k gate dielectric layer O10 on the substrate;

[0103] Step 7: Patterned plunger gate electrodes PG3 and PG4 are fabricated on the high-k gate dielectric layer O10 by electron beam exposure, metal evaporation, and stripping. Figure 22 is a schematic diagram of the planar layout of the shielding gate electrode SG3, barrier gate electrode BG3, and plunger gate electrodes PG3 and PG4 within the core region 400. The dashed lines in the figure only indicate the division of the core region 400 and do not represent any physical structure. There are 10 plunger gate electrodes PG3 and 5 plunger gate electrodes PG4. For the sake of simplicity, only 2 plunger gate electrodes PG3 and 1 plunger gate electrode PG4 are shown as examples in the figure. Within the core region 400 and the fan-out region 300, the leads (non-circular parts) of the plunger gate electrodes PG3 and PG4 are shielded by the shielding gate electrode SG3 to prevent their leads from interfering with the electric field of the conductive channel below.

[0104] Step 8: Grow a high-k gate dielectric layer O11 on the substrate.

[0105] In step S640, a plurality of peripheral connection electrodes 104 and peripheral leads 105 are formed. Each peripheral connection electrode 104 is electrically connected to the corresponding quantum dot electrode 302 through the peripheral lead 105 for receiving external control signals.

[0106] Before step S640, vias can be etched first. For example, vias 106 can be fabricated in the quantum dot control region 200 on the high-k gate dielectric layer using optical lithography to connect the quantum dot electrode 302 and the peripheral lead 105. Then, the peripheral lead and peripheral connection electrode are fabricated. For example, the peripheral lead 105 and peripheral connection electrode 104 can be fabricated on the high-k gate dielectric layer using optical lithography. In some embodiments, step S640 may include the following steps:

[0107] First, a contact window is formed. Using photoresist as a mask, the stacked gate dielectric layer located above the outer end of the quantum dot electrode 302 in the interconnect region 301 is selectively etched to expose the window at the outer end of the quantum dot electrode; at the same time, the stacked gate dielectric layer above the outer end of the source-drain ohmic contact region 103 is selectively etched to expose the window at the outer end of the ohmic contact region.

[0108] Next, peripheral leads and connecting electrodes are formed. Using photoresist as a mask, patterned peripheral leads 105 and peripheral connecting electrodes 104 are deposited by vapor deposition, connecting the quantum dot electrode 302 to the peripheral connecting electrode 104 through the peripheral leads 105; simultaneously, patterned source-drain ohmic contact regions 103 peripheral end protection electrodes are deposited by vapor deposition. The peripheral leads 105, peripheral connecting electrodes 104, and peripheral end protection electrodes of the source-drain ohmic contact regions 103 are made of Al / Ti, with a lower layer of approximately 20 nm thick Ti and an upper layer of approximately 250 nm thick Al, resulting in a total electrode thickness of 200–300 nm.

[0109] Through the above steps, a two-dimensional scalable germanium hole qubit array device was fabricated. This device exhibits good two-dimensional scalability and CMOS process compatibility, providing a feasible integration path for the large-scale production of semiconductor qubits.

[0110] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "outer periphery," and "center end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0111] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0112] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0113] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A two-dimensional scalable germanium hole qubit array device, characterized in that, include: A germanium-silicon heterojunction substrate, comprising a germanium quantum well layer, a silicon-germanium barrier layer, and a silicon capping layer arranged sequentially from bottom to top; Multiple source-drain ohmic contact regions, which penetrate the silicon capping layer and the silicon-germanium barrier layer and form ohmic contacts with the germanium quantum well layer; A multilayer gate dielectric layer is disposed on the upper surface of the silicon capping layer; The quantum dot control region, located above the multilayer gate dielectric layer, includes multiple quantum dot electrodes. These electrodes include: a single guiding gate electrode for forming an electron pool and connecting the source / drain to the quantum dot; multiple shielding gate electrodes for shielding against electric field interference generated by the upper gate layer; multiple barrier gate electrodes for adjusting the electron tunneling coupling strength between adjacent quantum dots; and multiple plunger gate electrodes for controlling the electrochemical potential of the quantum dot. The multiple quantum dot electrodes are stacked periodically and electrically isolated from each other by the multilayer gate dielectric layer. Multiple peripheral connection electrodes and multiple peripheral leads correspond one-to-one with the quantum dot electrodes in the quantum dot control region, with each peripheral connection electrode connected to its corresponding quantum dot electrode via the peripheral lead.

2. The two-dimensional scalable germanium hole qubit array device according to claim 1, characterized in that, From a top view, the quantum dot control region is divided into a core region, a fan-out region, and an interconnection region. The core region is located in the central area and includes multiple qubits and multiple charge-sensing quantum dots. The fan-out region surrounds the core region and is used to initially disperse and lead out the densely arranged quantum dot electrodes. The interconnection region is located in the outer region of the fan-out region and is used to further increase the lead spacing of the quantum dot electrodes to accommodate the peripheral connection electrodes.

3. The two-dimensional scalable germanium hole qubit array device according to claim 2, characterized in that, Within the core region, odd-numbered rows of qubits and even-numbered rows of qubits are alternately arranged in the column direction; and a barrier gate electrode is provided between every two adjacent layers of plunger gate electrodes.

4. The two-dimensional scalable germanium hole qubit array device according to claim 2, characterized in that, In the core region and the fan-out region, a shielding gate electrode is provided between any two adjacent barrier gate electrodes, and the shielding gate electrode is connected to the reference potential.

5. The two-dimensional scalable germanium hole qubit array device according to claim 2, characterized in that, In the fan-out region, the density of quantum dot electrode leads gradually decreases from the core region to the interconnect region, while the lead spacing gradually increases, achieving a smooth transition from high-density arrangement to peripheral connection.

6. A method for fabricating a two-dimensional scalable germanium hole qubit array device, characterized in that, include: A germanium-silicon heterojunction substrate is provided, wherein the germanium-silicon heterojunction substrate comprises a germanium quantum well layer, a silicon-germanium barrier layer and a silicon capping layer arranged sequentially from bottom to top; Multiple source-drain ohmic contact regions are formed on the germanium-silicon heterojunction substrate. These regions penetrate the silicon capping layer and the silicon-germanium barrier layer, forming ohmic contacts with the germanium quantum well layer. Gate dielectric layers and quantum dot electrodes are alternately formed on the upper surface of the silicon capping layer, resulting in a stacked structure comprising multiple gate dielectric layers and multiple quantum dot electrodes. The multiple quantum dot electrodes include a guide gate electrode, a shield gate electrode, a barrier gate electrode, and a plunger gate electrode. These multiple quantum dot electrodes are stacked in a periodic manner and electrically isolated from each other by the multiple gate dielectric layers. Multiple peripheral connection electrodes and multiple peripheral leads are formed, with each peripheral connection electrode electrically connected to the corresponding quantum dot electrode via a peripheral lead.

7. The preparation method according to claim 6, characterized in that, The method for providing a germanium-silicon heterojunction substrate includes: providing a silicon substrate; forming a silicon buffer layer on the silicon substrate; forming a germanium buffer layer on the silicon buffer layer; forming a silicon-germanium buffer layer with a germanium concentration gradient on the germanium buffer layer; forming a silicon-germanium relaxation buffer layer with constant concentration and uniform strain relaxation on the silicon-germanium buffer layer; forming a strained germanium quantum well layer on the silicon-germanium relaxation buffer layer; forming a silicon-germanium barrier layer on the germanium quantum well layer; and forming a silicon capping layer on the silicon-germanium barrier layer.

8. The preparation method according to claim 6, characterized in that, The process of forming multiple source-drain ohmic contact regions on the germanium-silicon heterojunction substrate includes: forming a first oxide insulating layer on the silicon capping layer; removing the first oxide insulating layer from the active region of the germanium-silicon heterojunction substrate to expose a portion of the silicon capping layer; forming a second oxide insulating layer in a portion of the exposed silicon capping layer; and forming multiple source-drain ohmic contact regions through the second oxide insulating layer, including any of the following schemes: Scheme 1: selectively removing a portion of the second oxide insulating layer to expose windows of the source-drain contact regions; depositing metal electrodes within the windows and performing annealing to diffuse the metal into the germanium quantum well layer, thereby forming the source-drain ohmic contact regions; Scheme 2: defining the source-drain regions through P-type ion implantation and performing annealing activation; selectively removing the second oxide insulating layer to expose windows of the source and drain contact regions, thereby forming the source-drain ohmic contact regions.

9. The preparation method according to claim 6, characterized in that, The alternating formation of gate dielectric layers and quantum dot electrodes on the upper surface of the silicon capping layer includes: forming a first gate dielectric layer on the silicon capping layer; forming a patterned guiding gate electrode on the first gate dielectric layer; forming a second gate dielectric layer on the guiding gate electrode; forming a first row of quantum dot electrodes and a last row of quantum dot electrodes on the second gate dielectric layer; sequentially forming a plurality of intermediate gate dielectric layers and corresponding quantum dot electrode layers, wherein each formed quantum dot electrode layer includes a symmetrically distributed nth row of quantum dot electrodes and a pi-nth row of quantum dot electrodes, where n is an integer greater than 1; finally forming three consecutive rows of quantum dot electrodes in the central region; wherein the quantum dot electrodes include electrodes for controlling computational quantum dots and electrodes for controlling charge-sensing quantum dots.

10. The preparation method according to claim 6, characterized in that, Forming multiple peripheral connection electrodes and multiple peripheral leads includes: forming multiple contact windows in the uppermost gate dielectric layer to expose the connection ends of each quantum dot electrode; forming multiple contact windows in the peripheral region of the source-drain ohmic contact region to expose the connection ends of the source-drain ohmic contact region; evaporating and patterning metal to form multiple peripheral connection electrodes and multiple peripheral leads, wherein the peripheral leads electrically connect the exposed quantum dot electrode connection ends to the corresponding peripheral connection electrodes, and simultaneously electrically connect the source-drain ohmic contact region to the corresponding peripheral connection electrodes.

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