Method for preparing grid electrode of hundred-bit quantum computing chip and quantum computing chip

Abstract

The invention discloses a preparation method of a grid electrode of a hundred-bit-level quantum computing chip and the quantum computing chip. The preparation method of the grid electrode of the hundred-bit-level quantum computing chip comprises the following steps: processing and preparing an alignment mark on a substrate processed by a laser direct writing technology on a hydrogen mask of a scanning tunneling microscope; processing a quantum device core structure on the substrate; secondarily processing a top electrode overlay mark on the substrate to obtain a second standard substrate; a plurality of top electrode layers are manufactured on the oxide layer in an overlay mode through the top electrode overlay marks, the top electrode layers are arranged in a staggered mode and partially overlapped in the vertical direction, and the hundred-bit-level quantum computing chip is obtained. According to the method, a plurality of top electrode layers are processed on the oxide layer in a multi-layer stacking mode, different layers do not influence one another, the space utilization rate of the quantum computing chip is greatly increased while the space between the top electrodes is guaranteed, and therefore preparation of the hundred-bit-level quantum computing chip can be achieved in the limited on-chip space.

Description

Technical Field

[0001] This invention relates to the field of quantum computing chip technology, and in particular to a method for fabricating a gate for a 100-bit-level quantum computing chip and a quantum computing chip. Background Technology

[0002] Since the beginning of the 21st century, the rapid development of fields such as big data and artificial intelligence has significantly increased the demand for computing power. Quantum computers based on quantum circuits have attracted widespread attention due to their superior computing speed. Quantum computers use fabrication processes similar to semiconductor chips, offering significant advantages in large-scale expansion and good scalability. A quantum computer primarily generates a quantum measurement and control system by using a quantum intermediate representation produced after compiling a quantum circuit program. This representation is then transmitted to a quantum computing chip via microwave cables, causing a response in the superconducting qubits and resulting in the controlled evolution of quantum states, thereby enabling the execution of the quantum program.

[0003] However, with the development of quantum computing chips, the number of qubits will inevitably move towards the hundreds of qubits level or even higher, requiring an increase in the number of top electrodes. However, due to the limited area of ​​the quantum computing chip used to integrate the top electrodes, coupled with the limitations of current electron beam lithography resolution, errors are unavoidable during the fabrication process. There is an upper limit to the density of top electrodes while maintaining their spacing. Therefore, a certain spacing must be ensured beforehand between the top electrodes fabricated in the limited area of ​​the quantum computing chip; otherwise, the top electrodes will connect together, affecting the control effect and thus limiting the number of top electrodes that can be fabricated. This makes it difficult to achieve hundreds of qubits of quantum computing chip design within a limited top electrode area.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method for fabricating the gate of a 100-bit quantum computing chip and a quantum computing chip. This addresses the problem in the prior art where maintaining the spacing between top electrodes makes it difficult to further increase the top electrode density, thus hindering the realization of 100-bit quantum computing in limited on-chip space.

[0006] The technical solution of the present invention is as follows: This invention provides a method for fabricating the gate of a 100-bit quantum computing chip, the steps of which include: Alignment marks for positioning were fabricated on a substrate processed by laser direct writing technology using a hydrogen mask for scanning tunneling microscope, resulting in a first standard substrate with alignment marks. The core structure of the quantum device is fabricated on the first standard substrate using scanning tunneling microscopy hydrogen mask lithography, and the core structure of the quantum device integrates several quantum dots. A second standard substrate is obtained by second-processing the top electrode and marking it. An oxide layer is grown on a second standard substrate with alignment marks and top electrode overlay marks on its surface; By using the top electrode overlay markings to overlay several top electrode layers on the oxide layer, the top electrode layers are staggered with each other and partially overlap in the vertical direction to obtain a 100-bit quantum computing chip.

[0007] A further step of the present invention involves fabricating several top electrode layers on an oxide layer using the top electrode overlay markings. These top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit-level quantum computing chip. The top electrode is positioned by overlay markings to determine the exposure location of the top electrode on the second standard substrate. At the exposure position on the second standard substrate, the top electrode and the corresponding fan-out structure layer are exposed under the first beam current value, and the exposure position is developed. A high-vacuum electron beam evaporation coating machine was used to deposit an aluminum film on the substrate to fabricate the top electrode. A dielectric layer for isolating the top electrode is grown on the top electrode using an atomic layer deposition apparatus. Repeat the above steps to perform overlay processing on several other top electrode layers, with each top electrode layer processed in the gap between two adjacent stacked top electrodes.

[0008] A further provision of the present invention includes the step of fabricating alignment marks for positioning on a substrate processed using laser direct writing technology on a hydrogen mask for scanning tunneling microscopy, to obtain a first standard substrate with alignment marks, comprising: Alignment marks are exposed on the substrate; a photoresist layer is spin-coated on the substrate, and the substrate is selectively exposed according to the alignment marks by laser direct writing; Develop the substrate after selective exposure; Based on the developed image, the substrate is etched using a reactive ion etching machine.

[0009] A further provision of the present invention includes the step of fabricating the core structure of the quantum device on the first standard substrate using scanning tunneling microscopy hydrogen mask lithography, wherein the core structure of the quantum device integrates a plurality of quantum dots. The core structure of the quantum device was fabricated on the substrate surface by photolithography using scanning tunneling microscope hydrogen mask lithography. An encapsulation and protective film is grown on the core structure of the quantum device; Scanning electron microscopy was used to locate the relative position between the core structure of the quantum device and the alignment mark.

[0010] In a further embodiment of the present invention, the top electrode overlay mark includes a first preset size overlay mark, a second preset size overlay mark, and a third preset size overlay mark, wherein the second preset size overlay mark is nested within the first preset size overlay mark, and the third preset size overlay mark is nested within the second preset size overlay mark; the first preset size overlay mark is smaller than the alignment mark; the second preset size overlay mark is smaller than the first preset size overlay mark, and the third preset size overlay mark is equal in size to the second preset size overlay mark; The step of overlaying and positioning the top electrode on the second standard substrate according to the top electrode overlay marking includes: A photomask is prepared on the second standard substrate; Scanning electron microscope images are obtained by scanning a photolithographic mask using a scanning electron microscope equipped with a pattern generator. Move the second standard substrate to the zero point position of the alignment corner, and perform three-point calibration according to the alignment marks; The focus is further shifted to the first preset size overlay mark of the top electrode overlay mark, and the first preset size overlay mark on the second standard substrate is calibrated sequentially using the image of the first preset size overlay mark in the scanning electron microscope image, thereby accurately positioning the second preset size overlay mark; The second preset size overlay mark on the second standard substrate is calibrated sequentially using the second preset size overlay mark image in the scanning electron microscope image, thereby accurately locating to the third preset size overlay mark; The third preset size overlay mark on the second standard substrate is calibrated sequentially using the third preset size overlay mark image in the scanning electron microscope image; Simultaneously, select the first preset size overlay mark, the second preset size overlay mark, and the third preset size overlay mark and the top electrode image, calibrate all the top electrode overlay marks, and locate the exposure position of the top electrode.

[0011] A further provision of the present invention includes, prior to the step of fabricating several top electrode layers on the oxide layer using the top electrode overlay markings, wherein the top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit-level quantum computing chip, the invention further includes: The left and right top electrode columns are located on a computer based on the position of the quantum dots. The distance between each top electrode in the left top electrode column is equal, the distance between each top electrode in the right top electrode column is equal, and the left and right top electrode columns are symmetrically arranged. The top electrodes in the left top electrode column are sequentially assigned to several top electrode layers, and the top electrodes in the right top electrode column are sequentially assigned to several top electrode layers. Each top electrode and its adjacent top electrode are located in different top electrode layers.

[0012] Based on the same inventive concept, the present invention also provides a quantum computing chip, which is fabricated using the above-described method for fabricating gates of a 100-bit-level quantum computing chip; wherein, the top electrode of the quantum computing chip includes several top electrode layers; the top electrodes of the quantum computing chip are symmetrically distributed on the core structure of the quantum device.

[0013] In a further embodiment of the present invention, the top electrode of the quantum computing chip includes a first top electrode layer, a second top electrode layer, and a third top electrode layer. The first top electrode layer, the second top electrode layer, and the third top electrode layer are stacked on top of each other, and the top electrodes in the first top electrode layer, the second top electrode layer, and the third top electrode layer are staggered from each other in the vertical direction. Each top electrode is connected to a fan-out structure, and the width of the fan-out structure is greater than the width of the top electrode. The core structure of the quantum computing chip includes an N×1 or N×M quantum dot array (N>3, M>1) composed of several quantum dots. The quantum dots are initialized, manipulated and read out by the top electrode.

[0014] This invention provides a method for fabricating the gate of a 100-bit quantum computing chip and the quantum computing chip itself. The method for fabricating the gate of a 100-bit quantum computing chip includes: fabricating alignment marks for positioning on a substrate processed by scanning tunneling microscope hydrogen mask using laser direct writing technology to obtain a first standard substrate with alignment marks; fabricating a core structure of a quantum device on the first standard substrate using scanning tunneling microscope hydrogen mask lithography, wherein the core structure of the quantum device integrates several quantum dots; fabricating a second top electrode overlay mark on the first standard substrate to obtain a second standard substrate; growing an oxide layer on the second standard substrate with alignment marks and top electrode overlay marks on its surface; and fabricating several top electrode layers on the oxide layer using the top electrode overlay marks, wherein the top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit quantum computing chip. The quantum computing chip fabrication method of the present invention utilizes the top electrode overlay marking and employs a multi-layer stacking approach to process several top electrode layers on the oxide layer. This method produces top electrode layers with smaller spacing and larger scale, and different layers do not affect each other. While ensuring the spacing of the top electrodes, it greatly improves the space utilization of the quantum computing chip, thereby enabling the fabrication of hundreds of bits of quantum computing chips on a limited on-chip space. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a flowchart of the steps involved in the fabrication method of the gate for a 100-bit quantum computing chip in this invention.

[0017] Figure 2 This is a schematic diagram of a substrate slice in this invention.

[0018] Figure 3 This is a schematic diagram of the alignment mark in this invention.

[0019] Figure 4 This is a schematic diagram of the core structure of the quantum device in this invention.

[0020] Figure 5 This is a schematic diagram showing the relative positions of the core structure of the quantum device and the alignment mark in this invention.

[0021] Figure 6 This is a schematic diagram of the distribution of the top electrode in this invention.

[0022] Figure 7 yes Figure 6 A magnified view of the top electrode spacing of one of the top electrode layers in region A.

[0023] Figure 8 This is a schematic diagram of the alignment mark and the top electrode overlay mark in this invention.

[0024] Figure 9 This is a schematic diagram of the marking on the top electrode in this invention.

[0025] Figure 10 This is a schematic diagram showing the relative positions of the core structure and top electrode of the quantum device in this invention.

[0026] Figure 11 This is a schematic diagram showing the relative positions of the core structure of the quantum device, the top electrode, and the third preset size overlay mark in this invention.

[0027] Figure 12 This is a two-dimensional charge stability diagram of the single-electron transistor in this invention.

[0028] Figure 13 This is a scanning image under a scanning tunneling microscope after the first top electrode layer is fabricated on the core structure of the quantum device in this invention.

[0029] Figure 14 This is a scanning image under a scanning tunneling microscope after the second top electrode layer is fabricated on the core structure of the quantum device in this invention.

[0030] Figure 15 This is a scanning image under a scanning tunneling microscope after the third top electrode layer is fabricated on the core structure of the quantum device in this invention.

[0031] The markings in the attached figures are as follows: 100, alignment mark; 200, top electrode overlay mark; 210, first preset size overlay mark; 220, second preset size overlay mark; 230, third preset size overlay mark. Detailed Implementation

[0032] This invention provides a method for fabricating the gate of a 100-bit quantum computing chip and a quantum computing chip itself. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0033] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0034] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0035] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0036] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0037] The inventors discovered that the rapid development of big data, artificial intelligence, and other fields in the 21st century has significantly increased the demand for computing power, rendering traditional computers inadequate for handling complex problems. Simultaneously, as semiconductor manufacturing processes approach their physical limits, the quantum tunneling effect's severe impact on the switching performance of computer MOSFETs is bringing Moore's Law to an end. Against this backdrop, further improving the computing power of traditional chips has become extremely difficult, and costs will also rise dramatically.

[0038] However, the emergence of quantum computers has brought new hope to this predicament. Unlike traditional computers, which exist in only a single "0" or "1" state, qubits exist simultaneously in a superposition of "0" and "1" states, and qubits can form entanglements. Leveraging superposition and entanglement, quantum computers can utilize a finite number of qubits to process more complex tasks within a reasonable timeframe, and may even be able to solve problems that traditional computers struggle with. Therefore, research on quantum computing chips for quantum computers is widely considered an important research direction. Silicon-based quantum computing systems have been proven to be excellent systems that meet the conditions for realizing universal quantum computing, especially the silicon-doped phosphorus (Si:P) system. This system not only has a long coherence time but also allows for fundamental electrical control of quantum dots and high-fidelity spin readout through ohmic contacts fabricated using micro-nano processing techniques.

[0039] To achieve precise control over quantum computing chips, top electrodes are typically integrated above the quantum dots. These electrodes have a larger leakage voltage. Applying a voltage to the top electrode above the corresponding doped site can alter the chemical potential of the doped atom at that site, enabling readout of spin information from that site using a single-electron transistor, while simultaneously controlling the coupling between adjacent sites. It can also change the driving frequency of the qubit, making it resonate with the oscillating magnetic field, allowing addressable operations on each qubit. In current technology, precise overlay of top electrodes has been achieved on quantum devices with a few qubits. However, with the development of quantum computing chips, the number of qubits will inevitably move towards the hundreds of qubits level or even higher, requiring a corresponding increase in the number of top electrodes. However, the area available for integrating top electrodes on a quantum computing chip is limited, and the resolution of current electron beam lithography is also limited. Therefore, the pitch of the top electrodes fabricated within the limited area of ​​the quantum computing chip cannot be too small; otherwise, the top electrodes will connect together, affecting the control effect. This inevitably results in a very limited number of top electrodes that can be fabricated. Moreover, due to resolution limitations, the fabricated top electrodes may break, posing a significant challenge to the integration of quantum computing chips.

[0040] To address the technical problems existing in the prior art, this patent proposes a method for fabricating the gate of a silicon-based atomic 100-bit quantum computing chip. This method can process as many top electrodes as possible in a limited area while ensuring high overlay accuracy, maximizing the use of chip space, and ensuring that the electrode structure is intact and that different top electrode layers do not interfere with each other during operation.

[0041] This invention provides a method for fabricating the gate of a 100-bit quantum computing chip, the steps of which include: Please refer to the following: Figure 1 and Figure 2First, the present invention prepares a substrate for fabricating a quantum computing chip. The substrate is preferably a 4-inch diameter Si (100), that is, a 100-oriented single-polished silicon wafer. Other sizes and materials of wafers can also be used as substrates to facilitate subsequent processing and cutting, which will not be elaborated here.

[0042] S100. Alignment marks for positioning are fabricated on a substrate processed by laser direct writing technology on a hydrogen mask of a scanning tunneling microscope to obtain a first standard substrate with alignment marks. Specifically, the alignment marks are all fabricated using photolithography and etching. Laser direct writing technology is used to expose the positions of the alignment marks, and after exposure, the corresponding positions are etched to obtain the alignment marks used for positioning. For example, as... Figure 3 As shown, nine alignment marks are designed on the substrate, forming a 3x3 matrix. The four corners of the matrix use the first alignment mark, the center uses the second alignment mark, and the midpoints of the four sides use the third alignment mark. This allows for precise location of the device when at least two alignment marks are visible in the image. The nine central alignment marks divide the area into four square regions, each of which can be used independently for quantum device fabrication. It should be noted that... Figure 2 , Figure 5 and Figure 8 The solid and dashed square lines are not actually applied to the wafer; they are used solely for software-aided design. The four corners of the substrate can also be marked with square markers to indicate the corner positions, enabling precise location of the nine alignment marks in the center.

[0043] Further, the step of fabricating alignment marks for positioning on a substrate processed using laser direct writing technology on a hydrogen mask for scanning tunneling microscopy to obtain a first standard substrate with alignment marks includes: S110. Expose alignment marks on the substrate; spin-coat a photoresist layer on the substrate, and selectively expose the substrate according to the alignment marks by laser direct writing; S120, Develop the substrate after selective exposure; S130. Based on the developed image, the substrate is etched using a reactive ion etching machine.

[0044] First, the alignment marks used are exposed on the wafer, which serves as the substrate. Specifically, a layer of photoresist is spin-coated onto the wafer surface using a spin coater. After baking on a hot plate, the wafer is selectively exposed using a laser direct-write method according to the designed alignment mark pattern. The exposed photoresist becomes soluble in the developer, resulting in a developed image. For example, the photoresist used can be S1805. The developer used is AZ Develpoer. After development, residual developer is removed by rinsing in deionized water and the wafer is dried. Finally, the pattern is checked for normality using an optical microscope. The substrate is then etched using a reactive ion etching machine according to the developed image to obtain a first standard substrate with alignment marks.

[0045] Furthermore, after the step of etching the substrate using a reactive ion etching machine based on the developed image, the method further includes: S140. A layer of photoresist is spin-coated onto the surface of the first standard substrate using a spin coater to prepare a slicing protective layer on the upper surface of the first standard substrate. S150. A semi-automatic dicing machine is used to cut the first standard substrate with a dicing protective layer into several rectangular silicon wafers, and the cut rectangular silicon wafers are used as the first standard substrate. S160. Immerse the first standard substrate in a photoresist cleaning solution to remove residual photoresist. S170. Perform a full cleaning of the first standard substrate to remove residual photoresist cleaning solution, organic contaminants, and metal contaminants.

[0046] Specifically, such as Figure 2 As shown, after verifying the pattern is normal, the silicon substrate is etched using a reactive ion etching machine. For example, an OXFORD INSTRUMENTS PlasmaPro 100 RIE etching machine is used, but other models can also be used, which will not be elaborated here. The residual photoresist on the wafer acts as a resist layer, enabling selective etching and removing material from exposed areas to form the desired structure and circuit pattern.

[0047] After etching, a layer of photoresist is first spin-coated using a spin coater as a protective layer for slicing. Then, a semi-automatic dicing machine is used to cut the silicon wafer into multiple rectangular silicon wafers. The purpose of slicing is to facilitate subsequent processing. After slicing, the rectangular silicon wafers are immersed in a photoresist remover to remove residual photoresist. For example, the photoresist remover can be 1165 solution or other types of photoresist removers.

[0048] After soaking to remove the resist, in order to meet the cleanliness requirements of STM (Scanning Tunneling Microscope) for processing quantum devices, the rectangular substrate after slicing is fully cleaned. Exemplarily, the full cleaning steps include: First, removing residual resist remover from the substrate. Specifically, the substrate is soaked in a neutralizing reagent for rinsing to dissolve a small amount of residual resist remover. After emptying the resist remover from the beaker, the first standard substrate is soaked in acetone solution, and then soaked in isopropanol solution to remove residual resist remover from the substrate, followed by rinsing with clean water. Second, the substrate is soaked in a piranha solution and then rinsed. Exemplarily, the piranha solution can be prepared at a ratio of H2SO4:H2O2 = 3:1. The substrate is soaked in the piranha solution, and after soaking, it is rinsed with clean water to remove organic contaminants and some metal from the substrate surface. It should be noted that other highly corrosive etching solutions that can remove impurities and organic contaminants from the substrate surface can also be used as the piranha solution, which will not be elaborated here. Finally, the first standard substrate was cleaned using the RCA standard cleaning method. The solution used in the RCA standard cleaning method can be prepared using one or more chemical reagents. For example, an RCA-2 solution was prepared with a ratio of H2O:HCl:H2O2 = 6:1:1. The RCA-2 solution was heated on a hot plate until bubbling occurred, and the substrate was then immersed in the solution to remove metallic contaminants such as Na, Fe, and Mg from the substrate surface. After immersion, the substrate was rinsed with clean water to complete the full cleaning process, and the first standard substrate was stored in a dedicated petri dish.

[0049] S200. The core structure of the quantum device is fabricated on the first standard substrate using scanning tunneling microscopy hydrogen mask lithography, wherein a number of quantum dots are integrated in the core structure of the quantum device. Specifically, the steps include: S210: The core structure of the quantum device is fabricated on the substrate surface by photolithography using scanning tunneling microscope hydrogen mask lithography technology. S220. Grow an encapsulation protective film on the core structure of the quantum device; S230. A scanning electron microscope is used to locate the relative position between the core structure of the quantum device and the alignment mark.

[0050] After thorough cleaning, the substrate can be used to fabricate the core structure of quantum devices. Specifically, the quantum devices are fabricated using scanning tunneling microscopy with hydrogen mask lithography and STM tip lithography. The core structure of the quantum devices is shown below. Figure 4As shown, it includes several quantum dots, several SETs (Single-Electron Transistors), and several gates. Preferably, the SETs and gates are arranged in pairs around the quantum dots to control the staggered arrangement of the SETs from various directions. The tail ends of each SET and each gate are connected to outwardly extending in-plane electrodes and to ohmic contact electrodes through the in-plane electrodes. The ohmic contact electrodes enable simple manipulation of the quantum dots. The specific implementation of the ohmic contact electrodes is prior art and will not be described in detail here. Preferably, the core structure of the quantum device includes four SETs and two gates, which are connected to outwardly extending in-plane electrodes to complete the fabrication of the core structure of the quantum device. Subsequently, a protective encapsulation layer with a first thickness is grown on the upper surface of the core structure of the quantum device. Preferably, the protective encapsulation layer is an MBE (Molecular Beam Epitaxy) Si layer, used to encapsulate and protect the quantum device substrate.

[0051] Furthermore, after STM fabricates the core structure of the quantum device, it is necessary to precisely locate the quantum device within the alignment mark region. This requires using SEM (Scanning Electron Microscope) to scan and obtain an image of the quantum device's position on the substrate, such as... Figure 5 As shown, the silicon wafer is placed in the field of view of a scanning electron microscope (SEM). After focusing on a dedicated focusing plate and adjusting parameters such as contrast and brightness, the field of view is moved to the core structure region. A SEM image containing the core structure of the quantum device with the etched markings centered is scanned. On a computer or any available host computer, the source file of the designed alignment marks is imported using Inkscape software, along with the scanned SEM image of the device. By scaling, panning, and cropping the SEM image, the alignment marks in the SEM image are aligned with the corresponding alignment marks in the source file. Then, the outline of the quantum device's core structure is scanned, and an image showing the relative position of the core structure and the markings is obtained and saved as a .SVG file. Subsequently, the saved .SVG file, containing the quantum device's core structure and alignment marks, is imported into Layout-edit software. The alignment marks are positioned to coincide with the designed alignment marks, accurately locating the core structure of the quantum device within the designed alignment marks, facilitating subsequent design and fabrication.

[0052] Because the top electrode requires high overlay precision, the alignment marks used for positioning cannot meet the required precision. Therefore, before fabricating the top electrode, an additional set of overlay marks needs to be fabricated. The top electrode, which is set on the upper surface of the core structure of the quantum device after fabrication, is smaller than the size of the alignment marks, and its position and size are different, thus enabling higher precision overlay fabrication.

[0053] S300: Secondary processing of the top electrode and marking on the first standard substrate to obtain the second standard substrate; To further improve the overlay accuracy, a second set of top electrode overlay marks is processed within the smallest rectangular area formed by the four adjacent alignment marks. For example, please refer to [the document / reference needed]. Figure 5 , Figure 8 and Figure 9 As shown, since the core structure of the quantum device is already positioned at the upper left corner of the substrate alignment mark 100, this area is used for illustration. Exemplarily, the top electrode overlay mark 200 includes a first preset-size overlay mark 210, a second preset-size overlay mark 220, and a third preset-size overlay mark 230. The second preset-size overlay mark is nested within the first preset-size overlay mark 210, and the third preset-size overlay mark 230 is nested within the second preset-size overlay mark. The first preset-size overlay mark 210 is smaller than the alignment mark 100; the second preset-size overlay mark 220 is smaller than the first preset-size overlay mark 210; and the third preset-size overlay mark 230 is the same size as the second preset-size overlay mark 220. The first preset-size overlay mark 210, the second preset-size overlay mark 220, and the third preset-size overlay mark 230 each contain four positioning overlay marks, and they gradually approach the core structure of the quantum device, thereby enabling the approximate positioning of the core structure of the quantum device by positioning the first, second, and third preset-size overlay marks.

[0054] S400, An oxide layer is grown on a second standard substrate with alignment mark 100 and top electrode overlay mark 200 on its surface; After the overlay marking is completed, an oxide layer is grown on the substrate surface to isolate the top electrode from other structures. Specifically, the substrate is loaded into an atomic layer deposition (ALD) apparatus. During the deposition process, based on chemical vapor deposition, a dielectric layer is obtained by repeatedly and alternately depositing precursor materials in the form of single-atom films on the substrate surface over several cycles. For example, water (H2O) and trimethylaluminium (TMA) can be used as precursors, and 90 cycles can be grown at a temperature of 200°C to obtain a dense Al2O3 film of a second thickness, which is used as the dielectric layer and on which the top electrode is fabricated. Preferably, a PICSUN ALD apparatus can be used, or other models of ALD apparatus can be used, which will not be described in detail here.

[0055] Furthermore, in some preferred embodiments, before the step of fabricating several top electrode layers on the oxide layer using the top electrode overlay marking 200, wherein each top electrode layer is staggered and partially overlaps in the vertical direction to obtain a 100-bit-level quantum computing chip, the method further includes: M100. The left and right top electrode columns are located on the computer according to the position of the quantum dots. The distance between each top electrode in the left top electrode column is equal, the distance between each top electrode in the right top electrode column is equal, and the left and right top electrode columns are symmetrically arranged. M200: The top electrodes in the left top electrode column are sequentially assigned to several top electrode layers, and the top electrodes in the right top electrode column are sequentially assigned to several top electrode layers, wherein each top electrode and its adjacent top electrode are located in different top electrode layers.

[0056] Specifically, before fabricating the top electrode, the design and fabrication process of the top electrode are simulated using computer software.

[0057] First, the parameters of the top electrode are adjusted. In silicon-based quantum computing systems, quantum dots are integrated into quantum devices fabricated using STM (Spatial Measurement Unit). Each quantum dot can contain multiple atomic nuclei, and qubits are encoded by the nuclear spin of the atomic nuclei. Therefore, each quantum dot can contain multiple qubits. Qubits can be initialized, manipulated, and read out through the SET (Search Engine Set) integrated near the atomic nuclei and the top electrode above the atomic nuclei. A single quantum dot can be controlled by multiple top electrodes arranged nearby. Different pairs or combinations of top electrodes controlling a single quantum dot can simultaneously affect its neighboring quantum dot positions, exhibiting significant differences in control. This allows for effective coupling between adjacent quantum dots, forming a fully connected, hundred-qubit-level quantum computing system. Therefore, the parameters of the quantum dots can be adjusted according to their positions as follows: Figure 6 The top electrode is arranged as shown.

[0058] exist Figure 6 In this design, a quantum dot array is located between the left and right top electrode columns. This array comprises a plurality of quantum dots arranged at equal intervals. Alternatively, it can be an N×1 or N×M quantum dot array (N>3, M>1), i.e., an N x 1 or N x M column quantum dot array. The quantum dots are initialized, manipulated, and readout controlled by the top electrodes. Preferably, to achieve 100-qubit-level quantum computing, the quantum dot array comprises at least 20 quantum dots. In this preferred embodiment, a 20 x 1 column quantum dot array is used as an example, comprising 20 quantum dots, each containing 5-6 qubits, achieving a 100-qubit scale. Above the quantum dots, the top electrodes are evenly distributed on the left and right sides of the quantum dots in three split-gate configurations. Each quantum dot is controlled by the top electrodes surrounding it. Figure 6 Quantum dot 5 can be controlled by four top electrodes (L3, L4, R3, and R4) distributed around it. Due to the long fabrication cycle of micro / nano devices, it is essential to optimize the top electrode structure parameters through simulation to reduce experimental costs. In simulation software, the placement of the top electrodes in the quantum device, the distance between top electrodes, the spacing between the left and right sets of top electrodes, and the structure of the top electrodes are adjusted. The top electrode voltage is also adjusted, and the two-dimensional charge stability diagram of the SET is simulated to test the control capability of the top electrodes over the quantum dot.

[0059] Specifically, please refer to the following: Figure 6 and Figure 7 The distance between top electrodes refers to the center-to-center distance between two adjacent electrodes. In this invention, the top electrode layers are mutually insulated; therefore, the spacing refers to the distance between the top electrodes within the top electrode layer. Figure 7 That is Figure 6The diagram illustrates the top electrodes within the same top electrode layer in region A. The spacing indicates the distance between two top electrodes. When the spacing becomes too small, short circuits may occur between top electrodes within the same top electrode layer, potentially damaging the quantum computing chip. In existing technologies, the control range of top electrodes when manipulating quantum dots is limited. Existing single-layer fabrication techniques, to ensure sufficient distance between top electrodes, result in low top electrode density; a single quantum dot or even multiple quantum dots may only have one electrode nearby, requiring control solely based on that single electrode. In this application, however, the top electrode distribution employs several top electrode layers. Within each top electrode layer, the distance between top electrodes remains relatively wide, preventing short circuits. Furthermore, when several top electrode layers are superimposed, the overall top electrode structure exhibits vertical misalignment and local overlap, increasing the number of top electrodes near the quantum dot. This results in multiple electrodes near a single quantum dot, allowing for coordinated control by multiple electrodes.

[0060] For ease of explanation, Figure 6 The vertical direction of the top electrode, i.e., the extension direction of the left and right top electrode columns, is the Y-axis direction. The horizontal direction, i.e., the direction of the line connecting any top electrode in the left top electrode column to the quantum dot (which serves as the center of symmetry) to its symmetrical top electrode in the right top electrode column, is the X-axis direction. The placement of the top electrodes and quantum dots is as follows: Figure 6 As shown.

[0061] During the test, the voltage of the Y-axis top electrode pair was fixed, and the voltage of the X-axis top electrode pair was swept from 0mV to 500mV to obtain the Coulomb peak of SET as a function of the Y-axis voltage. Then, the voltage of the Y-axis top electrode pair was increased, and the same process was performed on the X-axis top electrode pair. This process was repeated continuously to obtain the two-dimensional charge stability map of SET.

[0062] The image after scanning of the four top electrodes L3&L4 and R3&R4 is as follows: Figure 12 As shown in (a), the scanned images of the four top electrodes L4&L5 and R4&R5 are as follows. Figure 12 As shown in (b), the scanned images of the two top electrodes L3 and R3 are as follows: Figure 12 As shown in (c), the scanned images of the four top electrodes L12 & L13 and R12 & R13 are as follows. Figure 12 As shown in (d), the scanned images of the two top electrodes L1 and R1 are as follows: Figure 12As shown in (e), the green line represents the Coulomb peak of SET, and the line formed by connecting the breaks in the green line represents the tunneling line of the quantum dot. If there are no quantum dots between the electrodes, the green line in the figure will not break. When a break occurs, it indicates that a quantum dot has been detected nearby. The breaks are connected to form a straight line with a defined slope, which is the tunneling line of a single quantum dot. A tunneling line with a defined slope represents the presence of one quantum dot. For example, according to... Figure 12 The images obtained after scanning the four top electrodes L3 & L4 and R3 & R4 show that two quantum dots can be detected between the four top electrodes. During the simulation, the positions of the quantum dots are fixed. The control effect of the top electrodes is gradually optimized by adjusting various parameters such as the top electrode linewidth, single-layer spacing, the size of the gap between split gates, and the size of the overlap between different electrode layers, adjusting only one parameter at a time and rescanning the image. This process selects parameters that maximize the number of quantum dots near the top electrodes. For example, ideally, the two-dimensional charge stability maps obtained through L3 & L4 and R3 & R4 should detect quantum dots 3, 4, 5, and 6 nearby. However, in practice, only the two closest quantum dots are detected, which meets the actual requirements.

[0063] Based on the information in the SET two-dimensional stability plot under the top electrode scan, the design parameters of the top electrode were adjusted. After multiple adjustments and simulations, the final design of the top electrode was determined as follows: Figure 10 and Figure 11 As shown.

[0064] As can be seen, the top electrode structure in this invention adopts a multi-layer stacked + split-gate design. The top electrode is integrated on the center of the quantum computing chip and is symmetrically distributed on both sides of the quantum dot in left and right top electrode columns. The left side shows the position of the top electrode on the quantum device, and the right side shows its structure in the core region of the quantum device. Preferably, the top electrode in this invention is divided into three top electrode layers. For ease of understanding, the different colors of the top electrode represent the layers it belongs to. There are three layers: dark green, orange, and green, which are the first top electrode layer TG1, the second top electrode layer TG2, and the third top electrode layer TG3, respectively. Each layer adopts a split-gate design, with a selectable spacing of 50 nm. In the innermost horizontal line region, the top electrodes are on the same horizontal line, and in the vertical direction, the spacing between the top electrodes can be 80 nm. The second and third top electrode layers are evenly distributed between the first top electrode layer TG1, and each top electrode is designed as a single innermost line, with the number of lines increasing sequentially from the inside out. This design can avoid the occurrence of top electrode breakage during fabrication.

[0065] In other words, to maintain a certain spacing between top electrodes in the same top electrode layer while maximizing the top electrode density, adjacent top electrodes in the left and right top electrode columns are placed in different top electrode layers. Since different layers are isolated by dielectric layers, even if there is local overlap between top electrodes in the vertical direction, two adjacent top electrodes will not short-circuit.

[0066] S500: Using the top electrode overlay mark 200, several top electrode layers are overlaid on the oxide layer. The top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit quantum computing chip.

[0067] Furthermore, prior to the step of overlay positioning based on the top electrode overlay mark 200 to locate the exposure position of the top electrode on the second standard substrate, the method further includes: N100. Move the second standard substrate to the Faraday cup position, align the tip of the scanning electron microscope with the center of the aperture, detect the beam current and record it as the first beam current value.

[0068] Specifically, a Faraday cup is provided on the sample stage, which is used to detect the intensity and energy distribution of the electron beam. The electron beam of the SEM is directed to the center of the Faraday cup aperture, and the second standard substrate is placed at the Faraday cup position on the sample stage. The detected beam current value is the first beam current value.

[0069] A further step of the present invention involves fabricating several top electrode layers on the oxide layer using the top electrode overlay mark 200, wherein the top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit-level quantum computing chip. S510. Perform overlay positioning according to the top electrode overlay mark 200 to locate the exposure position of the top electrode on the second standard substrate. The step of overlaying and positioning the top electrode on the second standard substrate according to the top electrode overlay mark 200 includes: S511. Prepare a photomask on the second standard substrate; S512. A scanning electron microscope image is obtained by scanning a photolithographic mask using a scanning electron microscope equipped with a pattern generator. S513. Move the second standard substrate to the zero point position of the alignment corner, and perform three-point calibration according to the alignment mark 100; S514. Further focus on the first preset size overlay mark 210 of the top electrode overlay mark 200, and use the image of the first preset size overlay mark 210 in the scanning electron microscope image to calibrate the first preset size overlay mark 210 on the second standard substrate in sequence, thereby accurately positioning it to the second preset size overlay mark 220. S515. Using the image of the second preset size overlay mark 220 in the scanning electron microscope image, the second preset size overlay mark 220 on the second standard substrate is calibrated sequentially, and then precisely positioned to the third preset size overlay mark 230. S516. The third preset size overlay mark 230 on the second standard substrate is calibrated sequentially using the third preset size overlay mark 230 image in the scanning electron microscope image; S517. Simultaneously select the first preset size overlay mark 210, the second preset size overlay mark 220 and the third preset size overlay mark 230 with the top electrode image, calibrate all the top electrode overlay marks 200, and locate the exposure position of the top electrode.

[0070] S520. At the exposure position of the second standard substrate, the top electrode and the corresponding fan-out structure layer are exposed under the first beam current value, and the exposure position is developed. S530: A high-vacuum electron beam evaporation coating machine is used to deposit an aluminum film on the substrate to process the top electrode; S540. A dielectric layer for isolating the top electrode is grown on the top electrode using an atomic layer deposition apparatus. S550. Repeat the above steps to perform overlay processing on several other top electrode layers, with each top electrode layer processed in the gap between two adjacent stacked top electrodes.

[0071] Specifically, taking the fabrication process of the first top electrode layer TG1 as an example, the following steps are taken: First, an adhesion promoter is spin-coated onto the substrate using a spin coater to improve the photoresist adhesion and prepare a photomask for subsequent etching. A layer of photoresist adhesion promoter is spin-coated onto the surface, and the substrate surface is rinsed with deionized water and dried. Then, photoresist is spin-coated onto the substrate surface using the same parameters. After spin coating, the substrate is placed on a hot plate for baking, and after cooling, the photomask is obtained. The photoresist adhesion promoter can be Surpass 3000, and the drying step is performed in a nitrogen atmosphere.

[0072] The top electrode is exposed on the substrate. This exposure needs to be performed on an SEM equipped with a RAITH pattern generator, which fabricates nanostructures using direct electron beam exposure. The substrate is fixed on a dedicated substrate holder for sample injection. Parameters and a specific acquisition mode are set. For example, the RAITH pattern generator can be set to an accelerating voltage of 15 kV, an aperture of 10 μm, and an InLens acquisition mode. Focusing is completed on a dedicated focusing plate. After adjusting contrast and brightness, the write field is called, corrected, and saved. The beam current is measured and recorded at the Faraday cup position, aligned with the aperture center, to obtain the first beam current value. The substrate stage is moved to the lower left corner of the rectangular substrate, and the substrate zero point and positive X-axis direction are calibrated relative to the design. Figure 1 To align, locate the outermost square of alignment mark 100, perform three-point calibration, mark a point far from the processing area to determine the safe position of the needle tip, and further focus.

[0073] Further, the top electrode overlay marks 200 are used for overlay. The four outermost first preset size overlay marks 210 are selected for overlay. An exposure task is created and the write field is invoked. The 12th layer where the overlay marks are located is selected as the exposure area. For example, during the overlay process, the overlay window can be selected as 5 μm and the write field as 60 μm. Other overlay parameters can also be selected, which will not be elaborated here. The measured first beam current value is entered. For example, the first beam current value is about 20 pA. During the overlay process, a laser with the same first beam current value is used for processing. The dwell time is calculated, and the four first preset size overlay marks 210 are scanned and calibrated sequentially to accurately find the overlay marks of the inner layer. Then, the four second preset size overlay marks 220 of the middle layer are selected for overlay. The overlay window is 0.5 μm. Keeping the parameters unchanged, the four second preset size overlay marks 220 are scanned and calibrated sequentially. As the calibration progresses from the first preset size overlay mark 210 to the second preset size overlay mark 220, the selected overlay window parameters gradually decrease, and the accuracy after calibration gradually improves. After calibration, the 12th layer and the layer containing the top electrode of the internal linear structure are simultaneously selected, scanned, and calibrated again to further locate the exposure position of the top electrode. The top electrode is exposed immediately after calibration to prevent excessive waiting time from causing slight electron beam shifts that would affect overlay accuracy. After exposure, the layer containing the fan-out structure connected to the linear top electrode is selected, and the corresponding positions of the top electrode and the connected fan-out structure are exposed. The fan-out structure is used to splice with the binding electrode.

[0074] After exposure, the substrate is developed in a developer solution and then transferred to an IPA solution for fixing. After fixing, it is dried with nitrogen gas to obtain the top electrodes and fan-out structures of the first top electrode layer TG1. After development, an aluminum film is deposited on the substrate surface using a high-vacuum electron beam evaporation coating machine. After coating, the substrate is removed, immersed in a resist remover solution for resist removal, heated on a hot plate, then lifted off, and dried with nitrogen gas. The image of the first top electrode layer TG1 after processing is shown below. Figure 13 As shown.

[0075] Accordingly, Figure 14 This is a schematic diagram of the structure after the second top electrode layer TG2 has been fabricated. Figure 15 This is a schematic diagram of the structure after the third top electrode layer TG3 has been fabricated. It should be noted that the methods used to fabricate the other top electrodes are the same as those used to fabricate the first top electrode layer TG1. Furthermore, an alumina dielectric layer must be grown before fabricating the top electrodes to isolate the different top electrode layers. The fabrication process for the top electrodes is basically the same as for the first layer; only the corresponding layer number of the top electrode on the design pattern needs to be selected when choosing the number of exposure layers. Preferably, the quantum computing chip includes three top electrode layers, that is, the second top electrode layer TG2 and the third top electrode layer TG3 are fabricated based on the first top electrode layer TG1. The actual fabrication effects of the second top electrode layer TG2 and the third top electrode layer TG3 are as follows: Figure 14 and Figure 15 As shown. Compared to traditional single-top-electrode layer fabrication methods, which leave large gaps between top electrodes and have low space utilization, increasing the fabrication scale and reducing the spacing can easily lead to electrode connections, reducing the controllability of the top electrode. This patent uses a three-layer stacking method to fabricate the top electrode, and a dielectric layer is grown before fabricating each top electrode layer. The top electrodes fabricated using this method have smaller spacing and larger scale, and the different layers do not affect each other, greatly improving the space utilization of the quantum computing chip. In addition, compared with the traditional SADP / SAQP technology based on deposition and etching applied to STM atomically doped silicon-based quantum systems, the top electrode setting scheme in this invention does not require an etching step above the core structure of the quantum device, avoiding the possibility of damaging the core structure of the quantum device buried under the silicon substrate.

[0076] Based on the same inventive concept, the present invention also provides a quantum computing chip, which is fabricated using the above-described method for fabricating gates of a 100-bit-level quantum computing chip; wherein, the top electrode of the quantum computing chip includes several top electrode layers; the top electrodes of the quantum computing chip are symmetrically distributed on the core structure of the quantum device.

[0077] In a further embodiment of the present invention, the top electrode of the quantum computing chip includes a first top electrode layer TG1, a second top electrode layer TG2, and a third top electrode layer TG3. The first top electrode layer TG1, the second top electrode layer TG2, and the third top electrode layer TG3 are stacked on top of each other, and the top electrodes in the first top electrode layer TG1, the second top electrode layer TG2, and the third top electrode layer TG3 are staggered from each other in the vertical direction. Each top electrode is connected to a fan-out structure, and the width of the fan-out structure is greater than the width of the top electrode. The core structure of the quantum device of the quantum computing chip includes an N×1 or N×M quantum dot array (N>3, M>1) composed of several quantum dots. The quantum dots are initialized, manipulated, and readout operations controlled by the top electrode.

[0078] in, Figure 10 The diagram shows the design of the core electrode section. Electrodes of the same color represent those in the same layer. The design consists of three electrode layers with some overlap. Each electrode can extend outwards to connect to the main electrode. Furthermore, each electrode layer is designed with two symmetrical parts, a split-gate design, which further increases the electrode density and enhances the controllability of the top electrode over the qubit. In fabricating the top electrodes, the first layer is fabricated using photolithography and deposition techniques. Then, a dielectric layer is grown using atomic layer deposition (ALD), which isolates the different electrode layers. The second and third layers are fabricated using the same method. The width of a single top electrode is approximately 25-30 nm. After the three-layer top electrode fabrication, the overall spacing between the top electrodes is approximately 26.7 nm. Based on the reasonable size of a 14 nm spacing between adjacent bottom doped sites, combined with finite element simulation, it can be seen that for a single quantum dot site, at least six top electrodes can effectively control the Fermi level or chemical potential at that site. Simultaneously, according to… Figure 12 Two-dimensional scans of different or combined top electrodes can reveal the differences in the control of adjacent sites by different top electrodes, thereby enabling effective coupling between adjacent sites and forming a fully connected 20-site quantum computing system. Since each site typically forms 4 to 6 qubits depending on the number of activated internal doped atoms, this 20-site fully connected silicon-based quantum computing system can theoretically realize a quantum computing chip with hundreds of qubits. Compared with existing fabrication processes, this approach can fabricate a greater number of top electrodes within the limited area of ​​a quantum computing chip, significantly improving space utilization while ensuring the integrity of the electrode structure, enabling more precise control of the quantum computing chip.

[0079] In summary, this invention provides a method for fabricating the gate of a 100-bit quantum computing chip and the quantum computing chip itself. The method for fabricating the gate of a 100-bit quantum computing chip includes the following steps: fabricating alignment marks for positioning on a substrate processed by laser direct writing technology using a scanning tunneling microscope hydrogen mask, obtaining a first standard substrate with alignment marks; fabricating a core structure of a quantum device on the first standard substrate using scanning tunneling microscope hydrogen mask lithography, wherein the core structure of the quantum device integrates several quantum dots; fabricating a second top electrode overlay mark on the first standard substrate, obtaining a second standard substrate; growing an oxide layer on the second standard substrate with alignment marks and top electrode overlay marks on its surface; and fabricating several top electrode layers on the oxide layer using the top electrode overlay marks, wherein the top electrode layers are staggered and partially overlap in the vertical direction, thereby obtaining a 100-bit quantum computing chip. The quantum computing chip fabrication method of the present invention utilizes the top electrode overlay marking and employs a multi-layer stacking approach to process several top electrode layers on the oxide layer. This method produces top electrode layers with smaller spacing and larger scale, and different layers do not affect each other. While ensuring the spacing of the top electrodes, it greatly improves the space utilization of the quantum computing chip, thereby enabling the fabrication of hundreds of bits of quantum computing chips on a limited on-chip space.

[0080] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for fabricating a gate for a 100-bit quantum computing chip, characterized in that the steps include... include: Alignment marks for positioning were fabricated on a substrate processed by laser direct writing technology using a hydrogen mask for scanning tunneling microscope, resulting in a first standard substrate with alignment marks. The core structure of the quantum device is fabricated on the first standard substrate using scanning tunneling microscopy hydrogen mask lithography, and the core structure of the quantum device integrates several quantum dots. A second standard substrate is obtained by second-processing the top electrode and marking it. An oxide layer is grown on a second standard substrate with alignment marks and top electrode overlay marks on its surface; By using the top electrode overlay markings to overlay several top electrode layers on the oxide layer, the top electrode layers are staggered with each other and partially overlap in the vertical direction to obtain a 100-bit quantum computing chip.

2. The method for fabricating the gate of a 100-bit-level quantum computing chip according to claim 1, characterized in that, The steps for fabricating a 100-bit quantum computing chip by overlaying several top electrode layers on an oxide layer using the top electrode overlay markings, with each top electrode layer staggered and partially overlapping in the vertical direction, include: The top electrode is positioned by overlay markings to determine the exposure location of the top electrode on the second standard substrate. At the exposure position on the second standard substrate, the top electrode and the corresponding fan-out structure layer are exposed under the first beam current value, and the exposure position is developed. A high-vacuum electron beam evaporation coating machine was used to deposit an aluminum film on the substrate to fabricate the top electrode. A dielectric layer for isolating the top electrode is grown on the top electrode using an atomic layer deposition apparatus. Repeat the above steps to perform overlay processing on several other top electrode layers, with each top electrode layer processed in the gap between two adjacent stacked top electrodes.

3. The method for fabricating the gate of a 100-bit-level quantum computing chip according to claim 1, characterized in that, The step of fabricating alignment marks for positioning on a substrate processed using laser direct writing technology on a hydrogen mask of a scanning tunneling microscope to obtain a first standard substrate with alignment marks includes: Alignment marks are exposed on the substrate; a photoresist layer is spin-coated on the substrate, and the substrate is selectively exposed according to the alignment marks by laser direct writing; Develop the substrate after selective exposure; Based on the developed image, the substrate is etched using a reactive ion etching machine.

4. The method for fabricating the gate of a 100-bit-level quantum computing chip according to claim 1, characterized in that, The step of fabricating the core structure of the quantum device on the first standard substrate using scanning tunneling microscopy hydrogen mask lithography, wherein the core structure of the quantum device integrates several quantum dots, includes: The core structure of the quantum device was fabricated on the substrate surface by photolithography using scanning tunneling microscope hydrogen mask lithography. An encapsulation and protective film is grown on the core structure of the quantum device; Scanning electron microscopy was used to locate the relative position between the core structure of the quantum device and the alignment mark.

5. The method for fabricating the gate of a 100-bit-level quantum computing chip according to claim 2, characterized in that, The top electrode overlay marking includes a first preset size overlay marking, a second preset size overlay marking, and a third preset size overlay marking, wherein the second preset size overlay marking is nested within the first preset size overlay marking, and the third preset size overlay marking is nested within the second preset size overlay marking; The first preset size overprint mark is smaller than the alignment mark; The second preset size overprint mark is smaller than the first preset size overprint mark, and the third preset size overprint mark is equal in size to the second preset size overprint mark; The step of overlaying and positioning the top electrode on the second standard substrate according to the top electrode overlay marking includes: A photomask is prepared on the second standard substrate; Scanning electron microscope images are obtained by scanning a photolithographic mask using a scanning electron microscope equipped with a pattern generator. Move the second standard substrate to the zero point position of the alignment corner, and perform three-point calibration according to the alignment marks; The focus is further shifted to the first preset size overlay mark of the top electrode overlay mark, and the first preset size overlay mark on the second standard substrate is calibrated sequentially using the image of the first preset size overlay mark in the scanning electron microscope image, thereby accurately positioning the second preset size overlay mark; The second preset size overlay mark on the second standard substrate is calibrated sequentially using the second preset size overlay mark image in the scanning electron microscope image, thereby accurately locating to the third preset size overlay mark; The third preset size overlay mark on the second standard substrate is calibrated sequentially using the third preset size overlay mark image in the scanning electron microscope image; Simultaneously, select the first preset size overlay mark, the second preset size overlay mark, and the third preset size overlay mark and the top electrode image, calibrate all the top electrode overlay marks, and locate the exposure position of the top electrode.

6. The method for fabricating the gate of a 100-bit-level quantum computing chip according to claim 1, characterized in that, Before the step of fabricating several top electrode layers on the oxide layer using the top electrode overlay markings, wherein the top electrode layers are staggered and partially overlap in the vertical direction to obtain a 100-bit-level quantum computing chip, the process further includes: The left and right top electrode columns are located on a computer based on the position of the quantum dots. The distance between each top electrode in the left top electrode column is equal, and the distance between each top electrode in the right top electrode column is equal. The left and right top electrode columns are symmetrically arranged. The top electrodes in the left top electrode column are sequentially assigned to several top electrode layers, and the top electrodes in the right top electrode column are sequentially assigned to several top electrode layers. Each top electrode and its adjacent top electrode are located in different top electrode layers.

7. A quantum computing chip, characterized in that, The quantum computing chip is fabricated using the gate fabrication method for a 100-bit quantum computing chip as described in any one of claims 1 to 6; wherein the top electrode of the quantum computing chip includes several top electrode layers; the top electrodes of the quantum computing chip are symmetrically distributed on the core structure of the quantum device.

8. The quantum computing chip according to claim 7, characterized in that, The top electrode of the quantum computing chip includes a first top electrode layer, a second top electrode layer, and a third top electrode layer. The first top electrode layer, the second top electrode layer, and the third top electrode layer are stacked on top of each other, and the top electrodes in the first top electrode layer, the second top electrode layer, and the third top electrode layer are staggered from each other in the vertical direction. Each top electrode is connected to a fan-out structure, and the width of the fan-out structure is greater than the width of the top electrode. The core structure of the quantum computing chip includes an N×1 or N×M quantum dot array (N>3, M>1) composed of several quantum dots. The quantum dots are initialized, manipulated and read out by the top electrode.

Images