Transistor, semiconductor device and manufacturing method thereof, and electronic equipment

Abstract

The invention discloses a transistor, a semiconductor device, a manufacturing method of the semiconductor device and electronic equipment. The transistor comprises a first electrode, a second electrode, a semiconductor layer, a gate insulating layer and a gate electrode, wherein the semiconductor layer, the gate insulating layer and the gate electrode are located between the first electrode and the second electrode and are sequentially arranged; the first electrode and the second electrode are distributed on two sides of the semiconductor layer along a first direction, and the gate electrode is distributed on one side of the semiconductor layer along a second direction; the first direction is crossed with the second direction; the gate electrode extends along the first direction; the orthographic projection of the gate electrode on the plane perpendicular to the first direction is not overlapped with the orthographic projection of the first electrode on the plane perpendicular to the first direction. The orthographic projection of the gate electrode on the plane perpendicular to the first direction is not overlapped with the orthographic projection of the second electrode on the plane perpendicular to the first direction. The leakage current of the transistor provided by the embodiment of the invention is small.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a transistor, a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a transistor, a semiconductor device, a manufacturing method thereof, and an electronic device. The transistor has a small leakage current and a large on-state current.

[0006] This application provides a transistor comprising: a first electrode, a second electrode, a semiconductor layer, a gate insulating layer, and a gate electrode arranged sequentially between the first electrode and the second electrode; the first electrode and the second electrode are distributed on both sides of the semiconductor layer along a first direction, and the gate electrode is distributed on one side of the semiconductor layer along a second direction; the first direction intersects the second direction; the gate electrode extends along the first direction. The orthographic projection of the gate electrode on the plane perpendicular to the first direction does not overlap with the orthographic projection of the first electrode on the plane perpendicular to the first direction, and the orthographic projection of the gate electrode on the plane perpendicular to the first direction does not overlap with the orthographic projection of the second electrode on the plane perpendicular to the first direction.

[0007] In some embodiments of this application, the gate electrode is phase-spaced with at least one of the first electrode and the second electrode.

[0008] In some embodiments of this application, the semiconductor layer has a groove between the first electrode and the second electrode, the groove being recessed toward the gate electrode; Both the first electrode and the second electrode extend along the first direction, and the two ends of the groove are in contact with the end face of the first electrode and the end face of the second electrode, respectively.

[0009] In some embodiments of this application, the semiconductor layer extends to the sidewall of at least one of the first electrode and the second electrode.

[0010] This application embodiment also provides a semiconductor device, the semiconductor device comprising: A plurality of memory cells are located on a substrate, the plurality of memory cells being distributed at intervals along a row direction and a column direction parallel to the substrate on one side of the substrate; the memory cells include semiconductor device transistors as described above; the first direction is perpendicular to the substrate, and the second direction is the row direction; Bit lines extend along the row direction and are connected to the second electrode of the transistor; Word lines extend along the column direction and are connected to the gate electrode of the transistor.

[0011] In some embodiments of this application, the bit line is connected to the second electrode of a plurality of memory cells spaced apart along the row direction; The word line is connected to the gate electrodes of a plurality of memory cells spaced apart along the column direction, and the gate electrodes are part of the word line.

[0012] In some embodiments of this application, the gate insulating layers of two adjacent memory cells along the row direction are a single, integral structure; and / or, The gate insulating layer of the plurality of memory cells spaced apart along the column direction is a single structure.

[0013] This application also provides a method for manufacturing a semiconductor device, the method comprising: A plurality of transistor pillars are formed on a substrate at intervals along row and column directions parallel to the substrate, each transistor pillar including a first electrode layer, a sacrificial layer and a second electrode layer stacked sequentially along a direction away from the substrate; A semiconductor layer is formed on the sidewall of each of the transistor pillars; Each of the transistor pillars is spaced apart into two transistor subpillars in the row direction, and the sacrificial layer is removed during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer; each of the transistor subpillars includes a first electrode, a second electrode, and a semiconductor layer located between the first electrode and the second electrode, which are stacked and spaced apart in a direction away from the substrate, and the first electrode and the second electrode are formed by the spaced first electrode layer and the second electrode layer, respectively; A gate insulating layer and a gate electrode are sequentially formed on the inner sidewall of the semiconductor layer, and the transistor sub-pillar, the gate insulating layer and the gate electrode constitute a transistor.

[0014] In some embodiments of this application, the step of spacing each of the transistor pillars into two transistor sub-pillars in the row direction, and removing the sacrificial layer during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer, includes: Each of the transistor pillars is etched along the direction toward the substrate to form a gate trench extending along the column direction. The gate trench penetrates a column of transistor pillars spaced apart along the column direction. The gate trench space each of the transistor pillars into two transistor sub-pillars in the row direction, and the gate trench penetrates the sacrificial layer in the row direction, exposing the inner sidewall of the semiconductor layer covered by the sacrificial layer.

[0015] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a gate electrode on the inner sidewall of the semiconductor layer includes: An insulating layer is filled in the region of the gate trench corresponding to the first electrode; The gate insulating layer and the gate electrode layer are sequentially formed on the inner wall of the remaining gate trench; Disconnect the gate electrode layer on the bottom surface of the gate trench; The insulating layer is filled into the gate trench; The insulating layer and the gate electrode layer within the gate trench are etched back to expose the gate insulating layer located on the sidewall of the second electrode; The insulating layer is filled into the gate trench.

[0016] In some embodiments of this application, the width of each region of the gate trench along the direction toward the substrate is the same; The inner sidewall of the semiconductor layer located in the same transistor sub-pillar is flush with the sidewall of the first electrode on the side away from the semiconductor layer and the sidewall of the second electrode on the side away from the semiconductor layer in a direction perpendicular to the substrate.

[0017] In some embodiments of this application, forming a semiconductor layer on the sidewalls of each of the transistor pillars includes: The two sidewalls of the sacrificial layer distributed along the row direction are etched to recess the two sidewalls of the sacrificial layer distributed along the row direction by a set depth in the row direction; The semiconductor layer is formed on the two sidewalls of each of the transistor pillars distributed along the row direction; An isolation layer is filled in the gaps between the transistor pillars.

[0018] In some embodiments of this application, forming the semiconductor layer on the two sidewalls of each of the transistor pillars distributed along the row direction includes: The semiconductor layer is formed on the two sidewalls of each transistor pillar distributed along the row direction using an epitaxial growth process.

[0019] In some embodiments of this application, the material of the sacrificial layer is silicon-germanium, and the material of the semiconductor layer is silicon.

[0020] In some embodiments of this application, the formation of a plurality of transistor pillars spaced apart along row and column directions parallel to the substrate on the substrate, each transistor pillar comprising a first electrode layer, a sacrificial layer, and a second electrode layer stacked sequentially in a direction away from the substrate, includes: A first electrode layer, a sacrificial layer, and a second electrode layer are sequentially formed on one side of the substrate to obtain a stacked structure. The stacked structure is etched along the direction toward the substrate to form a plurality of trenches extending along the row direction and penetrating the stacked structure. The plurality of trenches are spaced apart in the column direction, and the plurality of trenches divide the stacked structure into a plurality of baffles. The trench is filled with an insulating layer; Each of the baffles is etched along a direction toward the substrate, forming at least one through-hole in each baffle, the through-hole spacing each baffle into a plurality of transistor pillars spaced apart along the row direction.

[0021] In some embodiments of this application, the manufacturing method further includes: After the transistors are formed, a bit line extending along the row direction is formed on the side of the second electrode away from the substrate, and the bit line is connected to the second electrodes of a plurality of transistors spaced apart along the row direction; and The gate electrodes of a plurality of transistors spaced apart along the column direction are connected to form word lines extending along the column direction.

[0022] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.

[0023] The transistors in this application adopt a side-gate structure, which completely interleaves the gate electrode with the source and drain, thereby reducing or avoiding leakage problems and enabling a larger on-state current.

[0024] Furthermore, in this embodiment, the transistors have drains and semiconductor layers distributed vertically, which reduces the area occupied by the memory cells and increases the integration density of the semiconductor devices. In addition, the structure and manufacturing process of both the transistors and semiconductor devices are relatively simple.

[0025] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0027] Figure 1A A top view of a transistor as an exemplary embodiment of this application; Figure 1B for Figure 1A A side view of the transistor shown; Figure 1C for Figure 1A A side view of the transistor from another angle; Figure 1D A top view of another transistor as an exemplary embodiment of this application; Figure 2A A schematic diagram of the longitudinal section structure of a semiconductor device in a section perpendicular to the substrate, which is an exemplary embodiment of this application; Figure 2B for Figure 2A The diagram shows a schematic diagram of the longitudinal section structure of the semiconductor device on the section perpendicular to the substrate (bb'). Figure 3 A schematic diagram of the longitudinal section structure of another semiconductor device in an exemplary embodiment of this application, on a section perpendicular to the substrate aa'. Figure 4 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application; Figure 5A A top view of a method for manufacturing a first semiconductor device, which is an exemplary embodiment of this application, after forming a stacked structure; Figure 5B for Figure 5A The diagram shows a schematic diagram of the longitudinal section of the semiconductor structure perpendicular to the substrate at the bb' section. Figure 6 A schematic diagram of the longitudinal section structure of a first semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a first trench, on a section perpendicular to the substrate bb'. Figure 7 A schematic diagram of the longitudinal section structure of a first semiconductor device manufacturing method according to an exemplary embodiment of this application, after filling the first trench with an isolation layer; Figure 8AA top view of a method for manufacturing a first semiconductor device, which is an exemplary embodiment of this application, after forming a through-hole; Figure 8B for Figure 8A The diagram shows a schematic longitudinal section of the semiconductor structure on the section aa' perpendicular to the substrate. Figure 9A A schematic diagram of the cross-sectional structure of a first semiconductor device manufacturing method, which is an exemplary embodiment of this application, after selective etching of the sacrificial layer, on a section parallel to the substrate; Figure 9B for Figure 9A The diagram shows a schematic longitudinal section of the semiconductor structure on the section aa' perpendicular to the substrate. Figure 10 A schematic diagram of the longitudinal section structure of a semiconductor device fabrication method according to an exemplary embodiment of this application, after a semiconductor layer is formed on the surface of a pillar; Figure 11 A schematic diagram of the longitudinal section structure of aa' section perpendicular to the substrate after filling the via with an isolation layer, which is an exemplary embodiment of the present application; Figure 12A A schematic diagram of the cross-sectional structure of a first semiconductor device manufacturing method, which is an exemplary embodiment of this application, after forming a second trench, on a section parallel to the substrate; Figure 12B for Figure 12A The diagram shows a schematic longitudinal section of the semiconductor structure on the section aa' perpendicular to the substrate. Figure 13 A schematic diagram of the longitudinal section structure of aa' section perpendicular to the substrate after forming a gate insulating layer and a gate electrode layer in a second trench, which is an exemplary embodiment of the present application. Figure 14A A schematic diagram of the cross-sectional structure of a first semiconductor device manufacturing method, which is an exemplary embodiment of this application, after the formation of the gate electrode, on a section parallel to the substrate; Figure 14B for Figure 14A The diagram shows a schematic longitudinal section of the semiconductor structure on the section aa' perpendicular to the substrate. Figure 15 A schematic diagram of the longitudinal section structure of a first semiconductor device manufacturing method, which is an exemplary embodiment of this application, after the formation of the gate electrode, on a section perpendicular to the substrate (aa'). Figure 16 This is a schematic diagram of the longitudinal section structure of a semiconductor device fabrication method according to an exemplary embodiment of the present application, after the gate electrode is formed and the second electrode is exposed, on a section perpendicular to the substrate aa'.

[0028] The meanings of the symbols in the attached diagram are as follows: 10-Substrate; 11-First electrode layer; 12-Sacrificial layer; 13-Second electrode layer; 14-Cover layer; 15-Isolation layer; 16-Insulating layer; 17-Contact layer; HM-Mask layer; 21-First electrode; 22-Second electrode; 23-Semiconductor layer; 24-Gate insulating layer; 25-Gate electrode; 25'-Gate electrode layer; T1-Trench; T2-Gate trench; K-Through hole; BL-Bit line; WL-Word line. Detailed Implementation

[0029] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0030] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0031] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0032] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0033] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0034] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0035] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0036] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0037] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0039] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0040] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0041] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0042] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0043] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0044] In this application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced with "semiconductor film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0045] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0046] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.

[0047] In this application, the spacing distribution can be understood as a separate distribution, which can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby realizing the electrical spacing between the two channels.

[0048] This application provides a transistor. Figure 1A A top view of a transistor as an exemplary embodiment of this application; Figure 1B for Figure 1A A side view of the transistor shown; Figure 1C for Figure 1A A side view of the transistor from another angle; Figure 1D A top view of another transistor as an exemplary embodiment of this application.

[0049] like Figures 1A to 1CAs shown, the transistor includes: a first electrode 21, a second electrode 22, a semiconductor layer 23, a gate insulating layer 24, and a gate electrode 25 arranged sequentially between the first electrode 21 and the second electrode 22; the first electrode 21 and the second electrode 22 are distributed on both sides of the semiconductor layer 23 along a first direction, and the gate electrode 25 is distributed on one side of the semiconductor layer 23 along a second direction; the first direction and the second direction intersect; the gate electrode 25 extends along the first direction; The orthographic projection of the gate electrode 25 on the plane perpendicular to the first direction does not overlap with the orthographic projection of the first electrode 21 on the plane perpendicular to the first direction, and the orthographic projection of the gate electrode 25 on the plane perpendicular to the first direction does not overlap with the orthographic projection of the second electrode 22 on the plane perpendicular to the first direction.

[0050] The transistors in this application adopt a side-gate structure, which completely interleaves the gate electrode with the source and drain, thereby reducing or avoiding leakage problems and enabling a larger on-state current.

[0051] Furthermore, the source and drain electrodes of the transistors and the semiconductor layer 23 in the embodiments of this application are distributed in the vertical direction, which can reduce the occupied area of ​​the memory cell and increase the integration density of the semiconductor device.

[0052] In some embodiments of this application, such as Figures 1A to 1C As shown, the gate electrode 25 is phase-spaced with at least one of the first electrode 21 and the second electrode 22.

[0053] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor layer 23 has a groove between the first electrode 21 and the second electrode 22, and the groove is recessed toward the gate electrode 25; The first electrode 21 and the second electrode 22 both extend along the first direction, and the two ends of the groove are in contact with the end face of the first electrode 21 and the end face of the second electrode 22, respectively.

[0054] In some embodiments of this application, such as Figure 1D As shown, the semiconductor layer 23 extends to the sidewall of at least one of the first electrode 21 and the second electrode 22.

[0055] This application also provides a semiconductor device. Figure 2A A schematic diagram of the longitudinal section structure of a semiconductor device in a section perpendicular to the substrate, which is an exemplary embodiment of this application; Figure 2B for Figure 2A The diagram shows a schematic diagram of the longitudinal cross-section of the semiconductor device on a section perpendicular to the substrate (bb').

[0056] like Figure 2A and Figure 2BAs shown, the semiconductor device includes: A plurality of memory cells are located on a substrate 10, the plurality of memory cells being distributed at intervals along a row direction and a column direction parallel to the substrate 10 on one side of the substrate 10; the memory cells include transistors as described above; the first direction is perpendicular to the substrate 10, and the second direction is the row direction; Bit line BL extends along the row direction and is connected to the second electrode 22 of the transistor; The word line WL extends along the column direction and is connected to the gate electrode 25 of the transistor.

[0057] In some embodiments of this application, the bit line BL is connected to the second electrode 22 of a plurality of memory cells spaced apart along the row direction; The word line WL is connected to the gate electrode 25 of a plurality of memory cells spaced apart along the column direction, and the gate electrode 25 is part of the word line WL.

[0058] In some embodiments of this application, the gate insulating layers 24 of two adjacent memory cells along the row direction are a single structure; and / or, The gate insulating layer 24 of the plurality of memory cells distributed at intervals along the column direction is an integral structure.

[0059] Figure 3 This is a schematic diagram of the longitudinal section structure of another semiconductor device in an exemplary embodiment of this application, on a section perpendicular to the substrate aa'.

[0060] In some embodiments of this application, such as Figure 3 As shown, the semiconductor device may further include a plurality of magnetic tunnel junctions (MTJs), which are located on the side of the first electrode 21 away from the bit line BL; one of the magnetic tunnel junctions (MTJs) is connected to one of the first electrodes 21.

[0061] like Figure 2A and Figure 3 As shown, the semiconductor device further includes a contact layer 17; the contact layer 17 is located between the second electrode 22 and the bit line BL and between the first electrode 21 and the magnetic tunnel junction MTJ.

[0062] The contact layer 17 between the second electrode 22 and the bit line BL serves to reduce the contact resistance between the second electrode 22 and the bit line BL. The contact layer 17 may include one or two layers of silicon-formed film and polysilicon-formed film. The contact layer 17 between the first electrode 21 and the magnetic tunnel junction MTJ serves to reduce the contact resistance between the first electrode 21 and the magnetic tunnel junction MTJ. The contact layer 17 may include one or both of a silicon film layer and a metal layer.

[0063] In some embodiments of this application, the semiconductor device may further include a plurality of capacitors, one of which is connected to a first electrode 21.

[0064] In some embodiments of this application, the semiconductor device may be a magnetic random access memory (MRAM) or a dynamic random access memory (DRAM).

[0065] In this application, semiconductor layer 23 can be understood as semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0066] For example, the material of the semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it can be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0067] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0068] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0069] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0070] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0071] In some embodiments of this application, the material of the bit line can be TiN, or it can be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive doped semiconductor materials (i.e., conductive semiconductor materials containing doped materials, such as doped polycrystalline silicon), conductive metal oxide semiconductor materials (such as indium tin oxide), etc. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0072] In some embodiments of this application, the materials of the gate electrode and the word line can be any one or more of the following different types of materials: For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals. It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials. Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.

[0073] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0074] Low-K materials, such as silicon oxide.

[0075] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0076] This application also provides a method for manufacturing a semiconductor device, which can be used to prepare the semiconductor device described above.

[0077] Figure 4 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application. Figure 4 As shown, the manufacturing method includes:

[0078] A plurality of transistor pillars are formed on a substrate at intervals along row and column directions parallel to the substrate, each transistor pillar including a first electrode layer, a sacrificial layer and a second electrode layer stacked sequentially along a direction away from the substrate; A semiconductor layer is formed on the sidewall of each of the transistor pillars; Each of the transistor pillars is spaced apart into two transistor subpillars in the row direction, and the sacrificial layer is removed during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer; each of the transistor subpillars includes a first electrode, a second electrode, and a semiconductor layer located between the first electrode and the second electrode, which are stacked and spaced apart in a direction away from the substrate, and the first electrode and the second electrode are formed by the spaced first electrode layer and the second electrode layer, respectively; A gate insulating layer and a gate electrode are sequentially formed on the inner sidewall of the semiconductor layer, and the transistor sub-pillar, the gate insulating layer and the gate electrode constitute a transistor.

[0079] In some embodiments of this application, the step of spacing each of the transistor pillars into two transistor sub-pillars in the row direction, and removing the sacrificial layer during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer, includes: Each of the transistor pillars is etched along the direction toward the substrate to form a gate trench extending along the column direction. The gate trench penetrates a column of transistor pillars spaced apart along the column direction. The gate trench space each of the transistor pillars into two transistor sub-pillars in the row direction, and the gate trench penetrates the sacrificial layer in the row direction, exposing the inner sidewall of the semiconductor layer covered by the sacrificial layer.

[0080] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a gate electrode on the inner sidewall of the semiconductor layer includes: An insulating layer is filled in the region of the gate trench corresponding to the first electrode; The gate insulating layer and the gate electrode layer are sequentially formed on the inner wall of the remaining gate trench; Disconnect the gate electrode layer on the bottom surface of the gate trench; The insulating layer is filled into the gate trench; The insulating layer and the gate electrode layer within the gate trench are etched back to expose the gate insulating layer located on the sidewall of the second electrode; The insulating layer is filled into the gate trench.

[0081] In some embodiments of this application, the width of each region of the gate trench along the direction toward the substrate is the same; The inner sidewall of the semiconductor layer located in the same transistor sub-pillar is flush with the sidewall of the first electrode on the side away from the semiconductor layer and the sidewall of the second electrode on the side away from the semiconductor layer in a direction perpendicular to the substrate.

[0082] In some embodiments of this application, forming a semiconductor layer on the sidewalls of each of the transistor pillars includes: The two sidewalls of the sacrificial layer distributed along the row direction are etched to recess the two sidewalls of the sacrificial layer distributed along the row direction by a set depth in the row direction; The semiconductor layer is formed on the two sidewalls of each of the transistor pillars distributed along the row direction; An isolation layer is filled in the gaps between the transistor pillars.

[0083] In some embodiments of this application, forming the semiconductor layer on the two sidewalls of each of the transistor pillars distributed along the row direction includes: The semiconductor layer is formed on the two sidewalls of each transistor pillar distributed along the row direction using an epitaxial growth process.

[0084] In some embodiments of this application, the sacrificial layer is made of silicon-germanium, and the semiconductor layer is made of silicon. For example, the semiconductor layer may be made of intrinsic silicon without doped materials or doped silicon containing doped materials.

[0085] In some embodiments of this application, the formation of a plurality of transistor pillars spaced apart along row and column directions parallel to the substrate on the substrate, each transistor pillar comprising a first electrode layer, a sacrificial layer, and a second electrode layer stacked sequentially in a direction away from the substrate, includes: A first electrode layer, a sacrificial layer, and a second electrode layer are sequentially formed on one side of the substrate to obtain a stacked structure. The stacked structure is etched along the direction toward the substrate to form a plurality of trenches extending along the row direction and penetrating the stacked structure. The plurality of trenches are spaced apart in the column direction, and the plurality of trenches divide the stacked structure into a plurality of baffles. The trench is filled with an insulating layer; Each of the baffles is etched along a direction toward the substrate, forming at least one through-hole in each baffle, the through-hole spacing each baffle into a plurality of transistor pillars spaced apart along the row direction.

[0086] In some embodiments of this application, the manufacturing method further includes: After the transistors are formed, a bit line extending along the row direction is formed on the side of the second electrode away from the substrate, and the bit line is connected to the second electrodes of a plurality of transistors spaced apart along the row direction; and The gate electrodes of a plurality of transistors spaced apart along the column direction are connected to form word lines extending along the column direction.

[0087] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0088] like Figures 5A to 16 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0089] S10: A substrate 10 is provided, and a first electrode layer 11, a sacrificial layer 12, a second electrode layer 13, and a capping layer 14 are sequentially deposited on one side of the substrate 10 to obtain a stacked structure located on one side of the substrate 10, such as... Figure 5A and Figure 5B As shown.

[0090] The sacrificial layer 12 can be selected from materials that have a larger etching selectivity ratio than the first electrode layer 11 and the second electrode layer 13. For example, the materials of the first electrode layer 11 and the second electrode layer 13 can both be silicon (Si); the material of the sacrificial layer 12 can be silicon germanium (SiGe); and the material of the capping layer 14 can be silicon oxide, such as silicon oxide.

[0091] S20: Etch the stacked structure to divide it into a plurality of transistor pillars spaced apart along the row and column directions parallel to the substrate 10.

[0092] For example, step S20 may include steps S21 to S23 described below.

[0093] S21: The stacked structure is etched along the direction toward the substrate 10 to form a plurality of trenches T1 extending in a row direction parallel to the substrate 10 and penetrating the stacked structure. The plurality of trenches T1 are spaced apart in a column direction parallel to the substrate 10, and the plurality of trenches T1 divide the stacked structure into a plurality of baffles, such as Figure 6 As shown.

[0094] In the description of this application, the row direction intersects the column direction; for example, the row direction and the column direction are perpendicular to each other. The row direction can be as follows: Figure 5A The column direction shown in the aa' direction can be as follows: Figure 5A The direction of bb' is shown.

[0095] For example, the trench T1 can be formed by dry etching, and the trench T1 can extend in a direction perpendicular to the substrate 10.

[0096] S22: Fill the trench T1 with the isolation layer 15, such as Figure 7 As shown.

[0097] For example, the material of the isolation layer 15 can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.

[0098] S23: A mask layer HM is formed on the surface of substrate 10. Then, the mask layer HM and the barrier walls are etched along the direction toward substrate 10, forming at least one through-hole K in each barrier wall. The through-hole K spaces each barrier wall into a plurality of transistor pillars spaced apart along the row direction. Figure 8A and Figure 8B As shown. Among them, Figure 8B The aa' section passes through the transistor pillar.

[0099] like Figure 8A As shown, the isolation layer 15 is exposed on both sides of the through hole K.

[0100] For example, a through-hole K can be formed by dry etching, and the through-hole K can extend in a direction perpendicular to the substrate 10.

[0101] The depth of the via K can be greater than the depth of the trench T1. For example, the trench T1 is exposed on the surface of the substrate 10, and the via K extends into the interior of the substrate 10.

[0102] S30: A semiconductor layer 23 is formed on the sidewall of each of the transistor pillars.

[0103] For example, step S30 may include steps S31 to S33 described below.

[0104] S31: Selectively etch the sacrificial layer 12 of the exposed transistor pillars on both sides within the via K, etching away a portion of each sidewall of the sacrificial layer 12 distributed along the row direction, so that the sidewalls of the sacrificial layer 12 distributed along the row direction are recessed relative to the first electrode layer 11 by a set depth, such as... Figure 9A and Figure 9B As shown. Among them, Figure 9A The cross section passes through the sacrificial layer 12.

[0105] During the selective etching of the sacrificial layer 12, only the two sidewalls of the sacrificial layer 12 distributed along the row direction are etched, while the two sidewalls of the sacrificial layer 12 distributed along the column direction are not etched because they are covered by the isolation layer 15.

[0106] S32: A semiconductor layer 23 is formed on the two sidewalls of each of the transistor pillars distributed along the row direction, such as... Figure 10 As shown.

[0107] For example, an epitaxial growth process can be used to form a semiconductor layer 23 on the two sidewalls of each of the transistor pillars distributed along the row direction.

[0108] For example, the material of the sacrificial layer 12 can be silicon germanium; the material of the semiconductor layer 23 can be silicon, for example, it can be intrinsic silicon without doped material or doped silicon with doped material.

[0109] By using epitaxial growth technology to form semiconductor layers, self-alignment of the semiconductor layers can be achieved, allowing semiconductor layers that meet the requirements to be obtained directly through epitaxial growth alone, without the need for further morphological modification of the semiconductor layers; moreover, controllable growth of semiconductor layer thickness can also be achieved.

[0110] S33: An isolation layer 15 covering the semiconductor layer 23 and filling the via K is deposited on the surface of the substrate 10, and the isolation layer 15 is planarized using a chemical mechanical polishing (CMP) process until the second electrode layer 13 is exposed. Figure 11 As shown.

[0111] S40: Each of the transistor pillars is spaced apart into two transistor subpillars in the row direction, and the sacrificial layer 12 is removed during the spacing process to expose the inner sidewall of the semiconductor layer 23 covered by the sacrificial layer 12; each of the transistor subpillars includes a first electrode 21 and a second electrode 22 stacked and spaced apart in a direction away from the substrate 10, and a semiconductor layer 23 located between the first electrode 21 and the second electrode 22, wherein the first electrode 21 and the second electrode 22 are formed by the spaced first electrode layer 11 and the second electrode layer 13, respectively.

[0112] For example, step S40 may include: S41: A capping layer 14 is formed on the surface of the substrate 10, and the capping layer 14 is patterned; S42: The transistor pillars and the isolation layer 15 are etched along the direction toward the substrate 10 to form a plurality of gate trenches T2 extending along the column direction and penetrating each transistor pillar and the isolation layer 15. The plurality of gate trenches T2 are spaced apart in the row direction, and the gate trenches T2 expose the inner sidewalls of the semiconductor layer 23 on both sidewalls of the transistor pillars, such as... Figure 12A and Figure 12B As shown. Among them, Figure 12A The cross section passes through the first electrode layer 11.

[0113] S50: A gate insulating layer 24 and a gate electrode 25 are sequentially formed on the inner sidewall of the semiconductor layer 23, and the transistor sub-pillar, the gate insulating layer and the gate electrode constitute a transistor.

[0114] For example, step S50 may include steps S51 to S56 as described below.

[0115] S51: Fill the region at the bottom of the gate trench T2 corresponding to the first electrode 21 with an insulating layer 16.

[0116] The purpose of filling the bottom of the gate trench T2 with the insulating layer 16 is, on the one hand, to isolate two adjacent transistors, and on the other hand, to isolate the first electrode layer 11 in the same transistor from the subsequently formed gate insulating layer 24 and gate electrode layer 25', so as to prevent the first electrode layer 11 from being connected to the subsequently formed gate electrode layer 25'.

[0117] The surface of the insulating layer 16 filling the bottom of the gate trench T2 can be flush with the surface of the first electrode 11 on the side away from the substrate 10.

[0118] For example, the insulating layer 16 can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing materials.

[0119] S52: A gate insulating layer 24 and a gate electrode layer 25' covering the inner wall of the remaining gate trench T2 are sequentially formed on the surface of the substrate 10, as shown in the figure. Figure 13 As shown.

[0120] The material of the gate electrode layer 25' can be TiN, or it can be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive doped semiconductor materials (i.e., conductive semiconductor materials containing doped materials, such as doped polycrystalline silicon), conductive metal oxide semiconductor materials (such as indium tin oxide), and other conductive materials.

[0121] S53: Etch away the gate electrode layer 25' on the bottom surface of the gate trench T2 and the top surface of the substrate 10, leaving only the gate electrode layer 25' on the two sidewalls of the gate trench T2, so that the gate electrode layer 25' in the gate trench T2 is broken into two parts in the row direction, such as... Figure 14A and Figure 14B As shown. Among them, Figure 14AThe cross section passes through the semiconductor layer 23 between the first electrode 21 and the second electrode 22.

[0122] Multiple gate electrodes 25, spaced apart along the column direction, are connected together to form a word line WL extending along the column direction.

[0123] S54: Fill the gate trench T2 with insulating layer 16.

[0124] S55: The insulating layer 16 and the gate electrode layer 25' within the gate trench T2 are etched back to expose the gate insulating layer 24 located on the sidewall of the second electrode 22. The remaining gate electrode layer 25' is the gate electrode 25, as shown below. Figure 15 As shown.

[0125] For example, the height of the remaining gate electrode layer 25', i.e., the gate electrode 25, in the direction perpendicular to the substrate 10 can be equal to the distance between the top surface of the first electrode 21 and the bottom surface of the second electrode 22.

[0126] S56: Fill the gate trench T2 with insulating layer 16, and use CMP to process the film layer on the top surface of substrate 10 until the second electrode 22 is exposed, such as... Figure 16 As shown.

[0127] S60: A bit line BL is formed on the side of the second electrode 22 away from the substrate 10.

[0128] For example, step S60 may include: S61: A contact layer 17 is formed on the surface of the second electrode 22; S62: A bit line BL extending along the row direction is formed on the side of the contact layer 17 away from the substrate 10, and the bit line BL is connected to the second electrodes 22 of a plurality of transistors spaced apart along the row direction, to obtain the following: Figure 2A and Figure 2B The semiconductor device shown.

[0129] The contact layer 17 formed in step S62 serves to reduce the contact resistance between the second electrode 22 and the bit line BL. The contact layer 17 may include one or both of the following: a silicon film and a polysilicon film.

[0130] Exemplarily, the manufacturing method may further include: S71: Invert the semiconductor device obtained in step S60 and process the substrate 10 using CMP process until the first electrode 21 is exposed; S72: A contact layer 17 is formed on the surface of the first electrode 21; S73: Multiple magnetic tunnel junctions (MTJs) are formed on the side of the contact layer 17 away from the bit line BL. Each MTJ is connected to a first electrode 21, resulting in the following configuration: Figure 3 The semiconductor device shown.

[0131] The contact layer 17 formed in step S72 serves to reduce the contact resistance between the first electrode 21 and the magnetic tunnel junction MTJ. The contact layer 17 may include one or both of a silicon film and a metal layer.

[0132] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.

[0133] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0134] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A transistor, characterized in that, include: A first electrode, a second electrode, a semiconductor layer, a gate insulating layer, and a gate electrode arranged sequentially between the first electrode and the second electrode; The first electrode and the second electrode are distributed on both sides of the semiconductor layer along a first direction, and the gate electrode is distributed on one side of the semiconductor layer along a second direction; the first direction and the second direction intersect; the gate electrode extends along the first direction; The orthographic projection of the gate electrode on the plane perpendicular to the first direction does not overlap with the orthographic projection of the first electrode on the plane perpendicular to the first direction, and the orthographic projection of the gate electrode on the plane perpendicular to the first direction does not overlap with the orthographic projection of the second electrode on the plane perpendicular to the first direction.

2. The transistor according to claim 1, characterized in that, The gate electrode is phase-spaced with at least one of the first electrode and the second electrode.

3. The transistor according to claim 1 or 2, characterized in that, The semiconductor layer has a groove between the first electrode and the second electrode, and the groove is recessed toward the gate electrode. Both the first electrode and the second electrode extend along the first direction, and the two ends of the groove are in contact with the end face of the first electrode and the end face of the second electrode, respectively.

4. The transistor according to claim 3, characterized in that, The semiconductor layer extends to the sidewall of at least one of the first electrode and the second electrode.

5. A semiconductor device, characterized in that, include: A plurality of memory cells located on a substrate, the plurality of memory cells being distributed at intervals along a row direction and a column direction parallel to the substrate on one side of the substrate; The memory cell includes a semiconductor device transistor according to any one of claims 1 to 4; the first direction is perpendicular to the substrate, and the second direction is the row direction; Bit lines extend along the row direction and are connected to the second electrode of the transistor; Word lines extend along the column direction and are connected to the gate electrode of the transistor.

6. The semiconductor device according to claim 5, characterized in that, The bit line is connected to the second electrode of a plurality of memory cells spaced apart along the row direction; The word line is connected to the gate electrodes of a plurality of memory cells spaced apart along the column direction, and the gate electrodes are part of the word line.

7. The semiconductor device according to claim 6, characterized in that, The gate insulating layers of two adjacent memory cells along the row direction are of a single, integral structure; and / or, The gate insulating layer of the plurality of memory cells spaced apart along the column direction is a single structure.

8. A method for manufacturing a semiconductor device, characterized in that, include: A plurality of transistor pillars are formed on a substrate at intervals along row and column directions parallel to the substrate, each transistor pillar including a first electrode layer, a sacrificial layer and a second electrode layer stacked sequentially along a direction away from the substrate; A semiconductor layer is formed on the sidewall of each of the transistor pillars; Each of the transistor pillars is spaced apart into two transistor subpillars in the row direction, and the sacrificial layer is removed during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer; each of the transistor subpillars includes a first electrode, a second electrode, and a semiconductor layer located between the first electrode and the second electrode, which are stacked and spaced apart in a direction away from the substrate, and the first electrode and the second electrode are formed by the spaced first electrode layer and the second electrode layer, respectively; A gate insulating layer and a gate electrode are sequentially formed on the inner sidewall of the semiconductor layer, and the transistor sub-pillar, the gate insulating layer and the gate electrode constitute a transistor.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The step of spacing each of the transistor pillars into two transistor sub-pillars in the row direction, and removing the sacrificial layer during the spacing process to expose the inner sidewall of the semiconductor layer covered by the sacrificial layer, includes: Each of the transistor pillars is etched along the direction toward the substrate to form a gate trench extending along the column direction. The gate trench penetrates a column of transistor pillars spaced apart along the column direction. The gate trench space each of the transistor pillars into two transistor sub-pillars in the row direction, and the gate trench penetrates the sacrificial layer in the row direction, exposing the inner sidewall of the semiconductor layer covered by the sacrificial layer.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The step of sequentially forming a gate insulating layer and a gate electrode on the inner sidewall of the semiconductor layer includes: An insulating layer is filled in the region of the gate trench corresponding to the first electrode; The gate insulating layer and the gate electrode layer are sequentially formed on the inner wall of the remaining gate trench; Disconnect the gate electrode layer on the bottom surface of the gate trench; The insulating layer is filled into the gate trench; The insulating layer and the gate electrode layer within the gate trench are etched back to expose the gate insulating layer located on the sidewall of the second electrode; The insulating layer is filled into the gate trench.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The width of each region of the gate trench along the direction toward the substrate is the same; The inner sidewall of the semiconductor layer located in the same transistor sub-pillar is flush with the sidewall of the first electrode on the side away from the semiconductor layer and the sidewall of the second electrode on the side away from the semiconductor layer in a direction perpendicular to the substrate.

12. A method for manufacturing a semiconductor device according to any one of claims 8 to 11, characterized in that, The formation of a semiconductor layer on the sidewalls of each of the transistor pillars includes: The two sidewalls of the sacrificial layer distributed along the row direction are etched to recess the two sidewalls of the sacrificial layer distributed along the row direction by a set depth in the row direction; The semiconductor layer is formed on the two sidewalls of each of the transistor pillars distributed along the row direction; An isolation layer is filled in the gaps between the transistor pillars.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The formation of the semiconductor layer on the two sidewalls of each of the transistor pillars distributed along the row direction includes: The semiconductor layer is formed on the two sidewalls of each transistor pillar distributed along the row direction using an epitaxial growth process.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The sacrificial layer is made of silicon-germanium, and the semiconductor layer is made of silicon.

15. A method for manufacturing a semiconductor device according to any one of claims 8 to 11, characterized in that, The method involves forming a plurality of transistor pillars on a substrate, spaced apart along row and column directions parallel to the substrate. Each transistor pillar includes a first electrode layer, a sacrificial layer, and a second electrode layer stacked sequentially in a direction away from the substrate. A first electrode layer, a sacrificial layer, and a second electrode layer are sequentially formed on one side of the substrate to obtain a stacked structure. The stacked structure is etched along the direction toward the substrate to form a plurality of trenches extending along the row direction and penetrating the stacked structure. The plurality of trenches are spaced apart in the column direction, and the plurality of trenches divide the stacked structure into a plurality of baffles. The trench is filled with an insulating layer; Each of the baffles is etched along a direction toward the substrate, forming at least one through-hole in each baffle, the through-hole spacing each baffle into a plurality of transistor pillars spaced apart along the row direction.

16. A method for manufacturing a semiconductor device according to any one of claims 8 to 11, characterized in that, Also includes: After the transistor is formed, a bit line extending along the row direction is formed on the side of the second electrode away from the substrate, and the bit line is connected to the second electrodes of a plurality of transistors spaced apart along the row direction. as well as The gate electrodes of a plurality of transistors spaced apart along the column direction are connected to form word lines extending along the column direction.

17. An electronic device, characterized in that, It includes a transistor according to any one of claims 1 to 4 or a semiconductor device according to any one of claims 5 to 7, or a semiconductor device obtained by the manufacturing method according to any one of claims 8 to 16.

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