Junction-free transistor and manufacturing method thereof

Abstract

The invention provides a junction-free transistor and a manufacturing method thereof, the junction-free transistor comprises a substrate, and a buried oxide layer, a core layer and a shell layer which are stacked on the substrate in sequence, and also comprises a grid electrode on the shell layer, source and drain electrodes located at two sides of the grid electrode, and side walls located between the grid electrode and the source and drain electrodes, the doping concentration of the shell layer is smaller than that of the core layer, and the doping concentration of the shell layer is smaller than that of the core layer. The side wall, facing the grid electrode, of the side wall comprises a first plane, the side wall, far away from the grid electrode, of the side wall comprises a second plane and a connecting surface, facing the nuclear layer, of the side wall, the connecting surface is used for connecting the first plane and the second plane, and the thickness of the side wall starts from the intersection position of the second plane and the connecting surface; and the core layer is in a descending trend in the direction close to the core layer. That is to say, the sharp corner of one side, far away from the grid electrode, of the side wall is canceled through the arrangement of the connecting surface, blocking of the sharp end of the side wall to a channel between the source drain and the channel is avoided, the series resistance of the device is reduced, the on-state current of the device is improved, and a high-performance working mode is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a junctionless transistor and a method for manufacturing the same. Background Technology

[0002] For over half a century, integrated circuit technology based on CMOS technology has followed Moore's Law, which aims to increase chip speed, integration density, and cost by shrinking device feature sizes. As the feature size of MOS devices continues to shrink proportionally, the distance between the source and drain becomes increasingly shorter. The channel is affected not only by the gate electric field but also by the drain electric field, resulting in a decrease in the gate's control over the channel. This effect of severe performance degradation due to channel size reduction is called the short-channel effect. To suppress the short-channel effect, ultra-shallow junctions must be formed in the device. Due to diffusion laws and the statistical properties of dopant atom distribution in semiconductors, forming ultra-shallow junctions with high doping concentration gradients in small-sized devices has become an increasingly difficult challenge for the semiconductor industry. This not only places extremely high demands on thermal budgets and process conditions but also significantly increases manufacturing costs.

[0003] To overcome the insurmountable obstacles faced by MOS devices at advanced process nodes, a new type of transistor has emerged: the junction-less (JL) transistor. Instead of requiring additional doping at the source and drain to form a PN junction, the source, drain, and channel are uniformly doped. Therefore, the JL transistor has no junction and achieves turn-off by depleting the carriers in the channel, such as... Figure 1 The diagram shows a schematic of a junctionless transistor, comprising silicon nanowires uniformly doped with a layered channel and source and drain electrodes on either side of the channel, a gate surrounding the channel, and gate oxide between the channel and the gate. Junctionless transistors possess advantages such as strong suppression of short-channel effects, multiple threshold modulation options, and low noise, making them promising contenders in the advancement of advanced technology nodes.

[0004] Junctionless transistors achieve turn-off by completely depleting the carriers in the channel through the work function difference between the gate material and the silicon nanowire. (Reference) Figure 2 The image shows an electron concentration contour plot of a current type of N-type junctionless transistor, as shown below. Figure 2 As shown in (a), when the device is off, the electrons in the channel are completely depleted, and no current flows through the channel. Applying a gate voltage can reduce the depletion of the channel portion, and when the device is on, a conductive channel is formed between the source and drain. Figure 2In (b) of the diagram, current is transported within the semiconductor. As the applied gate voltage increases, the cross-sectional area of ​​the conductive channel also increases. Figure 2 In (c) of the passage, when the gate voltage increases to the flat band voltage, the entire channel reaches the neutral condition. Figure 2 In (d) of the above, the current is transmitted throughout the silicon nanowire. If the gate voltage is increased further, an accumulation channel will be formed on the semiconductor surface.

[0005] At the manufacturing level, due to the uniform doping between the source and drain channels, the junctionless transistor process reduces the high-temperature annealing required for source / drain injection and doping activation, significantly lowering the thermal budget while reducing process complexity. Furthermore, junctionless transistors offer advantages in 3D sequential integration, being well-suited for manufacturing top-level devices with low thermal budgets. They also possess unique advantages in advanced technology nodes. Because the electric field lines at the gate edge of a junctionless transistor deplete part of the source and drain, the effective channel length is greater than the physical gate length when the transistor is off, thus reducing the impact of short-channel effects.

[0006] However, junctionless transistors also have some fundamental weaknesses: low mobility and negative threshold voltage. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a junctionless transistor that increases the on-state current, reduces the off-state current, and improves the device performance.

[0008] This application provides a junctionless transistor, including:

[0009] Substrate;

[0010] The substrate has a buried oxide layer, a core layer and a shell layer stacked sequentially, wherein the doping concentration of the shell layer is less than that of the core layer;

[0011] The gate on the shell;

[0012] The source and drain located on both sides of the gate;

[0013] A sidewall located between the gate and the source / drain, the sidewall facing the gate including a first plane, the sidewall away from the gate including a second plane, and a connecting surface connecting the first plane and the second plane on the side facing the core layer, the thickness of the sidewall starting at the intersection of the second plane and the connecting surface and decreasing in the direction close to the core layer.

[0014] Optionally, the distance between the intersection point and the plane containing the upper surface of the shell is in the range of 2-6 nm.

[0015] Optionally, the distance ranges from 2 to 4 nm.

[0016] Optionally, the connecting surface is an outwardly convex arc surface.

[0017] Optionally, the connecting surface includes a third plane, and the angle between the third plane and the first plane is greater than 45°.

[0018] Optionally, the third plane is connected to the first plane, and the connecting surface further includes a fourth plane between the third plane and the second plane, wherein the included angle between the third plane and the fourth plane is greater than 90°, and the included angle between the fourth plane and the second plane is greater than 90°.

[0019] Optionally, the connecting surface includes a plurality of sequentially connected fifth planes, and the first plane, the plurality of fifth planes, and the second plane constitute a stepped structure.

[0020] Optionally, the thickness of the core layer ranges from 3 to 10 nm, and the thickness of the shell layer ranges from 3 to 10 nm.

[0021] Optionally, the thickness of the core layer ranges from 3 to 5 nm, and the thickness of the shell layer ranges from 3 to 5 nm.

[0022] This application provides a method for manufacturing a junctionless transistor, including:

[0023] A substrate is provided on which a buried oxide layer, a core layer and a shell layer are sequentially stacked, wherein the doping concentration of the shell layer is less than that of the core layer;

[0024] A gate is formed on the shell layer, and source / drain regions are located on both sides of the gate, and a sidewall is located between the gate and the source / drain; the sidewall facing the gate includes a first plane, the sidewall away from the gate includes a second plane, and a connection surface connects the first plane and the second plane on the side facing the core layer, the thickness of the sidewall starts at the intersection of the second plane and the connection surface and decreases in the direction close to the core layer.

[0025] This application provides a junctionless transistor and a method for manufacturing the same. The junctionless transistor includes a substrate, a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate, a gate on the shell layer, source and drain on both sides of the gate, and a sidewall between the gate and the source and drain. The doping concentration of the shell layer is less than that of the core layer. The sidewall facing the gate includes a first plane, and the sidewall away from the gate includes a second plane. A connection surface connects the first plane and the second plane on the side facing the core layer. The thickness of the sidewall begins at the intersection of the second plane and the connection surface and decreases towards the core layer. In other words, by setting the connection surface, the sharp corners of the sidewalls away from the gate are eliminated, avoiding the obstruction of the path between the source / drain and the channel by the sidewall tips, reducing the series resistance of the device, increasing the on-state current of the device, and achieving a high-performance operating mode. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a current junctionless transistor structure;

[0028] Figure 2 This is a contour plot of electron concentration for a current type of N-type junctionless transistor.

[0029] Figure 3 This is a schematic diagram of a junctionless transistor provided in an embodiment of this application;

[0030] Figure 4 An electron distribution diagram of a core-shell junctionless device provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of another junctionless transistor structure provided in an embodiment of this application;

[0032] Figure 6 An electron distribution diagram of another core-shell junctionless device provided in an embodiment of this application;

[0033] Figure 7 A transfer characteristic curve of a core-shell structure operating in the linear region is provided for an embodiment of this application;

[0034] Figure 8 A graph showing the variation of series resistance with overload voltage, provided for an embodiment of this application;

[0035] Figure 9 A graph showing the transconductance as a function of gate voltage is provided for embodiments of this application;

[0036] Figure 10 and Figure 11 These are schematic diagrams of the structures of two junctionless devices provided in the embodiments of this application;

[0037] Figure 12 This is a schematic diagram of the structure of another junctionless device provided in the embodiments of this application;

[0038] Figure 13 This is a flowchart illustrating a method for manufacturing a junctionless transistor, as provided in an embodiment of this application. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0041] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0042] As described in the background section, junctionless transistors also have some problems. To address these challenges, a core-shell junctionless (CS-JL) transistor is proposed. The core-shell junctionless transistor is a novel junctionless transistor based on FDSOI technology. It adds an undoped shell layer to the junctionless transistor structure, and the silicon layer other than the shell layer is called the core layer. This structure retains the advantages of junctionless transistors while achieving a positive threshold voltage and high on-state current.

[0043] refer to Figure 3The diagram shows a schematic of a junctionless transistor according to an embodiment of this application. A core-shell structure layer is formed on a buried oxide layer 110 on a substrate 100, including a core layer 150 and a shell layer 160. The shell layer 160 has a low or no doping concentration, while the core layer 150 has a high doping concentration, consistent with the doping concentrations of the source and drain. The core layer 150 is located below the gate 170 and is flush with the sidewall of the gate 170. Compared to ordinary junctionless transistors, this design achieves low off-state current, high on-state current, and a positive threshold voltage, avoiding the low mobility and poor consistency problems caused by high doping in the source, drain, and channel of JL transistors.

[0044] However, the inventors discovered through research that, under low-doping conditions, existing sidewall technology in this junctionless transistor can affect or impede the current path, leading to a degraded device performance. This is because, in the on-state, the tips of the sidewalls that contact the source / drain block the normal transport of charge carriers between the source / drain and the channel, significantly increasing the device's series resistance, resulting in mobility degradation and a decrease in on-state current. This effect is even more pronounced in the case of short-channel transistors.

[0045] refer to Figure 4 The diagram shown is an electron distribution diagram of a core-shell junctionless device provided in an embodiment of this application. It was obtained through TCAD simulation, and the device structure corresponds to... Figure 3 The junctionless device in which both source / drain and core are 1×10 18 cm -3 The device features concentrated n-type doping with a top silicon layer thickness of 7 nm, including a 4 nm shell layer, a 3 nm core layer, a 20 nm gate length, and a gate voltage of Vg = 0.5 V. The colors in the source / drain and channel correspond to the electron concentration distribution. As the gate voltage increases, carriers begin to accumulate on the shell layer surface. When the voltage is high enough to form an inversion layer on the shell layer surface, although a surface channel has formed, the sharp edges of the sidewalls obstruct the connection between the surface channel and the source / drain, increasing the series resistance of the entire device. This leads to a degradation in carrier mobility, which in turn affects the device's on-state current.

[0046] Based on the above technical problems, this application provides a junctionless transistor and its manufacturing method. The junctionless transistor includes a substrate, a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate, a gate on the shell layer, source and drain on both sides of the gate, and a sidewall between the gate and the source and drain. The doping concentration of the shell layer is less than that of the core layer. The sidewall facing the gate includes a first plane, the sidewall away from the gate includes a second plane, and a connection surface connecting the first plane and the second plane on the side facing the core layer. The thickness of the sidewall starts at the intersection of the second plane and the connection surface and decreases in the direction close to the core layer. That is, by setting the connection surface, the sharp corner of the sidewall away from the gate is eliminated, avoiding the obstruction of the path between the source / drain and the channel by the sidewall tip, reducing the series resistance of the device, increasing the on-state current of the device, and achieving a high-performance operating mode.

[0047] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0048] See Figure 5 This figure is a schematic diagram of another junctionless transistor provided in an embodiment of this application. The junctionless transistor includes: a substrate 100, and a buried oxide (BOX) layer 110, a core layer 150, and a shell layer 160 sequentially stacked on the substrate 100. It also includes a gate 170 on the shell layer 160, source / drain layers 130 / 140 on both sides of the gate 170, and sidewalls 172 / 173 located between the gate 170 and the source / drain layers. The core-shell junctionless transistor achieves turn-off by depleting the carriers in the channel through the work function of the gate 170.

[0049] In this embodiment, the substrate 100 can be a semiconductor substrate to provide support for the film layer thereon. For example, it can be a silicon substrate, germanium substrate, etc. The substrate 100 can be circular during the manufacturing process. For example, it can be a silicon wafer. Multiple chips can be formed on it to form an array, so as to realize the same batch manufacturing of multiple chips and improve manufacturing efficiency.

[0050] A buried oxide layer 110, a core layer 150, and a shell layer 160 can be formed on the substrate 100. The core layer 150 and the shell layer 160 can be made of the same material. When the core layer 150 and the shell layer 160 are made of silicon, the substrate 100, the buried oxide layer 110, the core layer 150, and the shell layer 160 constitute an SOI substrate.

[0051] The buried oxide layer 110 is an insulating layer used to isolate the core layer 150 and the substrate 100, and to prevent the carriers in the core layer 150 from leaking from the substrate 100 during device operation. The buried oxide layer 110 can be, for example, silicon oxide, germanium oxide, etc.

[0052] The core layer 150, as part of the channel layer, can be made of silicon or germanium, and its thickness can range from 3 to 10 nm, specifically 3 to 5 nm, for example, 3 nm. The doping concentration of the core layer 150 is greater than or equal to 10. 19 cm -3 .

[0053] The shell 160, as part of the channel layer, can be made of silicon or germanium, and its thickness can range from 3 to 10 nm, specifically 3 to 5 nm, for example, 4 nm. The doping concentration of the shell 160 is less than that of the core layer 150, and it can be lightly doped or undoped, for example, the shell 160 can be an undoped film.

[0054] A gate 170 is provided on the shell 160, and a gate dielectric layer 171 may be formed between the gate 170 and the shell 160 to isolate the gate 170 and the shell 160. The gate dielectric layer 171 may be a high-k dielectric layer or silicon oxide, etc.

[0055] A source and drain can be disposed on both sides of the gate 170. In a first direction, a source electrode 130 can be formed on one side of the gate 170, and a drain electrode 140 can be formed on the other side. Sidewalls can be formed on the sidewalls of the gate 170 facing the source electrode 130 and the sidewalls facing the drain electrode 140. The sidewalls include a first sidewall 172 and a second sidewall 173, which are used to isolate the gate 170 from the source electrode 130 and the drain electrode 140, respectively. A source contact 131 can be formed on the source electrode 130, and a drain contact 141 can be formed on the drain electrode 140. The source contact 131 and the drain contact 141 can be metal silicides to reduce contact resistance. The following illustration uses the second sidewall 173 as an example.

[0056] The sidewall facing the gate 170 includes a first plane 17A, and the sidewall away from the gate 170 includes a second plane 17B. A connection surface 17C connects the first plane 17A and the second plane 17B on the side facing the core layer 150. The thickness of the sidewall begins at the intersection of the second plane 17B and the connection surface 17C (the position indicated by the dashed line in the figure) and decreases in the direction close to the core layer 150 (the downward direction in the figure). The sidewalls facing the source / drain are coplanar with the sidewalls facing the source / drain. In other words, the connection surface 17C eliminates the sharp corners of the sidewalls facing away from the gate 170, preventing the sidewall tips from blocking the path between the source / drain and the channel, reducing the device's series resistance, increasing the device's on-state current, and achieving a high-performance operating mode.

[0057] Specifically, the distance between the intersection of the second plane 17B and the connecting surface 17C and the plane containing the upper surface of the shell 160 is in the range of 2-6nm, specifically 2-4nm, for example, 2nm.

[0058] As one possible implementation, the connecting surface 17C can be an outwardly convex arc surface, as shown in the reference. Figure 5 As shown, the sharp corner of the sidewall facing the gate 170 is replaced with a rounded corner. When the voltage of the gate 170 gradually increases, the inversion channel formed on the surface of the shell layer will no longer be blocked by the sidewall and will be directly connected to the source and drain. This avoids the sidewall tip blocking the path between the source / drain and the channel. This reduces the series resistance of the entire device and increases the on-state current of the device.

[0059] refer to Figure 6 The diagram shown is an electron distribution diagram of another core-shell junctionless device provided in this application embodiment, which was obtained through TCAD simulation. The device structure corresponds to... Figure 5 The junctionless device in which both source / drain and core are 1×10 18 cm -3 The transistor features concentrated n-type doping with a top silicon layer thickness of 7 nm, including a 4 nm shell layer, a 3 nm core layer, a 20 nm gate length, and a gate voltage Vg = 0.5 V. The colors in the source / drain and channel correspond to the electron concentration distribution. As the gate voltage gradually increases, the inversion channel formed on the shell layer surface is no longer blocked by the sidewalls and directly connects to the source / drain, resulting in a junctionless transistor with lower series resistance and higher transconductance.

[0060] refer to Figure 7 The figure shown is a transfer characteristic curve of a core-shell structure operating in the linear region according to an embodiment of this application. Figure 7 Figure (a) shows the transfer characteristic curve. Figure 7 (b) shows a logarithmic coordinate graph, where the curve corresponding to the rounded corners indicates the device structure. Figure 5 In the context of junctionless devices, the curve corresponding to the sharp angle indicates that its device structure is... Figure 3 As can be seen from the figure, the novel core-shell junctionless device (i.e., the device with rounded corners) proposed in this scheme retains the good subthreshold characteristics of the original core-shell junctionless device while improving the on-state current of the device.

[0061] refer to Figure 8 The figure shown is a function graph of the series resistance as a function of overload voltage according to an embodiment of this application. The curve corresponding to the rounded corners indicates that its device structure is as follows. Figure 5 In the context of junctionless devices, the curve corresponding to the sharp angle indicates that its device structure is... Figure 3Among the junctionless devices, the series resistance of the novel core-shell junctionless device is reduced by about 50% compared to the original core-shell junctionless device. Due to the significant reduction in series resistance, the carrier mobility of the novel core-shell junctionless transistor (i.e., device with rounded corners) is significantly improved.

[0062] refer to Figure 9 The figure shown is a function graph of transconductance versus gate voltage provided in an embodiment of this application. The curves with rounded corners indicate the device structure. Figure 5 In the context of junctionless devices, the curve corresponding to the sharp angle indicates that its device structure is... Figure 3 Among junctionless devices, the novel core-shell junctionless transistor exhibits higher transconductance, indicating that this novel structure is more advantageous in terms of drive current.

[0063] As another possible implementation, the connecting surface 17C may include a third plane 17C1, wherein the angle between the third plane 17C1 and the first plane 17A is greater than 45°, as shown in the reference. Figure 10 and Figure 11 The diagram shown is a schematic diagram of two other junctionless devices provided in the embodiments of this application.

[0064] If the connecting surface 17C only includes the third plane 17C1, refer to Figure 10 As shown, the third plane 17C1 connects between the first plane 17A and the second plane 17B, which is equivalent to replacing the sharp corner of the sidewall away from the gate 170 with a bend, avoiding the obstruction of the path between the source / drain and the channel by the sidewall tip; if the connection surface 17C includes a fourth plane 17C2 in addition to the third plane 17C1, refer to Figure 11 As shown, the third plane 17C1 is connected to the first plane 17A, and the fourth plane 17C2 is connected between the second plane 17B and the third plane 17C1. The angle between the third plane 17C1 and the fourth plane 17C2 is greater than 90°, and the angle between the fourth plane 17C2 and the second plane 17B is greater than 90°. This is equivalent to the sharp corner of the sidewall away from the gate 170 being replaced with a bend, so as to avoid the sidewall tip blocking the passage between the source / drain and the channel.

[0065] Furthermore, the connecting surface 17C may also include a third plane 17C1 and an arc surface, or it may include a third plane 17C1, a fourth plane 17C2, and an arc surface. In designs that include a fourth plane 17C2, there may be multiple fourth planes 17C2 connected sequentially. These examples will not be illustrated here.

[0066] In one possible implementation, the connecting surface 17C may include a plurality of sequentially connected fifth planes 17C3, wherein the first plane 17A, the plurality of fifth planes 17C3, and the second plane 17B constitute a stepped structure, as shown in the reference. Figure 12 As shown, this is a schematic diagram of another junctionless device provided in an embodiment of this application. The fifth plane 17C3 includes a first subplane parallel to the first plane 17A and a second subplane parallel to the second plane 17B, thereby forming a stepped structure.

[0067] The junctionless transistor proposed in this application is partially compatible with the FDSOI manufacturing process. Compared to existing planar core-shell junctionless transistors, this novel core-shell junctionless transistor retains the advantages of existing core-shell junctionless transistors while reducing the device's series resistance and increasing the on-state current. This performance improvement also applies to short-channel applications. In other words, the new junctionless transistor exhibits superior characteristics in terms of drive current. While retaining good subthreshold characteristics, the device possesses a higher on-state current when turned on, achieving a high-performance operating mode. It is suitable for various application scenarios, has high market demand, and is expected to offer high economic benefits. This technical solution has significant value and importance for subsequent research on core-shell junctionless transistors at advanced technology nodes.

[0068] This application provides a junctionless transistor, including a substrate, a buried oxide layer, a core layer, and a shell layer sequentially stacked on the substrate, a gate on the shell layer, source and drain located on both sides of the gate, and a sidewall located between the gate and the source and drain. The doping concentration of the shell layer is less than that of the core layer. The sidewall facing the gate includes a first plane, and the sidewall away from the gate includes a second plane. A connection surface connects the first plane and the second plane on the side facing the core layer. The thickness of the sidewall starts at the intersection of the second plane and the connection surface and decreases towards the core layer. In other words, the sharp corner of the sidewall away from the gate is eliminated by the connection surface, avoiding the obstruction of the path between the source / drain and the channel by the sidewall tip, reducing the series resistance of the device, increasing the on-state current of the device, and achieving a high-performance operating mode.

[0069] Based on the junctionless transistor provided in the above embodiments, this application also provides a method for manufacturing a junctionless transistor, referencing... Figure 13 The diagram shown is a flowchart of a method for manufacturing a junctionless transistor according to an embodiment of this application. The method includes:

[0070] S101, a substrate is provided, on which a buried oxide layer, a core layer and a shell layer are sequentially stacked, wherein the doping concentration of the shell layer is less than that of the core layer;

[0071] S102, a gate is formed on the shell layer, and source / drain regions are located on both sides of the gate, and a sidewall is located between the gate and the source / drain; the sidewall facing the gate includes a first plane, the sidewall away from the gate includes a second plane, and a connection surface connects the first plane and the second plane on the side facing the core layer, the thickness of the sidewall starts at the intersection of the second plane and the connection surface and decreases in the direction close to the core layer.

[0072] Specifically, the source 130 and drain 140 can be formed first, and then the gate 170 can be formed between the source 130 and drain 140; alternatively, the gate 170 can be formed first, and then the source 130 and drain 140 can be formed on both sides of the gate 170. The source 130, drain 140 and gate 170 are formed through conventional semiconductor manufacturing processes, such as photolithography, etching, and deposition.

[0073] In this embodiment, a gate dielectric layer 171 may also be formed between the gate 170 and the shell 160, and a sidewall (including a first sidewall 172 and a second sidewall 173) located on the sidewall of the gate 170. The first sidewall 172 can separate the gate 170 and the source 130, and the second sidewall 173 can separate the gate 170 and the drain 140.

[0074] Sidewalls can be formed before or after the gate, and can be formed before or after the source / drain.

[0075] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A junctionless transistor, characterized in that, include: Substrate; The substrate has a buried oxide layer, a core layer and a shell layer stacked sequentially, wherein the doping concentration of the shell layer is less than that of the core layer; The gate on the shell; The source and drain located on both sides of the gate; A sidewall located between the gate and the source / drain, the sidewall facing the gate including a first plane, the sidewall away from the gate including a second plane, and a connecting surface connecting the first plane and the second plane on the side facing the core layer, the thickness of the sidewall starting at the intersection of the second plane and the connecting surface and decreasing in the direction close to the core layer.

2. The junctionless transistor according to claim 1, characterized in that, The distance between the intersection point and the plane containing the upper surface of the shell ranges from 2 to 6 nm.

3. The junctionless transistor according to claim 2, characterized in that, The distance ranges from 2 to 4 nm.

4. The junctionless transistor according to claim 1, characterized in that, The connecting surface is an outwardly convex arc surface.

5. The junctionless transistor according to claim 1, characterized in that, The connecting surface includes a third plane, and the angle between the third plane and the first plane is greater than 45°.

6. The junctionless transistor according to claim 5, characterized in that, The third plane is connected to the first plane, and the connecting surface also includes the fourth plane between the third plane and the second plane. The included angle between the third plane and the fourth plane is greater than 90°, and the included angle between the fourth plane and the second plane is greater than 90°.

7. The junctionless transistor according to claim 1, characterized in that, The connecting surface includes a plurality of sequentially connected fifth planes, and the first plane, the plurality of fifth planes and the second plane constitute a stepped structure.

8. The junctionless transistor according to any one of claims 1-7, characterized in that, The thickness of the core layer ranges from 3 to 10 nm, and the thickness of the shell layer ranges from 3 to 10 nm.

9. The junctionless transistor according to claim 8, characterized in that, The thickness of the core layer ranges from 3 to 5 nm, and the thickness of the shell layer ranges from 3 to 5 nm.

10. A method for manufacturing a junctionless transistor, characterized in that, A substrate is provided on which a buried oxide layer, a core layer and a shell layer are sequentially stacked, wherein the doping concentration of the shell layer is less than that of the core layer; A gate is formed on the shell layer, and source / drain regions are located on both sides of the gate, and a sidewall is located between the gate and the source / drain; the sidewall facing the gate includes a first plane, the sidewall away from the gate includes a second plane, and a connection surface connects the first plane and the second plane on the side facing the core layer, the thickness of the sidewall starts at the intersection of the second plane and the connection surface and decreases in the direction close to the core layer.

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