Oxide thin film transistor and display device
By employing stacked active layers in oxide thin-film transistors and utilizing different fabrication processes to form active layers with different carrier concentrations and stability, the problem of insufficient carrier mobility and stability is solved, achieving improved high carrier concentration and stability, making it suitable for high-resolution and high-refresh-rate display devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-04-07
- Publication Date
- 2026-05-29
AI Technical Summary
Existing oxide thin-film transistors have shortcomings in terms of carrier mobility and stability, especially in high-resolution and high-refresh-rate display devices, and the fabrication of stacked active layers is costly and difficult.
The first and second active layers are stacked together. They contain the same elements but have different densities and oxygen vacancy contents. Different carrier concentrations and stability are formed by different preparation process conditions, which reduces the preparation difficulty and cost. The carrier mobility and stability are improved by adjusting the on-state voltage to control the conduction of the device.
This technology achieves high carrier concentration and high stability in oxide thin-film transistors, reduces fabrication costs, and improves on-state current and stability, making it suitable for high-resolution and high-refresh-rate display devices.
Smart Images
Figure CN224306194U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of thin-film transistor technology, and more particularly to an oxide thin-film transistor and a display device. Background Technology
[0002] Thin Film Transistor (TFT) is a semiconductor switching device frequently used in display devices. As a key component for pixel control and driving in flat panel displays, the performance of TFT directly affects the development of display devices. Utility Model Content
[0003] The purpose of this disclosure is to provide an oxide thin-film transistor and a display device for improving the on-state current and stability of the oxide thin-film transistor.
[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:
[0005] On one hand, an oxide thin-film transistor is provided. The oxide thin-film transistor includes a gate, an active layer, a source, and a drain. The active layer includes a first active layer and a second active layer stacked together, with the first active layer closer to the gate than the second active layer. The first and second active layers contain the same metal element, and each contains at least two of indium, zinc, gallium, tin, aluminum, titanium, tantalum, tungsten, and molybdenum. The first and second active layers also contain oxygen, but the oxygen vacancy content differs between the first and second active layers, and / or the crystal states of the first and second active layers differ.
[0006] The oxide thin-film transistors provided in the embodiments of this disclosure allow the first and second active layers to be fabricated using the same target material. This reduces the fabrication difficulty and cost of the first and second active layers. Since the first and second active layers are fabricated using the same target material, it is unnecessary to consider the band structure and work function of the first and second active layers, or the heterojunction formed between them. The first and second active layers have different crystal states and / or different oxygen vacancy contents. For example, the same fabrication process can be used, but the first and second active layers can be fabricated under different process conditions to allow them to have different carrier concentrations and different stability, thereby obtaining an active layer that possesses both high carrier concentration and high stability, thus improving the on-state current and stability of the oxide thin-film transistor.
[0007] In some embodiments, the carrier concentration of the first active layer is greater than the carrier concentration of the second active layer.
[0008] In some embodiments, the source and the drain are in contact with the second active layer. The absolute value of the turn-on voltage of the second active layer is less than the absolute value of the turn-on voltage of the first active layer.
[0009] In some embodiments, the first active layer comprises a crystalline metal oxide, and / or the second active layer comprises an amorphous metal oxide.
[0010] In some embodiments, the oxygen vacancy content of the first active layer is greater than the oxygen vacancy content of the second active layer.
[0011] In some embodiments, the oxygen vacancy content of the first active layer is 12% to 30%; and / or, the oxygen vacancy content of the second active layer is 5% to 18%.
[0012] In some embodiments, the density of the first active layer is greater than the density of the second active layer.
[0013] In some embodiments, both the first active layer and the second active layer include at least oxygen, indium, and gallium.
[0014] In some embodiments, the materials of the first active layer and the second active layer are represented by the general formula: In X Ga (1～X) O, where X is 0.6 to 0.9.
[0015] In some embodiments, the source and the drain are in contact with the second active layer, and the orthographic projections of the source and the drain onto the reference plane do not coincide with the orthographic projection of the first active layer onto the reference plane; the reference plane is perpendicular to the stacking direction of the first active layer and the second active layer.
[0016] In some embodiments, the minimum spacing between the orthographic projections of the source and drain on the reference plane and the orthographic projection of the first active layer on the reference plane is 1 μm to 50 μm.
[0017] In some embodiments, the minimum spacing between the orthographic projections of the source and drain on the reference plane and the orthographic projection of the first active layer on the reference plane is 1 μm to 10 μm.
[0018] In some embodiments, the oxide thin-film transistor is a bottom-gate transistor. The thickness of the first active layer is 10 nm to 30 nm; and / or, the thickness of the second active layer is 10 nm to 25 nm.
[0019] On the other hand, an array substrate is provided. The array substrate includes the oxide thin-film transistors described in any of the above embodiments.
[0020] In another aspect, a display device is provided. The display device includes an array substrate, the array substrate including oxide thin-film transistors as described in any of the above embodiments.
[0021] In another aspect, a method for fabricating an oxide thin-film transistor is provided. The method includes forming a gate. A first active layer and a second active layer are formed using the same target material. The first active layer and the second active layer are stacked, with the first active layer closer to the gate than the second active layer. The first active layer and the second active layer contain the same metal element, and each contains at least two of indium, zinc, gallium, tin, aluminum, titanium, tantalum, tungsten, and molybdenum. The first active layer and the second active layer also contain oxygen; the first active layer and the second active layer have different densities, and / or the oxygen vacancy content of the first active layer and the second active layer is different.
[0022] In some embodiments, the preparation of the first active layer and the second active layer using the same target material includes: generating an initial first active layer; annealing the initial first active layer at a first temperature to form the first active layer; generating an initial second active layer; and annealing the initial second active layer at a second temperature to form the second active layer. The first temperature is greater than the second temperature.
[0023] In some embodiments, the first temperature is 330°C to 400°C; and / or, the second temperature is 230°C to 280°C.
[0024] In some embodiments, the preparation of the first active layer and the second active layer using the same target material further includes: preparing the first active layer in an oxygen and argon atmosphere, wherein the oxygen flow rate ratio to the total oxygen and argon flow rate is a first preset value; and preparing the second active layer in an oxygen and argon atmosphere, wherein the oxygen flow rate ratio to the total oxygen and argon flow rate is a second preset value. The first preset value is less than the second oxygen partial pressure.
[0025] In some embodiments, the first preset value is 0% to 50%; and / or, the first preset value is 2% to 50%.
[0026] In some embodiments, the first active layer and the second active layer are formed using a magnetron sputtering process. The sputtering power used to form the first active layer is greater than the sputtering power used to form the second active layer.
[0027] In some embodiments, the target material comprises Ga2O3 and In2O3, and the molar ratio between Ga2O3 and In2O3 is 10:90 mol% to 40:60 mol%.
[0028] In some embodiments, the fabrication method further includes fabricating a source and a drain, wherein the source and the drain are respectively in contact with the second active layer. The minimum spacing between the orthographic projections of the source and the drain onto the reference plane and the orthographic projection of the first active layer onto the reference plane is 1 μm to 50 μm.
[0029] The above-described display device and the method for fabricating oxide thin-film transistors have the same structure and beneficial technical effects as the oxide thin-film transistors provided in some of the above embodiments, and will not be described again here. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0031] Figure 1 This is a structural diagram of an oxide thin-film transistor with a bottom gate structure according to some embodiments;
[0032] Figure 2 This is a structural diagram of an oxide thin-film transistor with a top-gate structure according to some embodiments;
[0033] Figure 3 This is a device transfer characteristic curve of a thin film transistor prepared according to some embodiments when the active layer uses Ga2O3:In2O3 = 40:60 mol%.
[0034] Figure 4 This is a device transfer characteristic curve of a thin film transistor prepared according to some embodiments when the active layer uses Ga2O3:In2O3 = 30:70 mol%.
[0035] Figure 5 This is a device transfer characteristic curve of a thin film transistor prepared according to some embodiments when the active layer uses Ga2O3:In2O3 = 10:90 mol%.
[0036] Figure 6 X-ray diffraction patterns of the first and second active layers according to some embodiments;
[0037] Figure 7 This is a device transfer characteristic curve of an oxide thin-film transistor according to some embodiments;
[0038] Figure 8 The diagram shows the device transfer characteristics of an oxide thin-film transistor according to some embodiments under NBS (-20V gate bias).
[0039] Figure 9 The diagram shows the device transfer characteristics of an oxide thin-film transistor according to some embodiments under PBS (20V gate bias).
[0040] Figure 10 The diagram shows the device transfer characteristics of an oxide thin-film transistor according to some embodiments under PBTS (20V gate bias).
[0041] Figure 11 This is a device transfer characteristic curve of a single-layer active oxide thin-film transistor.
[0042] Figure 12 This is a graph showing the device transfer characteristics of a single-layer active oxide thin-film transistor under NBS (-20V gate bias).
[0043] Figure 13 The graph shows the device transfer characteristics of a single-layer active oxide thin-film transistor under PBS (20V gate bias).
[0044] Figure 14 This is a graph showing the device transfer characteristics of a single-layer active oxide thin-film transistor under PBTS (20V gate bias).
[0045] Figure 15 The diagram shows the device transfer characteristics of a thin-film transistor fabricated with a second active layer according to some embodiments under an oxygen partial pressure of 10%.
[0046] Figure 16 The diagram shows the device transfer characteristics of a thin-film transistor fabricated with a second active layer according to some embodiments under an oxygen partial pressure of 20%.
[0047] Figure 17 The diagram shows the device transfer characteristics of a thin-film transistor fabricated with a second active layer according to some embodiments under an oxygen partial pressure of 30%.
[0048] Figure 18 The diagram shows the device transfer characteristics of a thin-film transistor fabricated with a second active layer according to some embodiments under an oxygen partial pressure of 40%.
[0049] Figure 19This is a device transfer characteristic curve of a thin-film transistor fabricated under an oxygen partial pressure of 50% according to some embodiments of the second active layer. Detailed Implementation
[0050] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0052] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0053] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
[0054] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0055] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0056] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.
[0057] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0058] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).
[0059] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0060] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0061] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0062] Embodiments of this disclosure provide a display device, which is a product with image display functionality. Exemplarily, the display device can be any device that displays either moving (e.g., video) or stationary (e.g., still image) content, and whether it is text or an image.
[0063] In some embodiments, the display device described above may be an augmented reality (AR) device, a virtual reality (VR) device, or a mixed reality (MR) device. Alternatively, in other embodiments, the display device may also be a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, camera view display (e.g., a rearview camera display in a vehicle), wearable device, in-vehicle display, flight display, or any other product or component with display functionality.
[0064] In terms of the type of light emission of the display device, the aforementioned display device can be one of the following: Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diodes (Micro-LED), or Mini Light Emitting Diodes (mini-LED).
[0065] The display device may include an array substrate, which is a substrate in the display device that includes an array of thin-film transistors (TFTs). For example, if the display device is an LCD display device, it may further include a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate. If the display device is an OLED or QLED display device, it may further include a plurality of light-emitting devices disposed on the array substrate and an encapsulation layer, etc. If the display device is a Micro-LED or mini-LED display device, it may further include light-emitting chips disposed on the array substrate.
[0066] The array substrate may include multiple driving circuits. These driving circuits include, but are not limited to, pixel driving circuits, source driving circuits, and multiplexer (MUX) circuits. Thin-film transistors (TFTs) are crucial components in these driving circuits. During the operation of the array substrate, the corresponding driving circuits can be controlled by turning the TFTs on or off, thereby driving the display device to display images.
[0067] Depending on the material of the active layer of the thin-film transistor, thin-film transistors can include amorphous silicon (such as hydrogenated amorphous silicon: a~Si:H) thin-film transistors, low-temperature polycrystalline silicon (LTPS) thin-film transistors, metal oxide thin-film transistors (also known as oxide thin-film transistors), and organic thin-film transistors, etc.
[0068] Metal-oxide-slim (MOS) thin-film transistors (TFTs) possess numerous advantages, including low leakage current, high electron mobility, low processing temperature, good uniformity, low power consumption, and good processability in large-size display products, leading to their widespread application in display products. However, MOS TFTs also face some challenges in their application. For instance, while InGaZnO (IGZO) TFTs are widely used, the large amount of Ga doped into InGaZnO to suppress carrier concentration within the semiconductor reduces its carrier mobility, which is insufficient to meet the requirements of ultra-high resolution and high refresh rate display devices.
[0069] In oxide thin-film transistors (OSTs), carrier mobility and carrier concentration are positively correlated. However, for OSTs, increasing the carrier concentration in the active layer leads to a negative drift in the threshold voltage, requiring a larger negative gate voltage to shut down the OST, which is detrimental to its application in the display field. Therefore, improving carrier mobility in OSTs using stacked active layers (including at least two stacked active layers) has become an important research direction.
[0070] In related technologies, the design of stacked active layers requires consideration of the band structure and work function of adjacent active layers, and the formation of a high-quality heterojunction at the interface between the two active layers. A two-dimensional electron gas is then used to improve the overall carrier mobility of the active layer. This stacked active layer relies heavily on the band structure of the two active layers and their interface contact, which places certain demands on the selection of active layer materials and the fabrication process, increasing the difficulty of fabricating the stacked active layer and resulting in higher manufacturing costs.
[0071] To solve at least one of the above technical problems, see [reference] Figure 1 and Figure 2 The oxide thin-film transistor 100 provided in the embodiments of this disclosure can be disposed on a substrate 101. The oxide thin-film transistor 100 may include a gate 10, an active layer 20, a source 30, and a drain 40. The active layer 20 may include a first active layer 21 and a second active layer 22 stacked together. The first active layer 21 is closer to the gate 10 than the second active layer 22. That is, the first active layer 21 is located on the side of the second active layer 22 closer to the gate 10.
[0072] like Figure 1 As shown, the oxide thin-film transistor 100 can be a bottom-gate transistor. In this case, the gate 10, the first active layer 21, and the second active layer 22 are sequentially disposed along a direction away from the substrate 101. The oxide thin-film transistor 100 may also include a gate insulating layer 23 disposed between the gate 10 and the first active layer 21. The source 30 and the drain 40 are disposed on the side of the second active layer 22 away from the substrate 101. Exemplarily, the source 30 and the drain 40 may include the same material and be disposed in the same layer.
[0073] like Figure 2As shown, the oxide thin-film transistor 100 can be a top-gate transistor, in which case the second active layer 22, the first active layer 21, and the gate 10 are sequentially disposed along a direction away from the substrate 101. The oxide thin-film transistor 100 may also include a gate insulating layer 23 disposed between the gate 10 and the first active layer 21. The source 30 and drain 40 are disposed on the side of the gate 10 away from the substrate 101. Exemplarily, the source 30 and drain 40 may include the same material and be disposed in the same layer. An insulating layer 24 may also be included between the source 30 and drain 40 and the gate 10, and the source 30 and drain 40 are electrically connected to the active layer 20 through the insulating layer 24 and the gate insulating layer 23.
[0074] In some embodiments, the first active layer 21 and the second active layer 22 contain the same elements. Based on this, the first active layer 21 and the second active layer 22 can be formed using the same target material. This helps reduce the fabrication difficulty and cost of the first active layer 21 and the second active layer 22. Furthermore, since the first active layer 21 and the second active layer 22 are formed using the same target material, it is not necessary to consider the band structure and work function of the first active layer 21 and the second active layer 22, or the heterojunction formed between the first active layer 21 and the second active layer 22. The first active layer 21 and the second active layer 22 have different densities, and / or the oxygen vacancy content of the first active layer 21 and the second active layer 22 is different. For example, the same fabrication process (including but not limited to magnetron sputtering, atomic layer deposition, laser pulse deposition, solution spin coating, or jet printing) can be used to fabricate the first active layer 21 and the second active layer 22 under different process conditions (including but not limited to heat treatment temperature, deposition rate, and oxygen partial pressure) respectively. This allows the first active layer 21 and the second active layer 22 to have different carrier concentrations and different stability (such as negative bias stability (NBS), positive bias stability (PBS), and positive bias temperature stability (PBTS)). This results in an active layer 20 that can have both high carrier concentration and high stability, thereby improving the on-state current and stability of the oxide thin film transistor.
[0075] In some embodiments, the carrier concentration of the first active layer 21 is greater than that of the second active layer 22. Thus, by providing a first active layer 21 with a higher carrier concentration closer to the gate 10, the first active layer 21 can have a higher electron mobility and on-state current (compared to the second active layer 22). The channel layer of the oxide thin-film transistor 100 is mainly formed within the first active layer 21 or on the surface of the first active layer 21 near the gate 10. The second active layer 22 has a lower carrier concentration (compared to the first active layer 21), therefore it can have relatively higher stability and a more accurate turn-on voltage (closer to 0V).
[0076] In the embodiments of this disclosure, when describing the carrier concentration of the first active layer 21 (or the second active layer 22), it refers to the number of free electrons or holes per unit volume in the first active layer 21 (or the second active layer 22), and the unit may be: electrons / cubic centimeter ( / cm²). 3 Furthermore, the carrier concentration of the first active layer 21 (or the second active layer 22) can be measured by the Hall effect method.
[0077] In some embodiments, the source 30 and drain 40 are in contact with the second active layer 22. The absolute value of the turn-on voltage of the second active layer 22 is less than the absolute value of the turn-on voltage of the first active layer 21. For example, the turn-on voltage of the second active layer 22 is closer to 0V, which reduces the risk of threshold voltage drift (e.g., negative drift) of the second active layer 22. Moreover, since the second active layer 22 is in direct contact with the source 30 and drain 40, the on-state voltage of the oxide thin-film transistor can be mainly controlled by the on-state voltage of the second active layer 22. Furthermore, by adjusting the on-state voltage of the second active layer 22, the on-state voltage of the oxide thin-film transistor 100 can be brought closer to 0V, thereby achieving regulation of the on-state voltage of the oxide thin-film transistor 100 without affecting the carrier mobility of the first active layer 21.
[0078] In the embodiments of this disclosure, when describing the turn-on voltage of the first active layer 21 (or the second active layer 22), it refers to the gate voltage of the first active layer 21 (or the second active layer 22) when the source-drain current changes rapidly in the device transfer characteristic curve of the first active layer 21 (or the second active layer 22). The method for measuring this gate voltage may include: keeping the source and drain voltages of the first active layer 21 (or the second active layer 22) constant, gradually adjusting the gate voltage applied to the first active layer 21 (or the second active layer 22), and detecting the current between the source and drain. The voltage at which the current between the source and drain jumps is the aforementioned gate voltage.
[0079] In some embodiments, the first active layer 21 comprises a crystalline metal oxide, thereby enabling the first active layer 21 to have a higher carrier mobility. The crystalline state may include at least one of single-crystal, polycrystalline, nanocrystalline, and mixed-crystal states. And / or, the second active layer 22 comprises an amorphous metal oxide 22, thereby enabling the second active layer 22 to have better stability. For example, if the first active layer 21 is a polycrystalline metal oxide and the second active layer 22 is an amorphous metal oxide 22, an active layer 20 with both high carrier concentration and high stability can be obtained, thereby improving the on-state current and stability of the oxide thin-film transistor 100.
[0080] For example, the first active layer 21 and the second active layer 22 can be formed into different crystal states by different heat treatment temperatures, so that they have different carrier concentrations and thus exhibit different carrier mobilities and stability. For instance, the first active layer 21 can be annealed at a first temperature T1, and the second active layer 22 can be annealed at a second temperature T2, where the first temperature T1 is greater than the second temperature T2, so that the first active layer forms a crystalline state and the second active layer 22 forms an amorphous state.
[0081] In some embodiments, the oxygen vacancy content of the first active layer 21 is greater than the oxygen vacancy content of the second active layer 22. That is, the carrier concentration of the first active layer 21 is greater than the carrier concentration of the second active layer 22. The first active layer 21 can have a larger on-state current, which is beneficial to increase the on-state current of the active layer 20, thereby increasing the on-state current of the oxide thin film transistor 100.
[0082] In the embodiments of this disclosure, when describing the oxygen vacancies in the first active layer 21 (or the second active layer), it refers to the vacancies formed by the loss of oxygen atoms (oxygen ions) in the crystal lattice of the first active layer 21. Oxygen vacancies can be measured by X-ray photoelectron spectroscopy and the peak area can be calculated; alternatively, they can be measured and calculated by Raman spectroscopy, density functional theory (DFT) calculations, or other characterization methods. In some embodiments, the oxygen vacancy content of the first active layer 21 is 12% to 30% (including endpoint values). For example, the oxygen vacancy content of the first active layer 21 can be 12% to 18%, 18% to 24%, or 12% to 30%. For instance, the oxygen vacancy content of the first active layer 21 can be 12%, 15%, 18%, 20%, 24%, 28%, or 30%, etc. The embodiments of this disclosure will not list all of these.
[0083] The oxygen vacancy content of the second active layer 22 is 5% to 18% (including the endpoint value). For example, the oxygen vacancy content of the second active layer 22 can be 5% to 12% or 12% to 18%. For example, the oxygen vacancy content of the second active layer 22 can be 5%, 7%, 10%, 12%, 15%, or 18%, etc. The embodiments of this disclosure will not be listed one by one.
[0084] In the embodiments of this disclosure, when the oxygen vacancy content of the first active layer 21 is 12% to 30% and the oxygen vacancy content of the second active layer 22 is 5% to 18%, the oxygen vacancy content of the first active layer 21 still needs to be greater than the oxygen vacancy content of the second active layer 22.
[0085] In some embodiments, the density of the first active layer 21 is greater than the density of the second active layer 22. For example, both the first active layer 21 and the second active layer 22 can be formed using magnetron sputtering, and the sputtering power when forming the first active layer 21 is greater than the sputtering power when forming the second active layer 22. This results in fewer defects in the first active layer 21 than in the second active layer 22, thereby improving the stability of the first active layer 21.
[0086] In the embodiments of this disclosure, when describing the density of the first active layer 21 (or the second active layer 22), it refers to the thin film density of the first active layer 21, and its unit can be grams per cubic centimeter (g / cm³). 3 The density of the first active layer 21 (or the second active layer 22) can be measured by X-ray reflectivity (XRR).
[0087] In some embodiments, the first active layer 21 and the second active layer 22 each include oxygen (O) and at least two of indium (In), zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (Wu), and molybdenum (Mo).
[0088] For example, both the first active layer 21 and the second active layer 22 include oxygen (O) and indium (In), and the first and second active layers also include at least one of zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (Wu), and molybdenum (Mo). For instance, the materials of the first active layer 21 and the second active layer 22 may include semiconductor materials primarily composed of indium oxide and doped with at least one of Zn, Ga, Sn, Al, Ti, Ta, Wu, and Mo.
[0089] For example, both the first active layer 21 and the second active layer 22 include oxygen, indium, and gallium, that is, the material of the active layer 20 is indium gallium oxide (IGO). Alternatively, both the first active layer 21 and the second active layer 22 include oxygen, indium, gallium, and zinc, in which case the material of the active layer 20 is indium gallium oxide (IGZO). Alternatively, both the first active layer 21 and the second active layer 22 include oxygen, indium, and tin, in which case the material of the active layer 20 is indium tin oxide (ITO). Of course, the embodiments of this disclosure are not limited to these, and any other semiconductor material that meets the conditions of the above embodiments can be considered.
[0090] In one example, when the first active layer 21 and the second active layer 22 include oxygen, indium, and gallium, the general material formula for the first active layer 21 and the second active layer 22 can be expressed as In X Ga (1～X) O, where X is 0.6 to 0.9. That is, the molar ratio of indium (In) to the sum of indium (In) and gallium (Ga) is 0.6 to 0.9. For example, the value of X can be in the range of 0.6 to 0.7, or 0.7 to 0.8, or 0.8 to 0.9. For instance, the value of X can be 0.6, 0.7, 0.8, or 0.9.
[0091] For example, see Figure 3 , Figure 4 and Figure 5 , Figure 3 , Figure 4 and Figure 5 In X Ga (1～X) The device transfer characteristic curves of the oxide thin-film transistor 100 are shown when X takes the values of 0.6, 0.7, and 0.9. When X is 0.6, i.e., the molar ratio of indium (In) to the sum of indium (In) and gallium (Ga) is 0.6, the on-state voltage of the oxide thin-film transistor 100 is approximately 1.6V. When X is 0.7, i.e., the molar ratio of indium (In) to the sum of indium (In) and gallium (Ga) is 0.7, the on-state voltage of the oxide thin-film transistor 100 is approximately -0.4V. When X is 0.9, i.e., the molar ratio of indium (In) to the sum of indium (In) and gallium (Ga) is 0.9, the on-state voltage of the oxide thin-film transistor 100 is approximately -13.8V. Therefore, when the molar ratio of indium (In) to the sum of indium (In) and gallium (Ga) is 0.6 to 0.9, the oxide thin film transistor 100 can have a better off-state voltage.
[0092] in, Figure 3 , Figure 4 and Figure 5 In the oxide thin-film transistor 100 used for the device transfer characteristic curve, the gate 10 has a thickness of 300 nm, and the capacitance of the gate insulating layer 23 is 38 nF / cm. 2 The thickness is 200 nm. The thickness of the first active layer 21 is 15 nm, and the thickness of the second active layer 22 is 20 nm. The minimum spacing between the orthographic projections of the source electrode 30 and the drain electrode 40 on the reference plane and the orthographic projection of the first active layer 21 on the reference plane is 50 μm.
[0093] In some embodiments, such as Figure 1 and Figure 2 As shown, source 30 and drain 40 are in contact with the second active layer 22, and the orthographic projections of source 30 and drain 40 onto the reference plane (e.g., substrate 101) do not coincide with the orthographic projection of the first active layer 21 onto the reference plane. Thus, the on-state voltage of the second active layer 22 is the on-state voltage of the oxide thin-film transistor 100, preventing the first active layer 21 from directly connecting source 30 and drain 40 at a lower gate voltage. The stacking direction of the reference plane relative to the first active layer 21 and the second active layer 22 is (…). Figure 1 and Figure 2 (Vertical direction in the middle) is perpendicular.
[0094] In some embodiments, the minimum spacing D1 between the orthographic projections of the source 30 and drain 40 onto the reference plane and the orthographic projection of the first active layer 21 onto the reference plane is 1 μm to 50 μm. For example, the minimum spacing D1 between the orthographic projections of the source 30 and drain 40 onto the reference plane and the orthographic projection of the first active layer 21 onto the reference plane can be 1 μm to 10 μm, 10 μm to 30 μm, or 30 μm to 50 μm. For example, the aforementioned minimum spacing D1 can be 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc., and the embodiments disclosed herein will not be listed one by one.
[0095] In one embodiment, the minimum spacing D1 between the orthographic projections of the source 30 and drain 40 onto the reference plane and the orthographic projection of the first active layer 21 onto the reference plane is 1 μm to 10 μm. For example, the minimum spacing D1 can be 1 μm, 2 μm, 5 μm, 8 μm, or 10 μm, etc., and the embodiments disclosed herein will not be listed one by one.
[0096] In some embodiments, such as Figure 1As shown, when the oxide thin-film transistor is a bottom-gate transistor, the thickness of the first active layer 21 is 10 nm to 30 nm; and / or, the thickness of the second active layer 22 is 10 nm to 25 nm. Exemplarily, the thickness of the first active layer 21 can be 10 nm to 20 nm, or the thickness of the first active layer 21 can be 20 nm to 30 nm. The thickness of the second active layer 22 can be 10 nm to 18 nm, or the thickness of the first active layer 21 can be 18 nm to 25 nm. For example, the thickness of the first active layer 21 can be 10 nm, 15 nm, 20 nm, 23 nm, 26 nm, or 30 nm, etc., and the thickness of the second active layer 22 can be 10 nm, 15 nm, 18 nm, 20 nm, 23 nm, or 25 nm, etc., and the embodiments of this disclosure will not be listed one by one. The thickness of the first active layer 21 and the thickness of the second active layer 22 can be equal or unequal.
[0097] Some embodiments of this disclosure also provide a method for fabricating an oxide thin-film transistor. The following description uses the fabrication of a bottom-gate oxide thin-film transistor as an example to illustrate this method. This method can also be used to fabricate oxide thin-film transistors with a top-gate structure. The structure of an oxide thin-film transistor can be found in [reference needed]. Figure 1 The above preparation method may include steps S100 to S400.
[0098] S100: A gate 10 is formed on one side of a substrate 101.
[0099] For example, the above step S100 of forming a gate 10 on one side of the substrate 101 may include: forming a gate thin film of a predetermined thickness by sputtering process, and then patterning the metal thin film by photolithography process to obtain a gate 10 with the desired pattern.
[0100] For example, the preset thickness can be 100nm~200nm, 200nm~400nm, or 400nm~500nm, etc., and the embodiments of this disclosure do not specifically limit it. The material of the gate film can include a metallic conductive material, such as one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or the metallic conductive material can also be a metal stacked structure. For example, the metal stacked structure can be a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum-niobium-titanium (MoNb / Ti) stacked structure, a molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum-niobium-copper (MoNb / Cu) stacked structure, a molybdenum-nickel-titanium-copper (MTD / Cu) stacked structure, a molybdenum-niobium-copper-molybdenum-titanium-nickel (MoNb / One or a combination of the following structures: Cu / MTD stacked structure, molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) stacked structure, molybdenum-titanium-copper (MoTi / Cu) stacked structure, molybdenum-titanium-copper-molybdenum-nickel-titanium (MoTi / Cu / MTD) stacked structure, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structure, molybdenum-neodymium-copper stacked structure, MoNb-copper-MoNb stacked structure, and AlNb-molybdenum-AlNd stacked structure.
[0101] In a specific example, step S100 above may include depositing a 300 nm Al:Nd thin film by magnetron sputtering.
[0102] S200, a gate insulating layer 23 is formed on the side of the gate 10 away from the substrate 101.
[0103] For example, the above-mentioned gate insulating layer 23 can be formed by anodizing. The thickness of the gate insulating layer 23 can be 100nm to 300nm. For example, the thickness of the gate insulating layer 23 can be 100nm, 150nm, 200nm or 300nm, etc. The embodiments of this disclosure will not be listed one by one.
[0104] After step S200 above, the substrate can be processed as follows: the oxidized substrate is ultrasonically cleaned with isopropanol, deionized water and isopropanol for 30 minutes respectively, and then dried in an oven at 80°C.
[0105] S300 uses the same target material to prepare the first active layer 21 and the second active layer 22.
[0106] In some embodiments, the target material may include MO and In₂O₃, wherein M includes at least one selected from zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (Wu), and molybdenum (Mo). That is, the target material may include indium oxide and an oxide of at least one of the aforementioned metal elements. Exemplarily, the oxide of the at least one metal element may be zinc oxide (ZnO), gallium oxide (Ga₂O₃), tin oxide (SnO₂), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), tungsten oxide (WuO₃), and molybdenum oxide (MoO₃).
[0107] In a specific example, the target material may include Ga2O3 and In2O3, and the molar ratio between Ga2O3 and In2O3 is 10:90 mol% to 40:60 mol%. Exemplarily, the molar ratio between Ga2O3 and In2O3 may be 10:90 mol%, 20:80 mol%, 25:75 mol%, 30:70 mol%, or 40:60 mol%, etc., and will not be listed individually here. In the following embodiments of this disclosure, the application is described exemplary only by assuming that the target material may include Ga2O3 and In2O3.
[0108] In some embodiments, step S300 may include steps S311 to S314.
[0109] S311, generate the initial first active layer.
[0110] For example, a target material with a Ga2O3:In2O3 ratio of 20:80 mol% can be used, and the initial first active layer can be prepared by magnetron sputtering in an oxygen and argon atmosphere. The material of the initial first active layer is In. x Ga (1-x) O, where x is 0.8.
[0111] In a specific example, the target material can be pre-sputtered for 10 minutes and then used to prepare an initial first active layer with a thickness of 20 nm in an oxygen and argon environment; wherein the oxygen flow rate ratio of oxygen to argon can be 50%, that is, oxygen / (oxygen + argon) is 50%, or the flow rates of oxygen and argon are equal.
[0112] S312, the initial first active layer is annealed at a first temperature T1 to form the first active layer.
[0113] In some embodiments, the first temperature T1 can be 330°C to 400°C, such as 330°C, 340°C, 350°C, 370°C, 385°C or 400°C, etc. The embodiments disclosed herein will not be listed one by one.
[0114] S313, an initial second active layer is formed on the side of the first active layer 21 away from the substrate 101.
[0115] For example, the target material is still Ga2O3:In2O3 at a ratio of 20:80 mol%, and the initial second active layer is prepared by magnetron sputtering in an oxygen and argon atmosphere. The material of the initial second active layer is In. x Ga (1-x) O, where x is 0.8.
[0116] In a specific example, an initial second active layer with a thickness of 15 nm can be prepared in an oxygen and argon environment; wherein the oxygen flow rate ratio of oxygen to argon can be 50%, that is, oxygen / (oxygen + argon) is 50%, or the flow rates of oxygen and argon are equal.
[0117] S314, the initial second active layer is annealed at a second temperature to form the second active layer.
[0118] In some embodiments, the second temperature T2 can be 230°C to 280°C, such as 230°C, 240°C, 255°C, 270°C or 280°C, etc. The embodiments disclosed herein will not be listed one by one.
[0119] The first temperature T1 is greater than the second temperature T2.
[0120] In the embodiments described in steps S311 to S314 above, the target material, fabrication process, and gas atmosphere used to prepare the first active layer 21 and the second active layer 22 are exactly the same. The difference is that the first active layer 21 uses a higher heat treatment temperature so that the first active layer 21 formed can have a higher oxygen vacancy content than the second active layer 22. That is, the carrier concentration of the first active layer 21 can be greater than the carrier concentration of the second active layer 22. The second active layer 22 has better stability than the first active layer 21. In this way, an active layer 20 with both high carrier concentration and high stability can be obtained, which is beneficial to improving the on-state current and stability of oxide thin film transistors.
[0121] In a specific example, see Figure 6The X-ray diffraction (XRD) patterns of the first active layer 21 and the second active layer 22 in the oxide thin-film transistor formed through the above steps S311 to S314, with the first temperature T1 being 350℃ and the second temperature being 270℃, are shown below. Figure 6 From top to bottom, the active layers are the second active layer 22 and the first active layer 21. The first active layer 21 has multiple narrow and high diffraction peaks, exhibiting a polycrystalline state, while the second active layer exhibits an amorphous state. In addition, the first active layer 21 has a higher carrier concentration than the second active layer 22.
[0122] Alternatively, in some other embodiments, step S300 may include steps S321 to S322.
[0123] S321, in an oxygen and argon environment, and with the oxygen flow rate ratio of oxygen to argon being a first preset value X1, a first active layer 21 is prepared and formed.
[0124] For example, step S321 above may include using a target material with a Ga2O3:In2O3 ratio of 20:80 mol%, and using a magnetron sputtering process to prepare an initial first active layer with a thickness of 15 nm in an oxygen and argon atmosphere. The material of the initial first active layer is In. x Ga (1-x) O, where x is 0.8. The flow rate ratio of oxygen to the sum of oxygen and argon is a first preset value X1.
[0125] In some embodiments, the first preset value X1 is 0% to 50%, that is, the flow rate ratio of oxygen to the sum of oxygen and argon is 0% to 50%. Exemplarily, the first preset value X1 can be 0% to 15%, 15% to 35%, or 35% to 50%. For example, the flow rate ratio of oxygen to the sum of oxygen and argon can be 0%, 10%, 15%, 20%, 35%, 40%, or 50%, and these embodiments of the present disclosure will not be listed one by one.
[0126] After the initial first active layer is formed, it can be annealed at a third temperature T3 to form the first active layer 21.
[0127] S322, in an oxygen and argon environment, and with the oxygen-to-argon flow ratio being a second preset value X2, a second active layer 22 is prepared and formed.
[0128] For example, step S322 above may include using a target material with a Ga2O3:In2O3 ratio of 20:80 mol%, and using a magnetron sputtering process to prepare an initial second active layer with a thickness of 20 nm in an oxygen and argon atmosphere. The material of the initial second active layer is In. x Ga (1-x) O, where x is 0.8. Wherein, the flow rate ratio of oxygen to the sum of oxygen and argon is a second preset value X2, where the second preset value X2 is greater than the first preset value X1.
[0129] In some embodiments, the second preset value X2 is 2% to 50%, that is, the flow rate ratio of oxygen to the sum of oxygen and argon is 2% to 50%. Exemplarily, the second preset value X2 can be 2% to 15%, 15% to 35%, or 35% to 50%. For example, the flow rate ratio of oxygen to the sum of oxygen and argon is 2%, 10%, 15%, 20%, 35%, 40%, or 50%, and these embodiments of the present disclosure will not be listed one by one.
[0130] After the initial second active layer is formed, it can be annealed at a fourth temperature T4 to form the second active layer 21.
[0131] In the embodiments described in steps S321 and S322 above, the third temperature T3 used in the annealing process of the initial first active layer may be equal to or different from the fourth temperature T4 used in the annealing process of the initial second active layer. For example, if the heat treatment temperature of the first active layer 21 is greater than the heat treatment temperature of the second active layer 22, then the third temperature T3 can refer to the value range of the first temperature T1 mentioned above, and the fourth temperature T4 can refer to the value range of the second temperature T2 mentioned above; this will not be elaborated further here. For instance, the third temperature T3 may be equal to the first temperature T1, and the fourth temperature T4 may be equal to the second temperature. In a specific example, the third temperature T3 and the fourth temperature T4 are different, with the third temperature T3 being 350°C and the fourth temperature T4 being 270°C.
[0132] In the embodiments described in steps S321 and S322 above, the target material and fabrication process used to prepare the first active layer 21 and the second active layer 22 are the same. The difference is that the oxygen flow rate ratio of the first active layer 21 to the sum of oxygen and argon is higher when preparing the second active layer 21, so that the first active layer 21 formed can have a higher oxygen vacancy content than the second active layer 22. That is, the carrier concentration of the first active layer 21 can be greater than the carrier concentration of the second active layer 22. The second active layer 22 has better stability than the first active layer 21. In this way, an active layer 20 with both high carrier concentration and high stability can be obtained, which is beneficial to improving the on-state current and stability of oxide thin film transistors.
[0133] In some embodiments, step S300 may include fabricating a first active layer 21 and a second active layer 22 using a magnetron sputtering process. The sputtering power used to fabricate the first active layer 21 is greater than the sputtering power used to fabricate the second active layer 22. This results in a higher density of the first active layer 21 than the second active layer 22. Furthermore, the increased sputtering power promotes a higher oxygen vacancy content, meaning the first active layer 21 can have a higher oxygen vacancy content than the second active layer 22. Consequently, the carrier concentration of the first active layer 21 can be higher than that of the second active layer 22, and the second active layer 22 exhibits better stability than the first active layer 21. This results in an active layer 20 that combines high carrier concentration and high stability, which is beneficial for improving the on-state current and stability of the oxide thin-film transistor.
[0134] Furthermore, the first active layer 21 and the second active layer 22 formed in step S300 above have different sizes. For example, the second active layer 22 covers the first active layer 21, and a portion of the second active layer 22 does not cover the first active layer.
[0135] S400, source electrode 30 and drain electrode 40 are prepared, and source electrode 30 and drain electrode 40 are respectively in contact with the second active layer 22.
[0136] The minimum spacing between the orthographic projections of the source 30 and drain 40 onto the substrate 101 and the orthographic projection of the first active layer onto the substrate 101 is 1 μm to 50 μm. For example, the minimum spacing D1 between the orthographic projections of the source 30 and drain 40 onto the substrate 101 and the orthographic projection of the first active layer 21 onto the substrate 101 can be 1 μm to 10 μm, 10 μm to 30 μm, or 30 μm to 50 μm. For example, the aforementioned minimum spacing D1 can be 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc., and these will not be listed one by one in the embodiments disclosed herein. The structures of the source 30 and drain 40 are referred to above and will not be repeated here.
[0137] In some embodiments, in addition to the steps of preparing the first active layer and the second active layer with different sputtering powers, other steps, such as any of the steps of preparing the gate, active layer, source and drain mentioned above, can be performed using one of atomic layer deposition, laser pulse deposition, solution spin coating or jet printing. The embodiments of this disclosure will not be listed one by one.
[0138] To further verify the above-mentioned method for fabricating oxide thin-film transistors and the characteristics of the formed oxide thin-film transistors, the embodiments of this disclosure also provide the following two specific examples.
[0139] Example 1:
[0140] Methods for fabricating oxide thin-film transistors include:
[0141] A 300 nm Al:Nd gate film is deposited on a substrate 101 (glass substrate) by magnetron sputtering; then the metal film is patterned by photolithography to obtain a gate 10 with the desired pattern.
[0142] Next, an anodizing method was used to prepare a gate insulating layer 23 with a thickness of 200 nm. The capacitance of the gate insulating layer 23 was 38 nF / cm. 2 .
[0143] The substrate with the prepared gate insulating layer 23 was ultrasonically cleaned for 30 minutes each with isopropanol, deionized water and isopropanol, and then dried in an oven at 80°C.
[0144] After cleaning the substrate with plasma, a first active layer with a thickness of 20 nm was formed by magnetron sputtering using a target material of Ga2O3:In2O3 at a ratio of 20:80 mol% and an oxygen and argon atmosphere with an oxygen partial pressure of 50% (i.e., oxygen accounts for 50% of the flow rate of oxygen and argon).
[0145] Under atmospheric conditions, the first active layer is obtained by annealing at 350°C for 1 hour and then naturally cooling.
[0146] On the side of the first active layer away from the substrate 101, a magnetron sputtering method is used, and a target material of Ga2O3:In2O3 of 20:80 mol% is used. In an oxygen and argon atmosphere with an oxygen partial pressure of 50%, a mask is used to prepare an initial second active layer with a thickness of 15 nm.
[0147] Then, on the side of the initial second active layer away from the substrate 101, indium tin oxide with a thickness of 200 nm is formed as the source 30 and drain 40 by magnetron sputtering. The distance between the orthogonal projection of the source 30 and drain 40 on the substrate 101 and the orthogonal projection of the first active layer 21 on the substrate 101 is 50 μm.
[0148] The thin-film transistors were annealed at 270°C for 1 hour in an atmospheric environment, and then allowed to cool naturally.
[0149] See Figures 7-10 The oxide thin-film transistor formed by the above preparation method. Figure 7 As shown, with an on-state voltage close to 0V, the carrier mobility of the active layer can reach 67cm⁻¹. 2 / V·s. For example... Figure 8 , Figure 9 and Figure 10As shown, the oxide thin-film transistor exhibits good negative bias stability (threshold voltage drift of -2.6V / h), positive bias stability (threshold voltage drift of 4.4V / h), and positive bias thermal stability (threshold voltage drift of 0.6V / h).
[0150] In comparison, a single-layer active oxide thin-film transistor is also provided. The fabrication method of this single-layer active oxide thin-film transistor includes: fabricating a gate 10 and a gate insulating layer 23 using the same method as described above; forming an active layer using the same process conditions as the initial second active layer; forming a source 30 and a drain 40 with the same structural dimensions; and annealing at 270°C for 1 hour in an atmospheric environment, followed by natural cooling. The only difference between the fabrication process of this comparative example and the above example is that it does not include the process of fabricating the first active layer.
[0151] See Figures 11-14 The oxide thin-film transistor with a single active layer formed by the above preparation method, such as Figure 11 As shown, this oxide thin-film transistor has an on-state voltage of approximately -1.2V and a carrier mobility of 22cm⁻¹ in the active layer. 2 / V·s. In other words, the fabrication method provided by the embodiments of this disclosure can yield oxide thin-film transistors with higher carrier mobility. For example... Figure 8 , Figure 9 and Figure 10 As shown, the oxide thin-film transistor with the above-mentioned single active layer has good negative bias stability (threshold voltage drift of -9V / h), positive bias stability (threshold voltage drift of 9.2V / h), and positive bias thermal stability (threshold voltage drift of 8V / h); that is, the preparation method provided by the embodiments of this disclosure can obtain an oxide thin-film transistor with better stability.
[0152] Example 2:
[0153] Methods for fabricating oxide thin-film transistors include:
[0154] A 300 nm Al:Nd gate film is deposited on a substrate 101 (glass substrate) by magnetron sputtering; then the metal film is patterned by photolithography to obtain a gate 10 with the desired pattern.
[0155] Next, a gate insulating layer 23 with a thickness of 200 nm was prepared by anodizing. The capacitance of the gate insulating layer 23 was 38 nF / cm. 2 ,
[0156] The substrate with the prepared gate insulating layer 23 was ultrasonically cleaned for 30 minutes each with isopropanol, deionized water and isopropanol, and then dried in an oven at 80°C.
[0157] After cleaning the substrate with plasma, a first active layer with a thickness of 20 nm was formed by magnetron sputtering using a target material of Ga2O3:In2O3 at a ratio of 20:80 mol% and an oxygen and argon atmosphere with an oxygen partial pressure of 50% (i.e., oxygen accounts for 50% of the flow rate of oxygen and argon).
[0158] Under atmospheric conditions, the first active layer is obtained by annealing at 350°C for 1 hour and then naturally cooling.
[0159] On the side of the first active layer away from the substrate 101, a magnetron sputtering method is used, and a target material of Ga2O3:In2O3 of 20:80 mol% is used. In an oxygen and argon atmosphere with oxygen partial pressures of 10%, 20%, 30%, 40%, and 50%, respectively, an initial second active layer with a thickness of 15 nm is formed by mask fabrication.
[0160] Then, on the side of the initial second active layer away from the substrate 101, indium tin oxide with a thickness of 200 nm is formed as the source 30 and drain 40 by magnetron sputtering. The distance between the orthogonal projection of the source 30 and drain 40 on the substrate 101 and the orthogonal projection of the first active layer 21 on the substrate 101 is 50 μm.
[0161] The aforementioned thin-film transistors were annealed at 270°C for 1 hour in an atmospheric environment, followed by natural cooling, resulting in five types of oxide thin-film transistors with different oxygen contents in the second active layer 22. (See also...) Figures 15-19 As the oxygen partial pressure increases during the sputtering of the second active layer 22, oxygen vacancies in the second active layer 22 are repaired, causing the on-state voltage of the oxide thin-film transistor to shift positively, specifically to -8.0V, -6.0V, -4.2V, -2.0V, and -0.4V. Since the channel structure is mainly formed by the first active layer 21, the carrier mobility of the oxide thin-film transistors fabricated under the above five different oxygen partial pressures shows a maximum difference of less than 10%. This means that increasing the oxygen partial pressure during the fabrication of the second active layer 22 can rapidly adjust the on-state voltage of the oxide thin-film transistor, but it does not significantly affect the carrier mobility of the oxide thin-film transistor.
[0162] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An oxide thin-film transistor, characterized in that, It includes the gate, active layer, source, and drain; among which, The active layer includes a first active layer and a second active layer stacked together, wherein the first active layer is closer to the gate than the second active layer. The general formula for the materials of the first active layer and the second active layer is In. X Ga （1~X） O, where X is 0.6~0.9, the first active layer includes a crystalline metal oxide, and the second active layer includes an amorphous metal oxide.
2. The oxide thin-film transistor according to claim 1, characterized in that, The source and the drain are in contact with the second active layer, and the orthographic projections of the source and the drain on the reference plane do not coincide with the orthographic projections of the first active layer on the reference plane. The reference plane is perpendicular to the stacking direction of the first active layer and the second active layer.
3. The oxide thin-film transistor according to claim 2, characterized in that, The minimum spacing between the orthographic projections of the source and drain on the reference plane and the orthographic projection of the first active layer on the reference plane is 1 μm to 10 μm.
4. The oxide thin-film transistor according to claim 1, characterized in that, The oxide thin-film transistor is a bottom-gate transistor; The thickness of the first active layer is 10nm~30nm; and / or, The thickness of the second active layer is 10nm~25nm.
5. A display device, characterized in that, include: An array substrate comprising a thin-film transistor as described in any one of claims 1 to 4.