RC-LIGBT device integrated with double self-biased MOS tubes and capable of reducing saturation current

Abstract

The invention designs an RC-LIGBT device integrated with double self-biased MOS transistors and capable of reducing saturation current, and belongs to the technical field of semiconductors. The invention comprises a self-biased NMOS (N-channel Metal Oxide Semiconductor) at a collector side and a self-biased PMOS (P-channel Metal Oxide Semiconductor) at an emitter During forward conduction, the substrate of the self-biased NMOS inhibits electrons from directly reaching the collector through the collector N +, the Snapback effect is eliminated, injected holes enter the source of the self-biased PMOS, the voltage of the source is increased, self-biased opening of the PMOS is achieved, and the saturation current can be reduced through the caused hole extraction effect; during reverse conduction, a reverse electron current path of the device is provided after the self-biased NMOS is started, so that reverse conduction is realized; in the turn-off process, the opening of the self-bias NOMS provides an electron extraction channel, and the opening of the self-bias PMOS provides a hole extraction channel. According to the device, the Snapback effect is eliminated under the condition that an additional control electrode is not added, and compared with a traditional LIGBT, the saturation current is reduced by 21.2% when the collector voltage is 100 V, and the turn-off loss is reduced by 31.1%.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to an RC-LIGBT device that integrates dual self-biased MOS transistors to reduce saturation current. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors) are bipolar semiconductor power devices that combine the advantages of MOSFETs and BJTs, possessing significant characteristics such as low on-state voltage, low drive power consumption, and high operating frequency. They occupy a core position in modern electronic power systems, widely used in communication technology to facilitate efficient signal processing and transmission; in new energy equipment, such as solar inverters and electric vehicle charging stations, they enable precise energy conversion and control; and various consumer electronics fields also rely heavily on IGBTs to ensure stable equipment operation. Among them, LIGBTs (Lateral Insulated Gate Bipolar Transistors) are commonly used in SOI-based power intelligent systems due to their ease of integration onto Si substrates, and are a typical representative of bipolar semiconductor devices. However, traditional LIGBTs have two main performance shortcomings: First, their structure lacks a reverse conduction path, making it impossible to achieve natural reverse conduction, which limits their application in topologies such as bridge circuits; Second, during turn-off, because electrons cannot be directly and quickly extracted from the anode P+ region, the carriers stored in the drift region can only dissipate through slow recombination, resulting in a significant current tailing phenomenon, causing problems such as high turn-off losses and slow switching speed.

[0003] To address the reverse conduction problem of LIGBTs, RC-LIGBTs were developed. By introducing an n+ short-circuit region on the collector side and integrating an anti-parallel diode, it successfully achieves reverse conduction. During device turn-off, the anode N+ region can directly extract electrons from the drift region, improving the device's switching speed and reducing turn-off losses. However, RC-LIGBTs are not without their flaws. When the on-current is small, electrons injected into the NMOS transistor flow directly out of the anode N+ region, the P+ / N-buffer junction is not conducting, and the device is in unipolar mode with high on-resistance. As the on-current gradually increases, the voltage drop across the N-buffer region below the P+ region gradually increases. When this voltage drop exceeds the built-in potential of the P+ / N-buffer junction, holes begin to be injected from the P+ region into the drift region, causing conductivity modulation. The device then enters bipolar mode, the resistance drops significantly, and a snapback phenomenon occurs. This phenomenon not only generates electromagnetic noise, interfering with the normal operation of surrounding electronic equipment, but also threatens the reliability of the device itself, affecting its stability and lifespan in practical applications. Therefore, effectively eliminating the snapback phenomenon in RC-LIGBT design has become a critical issue that urgently needs to be addressed in this field. Summary of the Invention

[0004] This invention relates to an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors. Based on the conventional LIGBT structure, this invention integrates a self-biased PMOS at the emitter, a self-biased NMOS at the collector, and a gate voltage control region of the NMOS above the drift region. In forward conduction, the substrate of the self-biased NMOS suppresses electrons from directly reaching the collector via the N+ region, thus eliminating the snapback effect. Holes injected from the collector side into the PMOS source can increase its voltage. When the turn-on condition is met, the self-biased PMOS turns on, and the resulting hole extraction effect greatly reduces the saturation current. In reverse conduction, the self-biased NMOS provides a path for reverse electron current, achieving reverse conduction capability. In turn-off, the self-biased NMOS provides an electron extraction channel, and the self-biased PMOS provides a hole extraction channel, thereby reducing turn-off time and losses.

[0005] To achieve the above objectives, the present invention provides the following technical solution: The device integrates a self-biased PMOS on the emitter side and a self-biased NMOS on the collector side. A gate voltage control region for controlling the self-biased turn-on of the NMOS is also integrated above the device. This invention focuses on these three regions. Without adding an additional control electrode, the self-biased NMOS eliminates the snapback effect, provides a reverse-conducting electron current path, and provides an electron extraction channel during turn-off. The self-biased PMOS reduces saturation current and provides a hole extraction channel during turn-off. The gate voltage control region includes the P1+ region 9 connected to the emitter, the N- region 10, the floating electrode Foc region 10, the P2+ region 12 connected to the collector, and the oxide layer region 21 for isolation. This is equivalent to two diodes reverse-biased. Regardless of whether the voltage is forward or reverse, the potential at the floating electrode reaches its maximum to achieve reverse bias of the two diodes. Under forward conduction and turn-off conditions, the gate of the PMOS integrated on the emitter side is the gate G. P Region 8, and gate G P Region 8 is connected to P1+ in the gate voltage control region, and region 9 is connected to P+ on the emitter. P Region 5, substrate is N P Zone 6, source is extremely P- P Zone 7, the injected hole enters P- P Region 7 increases the source-gate voltage difference to achieve self-biased turn-on of the device, thereby reducing saturation current and providing a hole extraction path during turn-off. The collector-side integrated NMPOS includes N+ region 13 and gate G. N Region 14, P-base region 15, N-buffer region 16. Under forward conduction and turn-off conditions, the source of the self-biased NMOS is N-buffer region 16, the drain is N+ region 13, and the gate is G. N Region 14, Gate G N The voltage in region 14 originates from the floating electrode Foc region 10. The substrate is the P-base region 15. The substrate suppresses electrons from directly reaching the collector from the N+ region 13 to eliminate the snapback effect. The increase in the voltage of the Foc region 10 provides the NMOS with a gate voltage that meets the turn-on condition and provides an electron extraction channel during turn-off. During reverse conduction, the source of the self-biased NMOS is the N+ region 13, the drain is the N-buffer region 16, and the gate is the G... N Region 14, whose voltage comes from the floating electrode Foc region 10, and the substrate is P-base region 15. The increase in voltage of Foc region 10 provides NMOS with a sufficient gate voltage to turn on, and provides an electronic current path for reverse conduction to achieve reverse conduction capability.

[0006] The basic structure includes: emitter P+ region 1, emitter N+ region 2, P-well region 3, gate G region 4, collector P+ region 17, N-drift region 18, BOX region 19, and Substrate region 20.

[0007] The emitter P+ region 1 is to the left of the emitter N+ region 2 and they are both connected to the emitter; The P-well region 3 is located below the emitter P+ region 1 and the emitter N+ region 2, and below it is the N-drift region 18; The gate G region 4, from top to bottom on the left, consists of emitter N+ region 2, P-well region 3, and N-drift region 18; the right side, from top to bottom, consists of P+ region 2, emitter N+ region 3, P-well region 4, and N-drift region 18. P Zone 5, N P Section 6, P- P Zone 7; The gate G P Zone 8 is connected to the gate voltage control zone P1+ and zone 9. From top to bottom on the left, they are P+ P Zone 5, N P Section 6, below is P- P Section 7, to its left is N-drift section 18; The gate voltage control region is isolated from the device conductive region by the oxide layer region 21. Above the oxide layer region 21, from left to right, are P1+ region 9, N- region 10, floating electrode Foc region 10, and P2+12 region connected to the collector. Below is N-drift region 18. The gate G N To the left and below of section 14 is N-drift section 18, and to the right from top to bottom are N+ section 13, P-base section 15, and N-buffer section 16; The collector P+ region 17 is bordered by an N+ region 13 to the left and both are connected to the emitter, and the P-base region 15 is located below it. Above the P-base region 15, from left to right, are the N+ region 13, the collector P+ region 17, and below it is the N-buffer region (16); to the left is the gate G. N Zone 14; Above the N-buffer region 16 is the P-base region 15, and to the left is the gate G. N Section 14, below which is N-drift section 18; Above the BOX area 19 is the N-drift area 18, and below it is the Substrate area 20; Above the Substrate region 20 is the N-drift region 18, which is connected to the electrode Substrate; The beneficial effects of this invention are as follows: The gate voltage control region of the RC-LIGBT device integrating dual self-biased MOS transistors to reduce saturation current proposed in this invention can realize gate voltage control of the two self-biased MOS transistors. The self-biased PMOS is used to reduce saturation current and extract holes, while the self-biased NMOS is used to eliminate negative resistance effect, realize reverse conduction, and extract electrons, which greatly improves the performance stability of the device and greatly reduces turn-off loss and time.

[0008] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0009] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 A schematic diagram of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors is provided for the present invention. Figure 2(a) is the forward conduction equivalent circuit diagram of an RC-LIGBT device with integrated dual self-biased MOSFETs and reduced saturation current provided by the present invention, and Figure 2(b) is the reverse conduction equivalent circuit diagram of an RC-LIGBT device with integrated dual self-biased MOSFETs and reduced saturation current provided by the present invention. Figure 3(a) is the energy band diagram of the NMOS of the RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors provided by the present invention when it is forward-biased; Figure 3(b) is the energy band diagram of the PMOS of the RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors provided by the present invention when it is forward-biased. Figure 4 The present invention provides an energy band diagram of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors, showing the NMOS during reverse conduction. Figure 5 The forward and reverse conduction performance diagrams of an RC-LIGBT device with integrated dual self-biased MOSFETs to reduce saturation current are provided for this invention. Figure 6 A comparison diagram of the forward conduction characteristics of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOSFETs provided for this invention and a conventional device. Figure 7A comparison diagram of the turn-off characteristics of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOSFETs, provided for this invention, and a conventional device. Detailed Implementation

[0010] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0011] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0012] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0013] like Figure 1 As shown, this invention relates to an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOSFETs. The device integrates a self-biased PMOS on the emitter side and a self-biased NMOS on the collector side. A gate voltage control region for controlling the self-biasing of the NMOS is also integrated above the device. This invention focuses on these three regions. The gate of the PMOS integrated on the emitter side is the gate G. P In section 8, the drain electrode is connected to the emitter via P+. P Region 5, substrate is N P Zone 6, source is extremely P- PRegion 7. The gate voltage control region includes the P1+ region 9 connected to the emitter, the N- region 10, the floating electrode Foc region 10, the P2+ region 12 connected to the collector, and the oxide layer region 21 for isolation. The NMPOS integrated on the collector side includes the N+ region 13, the gate G... N Region 14, P-base region 15, N-buffer region 16. During forward conduction, the source of the self-biased NMOS is N-buffer region 16, the drain is N+ region 13, and the gate is G. N The voltage in region 14 originates from the floating electrode Foc region 10, and the substrate is the P-base region 15. During reverse conduction, the source of the self-biased NMOS is the N+ region 13, the drain is the N-buffer region 16, and the gate is G. N The voltage in region 14 comes from the floating electrode Foc region 10, and the substrate is P-base region 15.

[0014] The device drift region length, which is the total device length, is 25 μm. The basic structure includes: emitter P+ region 1, emitter N+ region 2, P-well region 3, gate G region 4, collector P+ region 17, N-drift region 18, BOX region 19, and Substrate region 20.

[0015] The emitter P+ region 1 is to the left of the emitter N+ region 2 and they are both connected to the emitter; The P-well region 3 is located below the emitter P+ region 1 and the emitter N+ region 2, and below it is the N-drift region 18, with a doping concentration of 1×10⁻⁶. 17 cm -3 ; The gate G region 4 has a depth of 3μm. From top to bottom on its left side are the emitter N+ region 2, P-well region 3, and N-drift region 18. From top to bottom on its right side are the P+ region 2, P-well region 3, and N-drift region 18. P Zone 5, N P Section 6, P- P Zone 7, P+ P The doping concentration in zone 5 is 1×10 19 cm -3 N P The doping concentration in zone 6 is 1×10 17 cm -3 P- P The doping concentration in zone 7 is 2 × 10⁻⁶. 15 cm -3 ; The gate G P Region 8 has a depth of 3μm and is connected to the gate voltage control region P1+ region 9. From top to bottom on the left, they are P+ P Zone 5, N P Section 6, below is P- PRegion 7, to its left is N-drift region 18, gate G P The doping concentration in zone 8 is 1×10 20 cm -3 The N-drift region has a doping concentration of 5 × 10⁸. 15 cm -3 ; The gate voltage control region is isolated from the device conductive region by the oxide layer region 21. Above the oxide layer region 21, from left to right, are the P1+ region 9, the N- region 10, the floating electrode Foc region 10, and the P2+12 region connecting the collector. Below is the N-drift region 18. The doping concentration of both the P1+ region 9 and the P2+12 region is 1×10⁻⁶. 19 cm -3 The N-region 10 doping concentration is 5 × 10⁻⁶. 15 cm -3 ; The gate G N Region 14 has a depth of 3 μm. To the left and below is N-drift region 18. To the right, from top to bottom, are N+ region 13, P-base region 15, and N-buffer region 16. The doping concentration of N+ region 13 is 1 × 10⁻⁶. 19 cm -3 The doping concentration of P-base region 15 is 1×10⁻⁶. 17 cm -3 The doping concentration of N-buffer region 16 is 1×10⁻⁶. 17 cm -3 ; The collector P+ region 17 is bordered by an N+ region 13 to the left and both are connected to the emitter, and the P-base region 15 is located below it. Above the P-base region 15, from left to right, are the N+ region 13, the collector P+ region 17, and below it is the N-buffer region (16); to the left is the gate G. N Zone 14; Above the N-buffer region 16 is the P-base region 15, and to the left is the gate G. N Section 14, below which is N-drift section 18; Above the BOX region 19 is the N-drift region 18, and below it is the Substrate region 20, with a doping concentration of 5 × 10⁻⁶. 15 cm -3 ; Above the Substrate region 20 is the N-drift region 18, which is connected to the electrode Substrate; Figure 2(a) shows the equivalent circuit diagram of the device in forward conduction. The gate voltage of both the self-biased NMOS and PMOS comes from the gate control region. The P1+ region 9, connected to the emitter, has a very low potential, providing the PMOS with a gate voltage lower than the source voltage. The gate voltage of the self-biased NMOS comes from the N- region 10 of the gate control region. Since the gate control region is equivalent to two diodes reverse-connected, within a reasonable range, regardless of the voltage changes, the potential of the N- region 10 is always the highest to achieve reverse bias of the two diodes. Therefore, the gate control region can provide a higher voltage to control the NMOS's turn-on. Figure 2(b) shows the equivalent circuit diagram of the device in forward conduction when it is in reverse conduction. Similarly, the gate control region can provide a higher voltage to control the NMOS's turn-on, while the P1+9 region connected to the emitter has a higher potential and cannot enable the PMOS to conduct. Figure 3(a) shows the energy band diagram of the NMOS in the forward conduction phase of an RC-LIGBT device with integrated dual self-biased MOS transistors and reduced saturation current provided by the present invention. As shown in the figure, with... V CE As the floating electrode potential gradually increases, the gate voltage of the NMOS also increases, which reduces the electron barrier in the P-base region 15 of the substrate, thus turning it on. Figure 3(b) shows the energy band diagram of the PMOS in the forward conduction of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors provided by the present invention. V CE As the collector-injected hole increases, it enters the source P- of the PMOS. P Section 7 is made to have a voltage higher than the gate voltage, gradually satisfying the turn-on condition and turning on; Figure 4 The present invention provides an energy band diagram of an RC-LIGBT device integrating dual self-biased MOSFETs to reduce saturation current during reverse conduction, showing the effect of reverse voltage. V EC As the voltage increases, the gate voltage and drain voltage also gradually increase, and an inversion layer will gradually form in the P-base region 15, thus turning on the circuit. Figure 5 The present invention provides a forward and reverse conduction performance diagram of an RC-LIGBT device integrating dual self-biased MOSFETs to reduce saturation current. The diagram shows that during forward conduction, a portion of the hole current reaches the drain P+ of the self-biased PMOS on the emitter side. P Zone 5; During reverse conduction, the electronic current enters the device through the self-biased NMOS on the collector side.

[0016] Figure 6The figure shows a comparison of the forward conduction characteristics of an RC-LIGBT device with reduced saturation current that integrates dual self-biased MOS transistors provided by the present invention and a conventional device. Since the self-biased PMOS of the present invention provides an additional hole extraction channel for the device, the saturation circuit with a collector voltage of 100V is shown in the figure. It can be seen that the saturation current of the present invention is much smaller than that of the conventional device. Figure 7 The diagram shows a comparison of the turn-off characteristics of an RC-LIGBT device integrating dual self-biased MOS transistors to reduce saturation current, as provided by this invention, with that of a conventional device. During the turn-off process, the self-biased NMOS provides an electron extraction channel for the device, and the self-biased PMOS provides a hole extraction channel for the device. Both can accelerate the extraction of non-equilibrium carriers and significantly reduce turn-off time and losses.

Claims

1. An RC-LIGBT device integrating dual self-biased MOSFETs to reduce saturation current, characterized in that: The device integrates a self-biased PMOS on the emitter side and a self-biased NMOS on the collector side. A gate voltage control region for controlling the self-biased NMOS is also integrated above the device. This invention focuses on these three regions. Without adding an additional control electrode, the self-biased NMOS can eliminate the snapback effect, provide a reverse-conducting electron current path, and provide an electron extraction channel when turned off. The self-biased PMOS reduces saturation current and provides a hole extraction channel when turned off. The gate voltage control region includes the P1+ region (9) connected to the emitter, the N- region (10), the floating electrode Foc region (10), the P2+ region (12) connected to the collector, and an oxide layer region (21) for isolation. This is equivalent to two diodes reverse-biased. Regardless of whether the voltage is forward or reverse, the potential at the floating electrode reaches its maximum to achieve reverse bias of the two diodes. Under forward conduction and turn-off conditions, the gate of the PMOS integrated on the emitter side is the gate G. P Region (8), and gate G P Region (8) is connected to region P1+ (9) in the gate voltage control region, and the drain is connected to region P+ on the emitter. P Region (5), substrate is N P Region (6), source is P- P Zone (7), the injected hole enters P- P Region (7) increases the source-gate voltage difference to achieve self-biased turn-on of the device, thereby reducing saturation current and providing a hole extraction channel during turn-off. The collector-side integrated NMPOS includes the N+ region (13) and the gate G N Region (14), P-base region (15), N-buffer region (16). Under forward conduction and turn-off conditions, the source of the self-biased NMOS is the N-buffer region (16), the drain is the N+ region (13), and the gate is G. N Region (14), gate G N The voltage in region (14) comes from the floating electrode Foc region (10), and the substrate is a P-base region (15). The substrate suppresses electrons from directly reaching the collector from the N+ region (13) to eliminate the snapback effect. The increase in the voltage of the Foc region (10) provides the gate voltage that meets the turn-on condition for the NMOS and provides an electron extraction channel when it is turned off. When reverse-biased, the source of the self-biased NMOS is the N+ region (13), the drain is the N-buffer region (16), and the gate is the G region (14). N The voltage of region (14) comes from the floating electrode Foc region (10), and the substrate is the P-base region (15). The increase in voltage of Foc region (10) provides sufficient gate voltage for NMOS to turn on, and provides an electronic current path for reverse conduction to achieve reverse conduction capability. The basic structure includes: emitter P+ region (1), emitter N+ region (2), P-well region (3), gate G region (4), collector P+ region (17), N-drift region (18), BOX region (19), and Substrate region (20). The emitter P+ region (1) is to the left of the emitter N+ region (2) and is connected to the emitter together; The P-well region (3) is located below the emitter P+ region (1) and the emitter N+ region (2), and below it is the N-drift region (18). The left side of the gate G region (4), from top to bottom, consists of the emitter N+ region (2), the P-well region (3), and the N-drift region (18), while the right side, from top to bottom, consists of the P+ region. P Zone (5), N P Zone (6), P- P District (7); The gate G P Zone (8) is connected to the gate voltage control zone P1+ zone (9). From top to bottom on the left side, P1+ is... P Zone (5), N P Section (6), below is P- P Zone (7), to its left is N-drift zone (18); The gate voltage control region is isolated from the device conductive region by the oxide layer region (21). Above the oxide layer region (21), from left to right, are the P1+ region (9), N- region (10), floating electrode Foc region (10), and P2+ region (12) connected to the collector. Below is the N-drift region (18). The gate G N The left and bottom of area (14) are N-drift area (18), and the right side from top to bottom are N+ area (13), P-base area (15), and N-buffer area (16). The collector P+ region (17) is connected to the emitter by the N+ region (13) to the left and the P-base region (15) below. Above the P-base region (15), from left to right, are the N+ region (13), the collector P+ region (17), and below it is the N-buffer region (16); to the left is the gate G. N District (14); Above the N-buffer region (16) is the P-base region (15), and to the left is the gate G. N Area (14), below which is N-drift area (18); Above the BOX area (19) is the N-drift area (18), and below it is the Substrate area (20). Above the Substrate region (20) is the N-drift region (18), which is connected to the electrode Substrate.

2. The RC-LIGBT device with reduced saturation current integrating dual self-biased MOSFETs according to claim 1, characterized in that: In a traditional LIGBT structure, a self-biased PMOS is integrated on the emitter side, a self-biased NMOS is integrated on the collector side, and a gate voltage control region is integrated above the drift region. During the forward conduction phase, the P-base region (15) of the self-biased NMOS substrate suppresses electrons from directly reaching the collector via the N+ region (13), thus eliminating the snapback effect. The voltage of the floating electrode provides the gate voltage for the self-biased NMOS to turn on, allowing the self-biased NMOS to conduct. Holes injected from the collector side enter the P-base region. P Region (7) can increase its voltage, which is the source voltage of the self-biased PMOS. The gate of the PMOS is connected to the gate voltage control region P1+. When the turn-on condition is met, the self-biased PMOS turns on, and the resulting hole extraction effect greatly reduces the saturation current of the device. During reverse conduction, the floating electrode provides the gate voltage condition for the self-biased NMOS to turn on, providing a reverse electron current path for the device to achieve reverse conduction. Under the turn-off condition, the self-biased NMOS is in the on state, providing an electron extraction channel for the device, and the self-biased PMOS is in the on state, providing a hole extraction channel for the device. Therefore, the turn-off time and turn-off loss can be reduced.

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