Semiconductor device and forming method thereof

Abstract

In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, where a lower of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region, an upper semiconductor nanostructure of the semiconductor nanostructures extending between the upper source / drain regions; forming a gate dielectric layer around the lower semiconductor nanostructure and the upper semiconductor nanostructure; forming a first metal-containing layer over the gate dielectric layer and around the lower semiconductor nanostructure; forming a second metal-containing layer over the first metal-containing layer and around the lower semiconductor nanostructure; and forming a third metal-containing layer over the gate dielectric layer and around the upper semiconductor nanostructure and over the second metal-containing layer. The invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain regions, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; removing the pseudo-nanostructures to form a first opening between the lower semiconductor nanostructures and to form a... A second opening is formed; a gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; a first metal-containing layer is formed above the gate dielectric layer and around the lower semiconductor nanostructure; a second metal-containing layer is formed above the first metal-containing layer, around the lower semiconductor nanostructure, and in the first opening; a third metal-containing layer is formed above the gate dielectric layer, around the upper semiconductor nanostructure, and above the second metal-containing layer; a lower gate electrode layer is deposited above the second metal-containing layer and the third metal-containing layer; and an upper gate electrode layer is deposited above the lower gate electrode layer, above the third metal-containing layer, and around the upper semiconductor nanostructure.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins include alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by the semiconductor layers and the dummy nanostructures being defined by the dummy layers; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain regions, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; and removing the dummy layers. The nanostructure forms a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; a gate dielectric layer is formed around the lower and upper semiconductor nanostructures; a first metal-containing layer is formed above the gate dielectric layer and around the lower and upper semiconductor nanostructures; a diffusion barrier layer is formed above the first metal-containing layer and around the lower and upper semiconductor nanostructures; the top portions of the first metal-containing layer and the diffusion barrier layer are removed to expose the portion of the gate dielectric layer disposed around the upper semiconductor nanostructure; and a gate electrode layer is deposited above the diffusion barrier layer and around the upper semiconductor nanostructure.

[0006] Some embodiments of this application provide a semiconductor device including: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures located above the plurality of first nanostructures extending between second source / drain regions; an isolation structure located between the plurality of first nanostructures and the plurality of second nanostructures; a first gate stack located around the plurality of first nanostructures, wherein the first gate stack includes: a first metal-containing layer located around the first nanostructures among the plurality of first nanostructures; a diffusion barrier layer located above the first metal-containing layer and around the first nanostructures among the plurality of first nanostructures; a second metal-containing layer located on the sidewall of the diffusion barrier layer; a lower gate electrode layer located above the second metal-containing layer; and a second gate stack located on the first gate stack and disposed around the plurality of second nanostructures. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 An exemplary schematic diagram of stacked transistors (such as complementary field-effect transistors (CFETs)) in a three-dimensional view according to some embodiments is shown.

[0009] Figures 2 to 20B This is a view of an intermediate stage in the fabrication of a CFET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] According to various embodiments, a semiconductor device including a CFET can be formed. The CFET includes a lower nanostructure FET and an upper nanostructure FET disposed above the lower nanostructure FET. Forming the semiconductor device may include forming an upper channel region of the upper nanostructure FET and a lower channel region of the lower nanostructure FET, the upper and lower channel regions being disposed above the fin. In embodiments, the upper nanostructure FET may be an NMOS transistor, and the lower nanostructure FET may be a PMOS transistor. A gate dielectric layer is formed around the upper and lower channel regions and above the fin. A first metal-containing layer may be formed above the gate dielectric layer and around the upper and lower channel regions. The first metal-containing layer may include titanium nitride (TiN), etc. Then, a diffusion barrier layer is formed above the first metal-containing layer and around the upper and lower channel regions. The diffusion barrier layer may include titanium tungsten nitride (TiWN), tungsten nitride (WN), etc., wherein the diffusion layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In one embodiment, the diffusion barrier layer may include low-temperature titanium nitride (TiN). Low-temperature titanium nitride (TiN) can be formed using a deposition process performed at a process temperature below 250°C. In another embodiment, the deposition process for forming low-temperature titanium nitride (TiN) can be performed at a process temperature below 350°C. Then, a suitable masking and etching process is performed to remove portions of the first metal-containing layer and diffusion barrier layer disposed around the upper channel region. After the masking and etching process, the remaining portions of the first metal-containing layer and diffusion barrier layer are disposed around the lower channel region. Then, a second metal-containing layer is formed over the gate dielectric layer and around the upper channel region, and on the sidewalls of the diffusion barrier layer disposed around the lower channel region. The second metal-containing layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), etc. Then, a lower gate electrode is formed over the second metal-containing layer and over the first metal-containing layer and diffusion barrier layer around the lower channel region. An upper gate electrode is formed on the surface of the second metal-containing layer over the lower gate electrode and around the upper channel region.

[0013] Advantageous features of one or more embodiments disclosed herein allow for the formation of a diffusion barrier layer disposed between a second metal-containing layer and a first metal-containing layer, wherein the formation of the diffusion barrier layer reduces work function metal interference and aluminum diffusion between the second and first metal-containing layers. Placing a diffusion barrier layer between the first and second metal-containing layers helps maintain stable work function characteristics of NMOS and PMOS transistors used in semiconductor devices. This improved stability results in better threshold voltage control, increased manufacturing yield, and enhanced device performance.

[0014] Figure 1An exemplary schematic diagram of a stacked transistor (such as a complementary field-effect transistor (CFET)) according to some embodiments is shown. Figure 1 This is a 3D view, in which some components of the CFET are omitted for clarity.

[0015] CFETs comprise multiple vertically stacked nanostructure FETs (e.g., nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, etc.). For example, a CFET may comprise a lower nanostructure FET of a first device type (e.g., n-type / p-type) and an upper nanostructure FET of a second device type opposite to the first device type (e.g., p-type / n-type). Specifically, a CFET may comprise a lower PMOS transistor and an upper NMOS transistor, or a CFET may comprise a lower NMOS transistor and an upper PMOS transistor. Each nanostructure FET comprises a semiconductor nanostructure 66 (including a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), wherein the semiconductor nanostructure 66 serves as a channel region for the nanostructure FET. The semiconductor nanostructure 66 may be a nanosheet, nanowire, etc. The lower semiconductor nanostructure 66L is used for the lower nanostructure FET, and the upper semiconductor nanostructure 66U is used for the upper nanostructure FET. Channel isolation materials ( Figure 1 Not explicitly stated in the text, see Figure 18 This is used to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L.

[0016] Gate dielectric 132 extends along the top, sidewalls, and bottom surface of semiconductor nanostructure 66. Gate electrode 134 (including lower gate electrode 134L and upper gate electrode 134U) is located above gate dielectric 132 and around semiconductor nanostructure 66. Source / drain regions 108 (including lower epitaxial source / drain region 108L and upper epitaxial source / drain region 108U) are disposed on opposite sides of gate dielectric 132 and gate electrode 134. Source / drain region 108 may refer to a source or drain, individually or collectively, depending on the context. Isolation components may be formed to separate desired source / drain regions 108 and / or desired gate electrode 134. For example, lower gate electrode 134L may optionally be separated from upper gate electrode 134U. Alternatively, lower gate electrode 134L may be coupled to upper gate electrode 134U. Furthermore, the upper epitaxial source / drain region 108U can be separated from the lower epitaxial source / drain region 108L by one or more dielectric layers. Figure 1 Not explicitly stated in the text, see Figure 18The isolation components between the channel region, gate, and source / drain regions allow for vertically stacked transistors, thereby improving device density. Due to the vertical stacking characteristics of CFETs, the schematic diagram can also be referred to as a stacked transistor or a folded transistor.

[0017] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and in the direction of current, for example, between the source / drain regions 108 of the CFET. Cross section B-B' is perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 134 of the CFET. For clarity, the following figures refer to these reference cross sections.

[0018] Figures 2 to 20B This is a view of an intermediate stage in the manufacture of a semiconductor device 20 including a CFET, according to some embodiments. Figure 2 , Figure 3A and Figure 4 It is shown that... Figure 1 A similar three-dimensional view. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 11A , Figure 18 , Figure 19 and Figure 20A It shows the line and Figure 1 A cross-sectional view of a section similar to the reference section A-A' in the diagram. Figure 3B , Figure 10B , Figure 11B , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 20B It shows the line and Figure 1 A cross-sectional view of a section similar to the reference section B-B' in the diagram.

[0019] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0020] A multilayer stack 52 is formed over a substrate 50. The multilayer stack 52 includes alternating dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B. Another subset of the upper semiconductor layer 56U and the first dummy layer 54A is disposed above the second dummy layer 54B. As will be described in more detail later, the dummy layers 54 will be removed, and the semiconductor layers 56 will be patterned to form the channel region of the CFET. Specifically, the lower semiconductor layer 56L will be patterned to form the channel region of the lower nanostructure FET of the CFET, and the upper semiconductor layer 56U will be patterned to form the channel region of the upper nanostructure FET of the CFET.

[0021] The multilayer stack 52 is shown as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0022] The first dummy layer 54A and the second dummy layer 54B may be formed of a first semiconductor material. The first semiconductor material may be selected from candidate semiconductor materials of the substrate 50. In some embodiments, the dummy layer 54 (e.g., the first dummy layer 54A and the second dummy layer 54B) is formed of or includes silicon germanium, and the second dummy layer 54B may be formed of germanium or silicon germanium having a higher percentage of germanium atoms than the first dummy layer 54A. The first dummy layer 54A and the second dummy layer 54B have high etch selectivity to each other, thereby allowing the second dummy layer 54B to be removed at a faster rate than the first dummy layer 54A in subsequent processing. The semiconductor layer 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U) is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may be selected from candidate semiconductor materials of the substrate 50. In some embodiments, the semiconductor layer 56 is formed of silicon. Semiconductor layer 56 and dummy layer 54 have high etch selectivity to each other, which allows dummy layer 54 (e.g., first dummy layer 54A and second dummy layer 54B) to be removed at a faster rate in subsequent processing than semiconductor layer 56 (e.g., lower semiconductor layer 56L and upper semiconductor layer 56U).

[0023] exist Figure 3A and Figure 3B In this process, fins 62 are formed in the substrate 50, and nanostructures 64 and 66 (including a first pseudo-nanostructure 64A, a second pseudo-nanostructure 64B, a lower semiconductor nanostructure 66L, an intermediate semiconductor nanostructure 66M, and an upper semiconductor nanostructure 66U) are formed in the multilayer stack 52. In some embodiments, nanostructures 64 and 66 and fins 62 can be formed in the multilayer stack 52 and the substrate 50, respectively, by etching trenches in the multilayer stack 52 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. Nanostructures 64 and 66 formed by etching multilayer stack 52 can define a first pseudo-nanostructure 64A from a first pseudo-layer 54A, a second pseudo-nanostructure 64B from a second pseudo-layer 54B, a lower semiconductor nanostructure 66L from some of the lower semiconductor layer 56L, an upper semiconductor nanostructure 66U from some of the upper semiconductor layer 56U, and an intermediate semiconductor nanostructure 66M from some of the lower semiconductor layer 56L and some of the upper semiconductor layer 56U. The first pseudo-nanostructure 64A and the second pseudo-nanostructure 64B can be further collectively referred to as pseudo-nanostructure 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U can be further collectively referred to as semiconductor nanostructure 66.

[0024] As will be described in more detail later, each of the nanostructures 64, 66 will be removed to form the channel region of the CFET. Specifically, the lower semiconductor nanostructure 66L will be used as the channel region of the lower nanostructure FET for the CFET. Furthermore, the upper semiconductor nanostructure 66U will be used as the channel region of the upper nanostructure FET for the CFET.

[0025] The intermediate semiconductor nanostructure 66M is a semiconductor nanostructure 66 located directly above / below (e.g., in contact with) the second pseudo-nanostructure 64B. Depending on the height of the subsequently formed source / drain regions, the intermediate semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions and may or may not be used as a functional channel region for the CFET. Subsequently, the second pseudo-nanostructure 64B will be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 66M can define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0026] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0027] Although each of the fins 62 and nanostructures 64, 66 is shown to always have a constant width, in other embodiments, the fins 62 and / or nanostructures 64, 66 may have tapered sidewalls, such that the width of each of the fins 62 and / or nanostructures 64, 66 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in shape.

[0028] Furthermore, an isolation region 70 is formed above the substrate 50 and between adjacent semiconductor fins 62. The isolation region 70 may include a pad and a filler material above the pad. Each of the pad and filler material may include a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. Forming the isolation region 70 may include: depositing a dielectric material; and performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove excess portions of the dielectric material, such as those above the nanostructures 64, 66. The deposition process may include ALD, high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or a combination thereof. In some embodiments, the isolation region 70 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric material is then recessed to define the isolation region 70. The dielectric material may be recessed such that the upper portions of the semiconductor fins 62 and nanostructures 64, 66 extend above the isolation region 70.

[0029] The previously described process is merely one example of how fins 62 and nanostructures 64, 66 can be formed. In some embodiments, fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form fins 62 and / or nanostructures 64, 66. The epitaxial structure can include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material being epitaxially grown can be doped in situ during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0030] exist Figure 4In this process, a pseudo-dielectric layer 72 is formed on fins 62 and / or nanostructures 64, 66. The pseudo-dielectric layer 72 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A pseudo-gate layer 74 is formed above the pseudo-dielectric layer 72, and a mask layer 76 is formed above the pseudo-gate layer 74. The pseudo-gate layer 74 can be deposited above the pseudo-dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited above the pseudo-gate layer 74. The pseudo-gate layer 74 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The pseudo-gate layer 74 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The pseudo-gate layer 74 can be formed from other materials that have high etch selectivity to insulating materials. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70, thereby extending the dummy dielectric layer 72 between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or the nanostructures 64, 66.

[0031] exist Figure 5 In this process, mask layer 76 can be patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to dummy gate layer 74 and dummy dielectric layer 72 to form dummy gate 84 and dummy dielectric 82, respectively. The dummy gate 84 covers the corresponding channel regions of nanostructures 64, 66. The pattern of mask 86 can be used to physically separate each of the dummy gate 84 from its adjacent counterpart. The dummy gate 84 can also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding fin 62. After patterning, mask 86 can optionally be removed, such as by any acceptable etching technique.

[0032] exist Figure 6In this process, gate spacers 90 are formed over nanostructures 64 and 66 and on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to pattern the dielectric material. Etching can be anisotropic. The dielectric material (when etched) has portions remaining on the sidewalls of the dummy gate 84 (thus forming gate spacers 90). In some embodiments, the dielectric material (when etched) may also have portions remaining on the sidewalls of fins 62 and / or nanostructures 64 and 66.

[0033] It should be noted that the previous disclosures generally described the process for forming the spacers. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, etc.

[0034] Source / drain recesses 94 are formed in fins 62, nanostructures 64, 66, and substrate 50. Epitaxial source / drain regions are subsequently formed in the source / drain recesses 94. The source / drain recesses 94 may extend through nanostructures 64, 66 and into substrate 50. Fins 62 may be etched such that the bottom surface of the source / drain recesses 94 is positioned above, below, or flush with the top surface of isolation region 70. In the illustrated example, the top surface of isolation region 70 is positioned above the bottom surface of the source / drain recesses 94. The source / drain recesses 94 can be formed by etching fins 62, nanostructures 64, 66, and substrate 50 using anisotropic etching processes (such as RIE, NBE, etc.). Gate spacers 90 and dummy gates 84 mask portions of fins 62, nanostructures 64, 66, and substrate 50 during the etching process used to form the source / drain recesses 94. Each layer of nanostructures 64, 66 and / or fins 62 can be etched using a single etching process or multiple etching processes. After the source / drain trenches 94 have reached the desired depth, a timed etching process can be used to stop the etching of the source / drain trenches 94.

[0035] exist Figure 7In this process, the sidewalls of the first pseudo-nanostructure 64A, exposed by the source / drain trench 94, are recessed to form a sidewall trench 96A. Furthermore, the second pseudo-nanostructure 64B is removed to form an opening 96B between the lower semiconductor nanostructure 66L (collectively referred to as the lower semiconductor nanostructure 66L) and the upper semiconductor nanostructure 66U (collectively referred to as the upper semiconductor nanostructure 66U). The sidewall trench 96A is then filled with a spacer. The opening 96B is then filled with an isolation structure.

[0036] The sidewall recess 96A can be formed by recessing the sidewalls of the first pseudo-nanostructure 64A using any acceptable etching process. The etching is selective for the first pseudo-nanostructure 64A (e.g., selectively etching the material of the first pseudo-nanostructure 64A at a rate faster than that of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the first pseudo-nanostructure 64A are shown as being straight after etching, the sidewalls can be concave or convex.

[0037] The opening 96B can be formed by removing the second pseudo-nanostructure 64B using any acceptable etching process. The etching is selective for the second pseudo-nanostructure 64B (e.g., selectively etching the material of the second pseudo-nanostructure 64B at a rate faster than that of the semiconductor nanostructure 66). The etching can be isotropic. The pseudo-gate 84 can be bonded to and support the upper semiconductor nanostructure 66U such that the upper semiconductor nanostructure 66U does not collapse after the opening 96B is formed.

[0038] In some embodiments, the same etching process is used to recess the sidewalls of the first pseudo-nanostructure 64A and to remove the second pseudo-nanostructure 64B. For example, the second pseudo-nanostructure 64B can be completely removed without completely removing the first pseudo-nanostructure 64A, and the first pseudo-nanostructure 64A can be recessed without significantly recessing the semiconductor nanostructure 66. The etching process is selective among the materials of the first pseudo-nanostructure 64A, the second pseudo-nanostructure 64B, and the semiconductor nanostructure 66. Specifically, the etching process selectively etches the material of the first pseudo-nanostructure 64A at a rate faster than the material of the semiconductor nanostructure 66, and also selectively etches the material of the second pseudo-nanostructure 64B at a rate faster than the material of the first pseudo-nanostructure 64A. Therefore, the etching rate of the first pseudo-nanostructure 64A is less than the etching rate of the second pseudo-nanostructure 64B, and greater than the etching rate of the semiconductor nanostructure 66. In some embodiments, the second pseudo-nanostructure 64B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the first pseudo-nanostructure 64A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 66 is formed of germanium-free silicon. The etching process may include a dry etching process using chlorine gas, with or without plasma.

[0039] The intermediate semiconductor nanostructure 66M is exposed by an opening 96B. In some embodiments, an etching process thins the intermediate semiconductor nanostructure 66M. Therefore, the thickness of the intermediate semiconductor nanostructure 66M can differ from (e.g., less than) the thickness of the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U. In some embodiments, after the etching process, the intermediate semiconductor nanostructure 66M is 0% to 20% thinner than the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U.

[0040] exist Figure 8 In this process, an internal spacer 98 is formed in the sidewall recess 96A and on the sidewall of the remaining portion of the first pseudo-nanostructure 64A. As described in more detail later, a source / drain region will subsequently be formed in the source / drain recess 94, and the first pseudo-nanostructure 64A will be replaced with a corresponding gate structure. The internal spacer 98 serves as an isolation member between the subsequently formed source / drain region and the subsequently formed gate structure. Furthermore, the internal spacer 98 can be used to prevent damage to the subsequently formed source / drain region by subsequent etching processes (such as etching processes used to form the gate structure). Additionally, an isolation structure 100 is formed in the opening 96B and between the intermediate semiconductor nanostructure 66M. The isolation structure 100 and the intermediate semiconductor nanostructure 66M will define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0041] The internal spacer 98 and the isolation structure 100 can be formed by conformally forming an insulating material in the source / drain recess 94, the sidewall recess 96A, and the opening 96B, and then subsequently etching the insulating material. The insulating material can be a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. The insulating material (when etched) has a portion retained in the sidewall recess 96A (thus forming the internal spacer 98) and a portion retained in the opening 96B (thus forming the isolation structure 100).

[0042] Although the outer walls of the internal spacer 98 and the isolation structure 100 are shown flush with the sidewalls of the semiconductor nanostructure 66, the outer walls of the internal spacer 98 and the isolation structure 100 may extend beyond the sidewalls of the semiconductor nanostructure 66 or be recessed relative to the sidewalls of the semiconductor nanostructure 66. Therefore, the internal spacer 98 and the isolation structure 100 may partially fill, fully fill, or overfill the sidewall recesses 96A and openings 96B, respectively. Furthermore, although the sidewalls of the internal spacer 98 and the isolation structure 100 are shown as straight, those sidewalls may be concave or convex.

[0043] The isolation structures 100 have similar dimensions to the second pseudo-nanostructures 64B that they replace. Therefore, the isolation structures 100 can have a large thickness, such as a thickness greater than that of the semiconductor nanostructures 66 and the first pseudo-nanostructure 64A, or the isolation structures 100 can have a small thickness, such as a thickness smaller than that of the semiconductor nanostructures 66 and the first pseudo-nanostructure 64A. In some embodiments, the isolation structures 100 are 60% to 90% thinner than the semiconductor nanostructure 66, and 40% to 90% thinner than the first pseudo-nanostructure 64A.

[0044] exist Figure 9 In the source / drain trench 94, a lower epitaxial source / drain region 108L and an upper epitaxial source / drain region 108U are formed. A first contact etch stop layer (CESL) 112 and / or a first interlayer dielectric (ILD) 114 may also be formed in the source / drain trench 94. The first ILD 114 is located between the upper epitaxial source / drain region 108U and the lower epitaxial source / drain region 108L. The lower epitaxial source / drain region 108L serves as the lower nanostructure FET of the CFET, and the upper epitaxial source / drain region 108U serves as the upper nanostructure FET of the CFET. Therefore, the first ILD 114 serves as an isolation region to prevent short circuits between the lower and upper nanostructure FETs. Furthermore, a second CESL 122 and / or a second ILD 124 may be formed on the upper epitaxial source / drain region 108U.

[0045] The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L but not the upper semiconductor nanostructure 66U. In some embodiments, the lower epitaxial source / drain region 108L applies stress to the corresponding channel region of the lower semiconductor nanostructure 66L to improve performance. The lower epitaxial source / drain region 108L is formed in a source / drain recess 94, such that each stack of the lower semiconductor nanostructure 66L is disposed between corresponding adjacent pairs of the lower epitaxial source / drain regions 108L. In some embodiments, an internal spacer 98 is used to separate the lower epitaxial source / drain region 108L from a first pseudo-nanostructure 64A, which will be replaced with a gate structure in a subsequent process.

[0046] The lower epitaxial source / drain region 108L is epitaxially grown in the lower portion of the source / drain recess 94. For example, the lower epitaxial source / drain region 108L can be grown laterally from the exposed sidewalls of the lower semiconductor nanostructure 66L and the bottom surface of the fin 62 / substrate 50 in the source / drain recess 94. During the epitaxy of the lower epitaxial source / drain region 108L, the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can be masked to prevent undesirable epitaxial growth on the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U. After the lower epitaxial source / drain region 108L is grown, the mask on the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can then be removed. The lower epitaxial source / drain region 108L has a conductivity type suitable for the device type of the lower nanostructure FET. In some embodiments, the lower epitaxial source / drain region 108L is an n-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon, the lower epitaxial source / drain region 108L may include a material on which tensile strain is applied to the lower semiconductor nanostructure 66L, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon-germanium, the lower epitaxial source / drain region 108L may include a material on which compressive strain is applied to the lower semiconductor nanostructure 66L, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The lower epitaxial source / drain region 108L may have a surface protruding from the corresponding upper surface of the lower semiconductor nanostructure 66L, and may have a small facet.

[0047] The lower epitaxial source / drain region 108L can be implanted with dopant to form the source / drain region, followed by annealing. The source / drain region can have a density of 10... 19 atoms / cm 3 and 1021 atoms / cm 3 The impurity concentration is within a certain range. For example, n-type impurity implantation or p-type impurity implantation can be performed. n-type impurities can be phosphorus, arsenic, antimony, etc. p-type impurities can be boron, boron fluoride, indium, etc. In some embodiments, the lower epitaxial source / drain region 108L is in-situ doped during growth.

[0048] Due to the epitaxial process used to form the lower epitaxial source / drain regions 108L, the upper surface of the lower epitaxial source / drain regions 108L has small planes that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 108L of the same nanostructure FET to merge.

[0049] The first ILD 114 is formed above the lower epitaxial source / drain region 108L. The first ILD 114 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process can be used.

[0050] The first CESL 112 can be formed between the first ILD 114 and the lower epitaxial source / drain region 108L. The first CESL 112 can be formed from a dielectric material that has high etch selectivity to the dielectric material of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0051] The first CESL 112 and / or the first ILD 114 can be formed by depositing material for the first CESL 112 and material for the first ILD 114, followed by a subsequent etch-back process. In some embodiments, the first ILD 114 is initially etched, leaving the first CESL 112 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 112 above the first ILD 114. After recessing, the sidewalls of the upper semiconductor nanostructure 66U are exposed.

[0052] The upper epitaxial source / drain region 108U contacts the upper semiconductor nanostructure 66U but not the lower semiconductor nanostructure 66L. In some embodiments, the upper epitaxial source / drain region 108U applies stress to the corresponding channel region of the upper semiconductor nanostructure 66U to improve performance. The upper epitaxial source / drain region 108U is formed in a source / drain recess 94, such that each stack of the upper semiconductor nanostructure 66U is disposed between corresponding adjacent pairs of the upper epitaxial source / drain regions 108U. In some embodiments, an internal spacer 98 is used to separate the upper epitaxial source / drain region 108U from a first pseudo-nanostructure 64A, which will be replaced with a gate structure in a subsequent process.

[0053] The upper epitaxial source / drain region 108U is epitaxially grown in the upper portion of the source / drain recess 94. For example, the upper epitaxial source / drain region 108U can be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. The upper epitaxial source / drain region 108U has a conductivity type suitable for the device type of the upper nanostructure FET. The conductivity type of the upper epitaxial source / drain region 108U can be opposite to that of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U can be doped in the opposite way to the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U is an n-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon, the upper epitaxial source / drain region 108U may include a material on which tensile strain is applied to the upper semiconductor nanostructure 66U, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the upper epitaxial source / drain region 108U is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon-germanium, the upper epitaxial source / drain region 108U may include a material on which compressive strain is applied to the upper semiconductor nanostructure 66U, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The upper epitaxial source / drain region 108U may have a surface protruding from the corresponding upper surface of the upper semiconductor nanostructure 66U, and may have a small facet.

[0054] The upper epitaxial source / drain region 108U can be implanted with dopant to form the source / drain region, followed by annealing. The source / drain region can have a 10... 19 atoms / cm 3 and 10 21 atoms / cm 3The impurity concentration is within a certain range. For example, n-type impurity implantation or p-type impurity implantation can be performed. n-type impurities can be phosphorus, arsenic, antimony, etc. p-type impurities can be boron, boron fluoride, indium, etc. In some embodiments, the upper epitaxial source / drain region 108U is in-situ doped during growth.

[0055] Due to the epitaxial process used to form the upper epitaxial source / drain regions 108U, the upper surface of the upper epitaxial source / drain regions 108U has small planes that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent upper epitaxial source / drain regions 108U remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent upper epitaxial source / drain regions 108U of the same nanostructure FET to merge.

[0056] The second ILD 124 is deposited above the upper epitaxial source / drain region 108U. The second ILD 124 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process can be used.

[0057] The second CESL 122 can be formed between the second ILD 124 and the upper epitaxial source / drain region 108U. The second CESL 122 can be formed from a dielectric material with high etch selectivity to the dielectric material of the second ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0058] The second CESL 122 and / or the second ILD 124 can be formed by depositing material for the second CESL 122 and material for the second ILD 124. A removal process is then performed to make the top surface of the second ILD 124 flush with the top surface of the gate spacer 90 and the mask 86 (if present) or dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, can be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the second ILD 124, the gate spacer 90, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 86 (if present) or dummy gate 84 is exposed through the second ILD 124. In the illustrated embodiment, the mask 86 is retained after the removal process. In other embodiments, mask 86 is removed, thereby exposing the top surface of dummy gate 84 through second ILD 124.

[0059] exist Figure 10A and Figure 10B In one or more etching steps, the dummy gate 84 is removed, thereby forming a recess 67 between the gate spacers 90. A portion of the dummy dielectric 82 located in the recess 67 is also removed. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a rate faster than the materials of the second ILD 124, the isolation structure 100, the internal spacers 98, and the gate spacers 90. Each recess 67 between the gate spacers 90 exposes a portion of the nanostructures 64, 66 that serves as a channel region in the resulting device and / or is located above the portion of the nanostructures 64, 66 that serves as a channel region in the resulting device. The portions of the nanostructures 64, 66 that serve as channel regions are disposed between adjacent pairs of the lower epitaxial source / drain regions 108L or between adjacent pairs of the upper epitaxial source / drain regions 108U. During removal, the dummy dielectric 82 may be used as an etch stop layer when the dummy gate 84 is etched. Then, after removing the dummy gate 84, the dummy dielectric 82 can be removed.

[0060] The remaining portion of the first pseudo-nanostructure 64A is then removed to extend the groove 67, and openings are formed in the region between the semiconductor nanostructures 66 and in the region between the bottommost lower semiconductor nanostructure 66L and the fin 62. The remaining portion of the first pseudo-nanostructure 64A can be removed by any acceptable etching process that selectively etches the material of the first pseudo-nanostructure 64A at a rate faster than that of the materials of the semiconductor nanostructure 66, the internal spacer 98, and the isolation structure 100. The etching can be isotropic. For example, when the first pseudo-nanostructure 64A is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, the internal spacer 98 is formed of silicon carbonitride, and the isolation structure 100 is formed of silicon carbonitride, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the semiconductor nanostructure 66 and to widen the openings between the semiconductor nanostructures 66.

[0061] exist Figure 11A and Figure 11B In this process, a gate dielectric 132 can be deposited in a recess 67, such as between an opening between the gate spacer 90 and the semiconductor nanostructure 66. The gate dielectric 132 can also be deposited on the top surface of the second ILD 124 and the gate spacer 90. The gate dielectric 132 may include one or more gate dielectric layers disposed around the lower semiconductor nanostructure 66L, the upper semiconductor nanostructure 66U, and the isolation structure 100. Specifically, the gate dielectric 132 is disposed on the top surface of the fin 62; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric 132 encloses all (e.g., four) sides of the semiconductor nanostructure 66. The gate dielectric 132 can be formed of oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. Additionally or optionally, the gate dielectric 132 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In embodiments, the gate dielectric 132 may include a dielectric material having a dielectric constant greater than that of the dielectric material of the gate spacer 90. The dielectric material of the gate dielectric 132 may be formed by molecular beam deposition (MBD), ALD, PECVD, etc. Although a single-layer gate dielectric 132 is shown, the gate dielectric 132 may include any number of interface layers and any number of main layers. For example, the gate dielectric 132 may include an interface layer and an overlying high-k dielectric layer. In embodiments, the interface layer may include oxides formed on the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 66. The interface layer may not be formed on the surface of the inner spacer 98.

[0062] exist Figure 12 In this embodiment, a metal-containing layer 164 can be formed above the gate dielectric 132 and around the semiconductor nanostructure 66 in the recess 67. In this embodiment, the lower semiconductor nanostructure 66L can be used as a lower nanostructure FET, which is a PMOS transistor, and the metal-containing layer 164 can include titanium nitride, etc., which is conformally deposited using a suitable deposition process such as CVD, ALD, PVD, etc. In this embodiment, the metal-containing layer 164 can be deposited above the gate dielectric 132 and around the upper semiconductor nanostructure 66U and the lower semiconductor nanostructure 66L. Furthermore, the metal-containing layer 164 can be formed around the intermediate semiconductor nanostructure 66M. The metal-containing layer 164 can also be formed above the top surface and sidewalls of the fin 62 and above the top surface of the second ILD 124, the gate spacer 90, and the isolation region 70. In this embodiment, the metal-containing layer 164 can be formed using a deposition process performed at a process temperature below 450°C. In another embodiment, the deposition process for forming the metal layer 164 can be carried out at a process temperature below 500°C.

[0063] After forming the metal-containing layer 164, a diffusion barrier layer 166 (which may also be referred to as the metal-containing layer) can be formed above the metal-containing layer 164 and around the semiconductor nanostructures 66 (e.g., upper semiconductor nanostructure 66U, lower semiconductor nanostructure 66L, and middle semiconductor nanostructure 66M) in the groove 67 to fill the openings between the semiconductor nanostructures 66. The diffusion barrier layer 166 may include titanium tungsten nitride (TiWN), tungsten nitride (WN), titanium nitride (TiN), etc., which are conformally deposited using suitable deposition processes such as CVD, ALD, PVD, etc. In embodiments where the diffusion barrier layer 166 includes titanium tungsten nitride (TiWN) or tungsten nitride (WN), the diffusion barrier layer 166 may have a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In embodiments where the diffusion barrier layer 166 comprises titanium nitride (TiN), the diffusion barrier layer 166 is formed using a low-temperature deposition process performed at a process temperature below 250°C, or in another embodiment, at a process temperature below 350°C. After performing the low-temperature deposition process, the diffusion barrier layer 166 may comprise titanium nitride (TiN) having an oxygen concentration higher than that of the metal-containing layer 164.

[0064] Advantages can be achieved by forming a diffusion barrier layer 166 above the metal-containing layer 164 and around the semiconductor nanostructure 66. The diffusion barrier layer 166 may comprise titanium tungsten nitride (TiWN) or tungsten nitride (WN), and the diffusion barrier layer 166 has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. These advantages include allowing for a reduction in the amount of tungsten in the metal-containing layer 164 and the subsequently formed metal-containing layer 170 (…). Figure 15 The diffusion barrier layer 166 reduces work function metal interference and metal mixing between the metal-containing layers 170 and 164. Furthermore, the diffusion barrier layer 166 allows for reduced aluminum diffusion from the metal-containing layer 170 to the metal-containing layer 164. For example, a diffusion barrier layer 166 with a tungsten concentration of less than 5 atomic percent may not be sufficient to adequately prevent aluminum diffusion from the metal-containing layer 170 to the metal-containing layer 164. Placing the diffusion barrier layer 166 between the metal-containing layers 164 and 170 helps maintain stable work function characteristics for both the lower nanostructure FET (e.g., a PMOS transistor) and the upper nanostructure FET (e.g., an NMOS transistor) of the semiconductor device 20. The reduction in work function metal interference and aluminum diffusion results in improved threshold voltage (Vt) control, increased manufacturing yield, and enhanced device performance.

[0065] Other advantages can be achieved by forming a diffusion barrier layer 166 above the metal-containing layer 164 and around the semiconductor nanostructure 66. The diffusion barrier layer 166 may comprise titanium nitride (TiN) formed using a low-temperature deposition process performed at a process temperature below 250°C, or in another embodiment, at a process temperature below 350°C. After performing the low-temperature deposition process, the diffusion barrier layer 166 may comprise titanium nitride (TiN) with an oxygen concentration higher than that of the material (e.g., titanium nitride) of the metal-containing layer 164. These advantages include allowing for a reduction in the oxygen concentration of the metal-containing layer 164 and the subsequently formed metal-containing layer 170 (…). Figure 15 The work function metal interference and metal mixing between the metal layers 164 and 170 are described in the text. The higher oxygen concentration in the low-temperature titanium nitride (TiN) of the diffusion barrier layer 166 provides enhanced ability to prevent aluminum diffusion from the metal-containing layer 170 to the metal-containing layer 164. For example, a diffusion barrier layer comprising titanium nitride (TiN) formed using a deposition process performed at a process temperature above 350°C would result in a reduced oxygen concentration in the diffusion barrier layer 166, and therefore, the diffusion barrier layer 166 may not be sufficient to prevent aluminum diffusion from the metal-containing layer 170 to the metal-containing layer 164. Placing an oxygen-rich diffusion barrier layer 166 between the metal-containing layers 164 and 170 helps maintain stable work function characteristics for both the lower nanostructure FET (e.g., a PMOS transistor) and the upper nanostructure FET (e.g., an NMOS transistor) of the semiconductor device 20. The reduction in work function metal interference and aluminum diffusion results in improved threshold voltage (Vt) control, increased manufacturing yield, and enhanced device performance.

[0066] In one embodiment, the diffusion barrier layer 166 may comprise a silicon layer formed by surface treatment of the surface containing the metal layer 164 using a silane (SiH4) gas. The surface treatment may be performed at a process temperature below 200°C, or in another embodiment, at a process temperature below 300°C. In an alternative embodiment, the diffusion barrier layer 166 may be a metal oxide formed by surface treatment of a portion of the surface containing the metal layer 164 using an oxygen-containing gas such as O2 or O3. The surface treatment may be performed at a process temperature below 200°C, or in another embodiment, at a process temperature below 300°C.

[0067] The advantages can be achieved by surface treating the surface of the metal-containing layer 164 with silane (SiH4) gas at a process temperature below 200°C or, in another embodiment, at a process temperature below 300°C, by forming a diffusion barrier layer 166 comprising silicon. In other embodiments, the diffusion barrier layer 166 is formed by oxidizing a portion of the surface of the metal-containing layer 164 by surface treating it at a process temperature below 200°C or, in another embodiment, at a process temperature below 300°C, wherein the surface treatment is performed using an oxygen-containing gas such as O2 or O3. These advantages include the diffusion barrier layer 166 being disposed between the metal-containing layer 164 and the subsequently formed metal-containing layer 170 (…). Figure 15 The presence of a diffusion barrier layer 166 between the metal layers 164 and 170 allows for reduced work function metal interference and metal mixing between them. Surface treatment using silane (SiH4) gas or oxygen-containing gas can modify the surface of the metal layer 164, forming either a silicon layer or an oxide surface portion, which provides enhanced protection against aluminum diffusion from the metal layer 170 to the metal layer 164. Placing a diffusion barrier layer 166 between the metal layers 164 and 170 helps maintain stable work function characteristics for both the lower nanostructure FET (e.g., a PMOS transistor) and the upper nanostructure FET (e.g., an NMOS transistor) of the semiconductor device 20. The reduction in work function metal interference and aluminum diffusion results in improved threshold voltage (Vt) variation control, increased manufacturing yield, and enhanced device performance.

[0068] exist Figure 13 In this process, a dummy layer 168 is formed in the groove 67 (such as above the top surface and sidewalls of the diffusion barrier layer 166 in the groove 67). In some embodiments, the dummy layer 168 may be formed on the previously deposited surface using any suitable process such as spin coating, CVD, PECVD, etc. Figure 12 The structure shown has a bottom anti-reflective coating (BARC) layer above it. In an embodiment, dummy layer 168 may fill groove 67. Dummy layer 168 may include silicon-based, oxygen-based, or carbon-based materials, such as aluminum oxide (Al₂O₃).x (where x represents the variable oxygen content), yttrium oxide (Y₂O₃), and lanthanum oxide (LaO₂). x (where x represents the variable oxygen content), etc.

[0069] After forming the dummy layer 168, a portion of the dummy layer 168 may be disposed above the top surface of the second ILD 124 and the gate spacer 90. After forming the dummy layer 168, a suitable etch-back process (e.g., a dry etching process using nitrogen (N2) and hydrogen (H2) gases as etchants) can be performed to remove the portion of the dummy layer 168 in the recess 67. For example, the etch-back process can remove the top portion of the dummy layer 168 located above the second ILD 124 and the gate spacer 90. Furthermore, the etch-back process can remove the top portion of the dummy layer 168 in the recess 67, thereby exposing the top surface and sidewalls of the diffusion barrier layer 166 disposed above the isolation structure 100 in the recess 67 after the etch-back process. In an embodiment, after the etch-back process, the topmost surface of the dummy layer 168 is located below the topmost surface of the isolation structure 100 and above the bottommost surface of the isolation structure 100.

[0070] exist Figure 14 In this embodiment, a pseudo-layer 168 is used as an etching mask to perform an etching process (e.g., a wet etching process using a solution including hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), water, combinations thereof, etc.) to remove exposed portions of the diffusion barrier layer 166 and the underlying metal-containing layer 164, and to form openings between the upper semiconductor nanostructures 66U. In another embodiment, the etching process may also remove portions of the diffusion barrier layer 166 and the metal-containing layer 164 disposed on the top and sidewalls of the gate spacer 90 and on the top surface of the second ILD 124. In yet another embodiment, after the etching process, the gate dielectric 132 disposed around and between the upper semiconductor nanostructures 66U and on the sidewalls of the isolation structure is exposed. Furthermore, the gate dielectric 132 disposed on the sidewalls and top surface of the intermediate semiconductor nanostructure 66M (which is disposed above the isolation structure 100) is exposed. Furthermore, after the etching process, portions of the diffusion barrier layer 166 and the metal-containing layer 164 can remain disposed on the sidewalls of the isolation structure 100 and the sidewalls of the intermediate semiconductor nanostructure 66M disposed below the isolation structure 100. After the etching process, a suitable ashing process is used to remove the dummy layer 168 in the groove 67. In an embodiment, the ashing process may include exposing the dummy layer 168 to oxygen plasma, etc.

[0071] exist Figure 15 In the middle, it is possible Figure 14A metal-containing layer 170 is deposited above the structure shown and in the recess 67 (such as above the exposed surface of the gate dielectric 132 and around the upper semiconductor nanostructure 66U). In an embodiment, the upper semiconductor nanostructure 66U can be used as an upper nanostructure FET, which is an NMOS transistor. The metal-containing layer 170 can also be formed on the top surface of the metal-containing layer 164 and on the top surface and sidewalls of the diffusion barrier layer 166. Furthermore, the metal-containing layer 170 can be formed on the top surface and sidewalls of the gate spacer 90 and on the top surface of the second ILD 124. The metal-containing layer 170 can include aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), etc., which are conformally deposited using suitable processes such as ALD, CVD, PVD, etc.

[0072] Figure 16 The formation of a lower gate electrode 134L and an upper gate electrode 134U above the lower gate electrode 134L is illustrated. The lower gate electrode 134L and the upper gate electrode 134U may include one or more gate electrode layers 133. For example, one or more gate electrode layers 133 may be disposed in the lower portion of the recess 67 between the gate spacers 90 and above the metal-containing layer 164, the metal-containing layer 170, the diffusion barrier layer 166, the gate dielectric 132, and the lower semiconductor nanostructure 66L to form the lower gate electrode 134L. In an embodiment, the metal-containing layer 164, the metal-containing layer 170, the diffusion barrier layer 166, and one or more gate electrode layers 133 together form the lower gate electrode 134L. Furthermore, one or more gate electrode layers 133 may be disposed in the upper portion of the recess 67 between the gate spacers 90, above the lower gate electrode 134L, above the gate dielectric 132, the metal-containing layer 170, and around the upper semiconductor nanostructure 66U to form the upper gate electrode 134U. In an embodiment, the metal-containing layer 170 and one or more gate electrode layers 133 together form the upper gate electrode 134U. In an embodiment, the top surface of the lower gate electrode 134L is located below the top surface of the isolation structure 100.

[0073] As an example of forming a lower gate electrode 134L and an upper gate electrode 134U, one or more gate electrode layers 133 are formed in the groove 67 using a suitable deposition process (such as CVD, ALD, etc.). In embodiments, the one or more gate electrode layers 133 may include titanium nitride, etc. In other embodiments, the one or more gate electrode layers 133 may be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although the one or more gate electrode layers 133 are in Figure 16The diagram shows a single layer, but one or more gate electrode layers 133 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials. In embodiments, the lower gate electrode 134L and the upper gate electrode 134U may include dipole inducing elements suitable for the device type of the lower nanostructure FET or the upper nanostructure FET, respectively. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0074] Figure 17 A semiconductor device 20 according to some other embodiments is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) denote... Figures 1 to 16 The embodiments shown depict identical components formed using the same process. Therefore, the process steps and applicable materials need not be repeated herein. The initial steps of this embodiment are essentially the same as... Figures 1 to 11B The same as shown.

[0075] Figure 17 The formation of the lower gate electrode 134L is illustrated. The lower gate electrode 134L may include one or more lower gate electrode layers disposed above the gate dielectric 132 and around the lower semiconductor nanostructure 66L. The lower gate electrode 134L is disposed in the lower portion of the recess 67 between the gate spacers 90 and in the opening between the lower semiconductor nanostructures 66L, as well as between the bottommost lower semiconductor nanostructure 66L and the fin 62. In an embodiment, the top surface of the lower gate electrode 134L is located below the top surface of the isolation structure 100. The lower gate electrode 134L may be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. For example, in an embodiment, the lower semiconductor nanostructure 66L may be used for a lower nanostructure FET, which is a PMOS transistor, and the lower gate electrode 134L may include titanium nitride (TiN), etc. Although Figure 17 The diagram shows a single-layer gate electrode, but the lower gate electrode 134L may include any number of power function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0076] The lower gate electrode 134L is formed of a material suitable for the device type of a lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a work function adjustment metal suitable for the device type of a lower nanostructure FET. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of a p-type work function adjustment metal, such as titanium nitride, tantalum nitride, combinations thereof, etc. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. Additionally or optionally, the lower gate electrode 134L may include a dipole inducing element suitable for the device type of a lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0077] As an example of forming the lower gate electrode 134L, one or more lower gate electrode layers are formed above the gate dielectric 132 and in the opening between the remaining portion of the recess 67 between the gate spacers 90 and the semiconductor nanostructure 66. The lower gate electrode layers can be formed, for example, using a suitable deposition process, such as CVD, ALD, etc. The lower gate electrode layers can then be recessed. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to recess the lower gate electrode layers. The etching can be isotropic, such as an etch-back process that removes the lower gate electrode layers from the upper portion of the recess 67 between the gate spacers 90, thereby leaving the lower gate electrode layers in the opening between the lower semiconductor nanostructures 66L.

[0078] Further reference Figure 17 A diffusion barrier layer 172 (which may also be referred to as a metal-containing layer) is formed in the groove 67 and above the lower gate electrode 134L (e.g., above the top surface of the lower gate electrode 134L). The diffusion barrier layer 172 can be formed by depositing a metal-containing material such as titanium tungsten nitride (TiWN), tungsten nitride (WN), titanium nitride (TiN), etc., over the lower gate electrode 134L, the semiconductor nanostructure 66, and the gate dielectric 132 using a suitable deposition process such as CVD, ALD, PVD, etc. The metal-containing material can then be patterned using an acceptable photolithography and etching process, and the remaining portion of the metal-containing material forms the diffusion barrier layer 172.

[0079] In embodiments where the diffusion barrier layer 172 comprises titanium tungsten nitride (TiWN) or tungsten nitride (WN), the diffusion barrier layer 172 may have a tungsten concentration ranging from 5 atomic percent to 15 atomic percent. In embodiments where the diffusion barrier layer 172 comprises titanium nitride (TiN), the diffusion barrier layer 172 is formed using a low-temperature deposition process performed at a process temperature below 250°C, or in another embodiment, at a process temperature below 350°C. After performing the low-temperature deposition process, the diffusion barrier layer 172 may comprise titanium nitride (TiN) having an oxygen concentration higher than that of the lower gate electrode 134L. In embodiments, the thickness T1 of the diffusion barrier layer 172 ranges from 2 nm to 20 nm.

[0080] Advantages can be achieved by forming a diffusion barrier layer 172 above the lower gate electrode 134L. The diffusion barrier layer 172 may comprise titanium tungsten nitride (TiWN) or tungsten nitride (WN), and has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. These advantages include allowing for reduced work function metal interference and metal mixing between the lower gate electrode 134L (e.g., comprising titanium nitride (TiN)) and the subsequently formed upper gate electrode 134U (e.g., comprising titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), etc., and described below). Furthermore, the diffusion barrier layer 172 allows for reduced diffusion of aluminum from the upper gate electrode 134U to the lower gate electrode 134L. For example, a tungsten concentration of less than 5 atomic percent in the diffusion barrier layer 172 would render it insufficient to adequately prevent aluminum diffusion from the upper gate electrode 134U to the lower gate electrode 134L. Placing a diffusion barrier layer 172 between the lower gate electrode 134L and the upper gate electrode 134U helps maintain stable work function characteristics for both the lower nanostructure FET (e.g., a PMOS transistor) and the upper nanostructure FET (e.g., an NMOS transistor) of the semiconductor device 20. The reduction in work function metal interference and aluminum diffusion results in a reduced threshold voltage (Vt) variation, increased manufacturing yield, and enhanced device performance. Furthermore, the minimum voltage (Vmin) required for stable operation of the semiconductor device 20 can be reduced (e.g., when the semiconductor device 20 is a static random access memory (SRAM) device).

[0081] Further advantages can be achieved by forming a diffusion barrier layer 172 above the lower gate electrode 134L. The diffusion barrier layer 172 may comprise titanium nitride (TiN) formed using a cryogenic deposition process performed at a process temperature below 250°C, or, in another embodiment, at a process temperature below 350°C. After performing the cryogenic deposition process, the diffusion barrier layer 172 may comprise titanium nitride (TiN) with an oxygen concentration higher than that of the material of the lower gate electrode 134L (e.g., titanium nitride). These advantages include allowing for reduced work function metal interference and metal mixing between the lower gate electrode 134L (e.g., comprising titanium nitride (TiN)) and the subsequently formed upper gate electrode 134U (e.g., comprising titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), etc., and described below). The higher oxygen concentration in the cryogenic titanium nitride (TiN) of the diffusion barrier layer 172 provides enhanced protection against aluminum diffusion from the upper gate electrode 134U to the lower gate electrode 134L. For example, the diffusion barrier layer 172, comprising titanium nitride (TiN) formed using a deposition process performed at a process temperature above 350°C, will result in a reduced oxygen concentration in the diffusion barrier layer 172, and therefore, the diffusion barrier layer 172 will not be able to adequately prevent aluminum from diffusing from the upper gate electrode 134U to the lower gate electrode 134L. Placing an oxygen-rich diffusion barrier layer 172 between the lower gate electrode 134L and the upper gate electrode 134U helps maintain stable work function characteristics for both the lower nanostructure FET (e.g., a PMOS transistor) and the upper nanostructure FET (e.g., an NMOS transistor) of the semiconductor device 20. The reduction in work function metal interference and aluminum diffusion results in a reduced threshold voltage (Vt) variation, increased manufacturing yield, and enhanced device performance. Furthermore, the minimum voltage (Vmin) required for stable operation of the semiconductor device 20 can be reduced (e.g., when the semiconductor device 20 is a static random access memory (SRAM) device).

[0082] After the diffusion barrier layer 172 is formed, an upper gate electrode 134U is formed above the lower gate electrode 134L and the diffusion barrier layer 172, thereby disposing the diffusion barrier layer 172 between the lower gate electrode 134L and the upper gate electrode 134U. The upper gate electrode 134U may include a metal-containing layer 135 disposed above and around the gate dielectric 132 and around the upper semiconductor nanostructure 66U, and one or more upper gate electrode layers disposed above the diffusion barrier layer 172 and the metal-containing layer 135. The upper gate electrode 134U is disposed in the upper portion of the recess 67 between the gate spacers 90 and in the opening between the upper semiconductor nanostructure 66U. The upper gate electrode 134U may be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. For example, in an embodiment, the upper semiconductor nanostructure 66U can be used as an upper nanostructure FET, which is an NMOS transistor, and one or more upper gate electrode layers containing the metal layer 135 and the upper gate electrode 134U can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), etc. In an embodiment, the upper gate electrode 134U can include any number of power function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0083] The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a work function adjustment metal suitable for the device type of the upper nanostructure FET. In some embodiments, the upper gate electrode 134U includes an n-type work function adjustment layer, which may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the upper gate electrode 134U includes a p-type work function adjustment layer, which may be formed of a p-type work function adjustment metal, such as titanium nitride, tantalum nitride, combinations thereof, etc. The work function adjustment metal of the upper gate electrode 134U may be different from the work function adjustment metal of the lower gate electrode 134L. Additionally or optionally, the upper gate electrode 134U may include a dipole inducing element suitable for the device type of the upper nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The dipole inducing element of the upper gate electrode 134U can be different from that of the lower gate electrode 134L.

[0084] As an example of forming the upper gate electrode 134U, a metal-containing layer 135 is formed around the semiconductor nanostructure 66U in the upper portion of the recess 67, and after the metal-containing layer 135 is formed, one or more upper gate electrode layers are formed in the upper portion of the recess 67, such as above the metal-containing layer 135, the diffusion barrier layer 172, and the lower gate electrode 134L, and in the openings between the upper semiconductor nanostructures 66U. The metal-containing layer 135 and the upper gate electrode layers can be formed, for example, using suitable deposition processes (such as CVD, ALD, etc.).

[0085] exist Figure 18 In this process, a removal process can be implemented to remove one or more gate electrode layers 133 and / or gate dielectric 132 (in Figure 16 (as described in the embodiments shown) or one or more upper gate electrode layers, including metal layer 135 and / or gate dielectric 132 (in Figure 17 The excess portion (described in the illustrated embodiment) is located above the top surface of the gate spacer 90 and the second ILD 124. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, may be utilized. When a planarization process is used, the top surfaces of the gate spacer 90, the second ILD 124, the gate dielectric 132, and the upper gate electrode 134U are coplanar (within process variations).

[0086] Gate dielectric 132 and gate electrode 134 (including lower gate electrode 134L and upper gate electrode 134U) form an alternative gate. Each corresponding pair of gate dielectric 132 and gate electrode 134 (including upper gate electrode 134U and / or lower gate electrode 134L) may be collectively referred to as a "gate structure" or "gate stack". Each gate structure extends along at least three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of semiconductor nanostructure 66. The gate structure may also extend along the sidewalls and / or top surface of semiconductor fin 62.

[0087] exist Figure 19In the second ILD 124, a source / drain contact 144 is formed to electrically couple to the upper epitaxial source / drain region 108U and / or the lower epitaxial source / drain region 108L. As an example of forming the source / drain contact 144, an opening for the source / drain contact 144 is formed through the second ILD 124 and the second CESL 122. The opening can be formed using acceptable photolithography and etching techniques. In the illustrated embodiment, the opening is formed using a self-aligned contact (SAC) process. A pad (not shown separately), such as a diffusion barrier layer or adhesive layer, and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process can be implemented to remove the material from the gate spacer 90, the second ILD 124 (see...). Figure 18 Excess material is removed from the top surface of the gate electrode 134U and the upper gate electrode 134U. The remaining pads and conductive material form the source / drain contacts 144 in the opening. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, are utilized. After the planarization process, the gate spacer 90, the second ILD 124 (see...) Figure 18 The top surfaces of the upper gate electrode 134U and the source / drain contact 144 are substantially coplanar (within the process variation).

[0088] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 142 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 142 can be formed prior to the material of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 108 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from openings used for the source / drain contacts 144 (such as from the surface of the metal-semiconductor alloy region 142). The material for the source / drain contacts 144 can then be formed on the metal-semiconductor alloy region 142.

[0089] exist Figure 20A and Figure 20B In this process, a third ILD 154 is deposited over the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contact 144. In some embodiments, the third ILD 154 is a flowable film formed by a flowable CVD method, followed by curing of the flowable film. In some embodiments, the third ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0090] In some embodiments, an etch stop layer (ESL) 152 is formed between the third ILD 154 and the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contact 144. The ESL 152 may include a dielectric material that has high etch selectivity to the dielectric material of the third ILD 154, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0091] A gate contact 156 and a source / drain via 158 are formed through the third ILD 154 to electrically couple to the upper gate electrode 134U and the source / drain contact 144, respectively. As an example of forming the gate contact 156 and the source / drain via 158, openings for the gate contact 156 and the source / drain via 158 are formed through the third ILD 154 and ESL 152. These openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed within the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 154. The remaining pads and conductive material form the gate contact 156 and the source / drain via 158 within the openings. The gate contact 156 and the source / drain via 158 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 156 and the source / drain via 158 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0092] The active devices shown are collectively referred to as device layers. In some embodiments, the contacts to the lower gate electrode 134L and the lower epitaxial source / drain region 108L can be formed on the back side of the device layer (e.g., the side opposite to the source / drain contact 144).

[0093] The embodiments of this disclosure have several advantageous features. The embodiments include forming a semiconductor device including a complementary field-effect transistor (CFET), wherein forming the semiconductor device may include forming an upper channel region of an upper nanostructure FET and a lower channel region of a lower nanostructure FET, the upper and lower channel regions being disposed above a fin. In an embodiment, the upper nanostructure FET may be an NMOS transistor, and the lower nanostructure FET may be a PMOS transistor. A gate dielectric layer is formed around the upper and lower channel regions and above the fin. A first metal-containing layer may be formed above the gate dielectric layer and around the upper and lower channel regions. The first metal-containing layer may include titanium nitride (TiN) or the like. Then, a diffusion barrier layer is formed above the first metal-containing layer and around the upper and lower channel regions. The diffusion barrier layer may include titanium tungsten nitride (TiWN), tungsten nitride (WN), or the like, wherein the diffusion layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In an embodiment, the diffusion barrier layer may include low-temperature titanium nitride (TiN). Low-temperature titanium nitride (TiN) can be formed using a deposition process performed at a process temperature below 250°C. In another embodiment, the deposition process for forming low-temperature titanium nitride (TiN) can be performed at a process temperature below 350°C. Then, a suitable masking and etching process is performed to remove portions of the first metal-containing layer and diffusion barrier layer disposed around the upper channel region. After the masking and etching process, the remaining portions of the first metal-containing layer and diffusion barrier layer are disposed around the lower channel region. Then, a second metal-containing layer is formed above the gate dielectric layer and around the upper channel region, as well as on the sidewalls of the diffusion barrier layer disposed around the lower channel region. The second metal-containing layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), etc. Then, a lower gate electrode is formed above the second metal-containing layer and above the first metal-containing layer and diffusion barrier layer around the lower channel region. An upper gate electrode is formed on the surface of the second metal-containing layer above the lower gate electrode and around the upper channel region.

[0094] One or more embodiments disclosed herein can allow the formation of a diffusion barrier layer disposed between a second metal-containing layer and a first metal-containing layer, wherein the formation of the diffusion barrier layer reduces work function metal interference and aluminum diffusion between the second and first metal-containing layers. Placing a diffusion barrier layer between the first and second metal-containing layers helps maintain stable work function characteristics of NMOS and PMOS transistors used in semiconductor devices. This improved stability results in better threshold voltage control, increased manufacturing yield, and enhanced device performance.

[0095] While the above embodiments describe the formation of a CFET structure having a PMOS transistor as a lower nanostructure FET and an NMOS transistor as an upper nanostructure FET, the embodiments of this disclosure are not limited thereto. In alternative embodiments, a CFET structure having an NMOS transistor as a lower nanostructure FET and a PMOS transistor as an upper nanostructure FET can be formed. For example, an aluminum-containing N-function metal (e.g., TiAl, TiAlC) can be formed around the lower semiconductor nanostructure 66L, and a diffusion barrier layer can be formed over the aluminum-containing metal. Subsequently, a P-function metal (e.g., TiN) can be formed around the upper semiconductor nanostructure 66U and over the diffusion barrier layer. The diffusion barrier layer in these alternative embodiments can include similar materials and can be formed using a process similar to that described in the above embodiments.

[0096] According to an embodiment, the method includes: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; removing the pseudo-nanostructures to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures. An opening is formed; a gate dielectric layer is formed around a lower semiconductor nanostructure and an upper semiconductor nanostructure; a first metal-containing layer is formed above the gate dielectric layer and around the lower semiconductor nanostructure; a second metal-containing layer is formed above the first metal-containing layer, around the lower semiconductor nanostructure, and in the first opening; a third metal-containing layer is formed above the gate dielectric layer, around the upper semiconductor nanostructure, and above the second metal-containing layer; a lower gate electrode layer is deposited above the second and third metal-containing layers; and an upper gate electrode layer is deposited above the lower gate electrode layer, above the third metal-containing layer, and around the upper semiconductor nanostructure. In an embodiment, the first metal-containing layer comprises titanium nitride. In an embodiment, forming the second metal-containing layer comprises performing a deposition process at a process temperature below 350°C, and wherein the second metal-containing layer comprises titanium nitride. In an embodiment, the oxygen concentration of the second metal-containing layer is higher than the oxygen concentration of the first metal-containing layer. In an embodiment, the second metal-containing layer comprises titanium tungsten nitride or tungsten nitride. In an embodiment, the second metal-containing layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In one embodiment, the third metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In another embodiment, the second metal-containing layer comprises an oxide.

[0097] According to an embodiment, the method includes: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins include alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by semiconductor layers and the dummy nanostructures being defined by dummy layers; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; and removing the dummy nanostructures to... A first opening is formed between the lower semiconductor nanostructures, and a second opening is formed between the upper semiconductor nanostructures; a gate dielectric layer is formed around the lower and upper semiconductor nanostructures; a first metal-containing layer is formed above the gate dielectric layer and around the lower and upper semiconductor nanostructures; a diffusion barrier layer is formed above the first metal-containing layer and around the lower and upper semiconductor nanostructures; the top portions of the first metal-containing layer and the diffusion barrier layer are removed to expose the portion of the gate dielectric layer disposed around the upper semiconductor nanostructures; and a gate electrode layer is deposited above the diffusion barrier layer and around the upper semiconductor nanostructures. In an embodiment, the method further includes forming a second metal-containing layer above the exposed portion of the gate dielectric layer and around the upper semiconductor nanostructures and above the diffusion barrier layer before depositing the gate electrode layer. In an embodiment, the second metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In an embodiment, removing the top portions of the first metal-containing layer and the diffusion barrier layer comprises performing an etching process using a solution comprising hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), or a combination thereof. In an embodiment, the diffusion barrier layer comprises titanium tungsten nitride or tungsten nitride. In an embodiment, the diffusion barrier layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In an embodiment, the diffusion barrier layer comprises titanium nitride, and wherein the oxygen concentration of the diffusion barrier layer is higher than the oxygen concentration of the first metal-containing layer.

[0098] According to an embodiment, the semiconductor device includes: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures located above the plurality of first nanostructures extending between second source / drain regions; an isolation structure located between the plurality of first nanostructures and the plurality of second nanostructures; and a first gate stack located around the plurality of first nanostructures, wherein the first gate stack includes: a first metal-containing layer located around the first nanostructures among the plurality of first nanostructures; a diffusion barrier layer located above the first metal-containing layer and around the first nanostructures among the plurality of first nanostructures; a second metal-containing layer located on the sidewall of the diffusion barrier layer; a lower gate electrode layer located above the second metal-containing layer; and a second gate stack located on the first gate stack and disposed around the plurality of second nanostructures. In an embodiment, the second metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In an embodiment, the diffusion barrier layer comprises titanium tungsten nitride or tungsten nitride. In an embodiment, the diffusion barrier layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In one embodiment, the diffusion barrier layer comprises titanium nitride, and wherein the oxygen concentration of the diffusion barrier layer is higher than the oxygen concentration of the first metal-containing layer.

[0099] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain regions, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; removing the pseudo-nanostructures to form a first opening between the lower semiconductor nanostructures and to form a... A second opening is formed; a gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; a first metal-containing layer is formed above the gate dielectric layer and around the lower semiconductor nanostructure; a second metal-containing layer is formed above the first metal-containing layer, around the lower semiconductor nanostructure, and in the first opening; a third metal-containing layer is formed above the gate dielectric layer, around the upper semiconductor nanostructure, and above the second metal-containing layer; a lower gate electrode layer is deposited above the second metal-containing layer and the third metal-containing layer; and an upper gate electrode layer is deposited above the lower gate electrode layer, above the third metal-containing layer, and around the upper semiconductor nanostructure.

[0100] In some embodiments, the first metal-containing layer comprises titanium nitride. In some embodiments, forming the second metal-containing layer comprises performing a deposition process at a process temperature below 350°C, wherein the second metal-containing layer comprises titanium nitride. In some embodiments, the oxygen concentration of the second metal-containing layer is higher than the oxygen concentration of the first metal-containing layer. In some embodiments, the second metal-containing layer comprises titanium tungsten nitride or tungsten nitride. In some embodiments, the second metal-containing layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In some embodiments, the third metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In some embodiments, the second metal-containing layer comprises an oxide.

[0101] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins include alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by the semiconductor layers and the dummy nanostructures being defined by the dummy layers; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain regions, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; and removing the dummy layers. The nanostructure forms a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; a gate dielectric layer is formed around the lower and upper semiconductor nanostructures; a first metal-containing layer is formed above the gate dielectric layer and around the lower and upper semiconductor nanostructures; a diffusion barrier layer is formed above the first metal-containing layer and around the lower and upper semiconductor nanostructures; the top portions of the first metal-containing layer and the diffusion barrier layer are removed to expose the portion of the gate dielectric layer disposed around the upper semiconductor nanostructure; and a gate electrode layer is deposited above the diffusion barrier layer and around the upper semiconductor nanostructure.

[0102] In some embodiments, the method further includes forming a second metal-containing layer over the exposed portion of the gate dielectric layer and around the upper semiconductor nanostructure and over the diffusion barrier layer, prior to depositing the gate electrode layer. In some embodiments, the second metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In some embodiments, removing the top portion of the first metal-containing layer and the diffusion barrier layer comprises performing an etching process using a solution comprising hydrogen peroxide (H₂O₂), ammonium hydroxide (NH₄OH), or combinations thereof. In some embodiments, the diffusion barrier layer comprises titanium tungsten nitride or tungsten nitride. In some embodiments, the diffusion barrier layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In some embodiments, the diffusion barrier layer comprises titanium nitride, and wherein the oxygen concentration of the diffusion barrier layer is higher than the oxygen concentration of the first metal-containing layer.

[0103] Some embodiments of this application provide a semiconductor device including: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures located above the plurality of first nanostructures extending between second source / drain regions; an isolation structure located between the plurality of first nanostructures and the plurality of second nanostructures; a first gate stack located around the plurality of first nanostructures, wherein the first gate stack includes: a first metal-containing layer located around the first nanostructures among the plurality of first nanostructures; a diffusion barrier layer located above the first metal-containing layer and around the first nanostructures among the plurality of first nanostructures; a second metal-containing layer located on the sidewall of the diffusion barrier layer; a lower gate electrode layer located above the second metal-containing layer; and a second gate stack located on the first gate stack and disposed around the plurality of second nanostructures.

[0104] In some embodiments, the second metal-containing layer comprises titanium aluminum or titanium aluminum carbide. In some embodiments, the diffusion barrier layer comprises titanium tungsten nitride or tungsten nitride. In some embodiments, the diffusion barrier layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent. In some embodiments, the diffusion barrier layer comprises titanium nitride, and wherein the oxygen concentration of the diffusion barrier layer is higher than the oxygen concentration of the first metal-containing layer.

[0105] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A multilayer stack is formed on a semiconductor substrate, the multilayer stack comprising alternating semiconductor nanostructures and pseudo-nanostructures; A lower source / drain region is formed, wherein the lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; An upper source / drain region is formed above the lower source / drain region, wherein the upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; The pseudo-nanostructure is removed to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; A gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; A first metal-containing layer is formed above the gate dielectric layer and around the lower semiconductor nanostructure; A second metal-containing layer is formed above the first metal-containing layer, around the lower semiconductor nanostructure, and in the first opening; A third metal-containing layer is formed above the gate dielectric layer, around the upper semiconductor nanostructure, and above the second metal-containing layer; A lower gate electrode layer is deposited above the second metal-containing layer and the third metal-containing layer; and An upper gate electrode layer is deposited above the lower gate electrode layer, above the third metal-containing layer, and around the upper semiconductor nanostructure.

2. The method according to claim 1, wherein, The first metal-containing layer includes titanium nitride.

3. The method according to claim 2, wherein, Forming the second metal-containing layer includes performing a deposition process at a process temperature below 350°C, wherein the second metal-containing layer comprises titanium nitride.

4. The method according to claim 3, wherein, The oxygen concentration of the second metal-containing layer is higher than that of the first metal-containing layer.

5. The method according to claim 1, wherein, The second metal-containing layer includes titanium tungsten nitride or tungsten nitride.

6. The method according to claim 5, wherein, The second metal-containing layer has a tungsten concentration in the range of 5 atomic percent to 15 atomic percent.

7. The method according to claim 1, wherein, The third metal-containing layer includes titanium aluminum or titanium aluminum carbide.

8. The method according to claim 1, wherein, The second metal-containing layer includes an oxide.

9. A method for forming a semiconductor device, comprising: A multilayer stack is formed over a semiconductor substrate, the multilayer stack comprising alternating semiconductor layers and dummy layers; The multilayer stack is patterned to form a fin, wherein the fin comprises alternating semiconductor nanostructures and pseudo-nanostructures, the semiconductor nanostructures being defined by the semiconductor layers and the pseudo-nanostructures being defined by the pseudo layers; A lower source / drain region is formed, wherein the lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; An upper source / drain region is formed above the lower source / drain region, wherein the upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; The pseudo-nanostructure is removed to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; A gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; A first metal-containing layer is formed above the gate dielectric layer and around the lower semiconductor nanostructure and the upper semiconductor nanostructure; A diffusion barrier layer is formed above the first metal-containing layer and around the lower semiconductor nanostructure and the upper semiconductor nanostructure; Remove the top portion of the first metal-containing layer and the diffusion barrier layer to expose the portion of the gate dielectric layer disposed around the upper semiconductor nanostructure; and A gate electrode layer is deposited above the diffusion barrier layer and around the upper semiconductor nanostructure.

10. A semiconductor device, comprising: Multiple first nanostructures extend between first source / drain regions; Multiple second nanostructures are located above the multiple first nanostructures, and the multiple second nanostructures extend between the second source / drain regions; An isolation structure is located between the plurality of first nanostructures and the plurality of second nanostructures; A first gate stack is located around the plurality of first nanostructures, wherein the first gate stack includes: A first metal-containing layer is located around the first nanostructure in the plurality of first nanostructures; A diffusion barrier layer is located above the first metal-containing layer and around the first nanostructure in the plurality of first nanostructures; A second metal-containing layer is located on the sidewall of the diffusion barrier layer; and The lower gate electrode layer is located above the second metal-containing layer; and A second gate stack is located on top of the first gate stack and disposed around the plurality of second nanostructures.

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