Method of forming semiconductor device

Abstract

The method includes forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer wrapping each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while a bottom portion of the high-k gate dielectric layer remains, where the etching back includes a dry etch to etch the first gate metal and to generate a copolymer by-product covering the exposed top portion of the high-k gate dielectric layer; and performing a post-cleaning process to remove the copolymer by-product, the post-cleaning process including a first wet cleaning to remove a silicon oxide component of the copolymer by-product and a second wet cleaning to remove a metal oxide component of the copolymer by-product. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a persistent trend in the integrated circuit (IC) industry towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., the smallest possible IC component size), thereby improving production efficiency and reducing associated costs. However, such scaling also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar advancements in IC manufacturing processes and technologies.

[0003] The metal gate can be etched back to deposit various additional layers for gate tuning and improving device performance. For example, the metal gate may include etched-back work-function metal, followed by the deposition of fill metal over the etched-back work-function metal. In another example, a first gate metal can be deposited over a stacked semiconductor device (e.g., a complementary field-effect transistor (CFET) device) having a top device located above a bottom device. The top portion of the first gate metal is then etched back and removed from the top device to form a gate for the bottom device. A second gate metal is then deposited over the first gate metal to form a gate for the top device.

[0004] Conventional metal etchback processes have low selectivity, which can lead to gate dielectric losses (e.g., when the gate metal is etched deeper), making them unsuitable for removing the gate metal in stacked devices (e.g., CFET devices). Furthermore, conventional etchback processes have weaker plasma penetration, making it more difficult to etch devices requiring greater etchback depths.

[0005] Therefore, while existing gate etchback processes are generally sufficient to meet their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0006] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back comprises dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer; and performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process comprising a first wet cleaning using a first wet solution to remove silicon oxide components of the copolymer byproducts and a second wet cleaning using a second wet solution to remove metal oxide components of the copolymer byproducts.

[0007] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back leaves copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer and inserted into one or more metal voids in the first gate metal, wherein the copolymer byproducts comprise silicon oxide; performing a post-cleaning process to remove the copolymer byproducts; and forming a second gate metal over the etched first gate metal, wherein the etched first gate metal forms a first gate electrode for the bottom device, and the second gate metal forms a second gate electrode for the top device.

[0008] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer, wherein the dry etching generates free radicals that penetrate the copolymer byproducts to etch the first gate metal; performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process comprising a first wet cleaning using a first wet solution to remove a first component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove a second component of the copolymer byproducts; and forming a second gate metal over the etched-back first gate metal. Attached Figure Description

[0009] Various aspects of the embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of this disclosure and should therefore not be considered limiting, as the embodiments of this disclosure are equally well applicable to other embodiments. Furthermore, the drawings may implicitly describe components not explicitly described in the detailed description.

[0010] Figures 1A to 1B A flowchart of a method for forming a stacked semiconductor device (e.g., a CFET device) according to embodiments of the present disclosure is shown in part or in whole.

[0011] Figures 2 to 9 The illustration shows an intermediate stage of manufacturing according to an embodiment of the present disclosure and according to Figures 1A to 1B A cross-sectional view of a stacked semiconductor device (e.g., a CFET device) processed by the method.

[0012] Figure 10 A flowchart of part or all of a method for metal gate etchback in a stacked semiconductor device (e.g., a CFET device) according to embodiments of the present disclosure is shown.

[0013] Figure 11 It shows in Figures 1A to 1B The method is followed by a top view of a semiconductor workpiece with lines A-A', B-B', and C-C' cut across the workpiece.

[0014] Figure 12A , Figure 13A , Figure 14A and Figure 15A The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut line A-A' in the middle and according to Figure 10 A cross-sectional view of a stacked semiconductor device processed by the method.

[0015] Figure 12B , Figure 13B , Figure 14B and Figure 15B The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut line B-B' in the middle and according to Figure 10 A cross-sectional view of a stacked semiconductor device processed by the method.

[0016] Figure 12C , Figure 13C , Figure 14C and Figure 15C The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut the line C-C' in the middle and according to Figure 10 A cross-sectional view of a stacked semiconductor device processed by the method.

[0017] Figure 16 A flowchart of part or all of a method for metal gate etchback in a stacked semiconductor device (e.g., a CFET device) according to another embodiment of the present disclosure is shown.

[0018] Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut line A-A' in the middle and according to Figure 16 A cross-sectional view of a stacked semiconductor device processed by the method.

[0019] Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut line B-B' in the middle and according to Figure 16 A cross-sectional view of a stacked semiconductor device processed by the method.

[0020] Figure 17C , Figure 18C , Figure 19C , Figure 20C and Figure 21C The following diagram illustrates the intermediate stages of manufacturing according to embodiments of the present disclosure. Figure 11 Cut the line C-C' in the middle and according to Figure 16 A cross-sectional view of a stacked semiconductor device processed by the method.

[0021] Figure 22 A manufacturing process including etch-back and post-cleaning processes according to embodiments of the present disclosure is illustrated.

[0022] Figures 23 to 24 Details of the post-cleaning process according to embodiments of the present disclosure are shown. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] Furthermore, when using terms such as "about," "approximately," or "substantially" to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range of the described value (such as within + / - 10% of the described value) or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" could encompass a size range from 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 10%. And when comparing the size or dimensions of a component with another component, phrases such as "substantially the same," "substantially identical," or "similar in size" can be understood as being within + / - 10% of the compared components. Additionally, the disclosed dimensions of different components may implicitly disclose size ratios between the different components.

[0026] This disclosure addresses various problems present in metal gate etch-back processes. Metal gate etch-back is typically implemented using Cl2 / BCl3 plasma etching with boron-containing polymers to protect metal seams (or metal voids). However, BCl3 etches the exposed high-k gate dielectric, and the Cl2 / BCl3 plasma has higher energy and weaker penetration. Therefore, metal gate etch-back does not achieve good selectivity for the underlying high-k material and metal seams. High-k gate dielectric losses also make these processes unsuitable for metal gate etch-back in CFETs or other stacked transistor devices.

[0027] For this and other reasons, embodiments of this disclosure provide a highly selective metal gate etch-back process to prevent damage to the exposed high-k gate dielectric layer. The etch-back process includes generating removable polymer byproducts to insert into metal seams and to protect the surface of the high-k gate dielectric layer. The etch-back process also includes (or subsequently) a post-cleaning process to selectively remove the polymer byproducts without damaging the high-k gate dielectric layer. The etch-back process may include using materials composed of Cl2 / SiCl4 / O2 or Cl... x / Si x Cl y / O x / CO x The free radicals formed perform dry etching. Dry etching generates heavy and removable oxide polymers (e.g., SiO₂). x This allows for insertion of the metal seam within the metal gate and coverage of the exposed surface of the high-k gate dielectric. This results in high selectivity for both the high-k content and the metal seam during metal etching. Removable oxide polymers are byproducts of the etching process and may include Si. x Ti y O zCopolymers (e.g., when the metal gate includes titanium). After etch-back, a wet cleaning process is performed. Wet cleaning may include applying NH4OH to remove the SiO component from the byproducts and applying HCl to remove the TiO component from the byproducts, thereby ensuring precise and complete polymer removal without damaging high-k materials or metal seams. This etch-back process is suitable for forming the gates of stacked devices (e.g., CFETs) because etch-back is selective to the gate metal and does not damage exposed gate dielectrics or other gate layers.

[0028] This disclosure describes a stacked semiconductor device, such as a CFET semiconductor device having vertically stacked NFETs and PFETs. However, this disclosure is applicable to any combination of stacked semiconductor devices, including an NFET stacked on top of a PFET, a PFET stacked on top of an NFET, an NFET stacked on top of an NFET, and a PFET stacked on top of a PFET.

[0029] Figures 1A to 1B A flowchart of part or all of a method 1000 for forming a stacked semiconductor device (e.g., CFET device 100) according to embodiments of the present disclosure is shown. Device 100 may be part of an integrated circuit (IC) chip, a system-on-a-chip (SoC), or a portion thereof, comprising a variety of passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device includes non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0030] Figures 2 to 9 The illustration shows an intermediate stage of manufacturing according to an embodiment of the present disclosure and according to Figures 1A to 1B A cross-sectional view of a stacked semiconductor device (e.g., CFET device 100) processed by method 1000. See below for reference. Figures 2 to 9 Description method 1000.

[0031] refer to Figure 2In method 1000, operation 1002 receives or provides a workpiece having a substrate 102 and a semiconductor stack 104 having staggered first semiconductor layers 104a and second semiconductor layers 104b above the substrate 102. The substrate 102 may be a silicon (Si) substrate or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), or diamond. The semiconductor stack 104 may also be referred to as an active region (or finned active region) that protrudes from the substrate 102 and extends longitudinally in the x-direction. Although not shown, additional semiconductor stacks 104 may be formed parallel to the y-direction, and the semiconductor stacks 104 may be constructed using structures such as shallow trench isolation (STI) (e.g., see...). Figure 12B and Figure 12C The isolation structures of the STI structure 206 in the middle are separated from each other.

[0032] The first semiconductor layer 104a has a different material composition than the second semiconductor layer 104b to achieve etch selectivity. For example, each of the first semiconductor layers 104a is made of silicon-germanium, and each of the second semiconductor layers 104b is made of silicon. It should be noted that the first semiconductor layer 104a includes an intermediate layer 107 having a different concentration composition than the remainder of the first semiconductor layer 104a. For example, the intermediate layer 107 is made of silicon-germanium, but has a higher germanium concentration than the remainder of the first semiconductor layer 104a. In a further embodiment of the example, the first semiconductor layer 104a is a SiGe layer having a germanium concentration ranging from 20% to 25% (atomic percentage), and the intermediate layer 107 is a silicon-germanium layer having a germanium concentration greater than 30% (atomic percentage), such as ranging from 40% to 60%. This allows for selective etching of the intermediate layer 107 in a later process step, where the intermediate layer 107 is replaced with a channel isolation layer to separate the top device of the CFET device 100 from the bottom device. It should be noted that the intermediate layer 107 does not necessarily have to be located exactly in the middle separating the top and bottom devices. This layer can be closer to the top or bottom of the stack, and therefore, the bottom device may have more or fewer semiconductor channels than the top device. Figure 2 In the illustrated embodiment, the first semiconductor layer 104a comprises a first material (i.e., germanium), the second semiconductor layer 104b comprises a second material (i.e., silicon), and the intermediate layer 107 of the first semiconductor layer 104a has a higher concentration of the first material (i.e., germanium) than the rest of the first semiconductor layer 104a. The second semiconductor layer 104b may have the same material composition as the substrate 102.

[0033] Still referencing Figure 2In method 1000, in operation 1004, a dummy gate structure 110 is formed over a channel region CR of a semiconductor stack 104. The channel region CR includes channel regions 102a-102d, which are part of a substrate 102. The dummy gate structure 110 defines respective CFET gate regions 108. For example, the CFET gate regions may include CFET gate regions 108a, 108b, 108c, and 108d. Each of the dummy gate structures 110 includes a dummy gate stack 109 and a gate spacer 111 above the sidewalls of the dummy gate stack 109. The dummy gate stack 109 may be made of polysilicon, and the gate spacer 111 may be made of silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.

[0034] Still referencing Figure 2 In method 1000, in operation 1006, a source / drain (S / D) trench 519 is formed in the source / drain (S / D) region SDR adjacent to the channel region CR, thereby exposing the sides of the semiconductor stack 104. The S / D trench 519 can be formed by a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include an optional etchant to remove the first semiconductor layer 104a and semiconductor layer 104b individually and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor stack 104 while minimally (or not at all) etching the dummy gate structure 110 (i.e., the dummy gate stack 109 and the gate spacer 111). In some embodiments, a photolithography process is performed to form a patterned mask layer covering portions of the dummy gate structure 110 and / or the isolation structure located between the semiconductor stacks 104, and the etching process uses the patterned mask layer as an etching mask when forming the S / D trench 519. It should be noted that the etching process can also slightly etch into the substrate 102. That is, when forming the S / D trench 519, the substrate 102 can be recessed to form protrusions defining the channel regions 102a, 102b, 102c and 102d.

[0035] Now for reference Figure 3In method 1000, in operation 1008, internal spacers 116 are formed in the channel region CR along the sidewalls of the first semiconductor layer 104a using any suitable process. For example, a side etching process is first performed to selectively etch the sidewalls of the first semiconductor layer 104a without etching (or substantially etching) the second semiconductor layer 104b. In other words, the side etching process is configured to etch laterally (e.g., along the x-direction) the first semiconductor layer 104a, thereby reducing the length of the first semiconductor layer 104a along the x-direction. The side etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. After performing the side etching process, air gaps are formed beneath each of the second semiconductor layers 104b. Then, as... Figure 3 As shown, an inner spacer 116 is formed in each of the air gaps. The inner spacers 116 are disposed directly below the gate spacer 111, and they can be substantially perpendicularly aligned with the gate spacer 111 along the z-direction.

[0036] The internal spacer 116 can be formed by a spacer deposition process and a spacer etching process. For example, a spacer deposition process is performed to form a spacer layer over the dummy gate structure 110 and over the components defining the S / D trench 519 (e.g., semiconductor layers 104a, 104b, and substrate 102). The spacer deposition process can include processes such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. The spacer layer partially (and in some embodiments, completely) fills the S / D trench 519. The spacer deposition process is configured to ensure that the spacer layer fills the air gaps between the semiconductor layers 104b and between the semiconductor layers 104b and the corresponding channel regions 102a-102d below the gate spacer 111. A spacer etching process is then performed, which selectively etches the spacer layer to form, as shown in the image. Figure 3 The internal spacer 116 is depicted, while the semiconductor layer 104b, dummy gate stack 109, and gate spacer 111 are minimally (or not at all) etched. In the disclosed embodiments, the spacer etching process includes anisotropic etching, such as plasma etching. The spacer layer (and therefore the internal spacer 116) comprises a material different from the material of the semiconductor layer 104b and the gate spacer 111 to achieve desired etch selectivity during the gate spacer etching process. In some embodiments, the spacer layer comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride).

[0037] Now for reference Figure 4In method 1000, in operation 1010, a first S / D component 210 is epitaxially grown in an S / D trench 519 for a bottom transistor device of a CFET device 100. The bottom transistor device may be an NFET transistor device or a PFET transistor device. Therefore, the first source / drain component 210 may include an n-type source / drain component corresponding to an n-type transistor region or a p-type source / drain component corresponding to a p-type transistor region. The first source / drain component 210 may be formed by epitaxial processes using CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the substrate 102 and / or semiconductor stack 104 (particularly, semiconductor layer 104b). The epitaxial source / drain component is doped with n-type dopant and / or p-type dopant. In some embodiments, for an n-type CFET transistor, the first epitaxial source / drain component 210 comprises silicon and may be doped with phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a phosphorus-doped silicon-carbon-SiC:P epitaxial source / drain component). In some embodiments, for a p-type CFET transistor, the first epitaxial source / drain component 210 comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component). In the illustrated embodiment, the first S / D component 210 is a p-type S / D component for a PFET device.

[0038] Still referencing Figure 4 The first source / drain components 210 only partially fill the source / drain trench 519. Specifically, they are grown (or grown and recessed) in the z-direction to the height below the intermediate layer 107. That is, the first S / D components 210 are in direct contact with the semiconductor layer 104b for the bottom transistor device below the intermediate layer 107, but not with the semiconductor layer 104b above the intermediate layer 107. It should be noted that in some embodiments, as shown, the first S / D components 210 do not need to be in direct contact with all the semiconductor layers 104b below the intermediate layer 107.

[0039] Still referencing Figure 4In method 1000, an S / D isolation layer 113 is formed over the first S / D component 210 in operation 1012. This can be accomplished by first conformally depositing a dielectric pad, such as an etch stop layer 115, via CVD, ALD, or other suitable processes; and then depositing the S / D isolation layer 113 over the etch stop layer 115. An etching process can then be performed to recess the top surfaces of the S / D isolation layer 113 and the etch stop layer 115. In some embodiments, operation 1012 includes: depositing the etch stop layer 115 and the S / D isolation layer 113; performing chemical mechanical polishing (CMP); and etching to recess the deposited material. In some embodiments, operation 1012 may apply selective deposition. The etch stop layer 115 may include silicon nitride, and the S / D isolation layer 113 may include a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include silicon or polymer-based materials such as FSG, carbon-doped silicon oxide, and black... (Applied Materials, Santa Clara, California), dry gel, aerogel, amorphous fluorocarbon, parylene, BCB, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, or combinations thereof.

[0040] The S / D isolation layer 113 only partially fills the S / D trench 519 because a second S / D component 310 will be formed above the S / D isolation layer 113. However, although only partially filled, the S / D isolation layer 113 should be thick enough to isolate the first S / D component 210 from the second S / D component 310 formed later. Therefore, in some embodiments, as shown, the S / D isolation layer 113 (or etch stop layer 115) can directly contact the sidewalls of the second semiconductor layer 104b, thereby isolating them from contacting the first S / D component 210 or the second S / D component 310. The S / D isolation layer 113 has a portion horizontally aligned with the intermediate layer 107 in the x-direction. The S / D isolation layer 113 is separated from the intermediate layer 107 by an internal spacer 116. In an embodiment, the S / D isolation layer 113 has a thickness in the z-direction greater than the thickness of the intermediate layer 107.

[0041] Now for reference Figure 5In method 1000, in operation 1014, a second S / D component 310 for a top transistor device of CFET device 100 is epitaxially grown in S / D trench 519 and over S / D isolation layer 113. The top transistor device may be an NFET transistor device or a PFET transistor device. Therefore, the second source / drain component 310 may include an n-type source / drain component corresponding to an n-type transistor region or a p-type source / drain component corresponding to a p-type transistor region. The second source / drain component 310 may be formed by epitaxial processes using CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the semiconductor stack 104 (particularly, semiconductor layer 104b). The epitaxial source / drain component is doped with n-type dopant and / or p-type dopant. In some embodiments, for an n-type CFET transistor, the second epitaxial source / drain component 310 comprises silicon and may be doped with phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a phosphorus-doped silicon-carbon-SiC:P epitaxial source / drain component). In some embodiments, for a p-type CFET transistor, the second epitaxial source / drain component 310 comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component). In the illustrated embodiment, the second S / D component 310 is an n-type S / D component for an NFET device.

[0042] Still referencing Figure 5 The second S / D component 310 can completely fill the S / D trench 519, such that the top surface of the second S / D component 310 is substantially coplanar with the top surface of the topmost second semiconductor layer 104b. Optionally, the second S / D component 310 can be grown on the top surface of the topmost second semiconductor layer 104b. It should be noted that the second S / D component 310 is in direct contact with the semiconductor layer 104b for the top transistor device above the intermediate layer 107, but not in direct contact with the semiconductor layer 104b below the intermediate layer 107. It should be noted that in some embodiments, as shown, the second S / D component 310 does not need to be in direct contact with all the semiconductor layers 104b above the intermediate layer 107.

[0043] Still referencing Figure 5In method 1000, an interlayer dielectric (ILD) layer 413 is formed over the second S / D component 310 in operation 1016. This can be accomplished by first conformally depositing a dielectric pad, such as an etch stop layer 415, via CVD, ALD, or other suitable processes; and then depositing the ILD layer 413 over the etch stop layer 415. A planarization process, such as CMP, can then be performed to planarize the top surfaces of the ILD layer 413, the etch stop layer 415, and the dummy gate structure 110. The etch stop layer 415 may include silicon nitride, and the ILD layer 413 may include a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include silicon or polymer-based materials, such as FSG, carbon-doped silicon oxide, black... (Applied Materials, Santa Clara, California), dry gel, aerogel, amorphous fluorocarbon, parylene, BCB, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, or combinations thereof.

[0044] Now for reference Figure 6 In method 1000, dummy gate stack 109 is removed from dummy gate structure 110 in operation 1018. The dummy gate stack 109 is removed by a suitable etching process, thereby creating a gate trench 619 and exposing semiconductor stack 104. The etching process is designed to selectively remove the dummy gate stack 109 with an etchant. In the depicted embodiment, the etching process completely removes the dummy gate stack 109 to expose the surfaces of semiconductor layers 104a and 104b in the xz plane. The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may include optional etchants to individually remove individual layers of the dummy gate stack 109, such as the dummy gate electrode layer, the dummy gate dielectric layer, and / or the hard mask layer. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 109 while minimally (or not at all) etching other components of the device 100, such as the ILD layer 413, gate spacer 111, semiconductor layer 104a, and semiconductor layer 104b. In some embodiments, a photolithography process is performed to form a patterned mask layer covering the ILD layer 413 and / or the gate spacer 111, and the etching process uses the patterned mask layer as an etching mask.

[0045] Still referencing Figure 6In method 1000, in operation 1020, the intermediate layer 107 is removed and replaced with a channel isolation layer 513. The intermediate layer 107 is removed by a suitable etching process. The etching process is designed to selectively remove the intermediate layer 107 with an etchant. As described above, the intermediate layer 107 has a different material concentration, such as a heavier germanium concentration than the other first semiconductor layers 104a (which also include germanium). This allows for selective etching of the intermediate layer 107 without etching the remaining semiconductor layers 104a. The remaining air gaps are then filled with a dielectric material to form the channel isolation layer 513. The channel isolation layer 513 may include a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the channel isolation layer 513 comprises a low-k dielectric material. For example, the channel isolation layer 513 may include oxide derivatives, such as fluorine-doped oxides, carbon-doped oxides, and / or hydrogen-doped oxides. In another example, the channel isolation layer 513 may comprise a porous oxide, such as a dry gel / aerogel. In another example, the channel isolation layer 513 may comprise an organic material, such as polyimide, Teflon / PTFE, and / or other polymers. In some embodiments, the formation of the channel isolation layer 513 includes etching, deposition, and anisotropic etching, such as plasma etching.

[0046] Now for reference Figure 7 In operation 1022, method 1000 forms suspended semiconductor channels 202 / 302 by removing the remaining first semiconductor layer 104a using a suitable etching process. The etching process is designed to selectively remove the remaining first semiconductor layer 104a with an etchant, while substantially not etching the second semiconductor layer 104b and the channel isolation layer 513. Therefore, the second semiconductor layer 104b becomes the suspended semiconductor channels 202 / 302. Suspended semiconductor channel 202 refers to the channel layer 202 for the bottom transistor device (e.g., the PFET channel of CFET device 100), and suspended semiconductor channel 302 refers to the channel layer 302 for the top transistor device (e.g., the NFET channel of CFET device 100).

[0047] Regarding the selective etching of the intermediate layer 107 and the first semiconductor layer 104a, various etching parameters, such as etchant composition, etching temperature, etchant solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof, can be adjusted. For example, an etchant is selected to etch the material of the intermediate layer 107 (e.g., the highest germanium concentration) at a higher rate than the remaining semiconductor layer 104a (e.g., the intermediate germanium concentration). And an etchant is selected for the etching process that etches the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a (e.g., the semiconductor layer 104a ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ()))").)"). This is done in some embodiments.)]) The ratio of fluorine-containing gas to oxygen-containing gas (e.g., O2), etch temperature, and / or RF power)" in some embodiments can be adjusted to selectively etch silicon-germanium (or silicon)). In some embodiments, a wet etching process is performed using an etching solution comprising ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the germanium-containing semiconductor layer. In some embodiments, a chemical vapor deposition (CVD) etching process using hydrochloric acid (HCl) is used.

[0048] Now for reference Figure 8 In operation 1024, method 1000 forms a gate dielectric layer 204 / 304 over each of the suspended semiconductor channels 202 / 302 above the channel regions 102a-102d. The gate dielectric layer 204 / 304 partially fills the gap between the suspended semiconductor channels 202 / 302 and may include a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO. xThe high-k dielectric materials used are ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. The gate dielectric layer 204 / 304 can be formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In an embodiment, an interface layer 203 / 303 is formed on the channel layer 202 / 302 prior to the formation of the gate dielectric layer 204 / 304. The interface layer 203 / 303 can be formed by thermal oxidation, chemical oxidation, ALD, CVD, or other suitable processes. Interface layer 203 / 303 may include dielectric materials such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof.

[0049] Still referencing Figure 8 The CFET gate region 108 is divided into a gate region 208 below the channel isolation layer 513 and a gate region 308 above the channel isolation layer 513. For descriptive purposes, gate region 208 is described as a PFET gate region 208, and gate region 308 is described as an NFET gate region 308. Therefore, the NFET gate region 308 is vertically located above the PFET gate region 208, such that the NFET device is formed above the PFET device. However, the embodiments disclosed herein are not limited thereto. In other embodiments, the PFET gate region 208 may be located above the NFET gate region 308, such that the PFET device is formed above the NFET device.

[0050] Still referencing Figure 8 The PFET gate region 208 includes an interface layer 203 directly located on the top and bottom surfaces of the channel layer 202. The PFET gate region also includes a gate dielectric layer 204 directly located on the top and bottom surfaces of the interface layer 203 and on the sides of the internal spacer 116. The NFET gate region 308 includes an interface layer 303 directly located on the top and bottom surfaces of the channel layer 302. The NFET gate region 308 also includes a gate dielectric layer 304 directly located on the top and bottom surfaces of the interface layer 303 and on the sides of the internal spacer 116 (and / or gate spacer 111).

[0051] Now for reference Figure 9In method 1000, in operation 1026, gate metal 120 (also referred to as a metal gate electrode or gate stack) is deposited over the first plurality of gate dielectric layers 204 and the second plurality of gate dielectric layers 304 to form corresponding CFET metal gate structures 508a, 508b, 508c, and 508d. It should be noted that the gate metal 120 is not strictly limited to containing only metal; it can encompass metal alloys, cermets, or any suitable conductive material. For example, the gate metal 120 may include Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, or any suitable material. In this embodiment, gate metal 120 (e.g., TiN) is deposited over the PFET gate region 208 and the NFET gate region 308. The gate metal 120 is then etched back or recessed to expose the NFET gate region 308. Then, another gate metal 120 (e.g., Ti) is deposited over the exposed NFET gate region 308. This allows for the selective formation of different gate electrodes for the bottom and top devices of the CFET device 100.

[0052] Gate metal 120 may include a capping layer, a work function metal layer, and a fill metal layer. The capping layer may include titanium nitride, tantalum nitride, or other suitable materials formed by a suitable deposition technique such as ALD. The fill metal layer may include aluminum, copper, silicides, suitable other metals, or metal alloys deposited by physical vapor deposition (PVD) or other suitable deposition techniques.

[0053] A power-function metal layer comprises a conductive layer of metal or metal alloy having an appropriate power function, thereby enhancing the performance of the corresponding FET for its device. The power-function (WF) metal layer differs for PFETs and NFETs, referred to as n-type WF metal and p-type WF metal, respectively. The choice of WF metal depends on the FET to be formed on the active region. For example, an n-type WF metal is a metal with a first power function, thereby reducing the threshold voltage of the associated NFET. For example, an n-type WF metal has a power function of about 4.2 eV or less. A p-type WF metal is a metal with a second power function, thereby reducing the threshold voltage of the associated PFET. For example, a p-type power-function metal has a WF of about 5.2 eV or higher. An n-type WF metal can include metals with a sufficiently low effective power function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. A p-type WF metal can include metals with a sufficiently large effective power function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof.

[0054] In some embodiments, the fill metal itself is n-type and p-type dedicated, except for the use of work function metals to adjust the respective n-type and p-type FETs. For example, a p-type gate metal 120 (which may include a p-type work function or fill metal) is deposited over the PFET gate region 208. The p-type gate metal 120 surrounds the channel 202. After gate etch-back, an n-type gate metal 120 (which may include an n-type work function or fill metal) is then deposited over the NFET gate region 308. The n-type gate metal 120 surrounds the channel 302. It should be noted that when the PFET gate region 208 and the NFET gate region 308 are flipped, the corresponding p-type and n-type gate metals 120 are also flipped accordingly.

[0055] Additional operations may be provided before, during, and after method 1000, and some of the described operations may be moved, replaced, or eliminated for additional embodiments of method 1000. Additional operations may include forming device-level contacts that connect to the metal gates of the S / D components 210 / 310 and / or the CFET metal gate structures 508a-508d. Additional operations may also include forming interconnect structures over the device-level contacts. The interconnect structures may include one or more interconnect layers having wires and vias embedded in a dielectric layer. One or more interconnect layers connect the gate, source, and drain electrodes of various transistors, as well as other circuitry in device 100, to partially or wholly form an integrated circuit. Additional operations may also include forming a passivation layer over the interconnect layers.

[0056] In stacked semiconductor devices (e.g., CFET device 100), forming a double gate (one for the top device and one for the bottom device) requires a metal gate etch-back process to prepare for the deposition of the top metal gate electrode. Metal gate etch-back can damage the exposed top gate dielectric layer (e.g., gate dielectric layer 304 for the top device). This and other problems are addressed by the methods described below.

[0057] Figure 10 A flowchart of part or all of a method 1100 for metal gate etch-back in a stacked semiconductor device (e.g., CFET device 100) according to an embodiment of the present disclosure is shown. In the embodiment, the semiconductor device 100 is received at the beginning of method 1100 at the end (or near the end) of method 1000, and the received semiconductor device 100 is processed according to method 1100. Reference is made below. Figure 11 , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C and Figures 15A to 15CMethod 1100 is described. For clarity, the accompanying drawings have been simplified to better understand the inventive concept of the embodiments of this disclosure. Additional components may be added to the semiconductor device 100, and in other embodiments of the semiconductor device 100, some of the components described below may be replaced, modified, or eliminated.

[0058] Figure 11 It shows in Figures 1A to 1B A top view of a semiconductor workpiece following method 1000 and having lines A-A', B-B', and C-C' cut across the workpiece. The workpiece corresponds to the end of method 1000 (e.g., Figure 9 The semiconductor device 100 is a manufacturing stage following the stage (shown in the diagram) or method 1000. The workpiece includes components corresponding to... Figures 2 to 9 The region shown and described is region 500. (Example) Figure 11 As shown, the semiconductor device 100 may include other regions as part of a larger semiconductor structure constituting an IC circuit. In the illustrated embodiment, the semiconductor device 100 includes two active regions 704 extending longitudinally along the x-direction. Each of the active regions 704 may correspond to the previously processed and described semiconductor stack 104. The semiconductor device 100 includes four CFET metal gate structures 508 (e.g., CFET metal gate structures 508a-508d) extending longitudinally along the y-direction. The CFET metal gate structures 508 extend across the channel regions of the active regions 704 and enclose corresponding semiconductor channels 202 and 302 in the channel regions. Each active region 704 includes a first S / D component 210 and a second S / D component 310 adjacent to the channel region. In the illustrated embodiment, each of the metal gate structures 508 extends across two active regions 704. Laterally located between the active regions and between the CFET metal gate structures 508 is an ILD structure 713, which may include one or more ILD layers (e.g., S / D isolation layer 113 and ILD layer 413) and one or more etch stop layers (e.g., etch stop layers 115 and 415).

[0059] Still referencing Figure 11 Line A-A' is longitudinally cut along the active region 704 in the x-direction and across the two metal gate structures 508. Line B-B' is longitudinally cut in the x-direction parallel to line A-A' and across the isolation structure between the active regions 704. The isolation structure can be as follows: Figure 12B and Figure 12C The shallow trench isolation (STI) structure 206 shown is illustrated. Line C-C' is longitudinally cut along the metal gate structure 508 in the y-direction and across the channel regions of two of the active regions 704. Figure 12A , Figure 13A , Figure 14A and Figure 15A It shows the intermediate stage of manufacturing and according to Figure 10 Method 1100 is a cross-sectional view of a semiconductor device 100 cut along line A-A'. Figure 12B , Figure 13B , Figure 14B and Figure 15B It shows the intermediate stage of manufacturing and according to Figure 10 Method 1100 processes a cross-sectional view of a semiconductor device 100 cut along line B-B'. Figure 12C , Figure 13C , Figure 14C and Figure 15C It shows the intermediate stage of manufacturing and according to Figure 10 Method 1100 processes a cross-sectional view of a semiconductor device 100 cut along line C-C'. Figures 12A to 12C At the same stage of manufacturing, Figures 13A to 13C At the same stage of manufacturing, Figures 14A to 14C They are at the same stage of manufacturing, and Figures 15A to 15C They are at the same stage of manufacturing.

[0060] For ease of understanding, the method 1100 and its related figures have been renamed. Figures 2 to 9 Some of the components described herein. This is for the purpose of better describing the various components in the context of the top transistor disposed above the bottom transistor. Now as described below, the bottom transistor of semiconductor device 100 is referred to as a bottom semiconductor channel 202 comprising a bottom gate electrode 120a and an adjacent bottom S / D component 210. And the top transistor of semiconductor device 100 is referred to as a top semiconductor channel 302 comprising a top gate electrode 120b and an adjacent top S / D component 310. The S / D isolation layer 113 is referred to as a bottom ILD (BILD) layer 113, and the ILD layer 413 is referred to as a top ILD (TILD) layer 413.

[0061] Method 1100 may include the various operations described with respect to method 1000, thereby forming Figures 12A to 12C The structure shown. For example, it has been previously described with respect to method 1000. Figure 12A The various components shown are illustrated, and for the sake of brevity, some of the components will not be described further.

[0062] Now for joint reference Figures 12A to 12C In method 1100, in operation 1102, a stack of semiconductor channels is formed over a substrate 102, the stack including a top semiconductor channel 302 for a top transistor 315 and a bottom semiconductor channel 202 for a bottom transistor 215. The top transistor 315 and the bottom transistor 215 can be formed on... Figure 11 The active region 704 described in the text is located in or above it. For example... Figure 12A and Figure 12C As shown, the top semiconductor channel 302 and the bottom semiconductor channel 202 are separated by the previously described channel isolation layer 513.

[0063] exist Figure 12B and Figure 12C In the cross-sectional view, an isolation structure, such as a shallow trench isolation (STI) structure 206, is formed above the substrate 102. The STI structure 206 isolates adjacent active regions 704. Figure 12C As shown, an active region 704 is formed over the substrate 102 to protrude over the STI structure 206. The STI structure 206 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In an embodiment, the STI structure 206 includes an oxide-based dielectric, such as silicon oxide. Reference Figure 12B An ILD structure 713 is formed over an STI structure 206 between two metal gate structures 508. In an embodiment, the ILD structure 713 can be formed at the same time as the BILD layer 113. The difference is that the ILD structure 713 is not recessed like the BILD layer 113 because it is not located in the S / D region. The ILD structure 713 can be formed by: firstly conformally depositing a dielectric pad, such as an etch stop layer 715, between the metal gate structures 508 and over the STI structure 206 via CVD, ALD, or other suitable processes; and then depositing the ILD structure 713 over the etch stop layer 715. In an embodiment, the ILD structure 713 comprises the same or similar material as the BILD layer 113, and the etch stop layer 715 comprises the same or similar material as the etch stop layer 115. It should be noted that in Figure 12B In the cross-sectional view, the gate spacer 111 extends continuously from the top surface of the metal gate structure 508 to the top surface of the STI structure 206.

[0064] Still referencing Figures 12A to 12C In method 1100, in operation 1104, a high-k gate dielectric layer is formed enclosing each of the top semiconductor channel 302 and the bottom semiconductor channel 202. The high-k gate dielectric layer includes a top portion for forming the top gate dielectric layer 304 and a bottom portion for forming the bottom gate dielectric layer 204. It should be noted that in... Figure 12B In the cross-sectional view, the high-k gate dielectric layer (e.g., gate dielectric layer 204 / 304) also lined the sidewalls of the gate spacer 111. Operation 1104 may correspond to the previously described operation 1024.

[0065] Still referencing Figures 12A to 12CIn method 1100, in operation 1106, a first gate metal (shown as bottom gate electrode 120a) is deposited over a high-k gate dielectric layer (e.g., gate dielectric layer 204 / 304). The first gate metal encloses each of the top semiconductor channel 302 and the bottom semiconductor channel 202 and will be recessed in a later step to form the bottom gate electrode 120a. In an embodiment, the first gate metal comprises titanium nitride (TiN). Due to the high aspect ratio in the region above the STI structure 206, such as Figure 12B As shown, a metal void (or seam) 125 may be formed within the first gate metal. Although not shown, the metal void 125 may also exist in other regions of the device 100. Operation 1106 may correspond to the previously described operation 1026.

[0066] Now for joint reference Figures 13A to 13C In method 1100, in operation 1108, the first gate metal (shown as the bottom gate electrode 120a) is etched back to expose the top portion of the high-k gate dielectric layer (e.g., shown as the top gate dielectric layer 304). The etch-back leaves copolymer byproducts 305. The copolymer byproducts 305 cover the surface of the exposed top gate dielectric layer 304 and further insert into the metal voids 125. The etch-back intentionally generates copolymer byproducts 305 to serve as a protective layer during the etch-back process. Specifically, as the first gate metal is etched back, the generated copolymer byproducts 305 simultaneously cover and protect the exposed top gate dielectric layer 304 and the metal voids 125 from etchant damage.

[0067] Etching back includes using Cl2 / SiCl4 / O2 or Cl x / Si x Cl y / O x / CO x Dry etching that forms (or from) free radicals. In this embodiment, the back etching uses free radical etching (instead of plasma etching). Free radical etching uses neutral free radicals for etching and is generally isotropic, depending on the chemical reaction between the neuroradicals and the surface atoms of the etched material. On the other hand, plasma etching typically uses charged ions within a plasma for directional etching. In this case, free radical etching has an advantage over plasma etching due to greater penetration for deeper back etching. Furthermore, free radical etching incorporates neutral free radicals that are highly selective in etching the metal and avoiding gate dielectric damage.

[0068] Copolymer byproduct 305 (in part) is generated due to the silicon component of free radicals. In this embodiment, copolymer byproduct 305 comprises silicon and oxides (e.g., SiO₂). xThe heavy removable polymer. To facilitate dry etching, the etchback process also includes a dry rinse using chlorine (Cl2) and / or methane (CH4) gas to remove residual polymer from the top etched surface of the first gate metal. Dry etching and dry rinsing can be cycled until the etchback gate (e.g., metal gate structure 508) is etched back to the desired height. Figure 13C As shown, the desired height can be just enough to still cover the bottom gate dielectric layer 204 (i.e., coplanar with the top surface of the topmost bottom semiconductor channel 202). However, the desired height can be anywhere between the top and bottom surfaces of the channel isolation layer 513. Therefore, the etched-back first gate metal forms the bottom gate electrode 120a for the bottom transistor 215. Regarding... Figure 22 Additional details of the etchback operation 1108 are described.

[0069] Now for joint reference Figures 14A to 14C Method 1100 performs a post-cleaning process in operation 1110 to remove copolymer byproduct 305. The post-cleaning process is a wet cleaning process. The post-cleaning process includes a first wet cleaning using a first wet solution to remove the silicon oxide component of copolymer byproduct 305 and a second wet cleaning using a second wet solution to remove the metal oxide component of copolymer byproduct 305. In this embodiment, the first wet solution includes NH4OH, and the second wet solution includes HCl. The post-cleaning process is a cyclic process that recursively performs the first and second wet cleaning. In embodiments where the first gate metal (i.e., the bottom gate electrode 120a) comprises titanium, the wet cleaning process uses NH4OH radicals to remove silicon oxide components from the copolymer byproduct 305. x Ti y O z The copolymer byproducts remove SiO components, and HCl is used to remove SiO components. x Ti y O z Copolymer byproduct removal of TiO components. Two types of wet cleaning complement each other to achieve complete removal of copolymer byproduct 305. (e.g.) Figure 14B As shown, the post-cleaning process also removes portions of the copolymer byproduct 305 that have intercalated into the metal voids 125. Regarding Figures 22 to 24 Additional details about post-cleaning operation 1108 are described.

[0070] Now for joint reference Figures 15A to 15CIn method 1100, in operation 1112, a second gate metal (shown as a top gate electrode 120b) is deposited over an etched-back first gate metal (shown as a bottom gate electrode 120a). In an embodiment, the second gate metal comprises aluminum (Al). The second gate metal wraps around and is deposited over the exposed and cleaned top gate dielectric layer 304 for the top transistor 315. Thereafter, a planarization process such as CMP can be performed to planarize the top surfaces of the second gate metal, gate spacer 111, ILD layer 413, and ILD structure 713. Thus, the second gate metal forms the top gate electrode 120b for the top transistor 315. In an embodiment, the top gate electrode 120b comprises a different material than the bottom gate electrode 120a. In an embodiment where the top transistor 315 is a PFET and the bottom transistor 215 is an NFET, the top gate electrode 120b has a higher work function than the bottom gate electrode 120a. In an embodiment where the top transistor 315 is an NFET and the bottom transistor 215 is a PFET, the top gate electrode 120b has a lower work function than the bottom gate electrode 120a. In this embodiment, the top transistor 315 is an NFET and the bottom transistor is a PFET, wherein the top gate electrode 120b comprises an n-type work function metal (e.g., aluminum) and the bottom gate electrode 120a comprises a p-type work function metal (e.g., titanium nitride).

[0071] Figure 16 A flowchart of part or all of a method 1600 for metal gate etch-back in a stacked semiconductor device (e.g., CFET device 100) according to another embodiment of this disclosure is shown. Method 1600 is similar to method 1100; therefore, for the sake of brevity, some of the similar components will not be described again. The difference in method 1600 is the inclusion of a sacrificial capping layer 307. The sacrificial capping layer 307 provides further protection for the top dielectric layer 304 during the metal gate etch-back process. The sacrificial capping layer 307 is formed after the formation of the gate dielectric layers 202 / 302 and before the deposition of the first gate metal (e.g., the bottom gate electrode 120a). In this embodiment, the sacrificial capping layer 307 comprises aluminum oxide (AlO2). x (See below for reference) Figures 17A to 17C , Figures 18A to 18C , Figures 19A to 19C , Figures 20A to 20C and Figures 21A to 21C Method 1600 is described. For clarity, the accompanying drawings have been simplified to better understand the inventive concept of the embodiments of this disclosure. Additional components may be added to the semiconductor device 100, and in other embodiments of the semiconductor device 100, some of the components described below may be replaced, modified, or eliminated.

[0072] Common Reference Figures 17A to 17C In method 1600, in operation 1102, a stack of semiconductor channels is formed over a substrate 102. The stack includes a top semiconductor channel 302 for a top transistor 315 and a bottom semiconductor channel 202 for a bottom transistor 215. The top semiconductor channel 302 and the bottom semiconductor channel 202 are separated by a channel isolation layer 513 as previously described. The top transistor 315 and the bottom transistor 215 can be formed on... Figure 11 The active region 704 described above or in the diagram. Operation 1102 has already been described and will not be repeated for the sake of brevity.

[0073] Still referencing Figures 17A to 17C In method 1600, in operation 1104, each high-k gate dielectric layer enclosing the top semiconductor channel 302 and the bottom semiconductor channel 202 is formed. The high-k gate dielectric layer includes a top portion for forming the top gate dielectric layer 304 and a bottom portion for forming the bottom gate dielectric layer 204. Operation 1104 has been previously described and will not be repeated for the sake of brevity.

[0074] Still referencing Figures 17A to 17C In method 1600, a sacrificial capping layer 307 is selectively formed vertically between the top semiconductor channels 302 in operation 1105. The sacrificial capping layer 307 is specifically designed to protect the high-k gate dielectric material during the metal gate etch-back process. The sacrificial capping layer 307 can be formed by first depositing a capping layer encapsulating the high-k gate dielectric layer over the high-k gate dielectric layer (i.e., the top gate dielectric layer 304 / bottom gate dielectric layer 204). The capping layer completely fills the gap vertically located between the top semiconductor channel 302 and the bottom semiconductor channel 202. A selective etch process is then performed to etch away excess portions of the capping layer (e.g., side and top portions), such that only the portion of the capping layer vertically located between the semiconductor channels 302 / 202 remains. Another selective etch process is then performed to remove the portion of the capping layer vertically located between the bottom semiconductor channels 202. In other words, the capping layer in the bottom transistor 215 (e.g., below the channel isolation layer 513) is selectively etched away, so that the capping layer is only present in the top transistor 315 (e.g., above the channel isolation layer 513). The remaining portion of the capping layer forms a sacrificial capping layer 307. In this embodiment, the capping layer comprises aluminum oxide.

[0075] Now for reference Figures 18A to 18CIn method 1600, in operation 1106, a first gate metal (shown as bottom gate electrode 120a) is deposited over a high-k gate dielectric layer (e.g., gate dielectric layers 204 / 304). Due to the presence of the sacrificial capping layer 307, the first gate metal vertically wraps around each of the bottom semiconductor channels 202, but not around the top semiconductor channels 302. This is because the sacrificial capping layer 307 blocks the spacing that is vertically located between the top semiconductor channels 302. Figure 18C As shown, a first gate metal (shown as bottom gate electrode 120a) is vertically formed between the bottom semiconductor channels 202 and on the sidewalls of the sacrificial capping layer 307. In other respects, regarding... Figures 18A to 18C Operation 1106 is similar to Figures 12A to 12C .

[0076] Now for reference Figures 19A to 19C In method 1600, the first gate metal (shown as bottom gate electrode 120a) is etched back in operation 1108 to expose the top portion of the high-k gate dielectric layer (e.g., shown as top gate dielectric layer 304). As in method 1100, the etch-back leaves copolymer byproducts 305. It should be noted that in this case, the first gate metal is etched back, while the sacrificial capping layer 307 remains in place. The presence of the sacrificial capping layer 307 provides additional etchant protection for the top gate dielectric layer 304. In methods 1100 and 1600, the etchant used during operation 1108 is highly selective for etching the first gate metal and highly selective relative to etching the high-k gate dielectric layer (and other surrounding components). However, due to the thinness of the high-k gate dielectric layer, the risk of etchant damage still exists. Therefore, the sacrificial capping layer 307 provides additional buffering to avoid etchant damage. In other respects, regarding Figures 19A to 19C Operation 1108 is similar to Figures 13A to 13C .

[0077] Now for joint reference Figures 20A to 20C Method 1600 performs a post-cleaning process in operation 1110 to remove copolymer byproduct 305 and sacrificial capping layer 307. Operation 1110 in method 1600 is similar to the operation of method 1100, except that the sacrificial capping layer 307 is also removed in addition to the post-cleaning process. In this embodiment, the sacrificial capping layer 307 is first removed by a first removal process, and then the copolymer byproduct 305 is removed by a second removal process. The first removal process can be any suitable selective etching process for the sacrificial capping layer 307. The second removal process corresponds to the post-cleaning process described with respect to method 1100. During the first removal process, the copolymer byproduct 305 protects the top gate dielectric layer 304 from etchant damage. In other aspects, regarding Figures 20A to 20C Operation 1110 is similar to Figures 14A to 14C .

[0078] Now for joint reference Figures 21A to 21C In method 1600, a second gate metal (shown as the top gate electrode 120b) is deposited over the etched-back first gate metal (shown as the bottom gate electrode 120a) in operation 1112. Operation 1112 has already been described and will not be repeated for the sake of brevity.

[0079] Figure 22 A manufacturing process including etch-back and post-cleaning processes according to embodiments of the present disclosure is illustrated. The etch-back process corresponds to operation 1108 and includes dry etching 1108a and dry rinsing 1108b. The post-cleaning process corresponds to operation 1110 and includes a first wet cleaning 1110a using NH4OH and a second wet cleaning 1110b using HCl. The etch-back process has a first consecutive cycle of dry etching 1108a and dry rinsing 1108b, and the post-cleaning process has a second consecutive cycle of the first wet cleaning 1110a and the second wet cleaning 1110b. Additional details of the etch-back and post-cleaning processes are described below.

[0080] In the etch-back process (i.e., operation 1108), dry etching 1108a applies plasma over CFET device 100. Dry etching 1108a is configured to selectively etch the exposed first gate without substantially etching other components (e.g., gate spacer 111, ILD layer, etc.). This exposes the top gate dielectric layer 304 in the top transistor device 315. Various types of ion shielding can be used to filter ions in the plasma, leaving neutral radicals for radical etching. The neutral radicals form heavy polymer byproducts (e.g., copolymer byproduct 305 containing SiO2), which can be used to insert into the metal voids 125 described herein and to protect and cover the top gate dielectric layer 304. The plasma radicals used for etching penetrate (or pass through) the polymer byproducts to etch the metal and avoid damage to the high-k dielectric and metal voids. For example, the etched gate metal can be TiN. TiN is etched by applying plasma with radicals Cl2+SiCl4+O2. The result is TiCl4+SiO2+N2+Cl2, which will be cleaned later by a post-cleaning process. Following dry etching 1108a, dry rinsing 1108b applies a different plasma over the CFET device 100, selectively removing polymer byproducts (e.g., copolymer byproduct 305) generated on the top surface of the first gate metal. This allows subsequent cycles of dry etching 1108a with radical Cl2 / SiCl4 to proceed efficiently, ensuring the continuity of the etching process. In some embodiments, dry rinsing 1108b also partially removes polymer byproducts (e.g., copolymer byproduct 305) on the high-k dielectric to avoid over-accumulation. Dry rinsing 1108b may apply chlorine (Cl2) and / or methane (CH4). The Cl2 in dry etching 1108a focuses on metal etching, while the Cl2 in dry rinsing 1108b focuses on Si-O bond dissociation. As previously shown and described, the etch-back process continues its first consecutive cycle until the desired gate height for the bottom transistor 215 is achieved.

[0081] Following the first consecutive etch-back cycle, a second consecutive post-clean cycle (i.e., operation 1110) begins. The post-cleaning process is a wet clean using NH4OH to remove oxide-containing byproducts (i.e., first wet clean 1110a) and HCl to remove metal-containing polymers (i.e., second wet clean 1110b). Therefore, all generated polymer byproducts (e.g., copolymer byproduct 305) are cleanly removed without high-k gate dielectric and metal damage, thus maintaining a stable threshold voltage and preventing device offset. Regarding Figures 23 to 24 Additional details about post-cleaning (i.e., operation 1110) are described.

[0082] Figure 23 A flowchart of the post-cleaning process (i.e., operation 1110) is provided. Figure 24 The chemical formulas involved in the post-cleaning process are provided. First, after dry etching the metal gate to the desired etch-back depth (e.g., operation 1108), Si... x Ti y O z Byproducts (e.g., copolymer byproduct 305) are retained. Subsequently, cyclic wet cleaning is performed at temperatures between 40 and 80 degrees Celsius. If the temperature is too low (e.g., below about 40 degrees Celsius), the residue of the corresponding target material may not be completely removed; while if the temperature is too high (e.g., above about 80 degrees Celsius), any benefits may outweigh the processing costs. The cyclic process removes SiO₂ separately by applying NH₄OH and HCl. x and TiO x In an embodiment, the first wet cleaning 1110a includes NH4OH cleaning—according to Figure 24 Reaction equations 1 and 2, NH4OH with Si x Ti y O z The copolymerization reaction selectively removes the SiO component, leaving Si x Ti y O z The TiO component of the byproduct. In an example, the second wet cleaning 1110b includes HCl cleaning—HCl reacts with the remaining TiO component, according to... Figure 24 Reactions 3 and 4 selectively remove it, leaving Si. x Ti y O z The byproduct SiO component, where the cyclic cleaning cycle begins again. In other words, the cleaning in the first wet clean 1110a exposes the TiO component, which is cleaned by step 2. The cleaning in the second wet clean 1110b exposes the SiO component, which is cleaned again by the first wet clean 1110a and exposes more TiO component, and so on. In this way, each of the first wet clean 1110a and the second wet clean 1110b prepares a suitable cleaning surface for the subsequent repeated steps. When Si is completely decomposed and removed... x Ti y O z During copolymerization, the cyclic cleaning cycle ends. The first wet cleaning 1110a and the second wet cleaning 1110b can be adjusted independently, with varying cycle times and concentrations for the target cleaning. By targeting silicon oxide and metal oxide components individually, Si... x Ti y O z The copolymer is more easily decomposed for complete removal. Furthermore, by removing the copolymer layer by layer in a cyclic process, damage to the underlying high-k gate dielectric is avoided.

[0083] While titanium nitride (TiN) has been described as an etched gate material, this disclosure is not limited thereto. This disclosure is also applicable to gate materials made of other metals or conductive materials. In any case, regardless of the metal or conductive material used, the etch-back process (i.e., operation 1108) selectively etches the gate metal and intentionally generates silicon oxide polymer byproducts to protect the exposed high-k gate dielectric layer and metal voids. Furthermore, the post-cleaning process (i.e., operation 1110) has a separate wet cleaning process to separately and cyclically remove the metal oxide and silicon oxide components of the polymer byproducts.

[0084] While not limiting, embodiments of this disclosure provide advantages for metal gate etchback. One exemplary advantage is the high selectivity between the high-k gate dielectric and the metal during metal gate etchback, preventing damage to the high-k gate dielectric. Another exemplary advantage is the intentional generation of silica copolymer byproducts to protect exposed high-k gate dielectric and metal voids from etching damage. Another exemplary advantage is the selective etching of gate metal by targeting only the gate metal with plasma radicals that penetrate the silica copolymer. Yet another exemplary advantage is the selective and complete removal of copolymer byproducts through cyclic wet cleaning without damaging the high-k gate dielectric.

[0085] One aspect of this disclosure relates to a method. The method includes: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer encompassing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer, while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer; and performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process including a first wet cleaning using a first wet solution to remove silicon oxide components of the copolymer byproducts and a second wet cleaning using a second wet solution to remove metal oxide components of the copolymer byproducts.

[0086] In one embodiment, dry etching includes applying Cl2 / SiCl4 radicals. In another embodiment, the first gate metal includes one or more metal seams, and the resulting copolymer byproduct is inserted into the metal seams. In yet another embodiment, the first gate metal comprises Ti, and the copolymer byproduct comprises Si. x Ti y O z In this embodiment, the post-cleaning process is a cyclical process that recursively performs the first wet cleaning and the second wet cleaning.

[0087] In one embodiment, the etching process further includes dry rinsing with chlorine and methane gases to remove residual polymer from the top etched surface of the first gate metal. In a further embodiment, dry etching and dry rinsing are performed cyclically until the first gate metal is etched back to the desired height.

[0088] In one embodiment, after a post-cleaning process, the method includes forming a second gate metal over a first gate metal that has been etched back.

[0089] In one embodiment, prior to forming the first gate metal, the method includes: selectively forming a capping layer vertically between top semiconductor channels, wherein the first gate metal is vertically formed between bottom semiconductor channels and on the sidewalls of the capping layer; etching back the first gate metal while the capping layer remains in place; and removing the capping layer after the etching back. In one embodiment, the capping layer comprises aluminum oxide.

[0090] Another aspect of this disclosure relates to a method. The method includes: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer encompassing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer, while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back leaves copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer and inserted into one or more metal voids in the first gate metal, wherein the copolymer byproducts include silicon oxide; performing a post-cleaning process to remove the copolymer byproducts; and forming a second gate metal over the etched-back first gate metal, wherein the etched-back first gate metal forms a first gate electrode for the bottom device, and the second gate metal forms a second gate electrode for the top device.

[0091] In an embodiment, the etch-back process includes cyclically performing dry etching and dry rinsing. Dry etching selectively etches the first gate metal without etching copolymer byproducts, and the copolymer byproducts protect the high-k gate dielectric layer and metal voids from etching. In an embodiment, dry rinsing uses chlorine gas, methane gas, or a combination thereof to remove residual polymer from the top etched surface of the first gate metal.

[0092] In one embodiment, the post-cleaning process includes a first wet cleaning using a first wet solution to remove the silica component of the copolymer byproduct and a second wet cleaning using a second wet solution to remove the metal oxide component of the copolymer byproduct. In another embodiment, the first wet solution comprises NH4OH, and the second wet solution comprises HCl. In yet another embodiment, the post-cleaning process is a cyclical process that recursively performs the first and second wet cleaning.

[0093] Another aspect of this disclosure relates to a method. The method includes: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer encompassing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer, while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer, wherein the dry etching generates free radicals that penetrate the copolymer byproducts to etch the first gate metal; performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process including a first wet cleaning using a first wet solution to remove a first component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove a second component of the copolymer byproducts; and forming a second gate metal over the etched-back first gate metal.

[0094] In the embodiments, the free radicals of dry etching include Cl2, SiCl4, O2, or combinations thereof, the copolymer byproducts include silicon and oxygen, and the first wet solution includes NH4OH and the second wet solution includes HCl.

[0095] In one embodiment, the back etching also includes dry rinsing with chlorine or methane gas to remove residual polymer from the top etched surface of the first gate metal.

[0096] In this embodiment, the post-cleaning process is carried out at a cyclic temperature between 40 and 80 degrees Celsius.

[0097] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back comprises dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer; and performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process comprising a first wet cleaning using a first wet solution to remove silicon oxide components of the copolymer byproducts and a second wet cleaning using a second wet solution to remove metal oxide components of the copolymer byproducts.

[0098] In some embodiments, the dry etching includes applying Cl2 / SiCl4 radicals. In some embodiments, the first gate metal includes one or more metal seams, and the generated copolymer byproduct is inserted into the metal seams. In some embodiments, the first gate metal includes Ti, and the copolymer byproduct includes Si. x Ti y O z In some embodiments, the post-cleaning process is a cyclic process that recursively performs the first wet cleaning and the second wet cleaning. In some embodiments, the etchback further includes performing a dry rinse using chlorine and methane gases to remove residual polymers on the top etched surface of the first gate metal. In some embodiments, the dry etching and the dry rinse are performed cyclically until the first gate metal is etched back to a desired height. In some embodiments, the method further includes: forming a second gate metal over the etched-back first gate metal after the post-cleaning process. In some embodiments, the method further includes: selectively forming a capping layer vertically between the top semiconductor channels before forming the first gate metal, wherein the first gate metal is vertically formed between the bottom semiconductor channels and on the sidewalls of the capping layer; etching back the first gate metal while the capping layer remains in place; and removing the capping layer after the etchback. In some embodiments, the capping layer comprises aluminum oxide.

[0099] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back leaves copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer and inserted into one or more metal voids in the first gate metal, wherein the copolymer byproducts comprise silicon oxide; performing a post-cleaning process to remove the copolymer byproducts; and forming a second gate metal over the etched first gate metal, wherein the etched first gate metal forms a first gate electrode for the bottom device, and the second gate metal forms a second gate electrode for the top device.

[0100] In some embodiments, the etchback includes cyclically performing dry etching and dry rinsing, wherein the dry etching selectively etches the first gate metal without etching the copolymer byproducts, and the copolymer byproducts protect the high-k gate dielectric layer and the metal voids from etching. In some embodiments, the dry rinsing uses chlorine, methane, or a combination thereof to remove residual polymer from the top etched surface of the first gate metal. In some embodiments, the post-cleaning process includes a first wet cleaning using a first wet solution to remove the silicon oxide component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove the metal oxide component of the copolymer byproducts. In some embodiments, the first wet solution includes NH4OH, and the second wet solution includes HCl. In some embodiments, the post-cleaning process is a cyclic process that recursively performs the first wet cleaning and the second wet cleaning.

[0101] Some embodiments of this application provide a method of forming a semiconductor device, comprising: forming a top semiconductor channel for a top device over a bottom semiconductor channel for a bottom device; forming a high-k gate dielectric layer enclosing each of the top semiconductor channel and the bottom semiconductor channel; forming a first gate metal over the high-k gate dielectric layer; etching back the first gate metal to expose a top portion of the high-k gate dielectric layer while retaining a bottom portion of the high-k gate dielectric layer, wherein the etching back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer, wherein the dry etching generates free radicals that penetrate the copolymer byproducts to etch the first gate metal; performing a post-cleaning process to remove the copolymer byproducts, the post-cleaning process comprising a first wet cleaning using a first wet solution to remove a first component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove a second component of the copolymer byproducts; and forming a second gate metal over the etched-back first gate metal.

[0102] In some embodiments, the free radicals of the dry etching include Cl2, SiCl4, O2, or combinations thereof, wherein the copolymer byproducts include silicon and oxygen, wherein the first wet solution includes NH4OH, and the second wet solution includes HCl. In some embodiments, the etch-back further includes dry rinsing with chlorine or methane gas to remove residual polymers on the top etched surface of the first gate metal. In some embodiments, the post-cleaning process is performed at a cycling temperature between 40°C and 80°C.

[0103] Details of the methods and systems according to embodiments of this disclosure are illustrated in the accompanying drawings. Features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A top semiconductor channel for the top device is formed above the bottom semiconductor channel for the bottom device; A high-k gate dielectric layer is formed to enclose each of the top semiconductor channel and the bottom semiconductor channel; A first gate metal is formed above the high-k gate dielectric layer; The first gate metal is etched back to expose the top portion of the high-k gate dielectric layer, while the bottom portion of the high-k gate dielectric layer is retained. The etch back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer. as well as A post-cleaning process is performed to remove the copolymer byproducts. The post-cleaning process includes a first wet cleaning using a first wet solution to remove the silica component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove the metal oxide component of the copolymer byproducts.

2. The method according to claim 1, wherein, The dry etching involves applying Cl2 / SiCl4 free radicals.

3. The method according to claim 1, wherein, The first gate metal includes one or more metal seams, and the generated copolymer byproduct is inserted into the metal seams.

4. The method according to claim 1, wherein, The first gate metal comprises Ti, and the copolymer byproduct comprises Si. x Ti y O z .

5. The method according to claim 1, wherein, The post-cleaning process is a cyclical process that recursively performs the first wet cleaning and the second wet cleaning.

6. The method according to claim 1, wherein, The etchback also includes dry rinsing with chlorine and methane gases to remove residual polymer from the top etched surface of the first gate metal.

7. The method according to claim 6, wherein, The dry etching and dry rinsing are performed cyclically until the first gate metal is etched back to the desired height.

8. The method according to claim 1, further comprising: After the post-cleaning process, a second gate metal is formed over the etched-back first gate metal.

9. A method for forming a semiconductor device, comprising: A top semiconductor channel for the top device is formed above the bottom semiconductor channel for the bottom device; A high-k gate dielectric layer is formed to enclose each of the top semiconductor channel and the bottom semiconductor channel; A first gate metal is formed above the high-k gate dielectric layer; The first gate metal is etched back to expose the top portion of the high-k gate dielectric layer, while the bottom portion of the high-k gate dielectric layer is retained. The etch back leaves copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer and inserted into one or more metal voids in the first gate metal. The copolymer byproducts include silicon oxide. A post-cleaning process is performed to remove the copolymer byproducts; and A second gate metal is formed above the first gate metal that has been etched back. The first gate metal etched back forms a first gate electrode for the bottom device, and the second gate metal forms a second gate electrode for the top device.

10. A method of forming a semiconductor device, comprising: A top semiconductor channel for the top device is formed above the bottom semiconductor channel for the bottom device; A high-k gate dielectric layer is formed to enclose each of the top semiconductor channel and the bottom semiconductor channel; A first gate metal is formed above the high-k gate dielectric layer; The first gate metal is etched back to expose the top portion of the high-k gate dielectric layer, while the bottom portion of the high-k gate dielectric layer is retained. The etch back includes dry etching to etch the first gate metal and to generate copolymer byproducts covering the exposed top portion of the high-k gate dielectric layer. The dry etching generates free radicals that penetrate the copolymer byproducts to etch the first gate metal. A post-cleaning process is implemented to remove the copolymer byproducts, the post-cleaning process comprising a first wet cleaning using a first wet solution to remove a first component of the copolymer byproducts and a second wet cleaning using a second wet solution to remove a second component of the copolymer byproducts; and A second gate metal is formed above the first gate metal that has been etched back.

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