Display device

Abstract

Provided is a display device which can minimize a threshold voltage deviation of a thin film transistor according to a position in a display area by using a hydrogen degassing path. The display device may include: a display panel including a display area in which gate lines, data lines, and thin film transistors are arranged, and first and second bezel areas around the display area; a gate driving circuit disposed in at least one of the first bezel region and the second bezel region, and configured to drive a gate line; and a dummy hole disposed in the display area and at least one of the first bezel area and the second bezel area, wherein each of the gate lines includes a start end connected to the gate driving circuit in any one of the first and second bezel regions and a tail end in the other of the first and second bezel regions, and a density of the dummy holes differs according to a distance from the tail end of each of the gate lines.

Description

Display device

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0152428, filed in Korea on October 31, 2024, the entire contents of which are hereby expressly incorporated by reference. Technical Field

[0003] This disclosure relates to a display device having a hydrogen degassing path. Background Technology

[0004] Display devices include thin-film transistors as switching or driving elements.

[0005] Oxide semiconductor thin-film transistors (OSTs), which use oxide semiconductor materials as the active layer, are widely used in display devices. OSTs offer advantages such as higher mobility than amorphous silicon thin-film transistors (ASTs), lower manufacturing costs than polycrystalline silicon SSTs, and lower cutoff current.

[0006] Oxide semiconductor thin-film transistors are greatly affected by hydrogen flowing into the active layer, and their electrical characteristics, such as threshold voltage, can be altered.

[0007] In a display device, due to the structural difference between the starting end of the gate line of the gate driving circuit in one side bezel region and the ending end of the gate line of the non-gate driving circuit in the other side bezel region, the amount of hydrogen flowing in can increase towards the ending end compared to the starting end of the gate line.

[0008] Therefore, as the hydrogen inflow increases closer to the end of the gate line in a display device compared to the beginning, the threshold voltage of the thin-film transistor can shift in the negative direction. In a display device, a threshold voltage deviation in the thin-film transistor can occur due to the difference in the amount of hydrogen inflow based on the distance from the end of the gate line. Summary of the Invention

[0009] Therefore, this disclosure aims to provide a display device that substantially avoids one or more problems caused by the limitations and disadvantages of the prior art.

[0010] In one aspect, this disclosure provides a display device that minimizes the threshold voltage deviation of thin-film transistors based on their location within a display area by utilizing a hydrogen degassing path.

[0011] In another aspect, this disclosure provides a display device that can prevent the threshold voltage of a thin-film transistor from shifting in the negative direction in the display area by utilizing a hydrogen degassing path.

[0012] Other advantages and features of this disclosure will be set forth in part in the description which follows and will be apparent in part to those skilled in the art upon viewing the following, or may be learned from practice of this disclosure. The technical benefits and other advantages of this disclosure may be realized and obtained from the written description and its claims, as well as the structures specifically pointed out in the accompanying drawings.

[0013] To achieve these and other benefits and in accordance with the purposes of this disclosure, as embodied and broadly described herein, this disclosure provides a display device comprising: a display panel including a display area in which gate lines, data lines and thin-film transistors are disposed, and a first border area and a second border area surrounding the display area; a gate driving circuit disposed in at least one of the first border area and the second border area and configured to drive the gate lines; and virtual vias disposed in the display area and at least one of the first border area and the second border area, wherein each of the gate lines may include a start end located in either the first border area or the second border area and connected to the gate driving circuit, and an end end located in the other border area of ​​the first border area and the second border area, and the density of the virtual vias may vary depending on the distance from the end of each gate line.

[0014] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0016] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure;

[0017] Figure 2 is a diagram illustrating a single-feed driving method for a display device according to an embodiment of the present disclosure;

[0018] Figure 3 is a diagram illustrating an interlacing driving method for a display device according to an embodiment of the present disclosure;

[0019] Figure 4 is a graph illustrating the threshold voltage deviation of a thin-film transistor based on the distance between the start and end points of a gate line in a display device according to a comparative example of the related technology.

[0020] Figures 5A and 5B are graphs illustrating the voltage-current characteristic deviation of thin-film transistors adjacent to the start and end of the gate line in a display device according to a comparative example of the related art.

[0021] Figure 6 is a plan view of a portion of the display area adjacent to the end of the gate line in a display device according to an embodiment of the present disclosure.

[0022] Figure 7 is a cross-sectional view of a thin-film transistor taken along line I-I' shown in Figure 6.

[0023] Figures 8A and 8B are cross-sectional views of the virtual hole structure taken along lines II-II' and III-III' shown in Figure 6.

[0024] Figures 9A to 9F are cross-sectional views of the virtual hole structure taken along line IV-IV' shown in Figure 6;

[0025] Figure 10 is a graph illustrating the hydrogen-generated energy of each material used in a display device according to an embodiment of the present disclosure;

[0026] Figure 11 is a diagram illustrating the hydrogen diffusion path of a thin-film transistor in a display device according to an embodiment of the present disclosure;

[0027] Figure 12 is a diagram illustrating the hydrogen degassing path of a thin-film transistor according to an embodiment of the present disclosure;

[0028] Figure 13 is a plan view of a portion of the display area adjacent to the end of the gate line in a display device according to an embodiment of the present disclosure.

[0029] Figures 14A to 14F are cross-sectional views illustrating the passivation hole structure taken along lines V-V', VI-VI', VII-VII' and VIII-VIII' shown in Figure 13;

[0030] Figures 15A and 15B are plan views and cross-sectional views illustrating the thin-film transistor structure in the gate drive circuit of a display device according to an embodiment of the present disclosure.

[0031] Figure 16 is a plan view of a portion of the display area adjacent to the end of the gate line in a display device according to an embodiment of the present disclosure.

[0032] Figures 17A to 17C are cross-sectional views illustrating the virtual hole structure taken along line IX-IX' shown in Figure 16 and the passivated hole structure taken along line X-X'.

[0033] Figure 18 is a diagram illustrating the application structure of the difference in virtual aperture density in a display device according to an embodiment of the present disclosure;

[0034] Figures 19A to 19C are plan views of a portion of each of the first to third regions shown in Figure 18;

[0035] Figure 20A is a graph illustrating the voltage-current characteristics of a thin-film transistor in a display device according to a comparative example of the related art; Figures 20B and 20C are graphs illustrating the voltage-current characteristics of a thin-film transistor in a display device according to an embodiment of the present disclosure; and

[0036] Figures 21A and 21B are graphs illustrating the voltage-current characteristics of thin-film transistors based on the density of virtual holes in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0037] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and its scope will be fully conveyed to those skilled in the art.

[0038] The shapes, dimensions, scales, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. The same reference numerals always refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that they would unnecessarily obscure the focus of this disclosure.

[0039] When using the terms “comprising,” “having,” and “including” as described in this disclosure, other parts may exist unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0040] When interpreting an element, it is interpreted as including a range of errors, although there is no explicit description of it.

[0041] When describing positional relationships, for example, when the positional order is described as "above", "above", "below", "below", and "next to", situations where there is no contact between them may be included unless "exactly" or "directly" is used.

[0042] When it is mentioned that the first element is "above" the second element, it does not mean that the first element is substantially above the second element in the drawing. The upper and lower parts of the related objects can change depending on the orientation of the objects. Therefore, the case of the first element being "above" the second element includes the case where the first element is "below" the second element in the drawing or in the actual configuration, as well as the case where the first element is "above" the second element.

[0043] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “directly” is used.

[0044] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0045] It should be understood that the term "at least one" includes all combinations relating to any one of them. For example, "at least one of the first element, the second element, and the third element" can include two or more elements selected from the first element, the second element, and the third element, as well as all combinations of each of the first element, the second element, and the third element.

[0046] Features of various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may interoperate with each other in various ways and be technically driven. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0047] Hereinafter, aspects of this disclosure will be described with reference to the accompanying drawings. Since the dimensions of each element shown in the drawings differ from actual dimensions for ease of description, this disclosure is not limited to the dimensions shown. Furthermore, all components of each display device, display apparatus, and display panel according to all aspects of this disclosure are operatively combined and configured.

[0048] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure, Figure 2 is a diagram illustrating a single-feed driving method of a display device according to an embodiment of the present disclosure, and Figure 3 is a diagram illustrating an interlaced driving method of a display device according to an embodiment of the present disclosure.

[0049] Referring to FIG1, the display device 1000 may include a display panel 100, a gate driving circuit 200, a data driving circuit 300, a timing controller 400, a level shifter 500, etc., and the gate driving circuit 200 may be built into the display panel 100.

[0050] The display device 1000 according to the embodiment may be a liquid crystal display device, but is not limited thereto. The display device 200 according to the embodiment may be any one of various display devices, including electroluminescent display devices, micro light-emitting diode (LED) display devices, etc. The electroluminescent display device may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0051] The display panel 100 according to an embodiment may include a display area DA in which a plurality of sub-pixels SP are arranged in a matrix and a border area BZ located around the display area DA. The display panel 100 according to an embodiment may further include a touch sensor overlapping the display area DA to sense a user's touch.

[0052] The display area DA of the display panel 100 may include multiple pixels consisting of three or four color subpixels that emit light of different colors, thereby displaying an image. The subpixels may include red subpixels that emit red light, green subpixels that emit green light, and blue subpixels that emit blue light, and may further include white subpixels that emit white light.

[0053] The display panel 100 according to the embodiment may be a liquid crystal panel. The display panel 100 may include a first substrate and a second substrate bonded together with a liquid crystal layer sandwiched between them, and a polarizing plate attached to the outer side of each of the first and second substrates. On the first substrate of the display panel 100, thin-film transistors for sub-pixels, as well as various signal lines and electrodes including gate lines GL and data lines DL connected to the thin-film transistors and pixel electrodes, may be arranged, and a driving circuit including a gate driving circuit 200 may be arranged. A common electrode may be arranged on either the first substrate or the second substrate of the display panel 100. A black matrix and a color filter for the sub-pixels may be arranged on either the first substrate or the second substrate of the display panel 100.

[0054] In the display panel 100, sub-pixels can be independently driven by thin-film transistors connected to gate lines GL and data lines DL. Each sub-pixel can be charged with the voltage difference between the data signal provided to the pixel electrode through the thin-film transistor and the common voltage provided to the common electrode, and the liquid crystal is driven according to the charging voltage, thereby adjusting the transmittance of light transmitted from the backlight unit through the display panel 100 and the polarizer. Each sub-pixel can represent the grayscale level of the image by multiplying the brightness of the backlight unit by the transmittance controlled according to the data signal in each sub-pixel.

[0055] The display panel 100 can be driven in a twisted nematic (TN) mode or a vertical alignment (VA) mode by a vertical electric field applied to the liquid crystal layer through the pixel electrodes and the common electrode, in an in-plane switching (IPS) mode by a horizontal electric field applied to the liquid crystal layer through the pixel electrodes and the common electrode, or in an edge field switching (FFS) mode by an edge electric field applied to the liquid crystal layer through the pixel electrodes and the common electrode.

[0056] The plurality of thin-film transistors arranged in the display area DA and the frame area BZ including the gate driving circuit 200 of the display panel 100 may include at least one of amorphous silicon thin-film transistors, polycrystalline silicon thin-film transistors, or oxide semiconductor thin-film transistors. The display panel 100 according to an embodiment may include coplanar oxide semiconductor thin-film transistors.

[0057] The display panel 100 according to an embodiment may include: signal lines including gate lines GL and data lines DL; and / or hydrogen degassing paths (virtual vias, passivation vias) disposed on at least one insulating layer overlapping or adjacent to the thin-film transistor. The display panel 100 according to an embodiment may apply a density of hydrogen degassing paths disposed in the direction of the gate line GL according to the difference in distance from the end of the gate line GL. Therefore, the display panel 100 may minimize the difference in the amount of hydrogen inflow caused by structural differences between the start and end points of the gate line GL, thereby minimizing the threshold voltage deviation of the thin-film transistor and preventing the threshold voltage of the thin-film transistor from shifting to a negative voltage. This will be described in detail later.

[0058] The gate driving circuit 200 can be arranged in either of two bezel regions BZ facing each other with the display area DA between them, or it can be arranged in both bezel regions BZ. The gate driving circuit 200 can be built into a bezel region BZ of the panel gate in panel (GIP) type, which includes a thin-film transistor formed with the same process as the thin-film transistor in the display area DA.

[0059] The gate drive circuit 200 can operate by receiving multiple gate control signals from the timing controller 400 via the level shifter 500. The gate drive circuit 200 can receive multiple gate control signals from the timing controller 400. The gate drive circuit 200 can be controlled by the multiple gate control signals and can individually drive the gate lines GL of the display panel 100. The gate drive circuit 200 can output a scan signal of the gate on voltage to the corresponding gate line GL during the driving period of each gate line GL, and can output a gate off voltage to the corresponding gate line GL during the non-driving period of each gate line GL.

[0060] The level shifter 500 can generate multiple gate control signals by receiving control signals from the timing controller 400 and performing level shifting or logic processing on the control signals, and output the gate control signals to the gate drive circuit 200.

[0061] The data drive circuit 300 can convert digital data provided from the timing controller 400 along with data control signals into analog data signals, thereby supplying the data signals to the data lines DL of the display panel 100. The data drive circuit 300 can subdivide multiple reference gamma voltages provided from the gamma voltage generator, and can convert digital data into analog data voltages by using the subdivided gamma voltages.

[0062] The data driving circuit 300 may include at least one data driving integrated circuit (IC). The data driving IC may be packaged on the bezel area BZ of the display panel 100 or packaged on a circuit film, and thus electrically connected to the display panel 100.

[0063] The timing controller 400 can receive source image data and timing control signals from an external host system. The host system can be any system of a portable terminal such as a computer, TV system, set-top box, tablet computer, or mobile phone. Timing control signals may include point clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc.

[0064] The timing controller 400 can control the gate drive circuit 200 and the data drive circuit 300 using timing control signals provided from the host system and timing setting information stored therein. The timing controller 400 can generate multiple gate control signals for controlling the drive timing of the gate drive circuit 200 and output the generated gate control signals to the gate drive circuit 200. According to an embodiment, the timing controller 400 can generate control signals for timing control, such that the level shifter 500 can generate multiple gate control signals to supply the gate control signals to the gate drive circuit 200, and can output the control signals to the level shifter 500. The timing controller 400 can generate multiple data control signals for controlling the drive timing of the data drive circuit 300 and output the generated data control signals to the data drive circuit 300.

[0065] The timing controller 400 can perform various image processing operations, including brightness correction for reducing power consumption, using input image data, and can output the image-processed data to the data drive circuit 300. The timing controller 400 can arrange the image-processed data into a sub-pixel arrangement suitable for the display panel 100, and output the arranged data to the data drive circuit 300.

[0066] The gate drive circuit 200 according to the embodiment can supply the scan signal to both ends of each gate line GL in a dual-feed manner, or it can supply the scan signal to one start end of each gate line GL in a single-feed manner. The gate drive circuit 200 according to the embodiment can supply the scan signal to the start end of the gate lines GL driven separately by interlacing scanning in a single-feed manner.

[0067] Referring to FIG2, the gate drive circuit 200 according to the embodiment may include multiple stage circuits GIP1 to GIPn arranged in a bezel region BZ1 (first bezel region) of the display panel 100 and individually connected to multiple gate lines GL1 to GLn of the display region DA. The multiple stage circuits GIP1 to GIPn may sequentially supply scan signals to the start end of each of the gate lines GL1 to GLn in a single-feed manner. The end of each of the gate lines GL1 to GLn may be located in another bezel region BZ2 (second bezel region).

[0068] Referring to FIG3, the gate driving circuit according to the embodiment may include a first gate driving circuit 200a and a second gate driving circuit 200b separately arranged in bezel regions BZ1 and BZ2, which are separated by a display area DA, in the display panel 100a. The first gate driving circuit 200a arranged in the left bezel region BZ1 (first bezel region) may include a plurality of odd-numbered stage circuits GIP1, GIP3, ..., GIPn-1 individually connected to the starting ends of the odd-numbered gate lines GL1, GL3, ..., GLn-1. The second gate driving circuit 200b arranged in the right bezel region BZ2 (second bezel region) may include a plurality of even-numbered stage circuits GIP2, GIP4, ..., GIPn individually connected to the starting ends of the even-numbered gate lines GL2, GL4, ..., GLn. The end of each of the even-numbered gate lines GL2, GL4, ..., GLn may be located in the left bezel region BZ1 (first bezel region).

[0069] According to the embodiment, the stage circuits GIP1, GIP3, ... GIPn-1 of the first gate drive circuit 200a can sequentially supply scan signals to the left start end of each of the odd-numbered gate lines GL1, GL3, ... GLn-1 in a single-feed manner. According to the embodiment, the stage circuits GIP2, GIP4, ... GIPn of the second gate drive circuit 200b can sequentially supply scan signals to the right start end of each of the even-numbered gate lines GL2, GL4, ... GLn in a single-feed manner. The structural difference of each of the gate lines GL1 to GLn in the display panels 100 and 100a according to the embodiments may be that the starting end located in any one of the first border region BZ1 and the second border region BZ2 is connected to and in contact with any one of the gate driving circuits 200, 200a and 200b, while the ending end located in the other border region of the first border region BZ1 and the second border region BZ2 does not contact the gate driving circuits 200, 200a and 200b. The display panels 100 and 100a according to the embodiments may include a display area DA and virtual holes in the border regions BZ1 and BZ2 that overlap or are adjacent to thin-film transistors and / or signal lines to serve as hydrogen degassing paths, thereby increasing the hydrogen degassing effect. The density of virtual holes in the display panels 100 and 100a according to the embodiments may be applied according to the difference in distance from the end of each gate line GL.

[0070] Therefore, the display panel 100 according to the embodiment can prevent the threshold voltage of the thin film transistor from moving to a negative voltage, and minimize the threshold voltage deviation of the thin film transistor by minimizing the difference in hydrogen inflow caused by the structural difference between the start and end of each gate line GL.

[0071] Figure 4 is a graph illustrating the threshold voltage deviation of a thin-film transistor based on the distance between the start and end points of the gate line in a comparative example of a display device according to the related art. Figures 5A and 5B are graphs illustrating the voltage-current characteristic deviation of thin-film transistors adjacent to the start and end points of the gate line in a comparative example of a display device according to the related art.

[0072] Referring to FIG4, the display area DAa of the display device according to the comparative example can be driven in an interlaced manner, such that odd-numbered gate lines GLo can be driven by the left gate driving circuit 20a, and even-numbered gate lines GLe can be driven by the right gate driving circuit 20b. In the display device according to the comparative example, it should be noted that the threshold voltage Vth of the thin-film transistor shifts negatively from the start end GLo start to the end GLo end of the odd-numbered gate lines connected to the left gate driving circuit 20a. In the display device according to the comparative example, it should be noted that the threshold voltage Vth of the thin-film transistor shifts negatively from the start end GLe start to the end GLe end of the even-numbered gate lines connected to the right gate driving circuit 20b.

[0073] Referring to Figures 4 and 5A, in the display area DAa of the display device according to the prior art comparative example, it should be noted that the threshold voltage Vth of the thin-film transistor adjacent to the start ends GLo start and GLe start of each gate line of the contact gate drive circuits 20a and 20b is close to 0V.

[0074] Referring to Figures 4 and 5B, in the display area DAa of the display device according to the prior art, it should be noted that the thin-film transistors at the ends Glo end and GLe end of each gate line that do not contact the gate drive circuits 20a and 20b have increased hydrogen inflow, causing the threshold voltage Vth to shift excessively in the negative direction, resulting in the threshold voltage Vth of the thin-film transistor being different from the starting ends Glo start and GLe start.

[0075] That is, as shown in Figure 4, taking an odd-numbered gate line Glo as an example, the threshold voltage starts at approximately zero in the left bezel region (i.e., the region corresponding to the left gate drive circuit 20a) and then moves in the negative direction as the gate line crosses the display region DAa, eventually becoming -6V or less. Therefore, as shown, the threshold voltage changes significantly as the gate line crosses the display region DAa. As shown in Figure 4, from the middle of the display region to the right bezel region (i.e., the region corresponding to the right gate drive circuit 20b), the transistor's threshold voltage remains approximately -6.5V. This changing negative threshold voltage affects the transistor's characteristics (e.g., the threshold voltage itself). As shown in Figure 4, the effect is greatest as the gate line crosses the display region and extends to the right bezel region (e.g., between 6 inches and 13 inches in Figure 4). Furthermore, as shown in Figure 4, the threshold voltage changes significantly from 1 inch to 6 inches, and then stabilizes at -6.5V. This changing and varying threshold voltage negatively affects the transistor's operation.

[0076] To address this issue, display panels 100 and 100a according to embodiments of the present disclosure may include virtual holes serving as hydrogen degassing paths to enhance the hydrogen degassing effect. Display panels 100 and 100a according to embodiments of the present disclosure can minimize differences in hydrogen inflow by differentially applying the density of virtual holes based on their distance from the end of the gate line GL, thereby minimizing threshold voltage deviations of the thin-film transistors.

[0077] The following will describe in detail a display device having a hydrogen degassing path according to an embodiment of the present disclosure.

[0078] Figure 6 is a plan view of a portion of the display area adjacent to the end of the gate line in the display area of ​​a display device according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view of a thin-film transistor taken along line I-I' shown in Figure 6. Figures 8A and 8B are cross-sectional views of virtual hole structures taken along lines II-II' and III-III' shown in Figure 6. Figures 9A to 9F are cross-sectional views of virtual hole structures taken along line IV-IV' shown in Figure 6.

[0079] Referring to Figures 6 and 7, the display device according to the embodiment may include: gate lines GL: GL1 and GL(i+1), data line DL, thin-film transistor (TFT), common electrode VCOM, pixel electrode PXL, common voltage supply line VL, and a thin-film transistor substrate on which multiple insulating layers are disposed. The multiple insulating layers may include a buffer layer BF, a gate insulating layer GI, interlayer insulating layers ILD1 and ILD2, passivation layers PAS1 and PAS2, and a planarization layer PNL.

[0080] The gate line GL can be arranged in a first direction (horizontal or row direction), and the data line DL can be arranged in a second direction (vertical or column direction) and can intersect the gate line GL with an interlayer insulating layer ILD1 and ILD2 between them. The thin-film transistor TFT can be arranged adjacent to the intersection of the gate line GL and the data line DL and thus connected to the gate line GL and the data line DL, and can be connected to the pixel electrode PXL arranged in the pixel region.

[0081] A thin-film transistor (TFT) according to an embodiment may include: a light-shielding electrode LS on a substrate SUB; a buffer layer BF covering the light-shielding electrode LS; an active layer ACT on the buffer layer BF; a gate insulating layer GI and a gate electrode GE stacked on the active layer ACT; interlayer insulating layers ILD1 and ILD2 covering the gate electrode GE; and a first source-drain electrode SD1 and a second source-drain electrode SD2 disposed on the interlayer insulating layer ILD2 and connected to the active layer ACT through contact holes CH1 and CH2. The thin-film transistor TFT according to an embodiment may have a coplanar structure.

[0082] The light-shielding electrode LS can be arranged on the substrate SUB, and a buffer layer BF covering the light-shielding electrode LS can be arranged.

[0083] The substrate SUB can be a glass substrate or a plastic substrate.

[0084] The light-shielding electrode LS protects the channel region of the active layer ACT by blocking light incident through the substrate SUB. The light-shielding electrode LS can be formed from a light-shielding metal layer with light-shielding properties. For example, the light-shielding metal layer can have a single-layer structure comprising at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and alloys thereof, or a multilayer structure having at least two of these metal layers stacked. The light-shielding electrode LS can be connected to the gate electrode GE via contact hole CH4 to function as a dual-gate. The common electrode supply line VL can be formed as a light-shielding metal layer using the same process as the light-shielding electrode LS.

[0085] The buffer layer (BF) prevents impurities such as hydrogen from flowing into the active layer (ACT) through the substrate (SUB). The buffer layer (BF) may comprise an inorganic insulating material with a low hydrogen concentration. For example, the buffer layer (BF) may comprise an oxide-based insulating material such as silicon oxide (SiOx) or aluminum oxide (Al2O3) with a low hydrogen content.

[0086] The active layer ACT can be disposed on the buffer layer BF, and the gate insulating layer GI and the gate electrode GE can be disposed overlapping each other on the channel region CA of the active layer ACT, and the gate electrode GE can be integrally formed with the gate line GL.

[0087] The active layer ACT may include oxide semiconductor materials. For example, the active layer ACT may include at least one of IGZO (InGaZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, GZO (GaZnO)-based oxide semiconductor materials, Go (GaO)-based oxide semiconductor materials, TO (SnO)-based oxide semiconductor materials, ITO (InSnO)-based oxide semiconductor materials, ITZO (InSnZnO)-based oxide semiconductor materials, IZO (InZnO)-based oxide semiconductor materials, ZO (ZnO)-based oxide semiconductor materials, IO (InO)-based oxide semiconductor materials, InO (InO)-based oxide semiconductor materials, ZnO-based oxide semiconductor materials, and FIZO-based oxide semiconductor materials. The active layer ACT may have a single-layer structure or a multilayer structure in which at least two oxide semiconductor layers are stacked.

[0088] The active layer ACT may include a channel region CA having semiconductor properties, and a first connection region SA1 and a second connection region SA2, which are connected to both sides of the channel region CA and are conductive. According to an embodiment, the first connection region SA1 and the second connection region SA2 of the active layer ACT may be conductive regions doped with dopants by ion implantation. For example, the dopants may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). According to an embodiment, the first connection region SA1 and the second connection region SA2 of the active layer ACT may be regions conductiveized by dry etching or plasma treatment when patterning the gate insulating layer GI and the gate electrode GE.

[0089] The gate insulating layer GI can be patterned to have the same shape as the gate electrode GE and gate line GL on the gate insulating layer GI.

[0090] The gate insulating layer GI may include an inorganic insulating material with a low hydrogen concentration. For example, the gate insulating layer GI may include at least one of silicon oxide (SiOx), aluminum oxide (Al2O3), hafnium oxide (HfOx), and zirconium oxide (ZrOx).

[0091] The gate electrode GE may overlap with the channel region CA of the active layer ACT and may overlap with the light-shielding electrode LS. The gate electrode GE may be formed together with the gate line GL from the gate metal layer and may be integrally formed with the gate line GL. The gate electrode GE may be included as part of the gate line GL, or may have a shape that protrudes from the gate line GL in a second direction. The gate electrode GE may be connected to the light-shielding electrode LS through a contact hole CH4 passing through the gate insulating layer GI and the buffer layer BF. The gate metal layer may have a single-layer structure including at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag) and alloys thereof, or may have a multilayer structure in which at least two metal layers are stacked.

[0092] Interlayer insulating layers (ILDs): ILD1 and ILD2, covering the active layer ACT, gate insulating layer GI, gate electrode GE, and gate line GL, can be disposed on the buffer layer BF. The interlayer insulating layers (ILDs) may comprise inorganic insulating materials. The interlayer insulating layers (ILDs) may have a single-layer or multilayer structure comprising at least one of silicon oxide (SiOx) and silicon nitride (SiNx). For example, the interlayer insulating layer (ILD) may have a multilayer structure in which a first interlayer insulating layer (ILD1) comprising silicon oxide (SiOx) with a low hydrogen concentration and a second interlayer insulating layer (ILD2) comprising silicon nitride (SiNx) with a higher hydrogen concentration than the first interlayer insulating layer (ILD1) are stacked.

[0093] The first source-drain electrode SD1 and the second source-drain electrode SD2 can be disposed together with the data line DL on the interlayer insulating layer ILD2. The first source-drain electrode SD1 can be connected to the first connection region SA1 of the active layer ACT through the contact hole CH1 passing through the interlayer insulating layers ILD2 and ILD1, and can be connected to the data line DL or integrally formed with the data line DL. The second source-drain electrode SD2 can be connected to the second connection region SA2 of the active layer ACT through the contact hole CH2 passing through the interlayer insulating layers ILD2 and ILD1. The second source-drain electrode SD2 can be connected to the pixel electrode PXL through the contact hole CH3. The first source-drain electrode SD1, the second source-drain electrode SD2, and the data line DL can be formed as a source-drain metal layer. For example, the source-drain metal layer may have a single-layer structure comprising at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag) and alloys thereof, or may have a multilayer structure in which at least two metal layers are stacked.

[0094] A first passivation layer PAS1 covering the source-drain electrodes SD1 and SD2 and the data line DL can be disposed on the interlayer insulating layer ILD2, and a planarization layer PNL can be disposed on the first passivation layer PAS1. A common electrode VCOM can be disposed on the planarization layer PNL, and a second passivation layer PAS2 covering the common electrode VCOM can be disposed on the planarization layer PNL. A pixel electrode PXL can be disposed on the second passivation layer PAS2.

[0095] The first passivation layer PAS1 and the second passivation layer PAS2 may comprise inorganic insulating materials, and the planarization layer PNL may comprise organic insulating materials. For example, the first passivation layer PAS1 may comprise silicon oxide (SiOx) with a low hydrogen concentration, and the second passivation layer PAS2 may comprise silicon nitride (SiNx) with a higher hydrogen concentration than the first passivation layer PAS1. The planarization layer PNL may comprise at least one organic insulating material selected from acrylic resins, epoxy resins, siloxane resins, polyimide resins, and polyamide resins.

[0096] Either the pixel electrode PX and the common electrode COM disposed in the pixel region may include multiple slits overlapping the other electrode, and an edge electric field may be applied to the liquid crystal layer, enabling the liquid crystal layer to be driven in FFS mode. The pixel electrode PX and the common electrode VCOM may be formed of a transparent conductive layer. For example, the transparent conductive layer may include either indium tin oxide (ITO) or indium zinc oxide (IZO).

[0097] The common electrode VCOM can overlap with the gate line GL with multiple insulating layers ILD1, ILD2, PAS1, and PNL between it, and can also overlap with the data line DL with multiple insulating layers PAS1 and PNL between it. The common electrode VCOM can also be used as a touch electrode.

[0098] The pixel electrode PXL can be connected to the second source-drain electrode SD2 of the thin-film transistor TFT through the contact hole CH3 passing through the second passivation layer PAS2, the planarization layer PNL and the first passivation layer PAS1.

[0099] Gate lines GLi and GL(i+1) can be driven by single-feed or interlaced methods. For example, one gate line GLi can be connected to a second gate driving circuit 200b (FIG. 3) arranged in the right frame region, and the other gate line GL(i+1) can be connected to a first gate driving circuit 200a (FIG. 3) arranged in the left frame region. Thin-film transistors (TFTs) connected to adjacent gate lines GLi and GL(i+1) can extend between adjacent gate lines GLi and GL(i+1) and can be connected to pixel electrodes PXL extending between adjacent gate lines GLi and GL(i+1).

[0100] Each of the gate lines GLi and GL(i+1) driven by a single-feed or interlaced method may include the start of a contact gate drive circuit (Figure 2: 200 or Figure 3: 200a or 200b) in one frame region and the end of a non-contact gate drive circuit (Figure 2: 200 or Figure 3: 200a or 200b) in the other frame region.

[0101] The display device according to the embodiment may include a first type of virtual aperture DH1 disposed at the ends of gate lines GLi and GL(i+1) and used as a hydrogen degassing path.

[0102] The display device according to the embodiment may further include at least one of a second type of virtual aperture DH2 arranged on signal lines (i.e., gate lines GL1 and GL(i+1)) adjacent to the thin-film transistor TFT in the display area and a third type of virtual aperture DH3 arranged on data lines DL.

[0103] The display device according to the embodiment may further include a plurality of fourth-type virtual holes DH4 disposed in a frame region between the ends of the gate lines GLi and GL(i+1) and the gate driving circuit, adjacent to the ends of the gate lines GLi and GL(i+1).

[0104] The display device according to the embodiment may further include virtual electrodes DM1, DM2, DM3, and DM4 respectively disposed in virtual holes DH1, DH2, DH3, and DH4. The virtual electrodes DM1, DM2, DM3, and DM4 can protect the signal lines GL and DL exposed through the virtual holes DH1, DH2, DH3, and DH4.

[0105] According to the embodiments, the virtual holes DH1, DH2, DH3, and DH4, together with the contact holes CH2 and CH3 of the thin-film transistor TFT, can serve as hydrogen degassing paths for hydrogen (H) included in the multiple layers to diffuse and degas during the thermal processing, thereby increasing hydrogen degassing. The virtual holes DH1, DH2, DH3, and DH4 arranged at the ends of gate lines GLi and GL(i+1) and their adjacent regions can increase the degassing of hydrogen (H) flowing through the ends of gate lines GLi and GL(i+1) and the gate insulating layer GI.

[0106] Therefore, in the display device according to the embodiment, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the hydrogen impact on the thin-film transistor TFT, thereby preventing or minimizing changes in the threshold voltage Vth.

[0107] In the display device according to the embodiment, as the virtual holes DH1, DH2, DH3 and DH4 are brought closer to the ends of the gate lines GLi and GL(i+1), the number and density of the virtual holes DH1, DH2, DH3 and DH4 can be increased to minimize the difference in hydrogen inflow based on the distance from the ends of the gate lines GLi and GL(i+1).

[0108] Therefore, the display device according to the embodiment can minimize the deviation of the threshold voltage Vth of the thin-film transistor TFT based on the distance from the ends of the gate lines GL1 and GL(i+1).

[0109] Referring to FIG8A, a first type of virtual aperture DH1 according to an embodiment can pass through multiple insulating layers stacked on the gate line GL to expose the end of the gate line GL. A second type of virtual aperture DH2 according to an embodiment can be arranged on the gate line GL with the same structure as the first type of virtual aperture DH1. The first type of virtual aperture DH1 and the second type of virtual aperture DH2 can have a structure passing through interlayer insulating layers ILD1 and ILD2, a first passivation layer PAS1, a planarization layer PNL, and a second passivation layer PAS2 on the gate line GL. The display device according to an embodiment may further include virtual electrodes DM1 and DM2 respectively disposed in the first type of virtual aperture DH1 and the second type of virtual aperture DH2 to contact the gate line GL. The virtual electrodes DM1 and DM2 can be disposed on the second passivation layer PAS2 and can contact the gate line GL via the first type of virtual aperture DH1 and the second type of virtual aperture DH2 respectively. The virtual electrodes DM1 and DM2 can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL and can protect the gate line GL exposed through the virtual apertures DH1 and DH2.

[0110] Referring to FIG8B, the third type virtual aperture DH3 according to an embodiment can penetrate multiple insulating layers stacked on the data line DL to expose the data line DL. The third type virtual aperture DH3 may have a structure that penetrates the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2 on the data line DL. The display device according to an embodiment may further include a virtual electrode DM3 disposed in the third type virtual aperture DH3 to contact the data line DL. The virtual electrode DM3 may be disposed on the second passivation layer PAS2 and can contact the data line DL through the third type virtual aperture DH3. The virtual electrode DM3 may be formed of the same transparent conductive layer in the same process as the pixel electrode PXL and can protect the data line DL exposed through the virtual apertures DH1 and DH2.

[0111] In the display device according to the embodiment, a plurality of fourth-type virtual holes DH4 arranged in the bezel region adjacent to the ends of the gate lines GLi and GL(i+1) may have any of a variety of structures such as the fourth-1 type virtual hole DH41 to the fourth-6 type virtual hole DH46 shown in Figures 9A to 9F.

[0112] Referring to FIG9A, the display device according to the embodiment may include a fourth-1 type virtual hole DH41 disposed in a frame region adjacent to the ends of gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM41a and DM41b in contact with each other through the fourth-1 type virtual hole DH41. The plurality of virtual electrodes DM41a and DM41b may have an electrically floating structure.

[0113] The 4-1 type virtual via DH41 may have a structure that passes through the interlayer insulating layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2 in the same manner as the first type virtual via DH1 and the second type virtual via DH2 on the gate line GL.

[0114] The virtual electrode DM41a disposed on the gate insulating layer GI can be formed from the same gate metal layer in the same process as the gate line GL. The virtual electrode DM41b disposed on the second passivation layer PAS2, passing through the type 4-1 virtual hole DH41, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to protect the virtual electrode DM41a exposed through the type 4-1 virtual hole DH41. Referring to FIG9B, the display device according to the embodiment may include a type 4-2 virtual hole DH42 disposed in a bezel region adjacent to the ends of the gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM42a and DM42b in contact with each other through the type 4-2 virtual hole DH42. The plurality of virtual electrodes DM42a and DM42b may have an electrically floating structure.

[0115] The fourth-second type of virtual via DH42 may have a structure that passes through the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2 in the same manner as the third virtual via DH3 on the data line DL1.

[0116] The virtual electrode DM42a disposed on the interlayer insulating layer ILD2 can be formed from the same source-drain metal layer in the same process as the data line DL. The virtual electrode DM42b disposed in the second passivation layer PAS2 through the type 4-2 virtual via DH42 can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to protect the virtual electrode DM42a exposed through the type 4-2 virtual via DH42.

[0117] Referring to FIG9C, the display device according to the embodiment may include a fourth-third type virtual aperture DH43 disposed in a frame region adjacent to the ends of gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM43a and DM43b in contact with each other through the fourth-third type virtual aperture DH43. The plurality of virtual electrodes DM43a and DM43b may have an electrically floating structure.

[0118] The fourth-third type of virtual via DH43 may have a structure that passes through a buffer layer BF, interlayer insulating layers ILD1 and ILD2, a first passivation layer PAS1, a planarization layer PNL, and a second passivation layer PAS2 stacked on a substrate SUB.

[0119] The virtual electrode DM43a disposed on the substrate SUB can be formed with the same light-shielding metal layer in the same process as the light-shielding electrode LS. The virtual electrode DM43b disposed on the second passivation layer PAS2 through the type 4-3 virtual hole DH43 can be formed with the same transparent conductive layer in the same process as the pixel electrode PXL to protect the virtual electrode DM43a exposed through the type 4-3 virtual hole DH43.

[0120] Referring to FIG9D, the display device according to the embodiment may include a fourth-fourth type virtual hole DH44 disposed in a frame region adjacent to the ends of gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM44a, DM44b and DM44c in contact with each other through the fourth-fourth type virtual hole DH44. The plurality of virtual electrodes DM44a, DM44b and DM44c may have an electrically floating structure.

[0121] The 4-4 type virtual via DH44 can have a structure that passes through interlayer insulating layers ILD1 and ILD2, first passivation layer PAS1, planarization layer PNL and second passivation layer PAS2.

[0122] The virtual electrode DM44a disposed on the substrate SUB can be formed with the same light-shielding metal layer in the same process as the light-shielding electrode LS. The virtual electrode DM44b disposed on the gate insulating layer GI can be formed with the same gate metal layer in the same process as the gate line GL, and can contact the virtual electrode DM44a through a contact hole passing through the gate insulating layer GI and the buffer layer BF. The virtual electrode DM44c disposed on the second passivation layer PAS2 through the type 4-4 virtual hole DH44 can be formed with the same transparent conductive layer in the same process as the pixel electrode PXL, so as to protect the virtual electrode DM44b through the type 4-4 virtual hole DH44.

[0123] Referring to FIG9E, the display device according to the embodiment may include: a fourth-fifth type virtual aperture DH45 disposed in a frame region adjacent to the ends of gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM45a, DM45b and DM45c in contact with each other through the fourth-fifth type virtual aperture DH45. The plurality of virtual electrodes DM45a, DM45b and DM45c may have an electrically floating structure.

[0124] The fourth- and fifth type virtual vias DH45 can have a structure that passes through interlayer insulating layers ILD1 and ILD2, first passivation layer PAS1, planarization layer PNL, and second passivation layer PAS2.

[0125] The virtual electrode DM45a disposed on the gate insulating layer GI can be formed from the same gate metal layer in the same process as the gate line GL. The virtual electrode DM45b disposed on the second interlayer insulating layer ILD2 can be formed from the same source-drain metal layer in the same process as the data line DL, and can contact the virtual electrode DM45a through contact holes through the interlayer insulating layers ILD2 and ILD1. The virtual electrode DM45c disposed on the second passivation layer PAS2 through the type 4-5 virtual hole DH45 can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to protect the virtual electrode DM45b exposed through the type 4-5 virtual hole DH45.

[0126] Referring to FIG9F, the display device according to the embodiment may include a fourth-to-sixth type virtual aperture DH46 disposed in a bezel region adjacent to the ends of gate lines GL1 and GL(i+1), and a plurality of virtual electrodes DM46a, DM46b, DM46c and DM46d in contact with each other through the fourth-to-sixth type virtual aperture DH46. The plurality of virtual electrodes DM46a, DM46b, DM46c and DM46d may have an electrically floating structure.

[0127] The virtual via of type 4-6, DH46, can have a structure that passes through interlayer insulating layers ILD1 and ILD2, first passivation layer PAS1, planarization layer PNL, and second passivation layer PAS2.

[0128] The virtual electrode DM46a disposed on the substrate SUB can be formed with the same light-shielding metal layer in the same process as the light-shielding electrode LS. The virtual electrode DM46b disposed on the gate insulating layer GI can be formed with the same gate metal layer in the same process as the gate line GL, and can contact the virtual electrode DM46a through contact holes passing through the gate insulating layer GI and the buffer layer BF. The virtual electrode DM46c disposed on the second interlayer insulating layer ILD2 can be formed with the same source-drain metal layer in the same process as the data line DL, and can contact the virtual electrode DM46b through contact holes passing through the interlayer insulating layers ILD2 and ILD1. The virtual electrode DM46d disposed on the second passivation layer PAS2 through the type 4-6 virtual hole DH46 can be formed with the same transparent conductive layer in the same process as the pixel electrode PXL to protect the virtual electrode DM46c exposed through the type 4-6 virtual hole DH46. Here, as shown in Figures 9A to 9F, the virtual electrodes DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, and DM46b arranged below the fourth type of virtual hole can be referred to as the fifth virtual electrode.

[0129] In the display device according to the embodiment, various types of virtual holes DH1, DH2, DH3 and DH4: DH41 to DH46 and virtual electrodes DM1, DM2, DM3 and DM4: DM41a to DM46d can be used as degassing paths for hydrogen (H) diffused from multiple layers including the active layer ACT and the insulating layers ILD2 and PAS2 during the heat treatment process, so as to increase hydrogen degassing.

[0130] In the display device according to the embodiment, the light-shielding metal layer used as the light-shielding electrode LS and the virtual electrodes DM43a, DM44a and DM46a, the gate metal layer used as the gate line GL, the gate electrode GE and the virtual electrodes DM41a, DM44b, DM45a and DM46b, and the source-drain metal layer used as the data line DL, the source-drain electrodes SD1 and SD2 and the virtual electrodes DM42a, DM45b and DM46c may include a hydrogen-capturing metal material to capture hydrogen, thereby suppressing hydrogen diffusion. The hydrogen-capturing metal material may include a metal material having a negative (-) hydrogen production energy (eV).

[0131] For example, hydrogen-capturing metal materials may include at least one of molybdenum-titanium alloy (MoTi), titanium (Ti), lithium (Li), hafnium (Hf), ruthenium (Lu), tantalum (Ta), magnesium (Mg), vanadium (V), rubidium (Rb), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), niobium (Nb), cesium (Cs), barium (Ba), and lanthanum (La).

[0132] Figure 10 is a graph illustrating the hydrogen generation energy of each material used in the display device according to an embodiment of the present disclosure, Figure 11 is a diagram illustrating the hydrogen diffusion path of the thin-film transistor in the display device according to an embodiment of the present disclosure, and Figure 12 is a diagram illustrating the hydrogen degassing path of the thin-film transistor according to an embodiment of the present disclosure.

[0133] Depending on the amount of hydrogen used in the materials used in the display panel and the inherent hydrogen generation energy (eV) of the corresponding material layer, hydrogen density diffusion may occur to the layers adjacent to the corresponding material layer.

[0134] Referring to FIG10, a molybdenum-titanium alloy (MoTi) among the materials (Cu, MoTi, Mo, Al, and Ti) used in the gate metal layer or source-drain metal layer according to the embodiment can have a negative (-) hydrogen generation energy of -0.6 eV and can be used for hydrogen capture. A silicon oxide (SiOx) with a relatively high hydrogen generation energy of 3.6 eV, used in the interlayer insulating layer ILD1 or the gate insulating layer GI according to the embodiment, can be used as a barrier to suppress hydrogen diffusion.

[0135] Referring to FIG11, in the display device according to the embodiment, hydrogen diffusing from the passivation layer PAS2 can diffuse to the active layer ACT via the interlayer insulating layer ILD, the gate electrode GE, and the gate insulating layer GI of the thin-film transistor. The interlayer insulating layer ILD and the gate insulating layer GI, which are made of silicon oxide (SiOx) with a high hydrogen generation energy of 3.6 eV, can be used as a barrier to suppress hydrogen diffusion.

[0136] The gate electrode GE may have a multilayer structure in which a lower gate metal layer comprising a molybdenum-titanium alloy (MoTi) and an upper gate metal layer comprising copper (Cu) are stacked. The lower gate metal layer, comprising a molybdenum-titanium alloy (MoTi) with a negative hydrogen generation energy of -0.6 eV, can capture hydrogen diffusing through the upper gate metal layer, which comprises copper (Cu) with a positive hydrogen generation energy of 0.6 V, thereby suppressing hydrogen diffusion into the gate insulating layer GI and the active layer ACT.

[0137] In one embodiment, the virtual electrodes DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, DM46b, and DM46c are formed from a light-shielding metal layer, a gate metal layer, or a source-drain metal layer comprising a hydrogen-capturing metal material such as a molybdenum-titanium alloy (MoTi) to suppress hydrogen diffusion and thereby reduce the impact of hydrogen on the thin-film transistor (TFT).

[0138] Referring to FIG12, in the thin-film transistor according to the embodiment, hydrogen (H) included in the channel region CA (IGZO) of the active layer ACT can be degassed into the contact hole CH2 (air) via the second connection region SA2 (conductive IGZO), the second source-drain electrode SD2 (Cu / MoTi), and the pixel electrode PXL (ITO) of the active layer ACT. The second connection region SA2 (conductive IGZO), the second source-drain electrode SD2 (Cu / MoTi), and the pixel electrode PXL (ITO) of the active layer ACT can have a lower hydrogen generation energy than the channel region CA (IGZO) of the active layer ACT.

[0139] According to the embodiments, the display device can reduce the hydrogen impact on the thin-film transistor TFT by increasing hydrogen degassing and hydrogen capture through virtual holes DH1, DH2, DH3 and DH4: DH41 to DH46 and virtual electrodes DM1, DM2, DM3 and DM4: DM41a to DM46d.

[0140] Figure 13 is a plan view of a portion of the display area adjacent to the end of the gate line in the display area of ​​a display device according to an embodiment of the present disclosure. Figures 14A to 14F are cross-sectional views illustrating the passivation hole structure taken along lines V-V', VI-VI', VII-VII' and VIII-VIII' shown in Figure 13. Figures 15A and 15B are plan and cross-sectional views illustrating the thin-film transistor structure in the gate drive circuit of a display device according to an embodiment of the present disclosure.

[0141] The display device according to the embodiment shown in FIG13 may include passivation holes PH1 to PH7 serving as hydrogen degassing paths. Compared with the display device according to the embodiment shown in FIG6, since the element including passivation holes PH1 to PH7 in place of virtual holes DH1, DH2, DH3 and DH4 is different from that in FIG6, and other elements are the same as those in FIG6, only the different elements will be described.

[0142] The display device according to an embodiment may include at least one of passivation holes PH1 and PH2 disposed in a second passivation layer PAS2 that overlaps or is adjacent to the ends of gate lines GLi and GL(i+1) driven in a single-feed or interlaced manner. Passivation hole PH1 may be disposed in a second passivation layer PAS2 that is divided into multiple portions and overlaps or is adjacent to the ends of gate lines GLi and GL(i+1). Passivation hole PH2 may be disposed integrally in the second passivation layer PAS2 that overlaps or is adjacent to the ends of gate lines GLi and GL(i+1).

[0143] The display device according to the embodiment may further include at least one of the following: passivation holes PH3 and PH7 disposed in a second passivation layer PAS2 that overlaps with or is adjacent to the thin-film transistor TFT in the display area; passivation holes PH4 and PH6 disposed in a second passivation layer PAS2 on a signal line (i.e., data line DL) adjacent to the thin-film transistor TFT; or passivation hole PH5 disposed in a second passivation layer PAS2 on gate lines GL1 and GL(i+1).

[0144] The display device according to the embodiment may include at least one of passivation holes PH1 to PH7. Here, passivation holes PH3, PH4, PH5, PH6 and PH7 disposed in the second passivation layer PAS2 (i.e., the upper passivation layer) in the display area may be referred to as first passivation holes, and passivation holes PH1 and PH2 disposed in the second passivation layer PAS2 in the frame area between the end of each gate line and the gate drive circuit may be referred to as second passivation holes.

[0145] The display device according to the embodiment may further include virtual electrodes arranged to overlap with and electrically float the passivation holes PH1 to PH7.

[0146] Referring to FIG14A, the display device according to the embodiment may include a passivation hole PH11 disposed in a second passivation layer PAS2 adjacent to the ends of gate lines GL1 and GL(i+1), and a virtual electrode DM51 disposed overlapping the passivation hole PH11. The virtual electrode DM51 may be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL.

[0147] Referring to FIG14B, the display device according to the embodiment may include a passivation hole PH12 disposed in a second passivation layer PAS2 adjacent to the ends of gate lines GL1 and GL(i+1), and virtual electrodes DM52a and DM52b disposed overlapping the passivation hole PH12. The virtual electrode DM52a may be formed of the same transparent conductive layer as the common electrode VCOM on the planarization layer PNL. The virtual electrode DM52b may be formed of the same transparent conductive layer as the pixel electrode PXL and the virtual electrode DM52a on the second passivation layer PAS2, and may be in contact with the virtual electrode DM52a through the passivation hole PH12.

[0148] Referring to FIG14C, the display device according to the embodiment may include a passivation hole PH31 disposed in a second passivation layer PAS2 on a thin-film transistor TFT, and a dummy electrode DM52 disposed overlapping the passivation hole PH31. The passivation hole PH31 may be disposed overlapping with a first source-drain electrode SD1 connected to an active layer ACT of the thin-film transistor TFT. The dummy electrode DM52 may be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL.

[0149] Referring to FIG14D, the display device according to the embodiment may include a passivation hole PH32 disposed in a second passivation layer PAS2 on a thin-film transistor TFT, and virtual electrodes DM53a and DM53b disposed overlapping the passivation hole PH32. The passivation hole PH32 may be disposed overlapping with a first source-drain electrode SD1 connected to an active layer ACT of the thin-film transistor TFT. The virtual electrode DM53a may be formed with the same transparent conductive layer as the common electrode VCOM on the planarization layer PNL. The virtual electrode DM53b may be formed with the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the virtual electrode DM53a, and may be in contact with the virtual electrode DM53a through the passivation hole PH32.

[0150] Referring to FIG14E, the display device according to the embodiment may include a passivation hole PH4 disposed in a second passivation layer PAS2 on a data line DL, and a virtual electrode DM54 disposed overlapping the passivation hole PH4. The passivation hole PH4 may be disposed overlapping the data line DL adjacent to the thin-film transistor TFT. The virtual electrode DM54 may be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL.

[0151] Referring to FIG14F, the display device according to the embodiment may include a passivation hole PH5 disposed in a second passivation layer PAS2 on a gate line GL, and a virtual electrode DM55 disposed overlapping the passivation hole PH5. The passivation hole PH5 may be disposed overlapping the gate line GL adjacent to the thin-film transistor TFT. The virtual electrode DM55 may be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL. Here, as shown in FIGS. 14A to 14F, the virtual electrode disposed in the first passivation hole may be referred to as the sixth virtual electrode, the virtual electrode disposed in the second passivation hole may be referred to as the seventh virtual electrode, the virtual electrode disposed below the first passivation hole may be referred to as the eighth virtual electrode, and the virtual electrode disposed below the second passivation hole may be referred to as the ninth virtual electrode.

[0152] In the display device according to the embodiment, virtual electrodes DM: DM51, DM52a, DM52b, DM52, DM53a, DM53b, DM54 and DM55 cover passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32, thereby preventing defects that may be caused by passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32 in subsequent processes after the heat treatment process.

[0153] In the display device according to embodiments of the present disclosure, the passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32 and the virtual electrodes DM: DM51, DM52a, DM52b, DM52, DM53a, DM53b, DM54 and DM55 can be used as degassing paths for hydrogen (H) included in the second passivation layer PAS2 during the heat treatment process to increase hydrogen degassing. Therefore, in the display device according to the embodiment, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the hydrogen impact on the thin-film transistor TFT, thereby preventing or minimizing changes in the threshold voltage Vth.

[0154] Referring to Figures 15A and 15B, the thin-film transistor TFT2 of the gate drive circuit in the display device according to an embodiment of the present disclosure may have a structure different from that of the thin-film transistor TFT of the display area shown in Figures 7 and 13.

[0155] In the display device according to the embodiment, the thin-film transistor TFT of the display area may have a 3-metal-layer structure including a light-shielding metal layer, a gate metal layer and a source-drain metal layer as shown in FIG7, and the thin-film transistor TFT2 of the gate driving circuit may have a 2-metal-layer structure including a light-shielding metal layer and a gate metal layer as shown in FIG15B.

[0156] The thin-film transistor TFT2 of the gate driving circuit according to an embodiment may include: a light-shielding electrode LS2 on a substrate SUB; a buffer layer BF covering the light-shielding electrode LS2; an active layer ACT2 on the buffer layer BF; a gate insulating layer GI and a gate electrode GE2 stacked on the active layer ACT; and second-1 source-drain electrodes SD21 and SD22 respectively connected to a first connection region and a second connection region of the active layer ACT2 exposed through contact holes CH21 and CH22 of the gate insulating layer GI. The light-shielding electrode LS2 may be connected to the gate electrode GE2 through contact hole CH23 to serve as a dual gate. The display device according to an embodiment may further include interlayer insulating layers ILD1 and ILD2, a first passivation layer PAS1, a planarization layer PNL, and a second passivation layer PAS2 stacked on the thin-film transistor TFT2 of the gate driving circuit.

[0157] Referring to FIG15B, the thin-film transistor TFT2 of the gate drive circuit according to the embodiment may have a structure in which the second interlayer insulating layer ILD2, including silicon nitride (SiNx), is not in direct contact with the second-first source-drain electrode SD21 and the second-second source-drain electrode SD22, and may not have a contact hole passing through the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2.

[0158] Referring to FIG7, the thin-film transistor TFT in the display area according to the embodiment includes a path in which the second interlayer insulating layer ILD2 contacts the first source-drain electrode SD1 and the second source-drain electrode SD2, and a contact hole CH3 passing through the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2, such that the amount of hydrogen flowing in can be increased more than that of the thin-film transistor TFT2 of the gate driving circuit.

[0159] The display device according to the embodiment may include at least one of a virtual aperture DH or a passivation aperture PH arranged in the display area, thereby increasing hydrogen degassing.

[0160] Therefore, the display device according to the embodiment can reduce or minimize the deviation of the threshold voltage Vth by reducing the hydrogen content difference between the thin-film transistor TFT in the display area and the thin-film transistor TFT2 in the gate drive circuit.

[0161] Figure 16 is a plan view of a portion of the display area adjacent to the end of the gate line in the display area of ​​a display device according to an embodiment of the present disclosure, and Figures 17A to 17C are cross-sectional views illustrating a virtual hole structure taken along line IX-IX' shown in Figure 16 and a passivation hole structure taken along line X-X'.

[0162] Referring to Figures 16 to 17C, the display device according to the embodiment may include a gate line Gla, a data line DLa, a thin-film transistor TFTa, a common electrode VCOMa, a pixel electrode PXLa, and a thin-film transistor substrate on which multiple insulating layers are disposed. The multiple insulating layers may include a buffer layer BF, a gate insulating layer GI, interlayer insulating layers ILD1 and ILD2, passivation layers PAS1 and PAS2, and a planarization layer PNL. Descriptions of repeated elements described with reference to Figures 6 and 7 will be omitted.

[0163] The thin-film transistor TFTa in the display area according to the embodiment may have a two-metal-layer structure. The thin-film transistor TFTa in the display area according to the embodiment may include: a light-shielding electrode LSa on a substrate SUB; a buffer layer BF covering the light-shielding electrode LSa; an active layer ACTa on the buffer layer BF; a gate insulating layer GI and a gate electrode GEa stacked on the active layer ACTa; and a first source-drain electrode SD1a and a second source-drain electrode SD2a respectively connected to a first connection region and a second connection region of the active layer ACTa exposed through contact holes CH1a and CH2a in the gate insulating layer GI.

[0164] According to the embodiment, interlayer insulating layers ILD1 and ILD2, a first passivation layer PAS1, a planarization layer PNL, and a second passivation layer PAS2 can be sequentially stacked on a thin-film transistor TFTa.

[0165] The data line DLa and the light-shielding electrode LSa can be arranged on the substrate SUB as the same light-shielding metal layer.

[0166] Gate line GLa, gate electrode GEa, and first source-drain electrode SD1a and second source-drain electrode SD2a can be formed on gate insulating layer GI as the same gate metal layer. Gate electrode GEa can be connected to light-shielding electrode LSa through contact hole CH4a passing through gate insulating layer GI and buffer layer BF. First source-drain electrode SD1a can be connected to data line DLa through contact hole CH5a passing through gate insulating layer GI and buffer layer BF. Second source-drain electrode SD2a can be connected to pixel electrode PXL through contact hole CH3a passing through interlayer insulating layers ILD1 and ILD2, first passivation layer PAS1, planarization layer PNL and second passivation layer PAS2.

[0167] A gate line GLa driven by a single-feed or interlaced method may include a starting end located in one frame region that contacts the gate drive circuit (Figure 2: 200 or Figure 3: 200a or 200b) and an ending end located in another frame region that does not contact the gate drive circuit.

[0168] The display device according to an embodiment may include at least one of virtual orifices DH21, DH22, DH23 and DH24 or passivation orifices PH31 and PH32 serving as hydrogen degassing paths. The display device according to an embodiment may further include virtual electrodes configured to overlap with the virtual orifices DH21, DH22, DH23 and DH24 and the passivation orifices PH31 and PH32.

[0169] Therefore, in the display device according to the embodiment, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the hydrogen effect on the thin film transistor TFTa, thereby preventing or minimizing changes in the threshold voltage Vth.

[0170] The display device according to the embodiment may include at least one of the following: a virtual hole DH21 disposed at the end of a gate line GLa; a virtual hole DH22 disposed on a signal line, i.e., a gate line GLa, adjacent to a thin-film transistor TFT in the display area; a virtual hole DH23 disposed on a data line DLa; or a virtual hole DH24 disposed in a frame region adjacent to the end of the gate line GLa; and may further include virtual electrodes disposed to overlap with the virtual holes DH21, DH22, DH23, and DH24.

[0171] The virtual aperture DH21 and the virtual aperture DH22 that overlap with the end of the gate line GLa may have the same structure as the virtual aperture DH1 shown in FIG8A above, and may further include the virtual electrode DM1 shown in FIG8A.

[0172] According to the embodiment, the virtual via DH24 arranged in the border region adjacent to the end of the gate line GLa may have the same structure as the virtual vias DH4: DH41 to DH46 shown in Figures 9A to 9F above, and may further include the virtual electrodes DM4: DM41a to DM46d shown in Figures 9A to 9F.

[0173] Referring to FIG17A, the virtual via DH23 overlapping the data line DLa according to the embodiment can be arranged to pass through the buffer layer BF, interlayer insulating layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2 stacked on the data line DLa. The virtual electrode DM23 arranged on the second passivation layer PAS2 and passing through the virtual via DH23 can contact the data line DLa.

[0174] Referring to Figures 17B and 17C, in the display device according to the embodiment, the passivation hole PH31 in the second passivation layer PAS2 arranged on the thin film transistor TFTa can overlap with the first source-drain electrode SD1a connected to the active layer ACTa, and can also overlap with the data line DLa.

[0175] The display device according to the embodiment may further include a virtual electrode DM31 (FIG. 17B) arranged to overlap with the passivation hole PH31, or may further include a plurality of virtual electrodes DM31a and DM31 (FIG. 17C) arranged to overlap with the passivation hole PH31. The virtual electrode DM31 may be formed with the same transparent conductive layer as the pixel electrode PXL. The virtual electrode DM31a may be formed with the same transparent conductive layer as the common electrode VCOM.

[0176] According to one embodiment, the passivation hole PH32 arranged in the frame region adjacent to the end of the gate line GLa may have the same structure as the passivation holes PH11 and PH12 shown in FIG14A and FIG14B above, and may further include the virtual electrodes DM51, DM51a and DM51b shown in FIG14A and FIG14B.

[0177] Figure 18 is a diagram illustrating the application structure of the virtual aperture density difference in a display device according to an embodiment of the present disclosure, and Figures 19A to 19C are plan views illustrating a portion of each of the first to third regions shown in Figure 18.

[0178] Referring to FIG18, in a display panel driven in an interlaced manner according to an embodiment, odd-numbered gate lines GLo may include a left starting end that is in contact with the stage circuit GIPo of the left gate driving circuit 200a in the left frame region BZ1 and a right ending end disposed in the right frame region BZ2. Even-numbered gate lines GLe may include a right starting end that is in contact with the stage circuit GIPe of the right gate driving circuit 200b in the right frame region BZ2 and a left ending end disposed in the left frame region BZ1.

[0179] The display panel according to the embodiment may include at least one of a virtual hole or a passivation hole that is arranged overlapping or adjacent to a thin-film transistor or signal line in the display area DA to serve as a hydrogen degassing path, thereby increasing hydrogen degassing.

[0180] In the display panel according to the embodiment, the density of virtual holes arranged in the display area DA can be applied differently depending on the distance from the ends of the gate lines GLo and GLe.

[0181] Referring to Figures 18 and 19A, in a display panel according to an embodiment, a virtual aperture DH can be arranged in a low density in a first region AA1 away from the ends of gate lines GLO and GLe.

[0182] Referring to Figures 18 and 19B, in a display panel according to an embodiment, a virtual aperture DH can be arranged at an intermediate density (medium density) in a second region AA2 located between a first region AA1 located away from the ends of the gate lines GLo and GLe and a third region AA3 located near the ends of the gate lines GLo and GLe.

[0183] Referring to Figures 18 and 19C, in a display panel according to an embodiment, virtual apertures DH can be arranged in a high density in a third region AA3 near the ends of gate lines GLo and GLe.

[0184] Therefore, the display panel according to the embodiment can prevent the threshold voltage of the thin-film transistor from shifting to a negative voltage and minimize the threshold voltage deviation of the thin-film transistor by minimizing the difference in hydrogen inflow caused by the structural difference between the start and end of each of the gate lines GLo and GLe.

[0185] Figure 20A is a graph illustrating the voltage-current characteristics of a thin-film transistor in a display device according to a comparative example of the related art. Figures 20B and 20C are graphs illustrating the voltage-current characteristics of a thin-film transistor in a display device according to an embodiment of the present disclosure.

[0186] Referring to FIG20A, when the display device according to the comparative example of the related art does not include a virtual hole overlapping with the thin film transistor, it is noted that the hydrogen inflow into the active layer of the thin film transistor can be increased, causing the threshold voltage of the thin film transistor to shift in the negative direction.

[0187] Referring to FIG20B, the display device according to an embodiment includes a virtual aperture disposed on a thin-film transistor through a first passivation layer, a planarization layer, and a second passivation layer, and a virtual electrode disposed overlapping the virtual aperture, thereby increasing hydrogen degassing through the virtual aperture and the virtual electrode. Therefore, it is noted that the threshold voltage of the thin-film transistor shifts in the positive direction but not in the negative direction.

[0188] Referring to FIG20C, even though the display device according to the embodiment includes a virtual hole (passivation hole) through the second passivation layer on the thin film transistor and a virtual electrode overlapping the virtual hole, it is noted that hydrogen degassing is also increased through the virtual hole and the virtual electrode, causing the threshold voltage of the thin film transistor to shift in the positive direction and not in the negative direction.

[0189] Figures 21A and 21B are graphs illustrating the voltage-current characteristics of thin-film transistors based on the density of virtual holes in a display device according to an embodiment of the present disclosure.

[0190] Referring to Figures 21A and 21B, in the display device according to the embodiment, it is noted that as the density of the virtual holes arranged around the thin-film transistor increases from a low density (Figure 21A) to a high density (Figure 21B), hydrogen degassing increases, causing the threshold voltage of the thin-film transistor to shift in the positive direction.

[0191] Based on this disclosure, the following beneficial effects can be obtained.

[0192] As described above, the display device according to the embodiments of this disclosure can apply different densities of hydrogen degassing paths (virtual holes and passivation holes) based on the distance to the end of the gate line driven in a single-feed or interlaced manner, thereby increasing the hydrogen degassing effect and minimizing the difference in hydrogen inflow.

[0193] Therefore, the display device according to the embodiments of the present disclosure can improve reliability and uniformity by minimizing the threshold voltage deviation of thin-film transistors based on their position in the display area.

[0194] The display device according to embodiments of this disclosure can reduce or minimize leakage current by preventing the threshold voltage of the thin-film transistor from shifting in the negative direction, thereby improving reliability and providing improved image quality with low power consumption.

[0195] The display device according to embodiments of the present disclosure can improve reliability by minimizing the threshold voltage deviation between a first thin-film transistor in a display region that is different from each other in the stacked structure and a second thin-film transistor in the gate drive circuit.

[0196] A display device according to some embodiments of the present disclosure may include: a display panel including a display area in which gate lines, data lines and thin-film transistors are disposed, and a first border area and a second border area surrounding the display area; a gate driving circuit disposed in at least one of the first border area and the second border area and configured to drive the gate lines; and virtual holes disposed in the display area and at least one of the first border area and the second border area, wherein each of the gate lines includes a start end located in either the first border area or the second border area and connected to the gate driving circuit, and an end end located in the other border area of ​​the first border area and the second border area, and the density of the virtual holes varies according to the distance from the end of each gate line.

[0197] According to some embodiments of the present disclosure, the display device may further include virtual electrodes respectively arranged in the virtual holes.

[0198] In a display device according to some embodiments, the density of virtual holes can be higher as the virtual holes are closer to the end of each gate line, and the density of virtual holes can be lower as the virtual holes are closer to the beginning of each gate line.

[0199] In a display device according to some embodiments, the gate driving circuit may be arranged in the first bezel region and may be connected to the start end of each of the gate lines located in the first bezel region, and the end end of the gate line may be arranged in the second bezel region.

[0200] In a display device according to some embodiments, the gate driving circuit may include: a first gate driving circuit disposed in a first bezel region and connected to the start end of each of the odd-numbered gate lines in the first bezel region; and a second gate driving circuit disposed in a second bezel region and connected to the start end of each of the even-numbered gate lines in the second bezel region, wherein the end of each of the odd-numbered gate lines may be disposed in the second bezel region, and the end of each of the even-numbered gate lines may be disposed in the first bezel region.

[0201] In a display device according to some embodiments, the virtual aperture may include at least one of the following: a first type of virtual aperture, the first type of virtual aperture being disposed on the end of each gate line to overlap with the end of each gate line; a second type of virtual aperture, the second type of virtual aperture being disposed on each gate line to overlap with each gate line; and a third type of virtual aperture, the third type of virtual aperture being disposed on each data line to overlap with each data line.

[0202] In a display device according to some embodiments, the virtual electrode may include at least one of the following: a first virtual electrode disposed in a first type of virtual hole; a second virtual electrode disposed in a second type of virtual hole; and a third virtual electrode disposed in the third type of virtual hole.

[0203] In a display device according to some embodiments, each of the first type of virtual aperture and the second type of virtual aperture may be arranged to pass through a plurality of insulating layers stacked on each gate line.

[0204] In a display device according to some embodiments, each of the first virtual electrode and the second virtual electrode may be disposed on the uppermost insulating layer among a plurality of insulating layers stacked on each gate line, and may be in contact with the gate line through each of the first type of virtual via and the second type of virtual via.

[0205] In a display device according to some embodiments, the third type of virtual hole may be arranged to pass through multiple insulating layers stacked on each data line.

[0206] In a display device according to some embodiments, the third virtual electrode may be arranged on the uppermost insulating layer among a plurality of insulating layers stacked on each data line, and may be in contact with the data line through the third type of virtual hole.

[0207] In a display device according to some embodiments, the virtual electrode may be arranged on the same transparent conductive layer as the pixel electrode connected to the thin-film transistor.

[0208] In a display device according to some embodiments, the virtual hole may further include a fourth type of virtual hole, the fourth type of virtual hole being disposed between the end of each gate line in at least one of the first bezel region and the second bezel region and the gate driving circuit.

[0209] In a display device according to some embodiments, the virtual electrode may further include: a fourth virtual electrode disposed in the fourth type of virtual hole; and at least one fifth virtual electrode disposed below the fourth type of virtual hole.

[0210] In a display device according to some embodiments, the fourth type of virtual hole may be arranged to pass through a plurality of insulating layers stacked on the at least one fifth virtual electrode, and the fourth virtual electrode may be arranged on the uppermost insulating layer among the plurality of insulating layers and contact the at least one fifth virtual electrode through the fourth type of virtual hole.

[0211] In a display device according to some embodiments, the fourth virtual electrode may be arranged on the same transparent conductive layer as the pixel electrode connected to the thin film transistor, and the at least one fifth virtual electrode may be arranged on the same metal layer as at least one electrode of the thin film transistor.

[0212] In a display device according to some embodiments, the thin-film transistor may include: a light-shielding electrode disposed on a substrate; an active layer disposed overlapping the light-shielding electrode and a buffer layer between the light-shielding electrode and the active layer; a gate electrode disposed between the active layer and a gate insulating layer; and a first source-drain electrode and a second source-drain electrode connected to a first connection region and a second connection region of the active layer respectively through a first contact hole and a second contact hole in an interlayer insulating layer covering the gate insulating layer and the gate electrode, wherein the at least one fifth virtual electrode may include at least one of the following: a light-shielding metal layer identical to the light-shielding electrode, a gate metal layer identical to the gate electrode, and a source-drain metal layer identical to the first source-drain electrode and the second source-drain electrode.

[0213] In a display device according to some embodiments, the thin-film transistor may include: a light-shielding electrode disposed on a substrate; an active layer disposed overlapping the light-shielding electrode and a buffer layer located between the light-shielding electrode and the active layer; a gate electrode disposed between the active layer and a gate insulating layer; and a first source-drain electrode and a second source-drain electrode connected to a first connection region and a second connection region of the active layer through a first contact hole and a second contact hole in the gate insulating layer, respectively, wherein the at least one fifth virtual electrode may include at least one of the following: a light-shielding metal layer identical to the light-shielding electrode, a gate metal layer identical to the gate electrode, and a source-drain metal layer identical to the first source-drain electrode and the second source-drain electrode.

[0214] In a display device according to some embodiments, the at least one fifth virtual electrode may include a hydrogen-capturing metal material, which is included in at least one of the light-shielding metal layer, the gate metal layer, and the source-drain metal layer.

[0215] A display device according to some embodiments of the present disclosure may further include at least one of the following: a first passivation hole disposed in an upper passivation layer in the display area; and a second passivation hole disposed in the upper passivation layer in at least one of the first and second border regions, located between the end of each gate line and the gate driving circuit.

[0216] The display device according to some embodiments of the present disclosure may further include at least one of the following: a sixth virtual electrode disposed in the first passivation hole; and a seventh virtual electrode disposed in the second passivation hole.

[0217] In a display device according to some embodiments, the first passivation hole may be arranged to overlap with or be adjacent to at least one of the gate line, the data line and the thin-film transistor.

[0218] The display device according to some embodiments of this disclosure may further include at least one of the following: an eighth virtual electrode disposed below the first passivation hole and in contact with the sixth virtual electrode through the first passivation hole; and a ninth virtual electrode disposed below the second passivation hole and in contact with the seventh virtual electrode through the second passivation hole.

[0219] In a display device according to some embodiments, at least one of the sixth virtual electrode or the seventh virtual electrode may be arranged on the same transparent conductive layer as the pixel electrode connected to the thin film transistor, and at least one of the eighth virtual electrode or the ninth virtual electrode may be arranged on the same transparent conductive layer as the common electrode overlapping the pixel electrode and the upper passivation layer.

[0220] The display device according to one or more embodiments of this disclosure can be applied to a variety of electronic devices. For example, the display device according to one or more embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic diaries, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigators, vehicle navigators, vehicle display devices, televisions, wallpaper display devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, and home appliances.

[0221] The various embodiments described above can be combined to provide other embodiments. If necessary, aspects of the embodiments can be modified to employ various implementation concepts to provide other embodiments.

[0222] In view of the above detailed description, these and other changes may be made to these embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents conferred by these claims. Therefore, the claims are not limited by this disclosure.

[0223] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be achieved by combinations or modifications of other embodiments by those skilled in the art. Therefore, content associated with combinations and modifications should be interpreted as being within the scope of this disclosure.

[0224] It will be apparent to those skilled in the art that the present disclosure described above is not limited to the embodiments and drawings described herein, and that various substitutions, modifications, and variations may be made in the present disclosure without departing from its scope. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalents of the claims fall within the scope of the present disclosure.

Claims

1. A display device, comprising: The display panel includes a display area in which gate lines, data lines and thin-film transistors are arranged, and a first border area and a second border area surrounding the display area. A gate driving circuit, wherein the gate driving circuit is disposed in at least one of the first frame region and the second frame region, and is configured to drive the gate line; And virtual holes, which are arranged in the display area and at least one of the first bezel area and the second bezel area, wherein each of the gate lines includes a start end located in either the first bezel area and the second bezel area and connected to the gate driving circuit and an end end located in the other bezel area of ​​the first bezel area and the second bezel area, and wherein the density of the virtual holes varies according to the distance from the end of each gate line.

2. The display device according to claim 1, further comprising virtual electrodes respectively arranged in the virtual holes.

3. The display device of claim 1, wherein the density of the virtual apertures is higher as the virtual apertures are closer to the end of each gate line, and the density of the virtual apertures is lower as the virtual apertures are closer to the beginning of each gate line.

4. The display device of claim 1, wherein the gate driving circuit is disposed in the first bezel region and connected to the start end of each of the gate lines located in the first bezel region, and wherein the end end of the gate line is disposed in the second bezel region.

5. The display device according to claim 1, wherein the gate driving circuit comprises: A first gate driving circuit is disposed in the first frame region and connected to the start end of each of the odd-numbered gate lines in the first frame region; and a second gate driving circuit is disposed in the second frame region and connected to the start end of each of the even-numbered gate lines in the second frame region, wherein the end of each of the odd-numbered gate lines is disposed in the second frame region and wherein the end of each of the even-numbered gate lines is disposed in the first frame region.

6. The display device of claim 2, wherein the virtual aperture includes at least one of the following: a first type virtual aperture, the first type virtual aperture overlapping the end of each gate line; a second type virtual aperture, the second type virtual aperture overlapping each gate line; and a third type virtual aperture, the third type virtual aperture overlapping each data line.

7. The display device according to claim 6, wherein the virtual electrode comprises at least one of the following: a first virtual electrode disposed in a first type of virtual hole; a second virtual electrode disposed in a second type of virtual hole; and a third virtual electrode disposed in the third type of virtual hole.

8. The display device of claim 6, wherein each of the first type of virtual aperture and the second type of virtual aperture passes through a plurality of insulating layers stacked on each gate line.

9. The display device of claim 7, wherein each of the first virtual electrode and the second virtual electrode is disposed on the uppermost insulating layer among a plurality of insulating layers stacked on each gate line, and is in contact with the gate line through each of the first type of virtual hole and the second type of virtual hole.

10. The display device of claim 6, wherein the third type of virtual hole passes through a plurality of insulating layers stacked on each data line.

11. The display device of claim 7, wherein the third virtual electrode is disposed on the uppermost insulating layer among a plurality of insulating layers stacked on each data line, and is in contact with the data line through the third type of virtual hole.

12. The display device of claim 7, wherein the virtual electrode and the pixel electrode connected to the thin-film transistor are arranged on the same transparent conductive layer on the same layer.

13. The display device of claim 6, wherein the virtual hole further comprises a fourth type of virtual hole, the fourth type of virtual hole being disposed between the end of each gate line in at least one of the first bezel region and the second bezel region and the gate driving circuit.

14. The display device according to claim 13, wherein the virtual electrode further comprises: A fourth virtual electrode is arranged in the fourth type of virtual hole; and at least one fifth virtual electrode arranged below the fourth type of virtual hole.

15. The display device of claim 14, wherein the fourth type of virtual aperture passes through a plurality of insulating layers stacked on the at least one fifth virtual electrode, and wherein the fourth virtual electrode is disposed on the uppermost insulating layer among the plurality of insulating layers and contacts the at least one fifth virtual electrode through the fourth type of virtual aperture.

16. The display device of claim 14, wherein the fourth virtual electrode and the pixel electrode connected to the thin film transistor are arranged on the same transparent conductive layer on the same layer, and wherein the at least one fifth virtual electrode and the at least one electrode of the thin film transistor are arranged on the same metal layer on the same layer.

17. The display device of claim 16, wherein the thin-film transistor comprises: Light-shielding electrodes arranged on the substrate; An active layer is arranged to overlap with the light-shielding electrode and a buffer layer is arranged between the light-shielding electrode and the active layer; A gate electrode disposed between the active layer and the gate insulating layer; The first source-drain electrode and the second source-drain electrode are respectively connected to the first connection region and the second connection region of the active layer through the first contact hole and the second contact hole in the interlayer insulating layer covering the gate insulating layer and the gate electrode, and wherein the at least one fifth virtual electrode includes at least one of the following: a light-shielding metal layer the same as the light-shielding electrode, a gate metal layer the same as the gate electrode, and a source-drain metal layer the same as the first source-drain electrode and the second source-drain electrode.

18. The display device of claim 17, wherein the at least one fifth virtual electrode comprises a hydrogen-capturing metal material, the hydrogen-capturing metal material being included in at least one of the light-shielding metal layer, the gate metal layer, and the source-drain metal layer.

19. The display device of claim 16, wherein the thin-film transistor includes a light-shielding electrode disposed on a substrate; an active layer overlapping the light-shielding electrode and a buffer layer located between the light-shielding electrode and the active layer; a gate electrode disposed between the active layer and a gate insulating layer; and a first source-drain electrode and a second source-drain electrode connected to a first connection region and a second connection region of the active layer through a first contact hole and a second contact hole in the gate insulating layer, respectively, and wherein the at least one fifth virtual electrode includes at least one of the following: a light-shielding metal layer identical to the light-shielding electrode, a gate metal layer identical to the gate electrode, and a source-drain metal layer identical to the first source-drain electrode and the second source-drain electrode.

20. The display device of claim 18, wherein the at least one fifth virtual electrode comprises a hydrogen-capturing metal material, the hydrogen-capturing metal material being included in at least one of the light-shielding metal layer, the gate metal layer, and the source-drain metal layer.

21. The display device according to claim 1, further comprising at least one of the following: a first passivation hole disposed in an upper passivation layer in the display area; and a second passivation hole disposed in the upper passivation layer in at least one of the first and second frame areas, located between the end of each gate line and the gate driving circuit.

22. The display device according to claim 21, further comprising at least one of the following: a sixth virtual electrode disposed in the first passivation hole; and a seventh virtual electrode disposed in the second passivation hole.

23. The display device of claim 21, wherein the first passivation hole overlaps with or is adjacent to at least one of the gate line, the data line, and the thin-film transistor.

24. The display device of claim 22, further comprising at least one of the following: an eighth virtual electrode disposed below the first passivation hole and in contact with the sixth virtual electrode through the first passivation hole; and a ninth virtual electrode disposed below the second passivation hole and in contact with the seventh virtual electrode through the second passivation hole.

25. The display device of claim 24, wherein at least one of the sixth virtual electrode or the seventh virtual electrode is arranged on the same transparent conductive layer as the pixel electrode connected to the thin film transistor, and wherein at least one of the eighth virtual electrode or the ninth virtual electrode is arranged on the same transparent conductive layer as the common electrode overlapping the pixel electrode and the upper passivation layer.

Images