Display panel and preparation method thereof

Abstract

The invention discloses a display panel and a preparation method of the display panel, the display panel comprises a display area and a non-display area arranged on the periphery of the display area, the non-display area comprises a bending area and a step area, the bending area is connected with the display area and the step area, and the display panel further comprises a substrate; the circuit layer is located in the non-display area; the protection layer is arranged on the side, away from the substrate, of the circuit layer and located in the non-display area, the surface, away from the substrate, of the protection layer is provided with a first groove located in the non-display area, and at least part of the first groove is located in the bending area. According to the design, the reliability of the display panel can be improved.

Description

Display panel and its manufacturing method Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Technology

[0002] In recent years, with the development and widespread adoption of display technology, display panels have been applied to various electronic devices, such as mobile phones, tablets, or other portable electronic devices.

[0003] However, the inventors of this application have found that the reliability of current display panels needs further improvement. Summary of the Invention

[0004] This application provides a display panel and a method for manufacturing the display panel, which can improve the reliability of the display panel.

[0005] A first aspect of this application provides a display panel, the display panel including a display area and a non-display area disposed around the display area, the non-display area including a bending area and a step area, the bending area connecting the display area and the step area, the display panel further including: a substrate; a circuit layer located in the non-display area; a protective layer disposed on the side of the circuit layer away from the substrate and located in the non-display area, wherein the surface of the protective layer away from the substrate has a first groove located in the non-display area, at least a portion of the first groove being located in the bending area.

[0006] In one embodiment, the material of the protective layer includes an insulating material.

[0007] Preferably, the insulating material includes at least one of organic insulating materials and inorganic insulating materials.

[0008] In one embodiment, the display panel further includes a pixel definition layer and an array layer located in the display area, the pixel definition layer being located on the side of the array layer facing away from the substrate, wherein the circuit layer and at least a portion of the film layers in the array layer are disposed in the same layer and of the same material.

[0009] Preferably, the protective layer and the film layer on the side of the array layer opposite to the substrate are of the same layer and the same material.

[0010] Preferably, the material of the pixel definition layer includes an inorganic insulating material.

[0011] Preferably, the protective layer is in the same layer as the pixel definition layer and is made of the same material.

[0012] Preferably, the number of conductive sublayers in the circuit layer is less than the number of conductive sublayers in the array layer.

[0013] Preferably, the conductive sublayer furthest from the substrate in the circuit layer of the bending region is in the same layer and made of the same material as the conductive sublayer furthest from the substrate in the array layer of the display region.

[0014] In one embodiment, the orthographic projection of the first groove on the substrate covers the orthographic projection of the circuit layer of the bending region on the substrate.

[0015] Preferably, the first groove is a through groove.

[0016] Preferably, the display panel further includes: an isolation structure disposed on the side of the pixel definition layer away from the substrate and at least partially located in the display area, the pixel definition layer having a pixel opening, the isolation structure having an isolation opening, the pixel opening and the orthographic projection of the isolation opening on the substrate at least partially overlapping, wherein the isolation structure includes a first end near the substrate and a second end away from the substrate, the orthographic projection of the first end on the substrate being located within the orthographic projection of the second end on the substrate.

[0017] In one embodiment, the display panel includes: a first insulating layer disposed on the side of the protective layer away from the substrate and located in the non-display area; the first insulating layer having a second groove, at least a portion of which is located in the bending area.

[0018] Preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate. The touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction away from the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The first insulating layer and the second insulating layer are in the same layer and made of the same material.

[0019] In one embodiment, the second groove is a through groove, and the orthographic projections of the first groove and the second groove on the substrate coincide.

[0020] Preferably, the display panel further includes: a first planarization layer, partially disposed on the side of the first insulating layer opposite to the substrate, and partially extending to the sidewalls of the first groove and the second groove.

[0021] Preferably, the first planarization layer has a third groove, which is a through groove, wherein the orthographic projection of the third groove on the substrate is located within the orthographic projection range of the first groove on the substrate.

[0022] In one embodiment, the second groove is a through groove, and the orthographic projection of the second groove on the substrate covers the orthographic projection of the first groove on the substrate.

[0023] Preferably, the display panel further includes: a first planarization layer disposed on the side of the first insulating layer away from the substrate and located in the non-display area; the first planarization layer has a third groove, the third groove being a through groove, wherein the orthographic projection of the third groove on the substrate coincides with the orthographic projection of the first groove on the substrate.

[0024] Preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate. The touch layer includes a first touch trace layer, a second insulating layer, a second touch trace layer, and a second planarization layer stacked sequentially in the direction away from the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The first planarization layer and the second planarization layer are on the same layer and made of the same material.

[0025] Preferably, the projection of the third groove is within the projection range of the second groove.

[0026] In one embodiment, the circuit layer includes pads located in the stepped area, and the protective layer has a first through-hole exposing the pads.

[0027] Preferably, at least a portion of the protective layer overlaps the surface of the pad on the side opposite to the substrate.

[0028] Preferably, the pad comprises at least two conductive layers stacked together.

[0029] Preferably, the display panel further includes: a first insulating layer, at least partially disposed on the side of the protective layer away from the substrate, and having a second through-hole exposing the pad; wherein the orthographic projection of the first through-hole on the substrate covers the orthographic projection of the second through-hole on the substrate, or the orthographic projections of the second through-hole and the first through-hole on the substrate coincide.

[0030] Preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate. The touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction away from the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The first insulating layer and the second insulating layer are in the same layer and made of the same material.

[0031] Preferably, the display panel further includes a conductive element, at least partially disposed on the side of the pad facing away from the substrate and electrically connected to the pad, wherein the conductive element is on the same layer as the second touch trace layer and is made of the same material.

[0032] A second aspect of this application provides a display panel, the display panel including a display area and a non-display area disposed around the display area, the non-display area including a bending area and a step area, the bending area connecting the display area and the step area, the display panel further including: a substrate; a circuit layer located in the non-display area, the circuit layer including pads located in the step area; a protective layer disposed on the side of the circuit layer away from the substrate, located in the non-display area, wherein the protective layer has a first through-hole exposing the pads.

[0033] In one embodiment, the display panel further includes a pixel definition layer and an array layer located in the display area, the pixel definition layer being located on the side of the array layer facing away from the substrate, wherein the circuit layer and at least a portion of the film layers in the array layer are disposed in the same layer and of the same material.

[0034] Preferably, the protective layer is in the same layer as the pixel definition layer and is made of the same material.

[0035] Preferably, at least a portion of the protective layer overlaps the surface of the pad on the side opposite to the substrate.

[0036] Preferably, the pad comprises at least two conductive layers stacked together.

[0037] Preferably, the display panel further includes: a first insulating layer, at least partially disposed on the side of the protective layer away from the substrate, and having a second through-hole exposing the pad; wherein the orthographic projection of the first through-hole on the substrate covers the orthographic projection of the second through-hole on the substrate, or the orthographic projections of the second through-hole and the first through-hole on the substrate coincide.

[0038] Preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate. The touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction away from the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The first insulating layer and the second insulating layer are in the same layer and made of the same material.

[0039] Preferably, the display panel further includes a conductive element, at least partially disposed on the side of the pad facing away from the substrate and electrically connected to the pad, wherein the conductive element is on the same layer as the second touch trace layer and is made of the same material.

[0040] A third aspect of this application also provides a method for manufacturing a display panel, the display panel including a display area and a non-display area, the method comprising: forming a circuit layer on one side of a substrate, at least a portion of the circuit layer being located in the non-display area; forming a protective layer on the side of the circuit layer facing away from the substrate, the orthogonal projection of the protective layer on the substrate at least covering the orthogonal projection of the circuit layer on the substrate; and forming a first groove on the surface of the protective layer facing away from the substrate, located in the non-display area, wherein at least a portion of the first groove is located in the bending area.

[0041] In one embodiment, the step of forming a protective layer on the side of the circuit layer away from the substrate, wherein the orthogonal projection of the protective layer on the substrate at least covers the orthogonal projection of the circuit layer on the substrate, includes: forming a protective layer on the side of the circuit layer away from the substrate, wherein the orthogonal projection of the protective layer on the substrate at least covers the orthogonal projection of the circuit layer on the substrate, and forming a pixel definition layer on the side of the array layer away from the substrate, wherein the pixel definition layer is made of the same material as the protective layer and is fabricated in the same layer.

[0042] Preferably, a pixel opening located in the display area is formed on the pixel definition layer, an isolation structure is formed on the side of the pixel definition layer opposite to the substrate, and a light-emitting device is formed in the pixel opening, wherein the isolation structure includes an isolation opening, and the pixel opening and the orthographic projection of the isolation opening on the substrate at least partially overlap.

[0043] In one embodiment, the step of forming a first groove in the non-display area on the surface of the protective layer opposite to the substrate includes: forming a first insulating layer on the side of the protective layer opposite to the substrate, wherein the first insulating layer is at least partially located in the bending area; and simultaneously patterning the first insulating layer and the protective layer to form the first groove and a second groove penetrating the first insulating layer.

[0044] Preferably, after simultaneously patterning the first insulating layer and the protective layer, forming the first groove and the second groove penetrating the first insulating layer, the method further includes: forming a first planarization layer on the side of the first insulating layer away from the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the first groove and the second groove; and patterning the first planarization layer to remove at least a portion of the first planarization layer located in the bending region.

[0045] Preferably, the step of forming a first insulating layer on the side of the protective layer away from the substrate, wherein the first insulating layer is at least partially located in the bending region, further includes: forming a first insulating layer on the side of the protective layer away from the substrate, and forming a second insulating layer in the touch layer on the side of the pixel definition layer away from the substrate, wherein the first insulating layer is at least partially located in the bending region, the touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer sequentially stacked in the direction away from the substrate, the first touch trace layer and the second touch trace layer are both at least partially located in the display area, wherein the first insulating layer and the second insulating layer are in the same layer and made of the same material.

[0046] Preferably, before the step of forming a first groove in the non-display area on the surface of the protective layer away from the substrate, the method includes: forming an isolation structure on the side of the pixel definition layer away from the substrate.

[0047] In one embodiment, the step of forming a first groove in the non-display area on the surface of the protective layer opposite to the substrate includes: forming a first insulating layer on the side of the protective layer opposite to the substrate, wherein the first insulating layer is at least partially located in the bending region; patterning the first insulating layer to form a second groove located in the bending region and penetrating the first insulating layer; forming a first planarization layer on the side of the first insulating layer opposite to the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the second groove; and simultaneously patterning the first planarization layer and the protective layer using a patterning process to form the first groove and a third groove penetrating the first planarization layer.

[0048] Preferably, the step of forming a first planarization layer on the side of the first insulating layer away from the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the second groove, includes: forming a first planarization layer on the side of the first insulating layer away from the substrate, and forming a second planarization layer in the touch layer on the side of the pixel definition layer away from the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the second groove, the touch layer includes a first touch trace layer, a second insulating layer, a second touch trace layer and a second planarization layer sequentially stacked in the direction away from the substrate, the first touch trace layer and the second touch trace layer are both at least partially located in the display area, wherein the first planarization layer and the second planarization layer are in the same layer and made of the same material.

[0049] Preferably, before the step of forming a first groove in the non-display area on the surface of the protective layer away from the substrate, the method includes: forming an isolation structure on the side of the pixel definition layer away from the substrate.

[0050] In one embodiment, the non-display area further includes a step area, the bend area connects the display area and the step area, the circuit layer includes pads located in the step area, and the method further includes: forming a first via on the protective layer to expose the pads.

[0051] Preferably, before the step of forming a first via on the protective layer to expose the pad, the method includes: forming an isolation structure on the side of the pixel definition layer opposite to the substrate.

[0052] Preferably, at least a portion of the protective layer overlaps the surface of the pad on the side opposite to the substrate.

[0053] Preferably, the pad comprises at least two conductive layers stacked together.

[0054] Preferably, after forming the first via exposing the pad on the protective layer, the method further includes: forming a first insulating layer on the side of the protective layer away from the substrate, the first insulating layer being at least located in the step region and filling the first via; patterning the first insulating layer to form a second via exposing the pad, wherein the orthographic projection of the first via on the substrate covers the orthographic projection of the second via on the substrate; or, the step of forming the first via exposing the pad on the protective layer includes: forming a first insulating layer on the side of the protective layer away from the substrate, the first insulating layer being at least located in the step region; simultaneously patterning the first insulating layer and the protective layer to form a second via penetrating the first insulating layer and a first via penetrating the protective layer to expose the pad.

[0055] Preferably, after forming the first via on the protective layer to expose the pad, the method includes: forming a conductive element on the side of the pad away from the substrate, and forming a second touch trace layer in the touch layer on the side of the pixel definition layer away from the substrate. The touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction away from the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The conductive element is in the same layer as the second touch trace layer and is made of the same material.

[0056] Unlike existing technologies, the advantages of this application are as follows: This application sets a pixel definition layer on the side of the circuit layer away from the substrate in the non-display area. The pixel definition layer can prevent damage to the circuit layer during the etching of the vapor deposition layer, thereby improving the reliability of the display panel. At the same time, after etching the vapor deposition layer, a first groove is etched on the pixel definition layer. The first groove is at least partially set in the bending area, which makes the overall thickness of the bending area smaller and can ensure that the bending area has better bending performance. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0058] Figure 1 is a top view of one embodiment of the display panel of this application;

[0059] Figure 2 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the first application scenario;

[0060] Figure 3 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the second application scenario;

[0061] Figure 4 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the third application scenario;

[0062] Figure 5 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the fourth application scenario;

[0063] Figure 6 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the fifth application scenario;

[0064] Figure 7 is a cross-sectional view of the display panel in Figure 1 along section lines M to M' in the sixth application scenario;

[0065] Figure 8 is a flowchart illustrating one embodiment of the method for manufacturing the display panel of this application;

[0066] Figure 9 is a structural schematic diagram of one embodiment of step S100 in Figure 8;

[0067] Figure 10 is a structural schematic diagram of one embodiment of step S200 in Figure 8;

[0068] Figure 11 is a structural schematic diagram of one embodiment of step S300 in Figure 8;

[0069] Figure 12 is a flowchart illustrating one embodiment of step S200 in Figure 8;

[0070] Figure 13 is a structural schematic diagram of one embodiment of step S210 in Figure 12;

[0071] Figure 14 is a structural schematic diagram of one embodiment of step S220 in Figure 12;

[0072] Figure 15 is a flowchart illustrating the first embodiment of step S400 in Figure 8;

[0073] Figure 16 is a structural schematic diagram of one embodiment of step S411 in Figure 15;

[0074] Figure 17 is a structural schematic diagram of one embodiment of step S412 in Figure 15;

[0075] Figure 18 is a structural schematic diagram of one embodiment of step S413 in Figure 15;

[0076] Figure 19 is a structural schematic diagram of one embodiment of step S414 in Figure 15;

[0077] Figure 20 is a flowchart illustrating the second embodiment of step S400 in Figure 8;

[0078] Figure 21 is a structural schematic diagram of one embodiment of step S421 in Figure 20;

[0079] Figure 22 is a structural schematic diagram of one embodiment of step S422 in Figure 20;

[0080] Figure 23 is a structural schematic diagram of one embodiment of step S423 in Figure 20;

[0081] Figure 24 is a structural schematic diagram of one embodiment of step S424 in Figure 20;

[0082] Figure 25 is a flowchart illustrating the first embodiment of step S500;

[0083] Figure 26 is a structural schematic diagram of one embodiment of step S510 in Figure 25;

[0084] Figure 27 is a structural schematic diagram of one embodiment of step S520 in Figure 25;

[0085] Figure 28 is a flowchart illustrating the second implementation of step S500. Detailed Implementation

[0086] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0087] Referring to Figure 1, a first aspect of this application provides a display panel 10, which includes a display area AA and a non-display area NA disposed around the display area AA. The non-display area NA includes a bending area BA and a step area SA. The bending area BA connects the display area AA and the step area SA. The bending area BA of the display panel 10 is connected to the step area SA and is used to bend the step area SA to the non-display surface of the display panel 10, thereby reducing the display bezel of the display panel 10. The step area SA can be used for bonding connection with a flexible circuit board (not shown).

[0088] Referring to Figure 2, the display panel 10 also includes a substrate 110, a circuit layer 120, and a protective layer 130. The circuit layer 120 is located in the non-display area NA.

[0089] Specifically, the circuit layer 120 includes at least one conductive layer, and an insulator layer is provided between the conductive layers. The circuit layer 120 is used to transmit electrical signals, and the film structure of the circuit layer 120 can be different in different areas of the display panel 10. For example, the circuit layer 120 includes a first inorganic insulator layer 121, a second inorganic insulator layer 122, a first organic insulator layer 123, and a second organic insulator layer 124 stacked together. The first inorganic insulator layer 121 and the second inorganic insulator layer 122 are outside the bending area BA. The first conductive layer 125 is located between the first inorganic insulator layer 121 and the second inorganic insulator layer 122, and the second conductive layer 126 is located between the first organic insulator layer 123 and the second inorganic insulator layer 124. The third conductive layer 127 is located between the first organic insulator layer 123 and the second organic insulator layer 122, and is electrically connected to the first conductive layer 125 through a via formed in the second inorganic insulator layer 122. The third conductive layer 127 is located between the first organic insulator layer 123 and the second organic insulator layer 124, and is electrically connected to the second conductive layer 126 through a via formed in the first organic insulator layer 123. The first conductive layer 125 and the second conductive layer 126 are both located outside the bending area BA. The third conductive layer 127 passes through the entire bending area BA, and its two ends extend outside the bending area BA and are electrically connected to the second conductive layer 126. It can be seen that the structure of the line layer 120 at different positions in the non-display area NA is different.

[0090] In the display area AA, the display panel 10 includes a substrate 110, an array layer 140 and a pixel definition layer 132 stacked in sequence. The display panel 10 also includes a light-emitting device 100, which is disposed in a pixel opening T defined by the pixel definition layer 132. The array layer 140 forms a pixel circuit (e.g., a 7T1C circuit) for driving the light-emitting device 100 to emit light.

[0091] Furthermore, the display panel 10 also includes an isolation structure 150 located on the side of the pixel definition layer 132 facing away from the substrate 110, and at least partially located in the display area AA. The pixel definition layer 130 is provided with a pixel opening T, and the isolation structure 150 is provided with an isolation opening K. The orthographic projections of the pixel opening T and the isolation opening K on the substrate 110 at least partially overlap. The isolation structure 150 includes a first end A1 close to the substrate 110 and a second end A2 facing away from the substrate 110. The orthographic projection of the first end A1 on the substrate 110 is located within the orthographic projection of the second end A2 on the substrate 110.

[0092] Specifically, in the display area AA, the pixel opening T in the pixel definition layer 132 is used to set the light-emitting device 100. The light-emitting device 100 includes a first electrode 101, a light-emitting material layer 102, and a second electrode 103 stacked sequentially. The first electrode 101 is located between the light-emitting material layer 102 and the substrate 110. At least a portion of the second electrode 103 extends into the isolation opening K and overlaps with the isolation structure 150 to achieve electrical connection. The orthographic projection of the first end A1 of the isolation structure 150 on the substrate 110 is located within the orthographic projection of the second end A2 on the substrate 110. When fabricating the light-emitting device 100, adjacent light-emitting devices 100 can be better separated by the isolation structure 150. When etching the vapor deposition film layer, the second end A2 can block the portion of the second electrode 103 overlapping with the isolation structure 150 from being etched. In addition, the isolation structure 150 can isolate the vapor deposition film layer when fabricating the light-emitting device 100 through the vapor deposition process, thereby forming an independent light-emitting device 100.

[0093] Further, referring to FIG2, the protective layer 130 is disposed on the side of the circuit layer 120 away from the substrate 110. The protective layer 130 is located in the non-display area NA. The surface of the protective layer 130 away from the substrate 110 is provided with a first groove C1 located in the non-display area NA. At least a portion of the first groove C1 is located in the bending area BA.

[0094] Specifically, the traditional method of directly fabricating light-emitting devices using a fine metal mask vapor deposition process does not require etching. However, the method of fabricating light-emitting devices 100 using vapor deposition plus photolithography involves full-area vapor deposition. After the film layer of the light-emitting device 100 is deposited, the deposited film layer in the non-light-emitting areas (including the outer area of ​​the light-emitting device 100 in the display area AA and the non-display area NA) needs to be etched to retain only the light-emitting device 100 in the pixel opening T. However, the outer area of ​​the light-emitting device 100 in the display area AA is etched. At the same time, etching can also damage the circuitry of the line layer 120 in the non-display area NA, thereby reducing the reliability of the display panel 10. Before etching the vapor deposition layer, this application provides a protective layer 130 covering the line layer 120 on the non-display area NA to block etching during the etching process and protect the underlying line layer 120. It can be understood that the protective layer 130 can be provided in a local area of ​​the non-display area NA to protect the conductive lines in the line layer 120, or it can be provided in the entire area of ​​the non-display area NA. After etching the vapor-deposited film layer (i.e., after the protective layer 130 has completed the protection of the circuit layer 120), this application further etches a portion of the protective layer 130 in the non-display area NA to form a first groove C1. The first groove C1 may be partially etched on the side of the protective layer 130 away from the substrate 110, while the side closer to the substrate 110 is retained. Alternatively, the protective layer 130 may be etched from the side closer to the substrate 110 to the side away from the substrate 110 to form a through groove. The first groove C1 is located at least in the bending area BA, which reduces the overall thickness of the bending area BA, making the bending area BA easier to bend and improving its bending performance. In summary, before etching the vapor-deposited film layer, this application provides a protective layer 130 on the circuit layer 120 of the non-display area NA. During the etching of the vapor-deposited film layer, the protective layer 130 is used to shield the etching process, thereby protecting the circuit layer 120. After etching the vapor-deposited film layer, the first groove C1 is etched through an etching process to reduce the film thickness of the bending area BA, thereby improving the bending performance.

[0095] In one embodiment, the material of the protective layer 130 includes an insulating material. By providing an insulating material, the impact on the circuit layer 120 can be reduced.

[0096] Furthermore, the insulating material includes at least one of organic insulating materials and inorganic insulating materials. Organic insulating materials include photoresist, and inorganic insulating materials include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0097] In one embodiment, referring to FIG2, at least a portion of the film layers in the circuit layer 120 and the array layer 140 are disposed in the same layer and made of the same material.

[0098] Specifically, some conductive sublayers in the circuit layer 120 and some conductive sublayers in the array layer 140 can be made of the same layer and the same material. "Mutual layer and same material" means that the conductive sublayers in the circuit layer 120 and the array layer 140 are fabricated using the same process. This reduces manufacturing costs and also helps to reduce the thickness of the display panel 10. Furthermore, the insulator layers in the circuit layer 120 and the insulator layers in the array layer 140 can also be made of the same layer and the same material. For example, in the display area AA, the array layer 140 includes a first inorganic insulator layer 121, a second inorganic insulator layer 122, a third inorganic insulator layer 141, a first organic insulator layer 123, and a second organic insulator layer 124, which are sequentially stacked on one side of the substrate 110. A polycrystalline silicon layer 142 is located between the substrate 110 and the first inorganic insulator layer 121. A first conductive layer 125 is located between the first inorganic insulator layer 121 and the second inorganic insulator layer 122. A second conductive layer 126 is located between the third inorganic insulator layer 141 and the first organic insulator layer 123. A third conductive layer 127 is located between the first organic insulator layer 123 and the second organic insulator layer 124. A capacitor layer 143 is located between the second inorganic insulator layer 122 and the third inorganic insulator layer 141. It can be seen that at least some of the film layers in the array layer 140 and the circuit layer 120 can be disposed in the same layer and with the same material. It should be noted that the array layer 140 and the circuit layer 120 in Figure 2 are only one possible implementation. The specific film layers of the array layer 140 and the circuit layer 120 can also be other, and there can be other options for the arrangement of the same layer and the same material.

[0099] In one embodiment, referring to FIG2, the protective layer 130 and the array layer 140 on the side opposite to the substrate 110 are the same layer and made of the same material.

[0100] Specifically, the protective layer 130 is made of the same material as the second organic insulator layer 124 and is prepared in the same layer. Since the first groove C1 is formed in the protective layer 130 in the bending region BA, the thickness of the second organic insulator layer 124 plus the protective layer 130 in the bending region BA is less than the thickness of the second organic insulator layer 124 plus the protective layer 130 in the non-bending region.

[0101] In one embodiment, referring to FIG3, the pixel definition layer 132 is made of an inorganic insulating material, including silicon oxide, silicon nitride, and silicon oxynitride. Furthermore, the protective layer 130 is co-layered with the pixel definition layer 132 and made of the same material. It is understood that in this embodiment, a separate process for fabricating the protective layer 130 is no longer required. The protective layer 130 in the non-display area NA can be fabricated simultaneously with the pixel definition layer 132 of the display area AA, thus combining the two layers into a single fabrication, reducing fabrication costs.

[0102] In one embodiment, referring to FIG3, the number of conductive sublayers in the line layer 120 is less than the number of conductive sublayers in the array layer 140. The array layer 140 includes pixel driving circuits, such as 7T1C, 8T2C, etc., and the circuit complexity is much higher than that of the line layer 120. Therefore, the array layer 140 requires more conductive sublayers to set up the circuits, so the overall thickness of the line layer 120 is less than the thickness of the array layer 140.

[0103] Further referring to Figure 3, the conductive sublayer furthest from the substrate 110 in the circuit layer 120 of the bending region BA is on the same layer and made of the same material as the conductive sublayer furthest from the substrate 110 in the array layer 140 of the display region AA. It is understood that, in order to protect the circuit layer 120, and more specifically, to protect the conductive sublayer furthest from the substrate 110 in the circuit layer 120 of the bending region BA, when the protective layer 130 prepared on the circuit layer 120 uses the same layer process as the film layer in the display region AA, it is necessary to select from the film layers that need to be further prepared after the conductive sublayer furthest from the substrate 110 in the array layer 140 of the display region AA is prepared, and to prepare the protective layer 130 simultaneously with the film layer prepared in the display region AA using the same layer process.

[0104] In one embodiment, referring to FIG3, the orthographic projection of the first groove C1 on the substrate 110 covers the orthographic projection of the circuit layer 120 of the bending region BA on the substrate 110.

[0105] Specifically, by thinning all the protective layers 130 on the side of the circuit layer 120 in the bending region BA that are away from the substrate 110, the bending effect at each position in the bending region BA is ensured to be consistent.

[0106] In one embodiment, referring to FIG3, the first groove C1 is a through groove, meaning that the protective layer 130 in the bending area BA is completely etched away. This avoids the influence of the thickness of the protective layer 130 on the bending of the bending area BA, resulting in the best bending effect of the bending area BA. Of course, it is understood that in some other embodiments, the first groove C1 may not be a through groove.

[0107] In one embodiment, referring to FIG4, the display panel 10 includes a first insulating layer 160, which is disposed on the side of the protective layer 130 away from the substrate 110. The first insulating layer 160 is located in the non-display area NA, and the first insulating layer 160 is provided with a second groove C2, at least a portion of which is located in the bending area BA.

[0108] Specifically, in the non-display area NA, a first insulating layer 160 is formed on the surface of the protective layer 130 facing away from the substrate 110. The material of the first insulating layer 160 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first insulating layer 160 can further protect the circuit layer 120 in the non-display area NA. At the same time, the first insulating layer 160 also has a second groove C2, which is at least formed in the bending area BA. This prevents the film thickness in the bending area BA from increasing, thereby ensuring the bending performance of the bending area BA.

[0109] In one embodiment, referring to FIG4, the display panel 10 includes a touch layer 170 disposed on the side of the pixel definition layer 132 away from the substrate 110. The touch layer 170 includes a first touch wiring layer 171, a second insulating layer 172 and a second touch wiring layer 173 stacked sequentially in the direction away from the substrate 110. The first touch wiring layer 171 and the second touch wiring layer 173 are at least partially located in the display area AA. The first insulating layer 160 and the second insulating layer 172 are in the same layer and made of the same material.

[0110] Specifically, after the pixel definition layer 132 is fabricated, an encapsulation layer 180 is fabricated on the entire surface of the display area AA, and then a touch layer 170 is fabricated. The touch layer 170 forms a touch structure through the first touch wiring layer 171 and the second touch wiring layer 173. The second insulating layer 172 plays an insulating role in the touch layer 170. The material of the second insulating layer 172 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. Since the first insulating layer 160 and the second insulating layer 172 are fabricated after the pixel definition layer 132 (i.e. after the protective layer 130), the second insulating layer 172 can be fabricated together when the first insulating layer 160 is fabricated. This reduces the coating process and thus reduces the fabrication cost.

[0111] In one embodiment, referring to FIG4, the second groove C2 is a through groove, and the orthographic projections of the first groove C1 and the second groove C2 on the substrate 110 coincide.

[0112] Specifically, the second groove C2 and the first groove C1 have the same shape and size, and their orthogonal projections on the substrate 110 coincide. Therefore, the protective layer 130 does not need to form the first groove C1 separately by etching. The first groove C1 can be etched together when the first insulating layer 160 etches the second groove C2. This reduces the manufacturing cost of the display panel 10. At the same time, considering that the second groove C2 and the first groove C1 are etched using the same etching process, the sidewalls of the second groove C2 and the first groove C1 are aligned.

[0113] In one embodiment, referring to FIG5, the display panel 10 further includes a first planarization layer 190, which is partially disposed on the side of the first insulating layer 160 away from the substrate 110 and partially extends to the sidewalls of the first groove C1 and the second groove C2.

[0114] Specifically, the first planarization layer 190 has a planarization effect on the surface it covers, and the first planarization layer 190 further covers the sidewalls of the first groove C1 and the second groove C2 to achieve a better covering effect. The material of the first planarization layer 190 includes organic adhesive.

[0115] In one embodiment, referring further to FIG5, the first planarization layer 190 is provided with a third groove C3, which is a through groove. The orthographic projection of the third groove C3 on the substrate 110 is within the orthographic projection range of the first groove C1 on the substrate 110. It can be understood that the third groove C3 is a barrel groove, which can avoid the presence of the first planarization layer 190 in the bending region BA from affecting the bending performance of the bending region BA.

[0116] In one embodiment, referring to FIG6, the second groove C2 is a through groove, and the orthographic projection of the second groove C2 on the substrate 110 covers the orthographic projection of the first groove C1 on the substrate 110.

[0117] Specifically, when etching grooves in the protective layer 130 and the first insulating layer 160, it can be done in two steps, and the second groove C2 etched is larger than the first groove C1.

[0118] In one embodiment, referring to FIG6, the display panel 10 further includes a first planarization layer 190, which is disposed on the side of the first insulating layer 160 away from the substrate 110 and is at least partially located in the non-display area NA. The first planarization layer 190 is provided with a third groove C3, which is a through groove, wherein the orthographic projection of the third groove C3 on the substrate 110 coincides with the orthographic projection of the first groove C1 on the substrate 110.

[0119] Specifically, the first planarization layer 190 has a third groove C3 in the non-display area NA, especially in the bending area BA. The third groove C3 is a through groove, thereby preventing the first planarization layer 190 from affecting the bending performance of the bending area BA. The orthographic projection of the third groove C3 on the substrate 110 coincides with the orthographic projection of the first groove C1 on the substrate 110. Therefore, when the protective layer 130 etches the first groove C1 and the first planarization layer 190 etches the third groove C3, the two etching processes are combined into one etching process. The sidewalls of the third groove C3 and the first groove C1 are aligned, which reduces the manufacturing cost of the display panel 10.

[0120] In one embodiment, referring to FIG7, the display panel 10 includes a touch layer 170 disposed on the side of the pixel definition layer 132 facing away from the substrate 110. The touch layer 170 includes a first touch wiring layer 171, a second insulating layer 172, a second touch wiring layer 173 and a second planarization layer 174 stacked sequentially in the direction facing away from the substrate 110. The first touch wiring layer 171 and the second touch wiring layer 173 are at least partially located in the display area AA. The first planarization layer 190 and the second planarization layer 174 are on the same layer and made of the same material.

[0121] Specifically, the second planarization layer 174 is made of organic adhesive. The second planarization layer 174 serves a planarization function, covering the height difference caused by the stacking of the first touch trace layer 171 and the second touch trace layer 173. The first planarization layer 190 and the second planarization layer 174 can be made of the same material and fabricated using the same process. Furthermore, the subsequent protective layer 130 can simultaneously cut out the first groove C1 while the third groove C3 is cut out of the second planarization layer 174; that is, cutting out the first groove C1 and the third groove C3 does not need to be done in two separate steps.

[0122] Furthermore, referring to Figure 7, the projection of the third groove C3 is within the projection range of the second groove C2. This improves the coverage effect of the first planarization layer 190 on the sidewalls of the first insulating layer 160.

[0123] In one embodiment, referring to FIG2, the circuit layer 120 includes pads 128 located in the step region SA, and the protective layer 130 is provided with a first through-hole H1 exposing the pads 128.

[0124] Specifically, during the etching of the vapor-deposited film layer, the step region SA is also etched at the same time. A protective layer 130 is set in the step region SA to protect the pads 128 located in the step region SA. However, considering that the pads 128 in the step region SA need to be electrically connected to the flexible circuit board in the future, after the etching of the vapor-deposited film layer is completed, the protective layer 130 on the surface of the pads 128 needs to be etched away to form the first through hole H1 to expose the surface of the pads 128.

[0125] In one embodiment, referring to FIG2, at least a portion of the protective layer 130 overlaps the surface of the pad 128 on the side opposite to the substrate 110. Thus, the protective layer 130 can cover a portion of the pad 128. For example, in FIG2, the protective layer 130 covers the edge of the pad 128, exposing the middle area of ​​the pad 128.

[0126] In one embodiment, referring to FIG. 2, the pad 128 includes at least two conductive sublayers stacked together. Specifically, the pad 128 may have at least two conductive sublayers directly contacting each other for electrical connection. For example, the second conductive sublayer 126 and the third conductive sublayer 127 in the figure are configured to increase the height of the pad 128 and increase the contact surface for electrical connection. This application does not limit the specific film layers in the pad 128 to the conductive sublayers.

[0127] In one embodiment, referring to FIG4, the display panel 10 further includes a first insulating layer 160, which is at least partially disposed on the side of the protective layer 130 away from the substrate 110, and has a second through hole H2 with exposed pads 128; wherein the orthographic projections of the second through hole H2 and the first through hole H1 on the substrate 110 coincide.

[0128] Specifically, the walls of the second through hole H2 and the first through hole H1 are aligned. During the fabrication process, the first through hole H1 and the second through hole H2 can be etched simultaneously in one etching process, thus saving the fabrication cost of the display panel 10. In some embodiments, the first groove C1 and the second groove C2 in the bending region BA, and the first through hole H1 and the second through hole H2 in the step region SA can be etched simultaneously.

[0129] In one embodiment, referring to FIG6, the display panel 10 further includes a first insulating layer 160, which is at least partially disposed on the side of the protective layer 130 away from the substrate 110, and has a second through hole H2 with exposed pads 128; wherein the orthographic projection of the first through hole H1 on the substrate 110 covers the orthographic projection of the second through hole H2 on the substrate 110.

[0130] Specifically, the protective layer 130 comprises organic materials and has low water resistance and hardness. A first insulating layer 160 is disposed on the surface of the protective layer 130 facing away from the substrate 110. The first insulating layer 160 comprises inorganic materials and has high water resistance and hardness, thus providing better protection when covering the surface of the protective layer 130. The orthogonal projection of the first through-hole H1 onto the substrate 110 covers the orthogonal projection of the second through-hole H2 onto the substrate 110. That is, the first insulating layer 160 can further extend to the sidewall of the protective layer 130 to achieve a more comprehensive coverage effect.

[0131] In one embodiment, referring to Figures 4 and 6, the first insulating layer 160 and the second insulating layer 172 in the stepped region SA are disposed of in the same layer and with the same material.

[0132] In one embodiment, referring to Figures 5 and 7, the display panel 10 further includes a conductive element 200, which is at least partially disposed on the side of the pad 128 away from the substrate 110 and electrically connected to the pad 128, wherein the conductive element 200 is on the same layer as the second touch trace layer 173 and is made of the same material.

[0133] Specifically, the conductive element 200 is disposed on the surface of the pad 128, which can increase the height of the electrical connection of the pad 128 and facilitate subsequent bonding connection with the flexible circuit board. Since the second touch trace layer 173 is after the second insulating layer 172 during the preparation of the touch layer 170, and both the second touch trace layer 173 and the conductive element 200 include conductive materials, the conductive element 200 can be prepared simultaneously when the second touch trace layer 173 is prepared, thereby reducing the preparation cost of the display panel 10.

[0134] Referring to Figure 2, this application also provides a display panel 10. The display panel 10 includes a display area AA and a non-display area NA disposed around the display area AA. The non-display area NA includes a bending area BA and a step area SA. The bending area BA connects the display area AA and the step area SA. The display panel 10 also includes a substrate 110, a circuit layer 120, and a protective layer 130. The circuit layer 120 is located in the non-display area NA and includes pads 128 located in the step area SA. The protective layer 130 is disposed on the side of the circuit layer 120 away from the substrate 110 and located in the non-display area NA. The protective layer 130 has a first through-hole H1 exposing the pads 128. The protective layer 130 is used to protect the circuit layer 120 from etching. The protective layer 130 has a first through-hole H1 on the surface of the pads 128 away from the substrate 110 to expose at least a portion of the surface of the pads 128. The specific principle can be found in the above embodiments.

[0135] In one embodiment, referring to FIG2, at least a portion of the film layers in the circuit layer 120 and the array layer 140 are disposed in the same layer and made of the same material.

[0136] Specifically, some conductive sublayers in the circuit layer 120 and some conductive sublayers in the array layer 140 can be made of the same layer and the same material. "Same layer and same material" means that the conductive sublayers in the circuit layer 120 and the array layer 140 are fabricated using the same process. This reduces manufacturing costs and also helps to reduce the thickness of the display panel 10. For a more detailed description, please refer to the embodiments described above.

[0137] In one embodiment, referring to FIG3, the protective layer 130 and the pixel definition layer 132 are in the same layer and made of the same material. It is understood that in this embodiment, a separate process is no longer required to prepare the protective layer 130. The protective layer 130 in the non-display area NA can be prepared at the same time as the pixel definition layer 132 of the display area AA. By combining the two film layers into one preparation, the preparation cost can be reduced.

[0138] In one embodiment, referring to FIG2, at least a portion of the protective layer 130 overlaps the surface of the pad 128 on the side opposite to the substrate 110. Thus, the protective layer 130 can cover a portion of the pad 128. For example, in FIG2, the protective layer 130 covers the edge of the pad 128, exposing the middle area of ​​the pad 128.

[0139] In one embodiment, referring to FIG. 2, the pad 128 includes at least two conductive sublayers stacked together. Specifically, the pad 128 may have at least two conductive sublayers directly contacting each other for electrical connection. For example, the second conductive sublayer 126 and the third conductive sublayer 127 in the figure are configured to increase the height of the pad 128 and increase the contact surface for electrical connection. This application does not limit the specific film layers in the pad 128 to the conductive sublayers.

[0140] In one embodiment, referring to FIG4, the display panel 10 further includes a first insulating layer 160, which is at least partially disposed on the side of the protective layer 130 away from the substrate 110, and has a second through hole H2 with exposed pads 128; wherein the orthographic projections of the second through hole H2 and the first through hole H1 on the substrate 110 coincide.

[0141] Specifically, the walls of the second through hole H2 and the first through hole H1 are aligned. During the fabrication process, the first through hole H1 and the second through hole H2 can be etched simultaneously in one etching process, thus saving the fabrication cost of the display panel 10. In some embodiments, the first groove C1 and the second groove C2 in the bending region BA, and the first through hole H1 and the second through hole H2 in the step region SA can be etched simultaneously.

[0142] In one embodiment, referring to FIG6, the display panel 10 further includes a first insulating layer 160, which is at least partially disposed on the side of the protective layer 130 away from the substrate 110, and has a second through hole H2 with exposed pads 128; wherein the orthographic projection of the first through hole H1 on the substrate 110 covers the orthographic projection of the second through hole H2 on the substrate 110.

[0143] Specifically, the protective layer 130 comprises organic materials and has low water resistance and hardness. A first insulating layer 160 is disposed on the surface of the protective layer 130 facing away from the substrate 110. The first insulating layer 160 comprises inorganic materials and has high water resistance and hardness, thus providing better protection when covering the surface of the protective layer 130. The orthogonal projection of the first through-hole H1 on the substrate 110 covers the orthogonal projection of the second through-hole H2 on the substrate 110. That is, the first insulating layer 160 can further extend to the sidewall of the protective layer 130 for more comprehensive coverage.

[0144] In one embodiment, referring to Figures 4 and 6, the first insulating layer 160 and the second insulating layer 172 in the stepped region SA are disposed of in the same layer and with the same material.

[0145] In one embodiment, referring to Figures 5 and 7, the display panel 10 further includes a conductive element 200, which is at least partially disposed on the side of the pad 128 away from the substrate 110 and electrically connected to the pad 128, wherein the conductive element 200 is on the same layer as the second touch trace layer 173 and is made of the same material.

[0146] Specifically, the conductive element 200 is disposed on the surface of the pad 128, which can increase the height of the electrical connection of the pad 128 and facilitate subsequent bonding connection with the flexible circuit board. Since the second touch trace layer 173 is after the second insulating layer 172 during the preparation of the touch layer 170, and both the second touch trace layer 173 and the conductive element 200 include conductive materials, the conductive element 200 can be prepared simultaneously when the second touch trace layer 173 is prepared, thereby reducing the preparation cost of the display panel 10.

[0147] Referring to Figures 1 and 8, a second aspect of this application provides a method for manufacturing a display panel 10, the display panel 10 including a display area AA and a non-display area NA, the method comprising:

[0148] S100: A circuit layer 120 is formed on one side of the substrate 110, and at least a portion of the circuit layer 120 is located in the non-display area NA.

[0149] Specifically, referring to Figure 9, the details of how each conductive sublayer in the circuit layer 120 is fabricated using a patterned process can be found in the embodiments described above, and will not be repeated here.

[0150] S200: A protective layer 130 is formed on the side of the circuit layer 120 away from the substrate 110, and the orthogonal projection of the protective layer 130 on the substrate 110 at least covers the orthogonal projection of the circuit layer 120 on the substrate 110.

[0151] Specifically, referring to Figure 10, a protective layer 130 is prepared on the side of the circuit layer 120 facing away from the substrate. The protective layer 130 covers the circuit layer 120 and is used to protect the circuit layer 120. After this step, a light-emitting device 100 needs to be prepared on the protective layer 130. During the preparation of the light-emitting device 100, considering the risk of etching the circuit layer 120 during the etching process, this application designs the protective layer 130 to protect the circuit layer 120, thereby ensuring the reliability of the display panel 10.

[0152] S300: A first groove C1 is formed on the surface of the protective layer 130 away from the substrate 110, located in the non-display area NA, wherein at least a portion of the first groove C1 is located in the bending area BA.

[0153] Specifically, referring to Figure 11, after the fabrication of the light-emitting device 100 is completed (i.e., after the etching and evaporation of the film layer is completed and the protective layer 130 has completed the protection of the circuit layer 120), the first groove C1 is etched in the protective layer 130 by an etching process. The first groove C1 is at least partially located in the bending region BA, so that the thickness of the bending region BA will not be very large, thus ensuring the bending performance of the bending region BA.

[0154] In one embodiment, referring to FIG12, the above step S200 includes:

[0155] S210: A protective layer 130 is formed on the side of the circuit layer 120 away from the substrate 110, the orthogonal projection of the protective layer 130 on the substrate 110 at least covers the orthogonal projection of the circuit layer 120 on the substrate 110, and a pixel definition layer 132 is formed on the side of the array layer 140 away from the substrate 110, wherein the pixel definition layer 132 and the protective layer 130 are made of the same material and are fabricated in the same layer.

[0156] Specifically, referring to Figure 13, the protective layer 130 and the pixel definition layer 132 are made of the same material and are fabricated in the same layer, covering the entire display area AA and the non-display area NA.

[0157] S220: A pixel opening T located in the display area AA is formed on the pixel definition layer 132, an isolation structure 150 is formed on the side of the pixel definition layer 132 away from the substrate 110, and a light-emitting device 100 is formed in the pixel opening T, wherein the isolation structure 150 includes an isolation opening K, and the pixel opening T and the orthogonal projection of the isolation opening K on the substrate 110 at least partially overlap.

[0158] Specifically, referring to Figure 14, after the protective layer 130 is prepared, the light-emitting device 100 is further prepared. During the preparation of the light-emitting device 100, etching is required to etch the film layer in the non-light-emitting device 100 area. Therefore, the protective layer 130 can protect the circuit layer 120 at this time to prevent the circuit layer 120 from being etched.

[0159] In one embodiment, referring to FIG15, the above step S400 includes:

[0160] S411: A first insulating layer 160 is formed on the side of the protective layer 130 away from the substrate 110, wherein the first insulating layer 160 is at least partially located in the bending region BA.

[0161] Specifically, referring to Figure 16, the first insulating layer 160 is prepared by a deposition process, and the material of the first insulating layer 160 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0162] S412: Simultaneously pattern the first insulating layer 160 and the protective layer 130 to form a first groove C1 and a second groove C2 penetrating the first insulating layer 160.

[0163] Specifically, referring to Figure 17, while the first insulating layer 160 is patterned by etching, the protective layer 130 is also patterned. Therefore, the orthographic projections of the first groove C1 and the second groove C2 on the substrate 110 coincide, and the sidewalls of the first groove C1 and the second groove C2 are aligned.

[0164] In one embodiment, referring to FIG15, after step S412 described above, the method further includes:

[0165] S413: A first planarization layer 190 is formed on the side of the first insulating layer 160 away from the substrate 110, wherein the first planarization layer 190 is at least partially located in the bending region BA and fills the first groove C1 and the second groove C2.

[0166] Specifically, referring to Figure 18, a first planarization layer 190 is prepared on the surface of the display panel 10, which can make the surface of the display panel 10 smoother. The material of the planarization layer 190 includes organic adhesive.

[0167] S414: Pattern the first planarization layer 190 to remove at least a portion of the first planarization layer 190 located in the bend region BA.

[0168] Specifically, referring to Figure 19, at least part of the planarization layer 190 in the bending region BA is removed by etching process to ensure that the overall thickness of the bending region BA is not too thick, thereby ensuring the bending performance of the bending region BA.

[0169] In one embodiment, step S411 further includes:

[0170] Referring to Figure 16, a first insulating layer 160 is formed on the side of the protective layer 130 facing away from the substrate 110, and a second insulating layer 172 is formed in the touch layer 170 on the side of the pixel definition layer 132 facing away from the substrate 110. The first insulating layer 160 is at least partially located in the bending region BA. The touch layer 170 includes a first touch wiring layer 171, a second insulating layer 172, and a second touch wiring layer 173 sequentially stacked in the direction facing away from the substrate 110. Both the first touch wiring layer 171 and the second touch wiring layer 173 are at least partially located in the display region AA. The first insulating layer 160 and the second insulating layer 172 are on the same layer and made of the same material. This reduces the cost of manufacturing the display panel 10.

[0171] Furthermore, prior to the above S400, an isolation structure 150 is formed on the side of the pixel definition layer 132 facing away from the substrate 110. Specifically, after the isolation structure 150 is fabricated, and the protective layer 130, which is fabricated in the same layer as the pixel definition layer 132, has completed its protection of the circuit layer 120, a first groove C1 can be formed in the protective layer 130.

[0172] In one embodiment, referring to FIG20, step S400 above includes:

[0173] S421: A first insulating layer 160 is formed on the side of the protective layer 130 away from the substrate 110, wherein the first insulating layer 160 is at least partially located in the bending region BA.

[0174] Specifically, referring to Figure 21, the first insulating layer 160 is prepared by a deposition process, and the material of the first insulating layer 160 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0175] S422: Pattern the first insulating layer 160 to form a second groove C2 located in the bending region BA and penetrating the first insulating layer 160.

[0176] Specifically, referring to Figure 22, the first insulating layer 160 located at least in the bending region BA is etched away by an etching process to form the second groove C2.

[0177] S423: A first planarization layer 190 is formed on the side of the first insulating layer 160 away from the substrate 110, wherein the first planarization layer 190 is at least partially located in the bending region BA and fills the second groove C2.

[0178] Specifically, referring to Figure 23, a first planarization layer 190 is prepared on the surface of the display panel 10, which can make the surface of the display panel 10 smoother. The material of the planarization layer 190 includes organic adhesive.

[0179] S424: Using a patterning process, the first planarization layer 190 and the protective layer 130 are patterned simultaneously to form a first groove C1 and a third groove C3 that penetrates the first planarization layer 190.

[0180] Specifically, referring to Figure 24, the first planarization layer 190 and the protective layer 130 in the bending area BA are removed simultaneously by etching. This aligns the groove walls of the first groove C1 and the third groove C3, while ensuring that the overall thickness of the bending area BA is not too thick, thereby ensuring the bending performance of the bending area BA.

[0181] In one embodiment, step S421 further includes:

[0182] Referring to Figure 23, a first planarization layer 190 is formed on the side of the first insulating layer 160 facing away from the substrate 110, and a second planarization layer 174 is formed in the touch layer 170 on the side of the pixel definition layer 132 facing away from the substrate 110. The first planarization layer 190 is at least partially located in the bending region BA and fills the second groove C2. The touch layer 170 includes a first touch wiring layer 171, a second insulating layer 172, a second touch wiring layer 173, and a second planarization layer 174, which are sequentially stacked in the direction facing away from the substrate 110. Both the first touch wiring layer 171 and the second touch wiring layer 173 are at least partially located in the display region AA. The first planarization layer 190 and the second planarization layer 174 are on the same layer and made of the same material. This reduces the cost of manufacturing the display panel 10.

[0183] Furthermore, prior to the above S400, an isolation structure 150 is formed on the side of the pixel definition layer 132 facing away from the substrate 110. Specifically, after the isolation structure 150 is fabricated, and the protective layer 130, which is fabricated in the same layer as the pixel definition layer 132, has completed its protection of the circuit layer 120, a first groove C1 can be formed in the protective layer 130.

[0184] In one embodiment, referring to FIG1, the non-display area NA further includes a step area SA, and a bend area BA connects the display area AA and the step area SA. The circuit layer 120 includes pads 128 located in the step area SA. Referring to FIG25, the method of this application further includes:

[0185] S500: A first through-hole H1 with exposed pad 128 is formed on the protective layer 130.

[0186] Specifically, in Figure 10, a protective layer 130 is prepared on the side of the pad 128 away from the substrate 110. The protective layer 130 is coated on the entire surface. To expose the surface of the pad 128 away from the substrate 110, at least part of the protective layer 130 on its surface needs to be removed by etching. The first through hole H1 in Figure 11 can be obtained by etching.

[0187] Furthermore, prior to step S500, the method further includes forming an isolation structure 150 on the side of the pixel definition layer 132 facing away from the substrate 110. Specifically, after the isolation structure 150 is fabricated, and the protective layer 130, which is fabricated in the same layer as the pixel definition layer 132, has completed its protection of the circuit layer 120, a first via H1 can be formed in the protective layer 130.

[0188] In one embodiment, referring to FIG11, at least a portion of the protective layer 130 overlaps the surface of the pad 128 on the side opposite to the substrate 110. Thus, the protective layer 130 can cover a portion of the pad 128. For example, in FIG2, the protective layer 130 covers the edge of the pad 128, exposing the middle area of ​​the pad 128.

[0189] In one embodiment, referring to FIG11, the pad 128 includes at least two conductive sublayers stacked together. Specifically, at least two conductive sublayers can be directly contacted and electrically connected in the pad 128. For example, the second conductive sublayer 126 and the third conductive sublayer 127 in the figure are used, which increases the height of the pad 128 and the contact surface for electrical connection. This application does not limit the specific film layers in the pad 128 to the conductive sublayers.

[0190] In one embodiment, referring to FIG25, after step S500 described above, the method further includes:

[0191] S510: A first insulating layer 160 is formed on the side of the protective layer 130 away from the substrate 110. The first insulating layer 160 is at least located in the step region SA and fills the first through hole H1.

[0192] Specifically, referring to Figure 26, the first insulating layer 160 is formed by a deposition process, and the first insulating layer 160 and the second insulating layer 172 of the touch layer 170 can be prepared in the same process.

[0193] S520: Pattern the first insulating layer 160 to form a second via H2 of exposed pad 128, wherein the orthogonal projection of the first via H1 on the substrate 110 covers the orthogonal projection of the second via H2 on the substrate 110.

[0194] Specifically, referring to Figure 27, the second via H2 etched by the etching process is smaller than the first via H1. Therefore, the first insulating layer 160 can not only cover the surface of the pixel definition layer 130 away from the substrate 110, but also cover the sidewall of the protective layer 130.

[0195] In one embodiment, referring to FIG28, step 500 above includes:

[0196] S501: A first insulating layer 160 is formed on the side of the protective layer 130 away from the substrate 110, and the first insulating layer 160 is located at least in the step region SA.

[0197] Specifically, referring to Figure 16, the first insulating layer 160 is prepared by a deposition process. The first insulating layer 160 and the second insulating layer 172 of the touch layer 170 can be prepared in the same process. The first insulating layer 160 covers the entire display panel 10.

[0198] S502: Simultaneously pattern the first insulating layer 160 and the protective layer 130 to form a second through hole H2 penetrating the first insulating layer 160 and a first through hole H1 penetrating the protective layer 130 to expose the pad 128.

[0199] Specifically, referring to Figure 17, the protective layer 130 is etched at the same time as the first insulating layer 160, thereby forming the first through hole H1 and the second through hole H2 with aligned hole walls. This can reduce the manufacturing process and lower the manufacturing cost of the display panel 10.

[0200] In one embodiment, after step S500, the method further includes:

[0201] Referring to Figure 18, a conductive element 200 is formed on the side of the pad 128 facing away from the substrate 110, and a second touch trace layer 173 is formed in the touch layer 170 on the side of the pixel definition layer 132 facing away from the substrate 110. The touch layer 170 includes a first touch trace layer 171, a second insulating layer 172, and a second touch trace layer 173 sequentially stacked in the direction facing away from the substrate 110. The first touch trace layer 171 and the second touch trace layer 173 are both at least partially located in the display area AA. The conductive element 200 and the second touch trace layer 173 are in the same layer and made of the same material. By fabricating in the same layer, the manufacturing cost of the display panel 10 can be reduced.

[0202] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area disposed around the display area. The non-display area includes a bending area and a step area. The bending area connects the display area and the step area. The display panel also includes: a substrate; a circuit layer located in the non-display area; and a protective layer disposed on the side of the circuit layer away from the substrate and located in the non-display area. The protective layer has a first groove on its surface away from the substrate located in the non-display area, and at least a portion of the first groove is located in the bending area.

2. The display panel according to claim 1, characterized in that, The material of the protective layer includes an insulating material; preferably, the insulating material includes at least one of organic insulating materials and inorganic insulating materials.

3. The display panel according to claim 1, characterized in that, The display panel further includes a pixel definition layer and an array layer located in the display area. The pixel definition layer is located on the side of the array layer facing away from the substrate. The circuit layer and at least a portion of the film layers in the array layer are disposed in the same layer and made of the same material. Preferably, the protective layer is in the same layer and made of the same material as the film layers on the side of the array layer facing away from the substrate. Preferably, the material of the pixel definition layer includes an inorganic insulating material. Preferably, the protective layer is in the same layer and made of the same material as the pixel definition layer. Preferably, the number of conductive sublayers in the circuit layer is less than the number of conductive sublayers in the array layer. Preferably, the conductive sublayer farthest from the substrate in the circuit layer in the bending region is the same as the conductive sublayer farthest from the substrate in the array layer in the display area. The electronic layers are on the same layer and made of the same material; preferably, the orthographic projection of the first groove on the substrate covers the orthographic projection of the circuit layer on the substrate in the bending area; preferably, the first groove is a through groove; preferably, the display panel further includes: an isolation structure disposed on the side of the pixel definition layer away from the substrate and at least partially located in the display area, the pixel definition layer having a pixel opening, the isolation structure having an isolation opening, the orthographic projection of the pixel opening and the isolation opening on the substrate at least partially overlapping, wherein the isolation structure includes a first end near the substrate and a second end away from the substrate, the orthographic projection of the first end on the substrate being located within the orthographic projection of the second end on the substrate.

4. The display panel according to claim 3, characterized in that, The display panel includes: a first insulating layer disposed on the side of the protective layer away from the substrate and located in the non-display area; the first insulating layer has a second groove, at least a portion of which is located in the bending area; preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate; the touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction away from the substrate; both the first touch trace layer and the second touch trace layer are at least partially located in the display area; wherein the first insulating layer and the second insulating layer are in the same layer and made of the same material.

5. The display panel according to claim 4, characterized in that, The second groove is a through groove, and the orthographic projections of the first groove and the second groove on the substrate coincide. Preferably, the display panel further includes: a first planarization layer, partially disposed on the side of the first insulating layer away from the substrate, and partially extending to the sidewalls of the first groove and the second groove. Preferably, the first planarization layer has a third groove, the third groove being a through groove, wherein the orthographic projection of the third groove on the substrate is within the orthographic projection range of the first groove on the substrate.

6. The display panel according to claim 4, characterized in that, The second groove is a through groove, and the orthographic projection of the second groove on the substrate overlaps the orthographic projection of the first groove on the substrate; preferably, the display panel further includes: a first planarization layer disposed on the side of the first insulating layer away from the substrate, located in the non-display area, the first planarization layer having a third groove, the third groove being a through groove, wherein the orthographic projection of the third groove on the substrate coincides with the orthographic projection of the first groove on the substrate; preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate, the touch layer including a first touch trace layer, a second insulating layer, a second touch trace layer and a second planarization layer sequentially stacked in the direction away from the substrate, the first touch trace layer and the second touch trace layer being at least partially located in the display area, wherein the first planarization layer and the second planarization layer are of the same layer and made of the same material; preferably, the projection of the third groove is within the projection range of the second groove.

7. The display panel according to claim 3, characterized in that, The circuit layer includes pads located in the stepped area, and the protective layer has a first through-hole exposing the pads; preferably, at least a portion of the protective layer overlaps the surface of the pads on the side away from the substrate; preferably, the pads include at least two stacked conductive layers; preferably, the display panel further includes: a first insulating layer, at least partially disposed on the protective layer on the side away from the substrate, and having a second through-hole exposing the pads; wherein, the orthographic projection of the first through-hole on the substrate covers the orthographic projection of the second through-hole on the substrate, or, the orthographic projections of the second through-hole and the first through-hole on the substrate coincide; Preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer opposite to the substrate. The touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer stacked sequentially in the direction opposite to the substrate. The first touch trace layer and the second touch trace layer are both at least partially located in the display area. The first insulating layer and the second insulating layer are on the same layer and made of the same material. Preferably, the display panel further includes a conductive element disposed at least partially on the side of the pads opposite to the substrate and electrically connected to the pads. The conductive element is on the same layer as the second touch trace layer and made of the same material.

8. A display panel, characterized in that, The display panel includes a display area and a non-display area disposed around the display area. The non-display area includes a bending area and a step area. The bending area connects the display area and the step area. The display panel further includes: a substrate; a circuit layer located in the non-display area, the circuit layer including pads located in the step area; and a protective layer disposed on the side of the circuit layer away from the substrate, located in the non-display area. The protective layer has a first through-hole exposing the pads.

9. The display panel according to claim 8, characterized in that, The display panel further includes a pixel definition layer and an array layer located in the display area. The pixel definition layer is located on the side of the array layer facing away from the substrate. The circuit layer and at least a portion of the film layers in the array layer are disposed on the same layer and made of the same material. Preferably, the protective layer is on the same layer as the pixel definition layer and made of the same material. Preferably, the material of the pixel definition layer includes an inorganic insulating material. Preferably, at least a portion of the protective layer overlaps the surface of the pad facing away from the substrate. Preferably, the pad includes at least two stacked conductive layers. Preferably, the display panel further includes a first insulating layer, at least partially disposed on the side of the protective layer facing away from the substrate, and having a second through-hole exposing the pad. The orthographic projection of the first through-hole onto the substrate covers... The orthographic projection of the second via on the substrate, or the orthographic projections of the second via and the first via on the substrate coincide; preferably, the display panel includes a touch layer disposed on the side of the pixel definition layer away from the substrate, the touch layer including a first touch trace layer, a second insulating layer and a second touch trace layer stacked sequentially in the direction away from the substrate, the first touch trace layer and the second touch trace layer are both at least partially located in the display area, wherein the first insulating layer and the second insulating layer are on the same layer and made of the same material; preferably, the display panel further includes a conductive element, at least partially disposed on the side of the pad away from the substrate and electrically connected to the pad, wherein the conductive element is on the same layer and made of the same material as the second touch trace layer.

10. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area. The method includes: forming a circuit layer on one side of a substrate, at least a portion of the circuit layer being located in the non-display area; forming a protective layer on the side of the circuit layer facing away from the substrate, the orthogonal projection of the protective layer on the substrate at least covering the orthogonal projection of the circuit layer on the substrate; forming a first groove in the non-display area on the surface of the protective layer facing away from the substrate, wherein at least a portion of the first groove is located in the bending area.

11. The method according to claim 10, characterized in that, The step of forming a protective layer on the side of the circuit layer away from the substrate, wherein the orthographic projection of the protective layer on the substrate at least covers the orthographic projection of the circuit layer on the substrate, includes: forming a protective layer on the side of the circuit layer away from the substrate, wherein the orthographic projection of the protective layer on the substrate at least covers the orthographic projection of the circuit layer on the substrate; and forming a pixel definition layer on the side of the array layer away from the substrate, wherein the pixel definition layer and the protective layer are made of the same material and are fabricated in the same layer; preferably, a pixel opening located in the display area is formed on the pixel definition layer, an isolation structure is formed on the side of the pixel definition layer away from the substrate, and a light-emitting device is formed in the pixel opening, wherein the isolation structure includes an isolation opening, and the orthographic projection of the pixel opening and the isolation opening on the substrate at least partially overlaps.

12. The method according to claim 11, characterized in that, The step of forming a first groove in the non-display area on the surface of the protective layer away from the substrate includes: forming a first insulating layer on the side of the protective layer away from the substrate, wherein the first insulating layer is at least partially located in the bending region; simultaneously patterning the first insulating layer and the protective layer to form the first groove and a second groove penetrating the first insulating layer; preferably, after simultaneously patterning the first insulating layer and the protective layer to form the first groove and the second groove penetrating the first insulating layer, the step further includes: forming a first planarization layer on the side of the first insulating layer away from the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the first groove and the second groove; patterning the first planarization layer to remove at least a portion of the first planarization layer located in the bending region; preferably, in the protective layer The step of forming a first insulating layer on the side away from the substrate, wherein the first insulating layer is at least partially located in the bending region, further includes: forming a first insulating layer on the side of the protective layer away from the substrate, and forming a second insulating layer in the touch layer on the side of the pixel definition layer away from the substrate, wherein the first insulating layer is at least partially located in the bending region, the touch layer includes a first touch trace layer, a second insulating layer, and a second touch trace layer sequentially stacked in the direction away from the substrate, the first touch trace layer and the second touch trace layer are both at least partially located in the display area, wherein the first insulating layer and the second insulating layer are in the same layer and made of the same material; preferably, before the step of forming a first groove located in the non-display area on the surface of the protective layer away from the substrate, the step includes: forming an isolation structure on the side of the pixel definition layer away from the substrate.

13. The method according to claim 11, characterized in that, The step of forming a first groove in the non-display area on the surface of the protective layer opposite to the substrate includes: forming a first insulating layer on the side of the protective layer opposite to the substrate, wherein the first insulating layer is at least partially located in the bending region; patterning the first insulating layer to form a second groove located in the bending region and penetrating the first insulating layer; forming a first planarization layer on the side of the first insulating layer opposite to the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the second groove; simultaneously patterning the first planarization layer and the protective layer using a patterning process to form the first groove and a third groove penetrating the first planarization layer; preferably, the first planarization layer is formed on the side of the first insulating layer opposite to the substrate, wherein the first planarization layer is at least partially located in the bending region and fills the second groove. The step of forming the second groove includes: forming a first planarization layer on the side of the first insulating layer away from the substrate, and forming a second planarization layer in the touch layer on the side of the pixel definition layer away from the substrate, wherein the first planarization layer is at least partially located in the bending area and fills the second groove, the touch layer includes a first touch trace layer, a second insulating layer, a second touch trace layer and the second planarization layer stacked sequentially in the direction away from the substrate, the first touch trace layer and the second touch trace layer are both at least partially located in the display area, wherein the first planarization layer and the second planarization layer are in the same layer and made of the same material; preferably, before the step of forming the first groove located in the non-display area on the surface of the protective layer away from the substrate, the step includes: forming an isolation structure on the side of the pixel definition layer away from the substrate.

14. The method according to claim 11, characterized in that, The non-display area further includes a stepped area, the bending area connects the display area and the stepped area, the circuit layer includes pads located in the stepped area, and the method further includes: forming a first via on the protective layer to expose the pads; preferably, before the step of forming the first via on the protective layer to expose the pads, the method includes: forming an isolation structure on the side of the pixel definition layer away from the substrate; preferably, at least a portion of the protective layer overlaps the surface of the pads on the side away from the substrate; preferably, the pads include at least two stacked conductive layers; preferably, after forming the first via on the protective layer to expose the pads, the method further includes: forming a first insulating layer on the side of the protective layer away from the substrate, the first insulating layer being at least located in the stepped area and filling the first via; patterning the first insulating layer to form a second via exposing the pads, wherein the orthographic projection of the first via on the substrate covers the second via on the substrate. The orthographic projection; or, the step of forming a first via on the protective layer to expose the pad includes: forming a first insulating layer on the side of the protective layer away from the substrate, the first insulating layer being at least located in the step region; simultaneously patterning the first insulating layer and the protective layer to form a second via penetrating the first insulating layer and a first via penetrating the protective layer to expose the pad; preferably, after the step of forming the first via on the protective layer to expose the pad, the step includes: forming a conductive element on the side of the pad away from the substrate, and forming a second touch trace layer in the touch layer on the side of the pixel definition layer away from the substrate, the touch layer including a first touch trace layer, a second insulating layer and a second touch trace layer stacked sequentially in the direction away from the substrate, the first touch trace layer and the second touch trace layer being at least partially located in the display area, wherein the conductive element and the second touch trace layer are in the same layer and made of the same material.

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