Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: a pixel circuit layer including a first pixel circuit, a second pixel circuit, and a third pixel circuit disposed in the same row; a first light emitting element configured to emit light of a first color, and including a first pixel electrode and a first light emitting layer on the first pixel electrode, the first pixel electrode on the pixel circuit layer and electrically connected to the first pixel circuit; a second light emitting element configured to emit light of the first color and including a second pixel electrode and a second light emitting layer on the second pixel electrode, the second pixel electrode on the pixel circuit layer and electrically connected to the second pixel circuit; and a third light emitting element configured to emit light of a second color different from the first color, and including a third pixel electrode on the pixel circuit layer and electrically connected to the third pixel circuit and a third light emitting layer on the third pixel electrode.

Description

Technical Field

[0001] This disclosure relates to display devices and electronic devices including display devices. More specifically, this disclosure relates to display devices that provide visual information and electronic devices including display devices. Background Technology

[0002] Electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, monitors, and smart TVs, include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen.

[0003] The display device includes multiple pixels for generating images and a driver for driving the pixels. Each pixel includes a light-emitting element and pixel circuitry connected to the light-emitting element. The pixel circuitry is driven by the driver, causing the light-emitting element to emit light. The layout design of the pixel circuitry and the light-emitting element is evolving towards maximizing luminous efficiency while improving resolution within a limited space. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device capable of reducing power consumption.

[0005] Embodiments of this disclosure also provide electronic devices including a display device.

[0006] In one or more embodiments, the display device includes: a pixel circuit layer including a first pixel circuit, a second pixel circuit, and a third pixel circuit disposed in the same row; a first light-emitting element configured to emit light of a first color, and including a first pixel electrode and a first light-emitting layer on the first pixel electrode, the first pixel electrode being on the pixel circuit layer and electrically connected to the first pixel circuit; a second light-emitting element configured to emit light of the first color, and including a second pixel electrode and a second light-emitting layer on the second pixel electrode, the second pixel electrode being on the pixel circuit layer and electrically connected to the second pixel circuit; and a third light-emitting element configured to emit light of a different color than the first color. The light is of a second color and includes a third pixel electrode and a third light-emitting layer on the third pixel electrode, the third pixel electrode being on the pixel circuit layer, electrically connected to the third pixel circuit, and overlapping with each of the first pixel circuit, the second pixel circuit, and the third pixel circuit in a planar view; a first write gate line extending in the pixel circuit layer along a first direction and configured to provide a first write gate signal to the first pixel circuit and the third pixel circuit; and a second write gate line extending in the pixel circuit layer along the first direction and configured to provide a second write gate signal, applied at a timing different from the application timing of the first write gate signal, to the second pixel circuit.

[0007] In one or more embodiments, the third pixel electrode includes: a first main portion that overlaps with a third pixel circuit in a plan view; and a first extension portion that extends from the first main portion and overlaps with each of the first pixel circuit, the second pixel circuit, and the third pixel circuit in a plan view.

[0008] In one or more embodiments, the pixel circuit layer further includes: a fourth pixel circuit electrically connected to the second write gate line; a fifth pixel circuit electrically connected to the first write gate line; and a sixth pixel circuit electrically connected to the second write gate line.

[0009] In one or more embodiments, the second pixel circuit, the first pixel circuit, the third pixel circuit, the fourth pixel circuit, the fifth pixel circuit, and the sixth pixel circuit are arranged repeatedly along a first direction in the order of the second pixel circuit, the first pixel circuit, the third pixel circuit, the fourth pixel circuit, the fifth pixel circuit, and the sixth pixel circuit.

[0010] In one or more embodiments, the display device further includes: a fourth light-emitting element configured to emit light of a second color, and including a fourth pixel electrode and a fourth light-emitting layer on the fourth pixel electrode, the fourth pixel electrode being on a pixel circuit layer and electrically connected to a fourth pixel circuit; a fifth light-emitting element configured to emit light of a third color different from the first and second colors, and including a fifth pixel electrode and a fifth light-emitting layer on the fifth pixel electrode, the fifth pixel electrode being disposed on the pixel circuit layer and electrically connected to the fifth pixel circuit; and a sixth light-emitting element configured to emit light of the third color, and including a sixth pixel electrode and a sixth light-emitting layer on the sixth pixel electrode, the sixth pixel electrode being on the pixel circuit layer and electrically connected to the sixth pixel circuit.

[0011] In one or more embodiments, the fourth pixel electrode includes: a second main portion that overlaps with the sixth pixel circuit in a plan view; and a second extension portion that extends from the second main portion and overlaps with each of the fourth pixel circuit and the fifth pixel circuit.

[0012] In one or more embodiments, the second extension portion of the fourth pixel electrode is spaced apart from the fifth pixel electrode in a plan view and extends along at least a portion of the fifth pixel electrode.

[0013] In one or more embodiments, the sixth pixel electrode includes: a third main portion overlapping each of the first pixel circuit and the second pixel circuit adjacent to the sixth pixel circuit; and a third extension portion extending from the third main portion and overlapping each of the second pixel circuit and the sixth pixel circuit.

[0014] In one or more embodiments, a first extension portion of the third pixel electrode is spaced apart from a third main portion of the sixth pixel electrode in a plan view and extends along at least a portion of the third main portion.

[0015] In one or more embodiments, the display device further includes: a plurality of first auxiliary electrodes on a pixel circuit layer, adjacent to a sixth pixel electrode and arranged along a second direction intersecting a first direction; and a pixel defining layer on the first auxiliary electrodes, wherein an aperture is defined in the pixel defining layer and the aperture exposes the upper surface of at least one of the plurality of first auxiliary electrodes.

[0016] In one or more embodiments, the display device further includes: a plurality of second auxiliary electrodes on the pixel circuit layer, adjacent to the fifth pixel circuit and arranged along a second direction, wherein the pixel defining layer completely covers the upper surface of each of the second auxiliary electrodes.

[0017] In one or more embodiments, the display device further includes: a first data line extending in the pixel circuit layer along a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit; a second data line extending in the pixel circuit layer along the second direction and electrically connected to the third pixel circuit and the fourth pixel circuit; and a third data line extending in the pixel circuit layer along the second direction and electrically connected to the fifth pixel circuit and the sixth pixel circuit.

[0018] In one or more embodiments, the first data line is located between adjacent first pixel circuits and second pixel circuits in a plan view, the second data line is located between adjacent third pixel circuits and fourth pixel circuits in a plan view, and the third data line is located between adjacent fifth pixel circuits and sixth pixel circuits in a plan view.

[0019] In one or more embodiments, the display device includes: a pixel circuit layer including a first pixel circuit, a second pixel circuit spaced apart from the first pixel circuit in a first direction, and a third pixel circuit, a fourth pixel circuit, a fifth pixel circuit, and a sixth pixel circuit arranged sequentially along the first direction between the first pixel circuit and the second pixel circuit; a first light-emitting element configured to emit light of a first color, and including a first pixel electrode and a first light-emitting layer on the first pixel electrode, the first pixel electrode being on the pixel circuit layer and electrically connected to the first pixel circuit; a second light-emitting element configured to emit light of the first color, and including a second pixel electrode and a second light-emitting layer on the second pixel electrode, the second pixel electrode being on the pixel circuit layer, electrically connected to the second pixel circuit, and overlapping with each of the second pixel circuit, the fifth pixel circuit, and the sixth pixel circuit in a plan view; and a third light-emitting element configured to emit light of a second color different from the first color, and including a third pixel electrode and a third light-emitting layer on the third pixel electrode, the third pixel electrode being on the pixel circuit layer and electrically connected to the third pixel circuit.

[0020] In one or more embodiments, the second pixel electrode includes: a main portion that overlaps with the fifth pixel circuit in a plan view; and an extension portion that extends from the main portion along a first direction and overlaps with each of the second pixel circuit and the sixth pixel circuit in a plan view.

[0021] In one or more embodiments, the display device further includes: a first write gate line extending in a pixel circuit layer along a first direction and configured to provide a first write gate signal to each of a first pixel circuit, a third pixel circuit, and a fifth pixel circuit; and a second write gate line extending in the pixel circuit layer along the first direction and configured to provide a second write gate signal, applied at a timing different from the application timing of the first write gate signal, to a second pixel circuit, a fourth pixel circuit, and a sixth pixel circuit.

[0022] In one or more embodiments, the display device further includes: a first data line extending in the pixel circuit layer along a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit; a second data line extending in the pixel circuit layer along the second direction and electrically connected to each of the third pixel circuit and the fourth pixel circuit; and a third data line extending in the pixel circuit layer along the second direction and electrically connected to each of the fifth pixel circuit and the sixth pixel circuit.

[0023] In one or more embodiments, the display device further includes: a fourth light-emitting element configured to emit light of a second color, and including a fourth pixel electrode and a fourth light-emitting layer on the fourth pixel electrode, the fourth pixel electrode being on a pixel circuit layer and electrically connected to a fourth pixel circuit; a fifth light-emitting element configured to emit light of a third color different from the first and second colors, and including a fifth pixel electrode and a fifth light-emitting layer on the fifth pixel electrode, the fifth pixel electrode being on a pixel circuit layer and electrically connected to a fifth pixel circuit; and a sixth light-emitting element configured to emit light of the third color, and including a sixth pixel electrode and a sixth light-emitting layer on the sixth pixel electrode, the sixth pixel electrode being on a pixel circuit layer and electrically connected to a sixth pixel circuit.

[0024] In one or more embodiments, the display device further includes: a plurality of first auxiliary electrodes on a pixel circuit layer, adjacent to a fifth pixel electrode and arranged along a second direction intersecting a first direction; a plurality of second auxiliary electrodes on a pixel circuit layer, adjacent to a sixth pixel circuit and arranged along the second direction; and a pixel defining layer on the first and second auxiliary electrodes, wherein an aperture is defined in the pixel defining layer and the aperture exposes the upper surface of at least one of the first auxiliary electrodes, wherein the pixel defining layer completely covers the upper surface of each of the second auxiliary electrodes, and wherein a virtual line connecting the center of the fifth pixel electrode and the center of the sixth pixel electrode has a zigzag shape along the first direction.

[0025] In one or more embodiments, the electronic device includes: a processor configured to output input image data and input control signals; and the aforementioned display device configured to be driven based on the input image data and input control data.

[0026] In a display device according to an embodiment of the present disclosure, a data voltage can be provided to each of the pixels included in a first pixel group in response to a first write gate signal applied via a first write gate line. Additionally, a data voltage can be provided to each of the pixels included in a second pixel group arranged in the same row as the pixels included in the first pixel group in response to a second write gate signal applied via a second write gate line at a timing different from the application timing of the first write gate signal. Accordingly, the display device can selectively output the data voltage to one of a plurality of pixels arranged in the same row. Consequently, the power efficiency of the display device can be improved, and the number of pixels arranged in the display area of ​​the display device can be increased, thereby improving display quality. Attached Figure Description

[0027] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0029] Figure 2 It is a diagram. Figure 1 A view of a portion of the display device.

[0030] Figure 3 The illustration includes Figure 1 The circuit diagram of the pixels in the display panel.

[0031] Figure 4 It is a diagram. Figure 3 A circuit diagram illustrating an example of pixel manipulation.

[0032] Figure 5 It is a diagram. Figure 3 A circuit diagram of another example of pixel operation.

[0033] Figure 6 , Figure 7 and Figure 8 The illustration includes Figure 1 A layout diagram illustrating an example of the arrangement of pixels in a display panel.

[0034] Figure 9 It is a diagram. Figure 8 A cross-sectional view of each of the A1, A2 and A3 areas.

[0035] Figure 10 The illustration includes Figure 1 Another example of the layout diagram showing the arrangement of pixels in a display panel.

[0036] Figure 11 and Figure 12 The illustration includes Figure 1 A layout diagram showing another example of the arrangement of pixels in a display panel.

[0037] Figure 13 This is an explanation Figure 12 A plan view illustrating an example arrangement of pixel electrodes and auxiliary electrodes.

[0038] Figure 14 This is an explanation Figure 12 A plan view of another example of the arrangement of pixel electrodes and auxiliary electrodes.

[0039] Figure 15 This is a block diagram illustrating an electronic device according to one or more embodiments.

[0040] Figure 16 This is a view illustrating an example of an electronic device implemented as a smartphone. Detailed Implementation

[0041] In the following description, the present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0042] Instead, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of this disclosure to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0043] It will be understood that although the terms “first,” “second,” and “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0046] Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein may be performed in the appropriate order. Unless otherwise stated, any and all examples and the use of exemplary language (e.g., "for example") are intended merely to better illustrate this disclosure and do not constitute a limitation on the scope of this disclosure. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of this disclosure as used herein.

[0047] In the following, a display device and an electronic device including the display device according to one or more embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0048] In view of this disclosure as a whole, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other and may be technically associated with and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0049] Figure 1 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0050] refer to Figure 1 The display device 1 according to one or more embodiments of the present disclosure may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0051] In one or more embodiments, the drive controller 200 and the data driver 500 may be integrally formed. In one or more embodiments, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. For example, a drive module in which the drive controller 200 and the data driver 500 are integrally formed may be referred to as a timing controller embedded data driver (TED).

[0052] The display panel 100 may include a display portion defined for displaying an image and a peripheral portion adjacent to the display portion. In one or more embodiments, the display panel 100 may be an organic light-emitting diode (OLED) display panel including an organic light-emitting diode (OLED). In another embodiment, the display panel 100 may be a quantum dot organic light-emitting diode (OLED) display panel including an organic light-emitting diode (OLED) and a quantum dot color filter. In yet another embodiment, the display panel 100 may be a quantum dot nanolight-emitting diode (NLED) display panel including a nanolight-emitting diode and a quantum dot color filter. However, the type of display panel 100 according to one or more embodiments of this disclosure is not necessarily limited to these.

[0053] The display panel 100 may include multiple pixels PX, multiple grid lines GL, and multiple data lines DL. Each of the multiple pixels PX, multiple grid lines GL, and multiple data lines DL may be disposed in the display portion of the display panel 100. The display panel driver may be disposed in the peripheral portion of the display panel 100.

[0054] In this disclosure, the plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Additionally, a third direction DR3 (see...) Figure 9 It can be perpendicular to the plane.

[0055] Multiple pixels (PXs) can be arranged in a matrix form comprising multiple pixel rows and multiple pixel columns. Multiple pixels (PXs) can be arranged along a first direction DR1 and a second direction DR2. Each of the multiple pixels (PXs) can emit light of a different color. For example, in a multiple pixel (PX) array, one pixel (e.g., Figure 2 The first pixel PX1 or the second pixel PX2 can emit light of the first color, and another pixel in the plurality of pixels PX (e.g., ...) ... Figure 2 The third pixel PX3 or the fourth pixel PX4 can emit light of the second color, and another pixel in the plurality of pixels PX (e.g., Figure 2 The fifth pixel PX5 or the sixth pixel PX6 may emit light of a third color. In one or more embodiments, the first color of light may be green, the second color of light may be red, and the third color of light may be blue. However, the color of light emitted by each of the plurality of pixels PX according to one or more embodiments of the present disclosure is not necessarily limited to this. For example, each of the plurality of pixels PX may be combined to emit magenta, cyan, and yellow light.

[0056] Each of the multiple gate lines GL can extend along a first direction DR1. The multiple gate lines GL can be spaced apart from each other along a second direction DR2 (e.g., spaced apart). Each of the multiple data lines DL can extend along the second direction DR2. The multiple data lines DL can be spaced apart from each other along the first direction DR1 (e.g., spaced apart).

[0057] In one or more embodiments, each of the plurality of pixels PX may be electrically connected to at least one of the plurality of gate lines GL and at least one of the plurality of data lines DL.

[0058] The drive controller 200 may receive input image data IMG and input control signal CONT from an external device, such as the main processor of a graphics processing unit (GPU). In one or more embodiments, the input image data IMG may include red image data, green image data, and blue image data. In one or more embodiments, the input image data IMG may further include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and / or cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0059] The drive controller 200 can generate gate control signal CONT1, data control signal CONT2, gamma control signal CONT3, and data signal DATA based on the input image data IMG and the input control signal CONT.

[0060] The drive controller 200 can generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT. The drive controller 200 can output the gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0061] The drive controller 200 can generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT. The drive controller 200 can output the data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0062] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0063] The drive controller 200 can generate a gamma control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400. The drive controller 200 can output the gamma control signal CONT3 to the gamma reference voltage generator 400.

[0064] The gate driver 300 can generate a gate output signal for driving multiple gate lines GL in response to the gate control signal CONT1 input from the drive controller 200.

[0065] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a gamma control signal CONT3 input from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. In one or more embodiments, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0066] Data driver 500 can receive data control signal CONT2 and data signal DATA from drive controller 200. Data driver 500 can receive gamma reference voltage VGREF from gamma reference voltage generator 400. Data driver 500 can generate data voltage (e.g., Figure 2 The data driver 500 can use a gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage. The data driver 500 can output the data voltage to each of multiple data lines DL.

[0067] Figure 2 It is a diagram. Figure 1 A view of a portion of the display device. For example, Figure 2 This is a view illustrating a portion of each of the display panel 100, the gate driver 300, and the data driver 500 included in the display device 1.

[0068] refer to Figure 1 and Figure 2 The plurality of pixels PX included in the display panel 100 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6. The first pixel PX1, the third pixel PX3, and the fifth pixel PX5 may define a first pixel group PXG1. The second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6 may define a second pixel group PXG2.

[0069] First pixel PX1 and second pixel PX2 can emit light of the same color. For example, each of first pixel PX1 and second pixel PX2 can emit light of a first color. Third pixel PX3 and fourth pixel PX4 can emit light of the same color. For example, third pixel PX3 and fourth pixel PX4 can each emit light of a second color. Fifth pixel PX5 and sixth pixel PX6 can emit light of the same color. For example, fifth pixel PX5 and sixth pixel PX6 can each emit light of a third color. In one or more embodiments, the first color light, the second color light, and the third color light can be different colors.

[0070] In one or more embodiments, pixels PX may be repeatedly arranged in a row as multiple groups, including first pixel PX1, second pixel PX2, third pixel PX3, fourth pixel PX4, fifth pixel PX5 and sixth pixel PX6.

[0071] Multiple write gates GL may include a first write gate GWL1 and a second write gate GWL2. The first write gate GWL1 may be electrically connected to pixels included in the first pixel group PXG1. For example, the first write gate GWL1 may be electrically connected to each of the first pixel PX1, the third pixel PX3, and the fifth pixel PX5. The second write gate GWL2 may be electrically connected to pixels included in the second pixel group PXG2. For example, the second write gate GWL2 may be electrically connected to each of the second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6.

[0072] Specifically, a portion of the pixels arranged along a row (e.g., first pixel PX1, third pixel PX3, and fifth pixel PX5) can be electrically connected to the first write gate GWL1. Additionally, another portion of the pixels arranged along the same row (e.g., second pixel PX2, fourth pixel PX4, and sixth pixel PX6) can be electrically connected to the second write gate GWL2.

[0073] In other words, the first pixel group PXG1 can be defined as a group that includes pixels referred to as odd-numbered pixels in this disclosure and receives the first write gate signal GW1, and the second pixel group PXG2 can be defined as a group that includes pixels referred to as even-numbered pixels in this disclosure and receives the second write gate signal GW2.

[0074] In one or more embodiments, the first write gate line GWL1 and the second write gate line GWL2 can be extended along the first direction DR1 by arranging pixels PX that are disposed along a row and electrically connected to the first write gate line GWL1 and the second write gate line GWL2 between the first write gate line GWL1 and the second write gate line GWL2. However, the arrangement of each of the first write gate line GWL1 and the second write gate line GWL2 according to the present disclosure is not necessarily limited to this, and both the first write gate line GWL1 and the second write gate line GWL2 can be disposed on the second direction DR2 or in the opposite direction to the second direction DR2 from each of the pixels PX that are electrically connected to the first write gate line GWL1 and the second write gate line GWL2.

[0075] A first write gate signal GW1 can be applied to a first write gate line GWL1. A second write gate signal GW2 can be applied to a second write gate line GWL2. During a first time period in which the first write gate signal GW1 is applied, the first write gate signal GW1 may have write transistors (e.g., for turning on each of the first pixel PX1, the third pixel PX3, and the fifth pixel PX5) for turning on write transistors (e.g., ...). Figure 3 The voltage level of transistor T2-1. For example, the first write gate signal GW can have an active level during the first period in which the write transistor is turned on.

[0076] During the second time period in which the second write gate signal GW2 is applied, the second write gate signal GW2 may have write transistors (e.g., for turning on each of the second pixel PX2, the fourth pixel PX4, and the sixth pixel PX6) for turning on the write transistors (e.g., Figure 3 The voltage level of the second-to-2 transistor (T2-2). For example, the second write gate signal GW2 can have an active level during the second period in which the write transistor is turned on.

[0077] In one or more embodiments, the timing of applying the first write gate signal GW1 and the timing of applying the second write gate signal GW2 may be different from each other.

[0078] In one or more embodiments, the first write gate line GWL1 and the second write gate line GWL2 may be spaced apart from each other in the second direction DR2 (e.g., spaced apart). Multiple first write gate lines GWL1 may be provided along the second direction DR2. Multiple second write gate lines GWL2 may be provided along the second direction DR2. That is, the first write gate line GWL1 to which the first write gate signal GW1 is applied and the second write gate line GWL2 to which the second write gate signal GW2 is applied may be alternately and repeatedly provided within the display panel 100.

[0079] However, the multiple gate lines GL according to this disclosure are not necessarily limited to this, and the multiple gate lines GL may further include gate lines to which gate signals other than the first write gate signal GW1 and the second write gate signal GW2 are applied. For example, the multiple gate lines GL may further include gate lines to which gate signals other than the first write gate signal GW1 and the second write gate signal GW2 are applied. Figure 3 The gate lines of the gate signals (e.g., reference signal GR, initialization signal GI, first emission signal EM1 and second emission signal EM2).

[0080] The multiple data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The data driver 500 may include multiple output buffers OBF that apply a data voltage VDATA to each of the multiple data lines DL. The multiple output buffers OBF may include a first output buffer OBF1, a second output buffer OBF2, and a third output buffer OBF3.

[0081] The first output buffer OBF1 can apply a data voltage VDATA to the first pixel PX1 and the second pixel PX2 via the first data line DL1. For example, the data voltage VDATA applied to the first data line DL1 can be provided to each of the first pixel PX1 and the second pixel PX2. Specifically, the data voltage VDATA can be provided to the first pixel PX1 during a first time period, and the data voltage VDATA can be provided to the second pixel PX2 during a second time period.

[0082] The second output buffer OBF2 can apply a data voltage VDATA to the third pixel PX3 and the fourth pixel PX4 via the second data line DL2. For example, the data voltage VDATA applied to the second data line DL2 can be provided to each of the third pixel PX3 and the fourth pixel PX4. Specifically, the data voltage VDATA can be provided to the third pixel PX3 during a first time period, and the data voltage VDATA can be provided to the fourth pixel PX4 during a second time period.

[0083] The third output buffer OBF3 can apply a data voltage VDATA to the fifth pixel PX5 and the sixth pixel PX6 via the third data line DL3. For example, the data voltage VDATA applied to the third data line DL3 can be provided to each of the fifth pixel PX5 and the sixth pixel PX6. Specifically, during a first time period, the data voltage VDATA can be provided to the fifth pixel PX5, and during a second time period, the data voltage VDATA can be provided to the sixth pixel PX6.

[0084] In one or more embodiments, the data driver 500 may not include a demultiplexing circuit that selectively outputs the data voltage VDATA to a portion of the multiple data lines DL. In other words, within the display device 1, the demultiplexing circuit that electrically connects the multiple output buffers OBF and the multiple data lines DL may not be provided between the multiple output buffers OBF and the multiple data lines DL.

[0085] Figure 3 The illustration includes Figure 1 The circuit diagram of the pixels in the display panel. Figure 4 It is a diagram. Figure 3 A circuit diagram illustrating an example of pixel manipulation. Figure 5 It is a diagram. Figure 3 A circuit diagram of another example of pixel operation.

[0086] refer to Figure 3 , Figure 4 and Figure 5 The first pixel PX1 may include a first pixel circuit PC1 and a first light-emitting element EL1. The second pixel PX2 may include a second pixel circuit PC2 and a second light-emitting element EL2. The first pixel circuit PC1 may include a first transistor T1-1, a second transistor T2-1, a third transistor T3-1, a fourth transistor T4-1, a fifth transistor T5-1, a sixth transistor T6-1, a first storage capacitor CST1, and a first holding capacitor CH1. The second pixel circuit PC2 may include a first transistor T1-2, a second transistor T2-2, a third transistor T3-2, a fourth transistor T4-2, a fifth transistor T5-2, a sixth transistor T6-2, a second storage capacitor CST2, and a second holding capacitor CH2.

[0087] Apart from the fact that different write signals (e.g., the first write gate signal GW1 and the second write gate signal GW2) are applied to the first pixel circuit PC1 and the second pixel circuit PC2, these circuits can have substantially the same structure and can perform substantially the same function.

[0088] Transistor T1-1 (1-1) may include a gate terminal electrically connected to node N1-1 (1-1), a back gate terminal electrically connected to node N2-1 (2-1), a first terminal receiving a first power voltage ELVDD, and a second terminal electrically connected to node N3-1 (3-1). Transistor T1-1 (1-1) may generate current (e.g., a drive current) based on the voltages at nodes N1-1 and N2-1 (1-1) and (i.e., the voltage stored in the first storage capacitor CST1). Transistor T1-1 (1-1) may be referred to as a drive transistor for generating the drive current. Transistor T1-1 (1-1) may provide the drive current to a first light-emitting element EL1.

[0089] Transistor T1-2 may include a gate terminal electrically connected to node N1-2, a back gate terminal electrically connected to node N2-2, a first terminal receiving a first power voltage ELVDD, and a second terminal electrically connected to node N3-2. The structure and operation of transistor T1-2 may be substantially the same as or similar to the structure and operation of transistor T1-1.

[0090] In one or more embodiments, each of the first-1 transistor T1-1 and the first-2 transistor T1-2 may have a dual-gate structure including a gate terminal and a back gate terminal. However, the structure of the first-1 transistor T1-1 and the first-2 transistor T1-2 according to the present disclosure is not necessarily limited thereto, and each of the first-1 transistor T1-1 and the first-2 transistor T1-2 may not include a back gate terminal and may include a single gate terminal.

[0091] The second-first transistor T2-1 may include a gate terminal for receiving a first write gate signal GW1, a first terminal electrically connected to the first-first node N1-1, and a second terminal connected to the first data line DL1. The second-first transistor T2-1 may be turned on or off by the first write gate signal GW1. For example, the second-first transistor T2-1 may apply a data voltage VDATA from the first data line DL1 to the first-first node N1-1 in response to the first write gate signal GW1. Specifically, during a first period when the first write gate signal GW1 is applied, the data voltage VDATA may be provided to the first pixel PX1 through the second-first transistor T2-1. The second-first transistor T2-1 may be referred to as a write transistor or a scan transistor for transmitting the data voltage VDATA.

[0092] Transistor T2-2 (2-2) may include a gate terminal for receiving the second write gate signal GW2, a first terminal electrically connected to node N1-2 (1-2), and a second terminal connected to the first data line DL1. The structure and operation of transistor T2-2 may be substantially the same as or similar to those of transistor T2-1 (2-1). For example, transistor T2-2 may be turned on or off by the second write gate signal GW2. Specifically, during a second period in which the second write gate signal GW2 is turned on, the data voltage VDATA may be provided to the second pixel PX2 through transistor T2-2.

[0093] In one or more embodiments, the timing of the first time period and the second time period may be different from each other. For example, the start point of the timing of the first time period and the start point of the timing of the second time period may be different. Specifically, the start point of the timing of the second time period may be before the start point of the timing of the first time period. Additionally, the end point of the first time period and the end point of the second time period may be different. Specifically, the end point of the second time period may be before the end point of the first time period. In one or more embodiments, the length of the first time period and the length of the second time period may be equal. In other words, the second time period may be before the first time period. However, this disclosure is not limited to this, and the second time period may be after the first time period.

[0094] In one or more embodiments, the first write gate signal GW1 during the first time period may have an activation level. For example, the activation level may be a high level. Specifically, during a period in which the first write gate signal GW1 has an activation level and the second write gate signal GW2 does not have an activation level, the data voltage VDATA may be provided to the first pixel PX1.

[0095] In one or more embodiments, the second write gate signal GW2 in the second time period may have an active level. For example, the active level may be a high level. Specifically, during a period when the second write gate signal GW2 has an active level and the first write gate signal GW1 does not have an active level, the data voltage VDATA may be provided to the second pixel PX2.

[0096] However, the voltage level of each of the first write gate signal GW1 and the second write gate signal GW2 according to this disclosure need not be limited to this, and the voltage level of each of the first write gate signal GW1 and the second write gate signal GW2 used to turn on the write transistor can be low.

[0097] In one or more embodiments, the first time period and the second time period may partially overlap. For example, the second time period may have an activation level during a period in which the first time period has an activation level. Accordingly, during the time period in which the first time period and the second time period overlap, transistors 2-1 and 2-2 are concurrently (e.g., simultaneously) turned on, and the data voltage VDATA can be applied to the first pixel PX1 and the second pixel PX2 concurrently (e.g., simultaneously) through transistors 2-1 and 2-2.

[0098] Transistor T3-1 (3-1) may include a gate terminal for receiving a reference signal GR, a first terminal to which a reference voltage VREF is applied, and a second terminal electrically connected to node N1-1 (1-1). Transistor T3-1 (3-1) may be turned on or off by the reference signal GR. For example, transistor T3-1 (3-1) may apply the reference voltage VREF to node N1-1 (1-1) in response to the reference signal GR. Transistor T3-1 (3-1) may be referred to as a reference transistor or a reset transistor for applying the reference voltage VREF to node N1-1 (1-1).

[0099] Transistor T3-2 (3-2) may include a gate terminal for receiving a reference signal GR, a first terminal for which a reference voltage VREF is applied, and a second terminal electrically connected to node N1-2 (1-2). The structure and operation of transistor T3-2 (3-2) may be substantially the same as or similar to the structure and operation of transistor T3-1 (3-1).

[0100] Transistor T4-1 (4-1) may include a gate terminal for receiving an initialization signal GI, a first terminal to which an initialization voltage VINT is applied, and a second terminal electrically connected to node N4-1 (4-1). Transistor T4-1 (4-1) may be turned on or off by the initialization signal GI. For example, transistor T4-1 (4-1) may apply the initialization voltage VINT to node N4-1 (4-1) in response to the initialization signal GI. Transistor T4-1 (4-1) may be referred to as the initialization transistor for initializing node N4-1 (4-1).

[0101] Transistor T4-2 (4-2) may include a gate terminal for receiving the initialization signal GI, a first terminal for receiving the initialization voltage VINT, and a second terminal electrically connected to node N4-2 (4-2). The structure and operation of transistor T4-2 (4-2) may be substantially the same as or similar to the structure and operation of transistor T4-1 (4-1).

[0102] Transistor T5-1 (5-1) may include a gate terminal for receiving a first light-emitting signal EM1, a first terminal for receiving a first power voltage ELVDD, and a second terminal electrically connected to the first terminal of transistor T1-1 (1-1). Transistor T5-1 (5-1) may be turned on or off by the first light-emitting signal EM1. For example, during the period in which transistor T5-1 (5-1) is turned on, transistor T5-1 (5-1) may supply the first power voltage ELVDD to transistor T1-1 (1-1). Transistor T5-1 (5-1) may be referred to as a light-emitting transistor or an operating control transistor for forming a current path from the power voltage line to which the first power voltage ELVDD is applied to transistor T1-1 (1-1).

[0103] Transistor T5-2 (5-2) may include a gate terminal for receiving a first light-emitting signal EM1, a first terminal for receiving a first power voltage ELVDD, and a second terminal electrically connected to the first terminal of transistor T1-2 (5-2). The structure and operation of transistor T5-2 (5-2) may be substantially the same as or similar to the structure and operation of transistor T5-1 (5-1).

[0104] Transistor T6-1 (6-1) may include a gate terminal for receiving the second light-emitting signal EM2, a first terminal electrically connected to node N3-1 (3-1), and a second terminal electrically connected to node N4-1 (4-1). Transistor T6-1 (6-1) can be turned on or off by the second light-emitting signal EM2. For example, during the period when transistor T6-1 (6-1) is turned on, it can provide a drive current to the first light-emitting element EL1. Transistor T6-1 (6-1) may be referred to as a light-emitting control transistor that controls the drive current provided to the first light-emitting element EL1.

[0105] Transistor T6-2 (6-2) may include a gate terminal for receiving the second light-emitting signal EM2, a first terminal electrically connected to node N3-2 (3-2), and a second terminal electrically connected to node N4-2 (4-2). The structure and operation of transistor T6-2 (6-2) may be substantially the same as or similar to the structure and operation of transistor T6-1 (6-1).

[0106] The first storage capacitor CST1 may include a first terminal electrically connected to node 1-1 N1-1 and a second terminal electrically connected to node 3-1 N3-1. The first storage capacitor CST1 may store the data voltage VDATA transmitted through transistor 2-1 T2-1.

[0107] The second storage capacitor CST2 may include a first terminal electrically connected to node 1-2 N1-2 and a second terminal electrically connected to node 3-2 N3-2. The structure and operation of the second storage capacitor CST2 may be substantially the same as or similar to the structure and operation of the first storage capacitor CST1.

[0108] The first holding capacitor CH1 may include a first terminal receiving a first power voltage ELVDD and a second terminal electrically connected to node 2-1 N2-1. The second terminal of the first holding capacitor CH1 may be electrically connected to the back gate terminal of transistor 1-1 T1-1. The first holding capacitor CH1 may be a capacitor used to hold the voltage of node 2-1 N2-1.

[0109] The second holding capacitor CH2 may include a first terminal receiving the first power voltage ELVDD and a second terminal electrically connected to node N2-2. The second terminal of the second holding capacitor CH2 may be electrically connected to the back gate terminal of transistor T1-2. The structure and operation of the second holding capacitor CH2 may be substantially the same as or similar to the structure and operation of the first holding capacitor CH1.

[0110] The first light-emitting element EL1 may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the first light-emitting element EL1 is electrically connected to the second terminal of the 6-1 transistor T6-1, and the second terminal can be supplied with a second power voltage ELVSS. The first light-emitting element EL1 can generate light with a brightness corresponding to the driving current. In one or more embodiments, the second power voltage ELVSS may have a voltage level different from the voltage level of the first power voltage ELVDD. For example, the voltage level of the second power voltage ELVSS may be lower than the voltage level of the first power voltage ELVDD. However, the relationship between the voltage levels of the first power voltage ELVDD and the second power voltage ELVSS according to this disclosure is not necessarily limited to this.

[0111] The second light-emitting element EL2 may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the second light-emitting element EL2 is electrically connected to the second terminal of the 6-2 transistor T6-2, and the second terminal can be supplied with a second power voltage ELVSS. The structure and operation of the second light-emitting element EL2 may be substantially the same as or similar to the structure and operation of the first light-emitting element EL1.

[0112] In one or more embodiments, the first light-emitting element EL1 and the second light-emitting element EL2 can emit light of the same color. For example, the first light-emitting element EL1 and the second light-emitting element EL2 can emit light of a first color.

[0113] In one or more embodiments, each of transistors T1-1 (1-1), T1-2 (1-2), T2-1 (2-1), T2-2 (2-2), T3-1 (3-1), T3-2 (3-2), T4-1 (4-1), T4-2 (4-2), T5-1 (5-1), T5-2 (5-2), T6-1 (6-1), and T6-2 (6-2) may be an NMOS transistor.

[0114] However, the type of each of the first-1 transistor T1-1, the first-2 transistor T1-2, the second-1 transistor T2-1, the second-2 transistor T2-2, the third-1 transistor T3-1, the third-2 transistor T3-2, the fourth-1 transistor T4-1, the fourth-2 transistor T4-2, the fifth-1 transistor T5-1, the fifth-2 transistor T5-2, the sixth-1 transistor T6-1, and the sixth-2 transistor T6-2 according to this disclosure is not necessarily limited to this. Furthermore, at least one of the following transistors can be a PMOS transistor: transistor 1-1 T1-1, transistor 1-2 T1-2, transistor 2-1 T2-1, transistor 2-2 T2-2, transistor 3-1 T3-1, transistor 3-2 T3-2, transistor 4-1 T4-1, transistor 4-2 T4-2, transistor 5-1 T5-1, transistor 5-2 T5-2, transistor 6-1 T6-1, and transistor 6-2 T6-2.

[0115] Included Figure 3 , Figure 4 and Figure 5The number of transistors in a pixel (e.g., first pixel PX1 or second pixel PX2) is illustrated as 6, and the number of capacitors is illustrated as 2. However, the number of transistors and capacitors included in a pixel according to this disclosure is not necessarily limited to these. For example, a pixel may include 5 or fewer transistors or 7 or more transistors, or a pixel may include one capacitor or three or more capacitors.

[0116] Further reference Figure 2 The circuit structure and operation method of the first pixel PX1 and the second pixel PX2 can be illustrated in... Figure 3 , Figure 4 and Figure 5 However, this disclosure is not limited to this, and the circuit structure and operation method of the third pixel PX3 and the fourth pixel PX4 can be substantially the same as the circuit structure and operation method of the first pixel PX1 and the second pixel PX2. Furthermore, the circuit structure and operation method of the fifth pixel PX5 and the sixth pixel PX6 can be substantially the same as the circuit structure and operation method of the first pixel PX1 and the second pixel PX2.

[0117] For example, the first pixel PX1 can be substantially the same as the third pixel PX3 and the fifth pixel PX5, and the second pixel PX2 can be substantially the same as the fourth pixel PX4 and the sixth pixel PX6. Furthermore, the third pixel PX3 and the fourth pixel PX4 can have a structure connected to the second data line DL2 and include a light-emitting element that emits light of a second color, and the fifth pixel PX5 and the sixth pixel PX6 can have a structure connected to the third data line DL3 and include a light-emitting element that emits light of a third color.

[0118] Figure 6 , Figure 7 and Figure 8 The illustration includes Figure 1 A layout diagram illustrating an example of the arrangement of pixels in a display panel. Figure 9 It is a diagram. Figure 8 A cross-sectional view of each of the A1, A2 and A3 areas.

[0119] For example, Figure 6 , Figure 7 and Figure 8 This is a layout diagram used to illustrate the arrangement of each of the pixel circuit layer PXC and the light-emitting element layer DEL in the display area DA, which are included in the display panel 100.

[0120] refer to Figure 6 , Figure 7 , Figure 8 and Figure 9The display panel 100 may include a pixel circuit layer PXC and a light-emitting element layer DEL. The pixel circuit layer PXC may include a substrate SUB, a bottom metal layer BML, a buffer layer BFL, an active layer ACT, a gate insulating layer GIL, a gate electrode GE, an insulating layer ISL, a source electrode SE, a drain electrode DE, a first via insulating layer VIA1, a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3, a fourth connection electrode CNE4, a fifth connection electrode CNE5, a sixth connection electrode CNE6, a seventh connection electrode CNE7, an eighth connection electrode CNE8, a ninth connection electrode CNE9, a tenth connection electrode CNE10, an eleventh connection electrode CNE11, a twelfth connection electrode CNE12, a first data line DL1, a second data line DL2, a third data line DL3, an auxiliary voltage line AVL1, and a second via insulating layer VIA2. The active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may together form a transistor TR. The transistor TR may correspond to transistor T6-1 (6-1).

[0121] The light-emitting element layer (DEL) may include a pixel electrode layer (PXL), a pixel limiting layer (PDL), a light-emitting layer (EML), and a common electrode (CME). The pixel electrode layer (PXL) may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), a third pixel electrode (PXE3), a fourth pixel electrode (PXE4), a fifth pixel electrode (PXE5), a sixth pixel electrode (PXE6), a seventh pixel electrode (PXE7), an eighth pixel electrode (PXE8), a ninth pixel electrode (PXE9), a tenth pixel electrode (PXE10), an eleventh pixel electrode (PXE11), a twelfth pixel electrode (PXE12), a first auxiliary electrode (AXE1), and a second auxiliary electrode (AXE2). The light-emitting layer (EML) may include a first light-emitting layer (EML1), a second light-emitting layer (EML2), a third light-emitting layer (EML3), a fourth light-emitting layer (EML4), a fifth light-emitting layer (EML5), a sixth light-emitting layer (EML6), a seventh light-emitting layer (EML7), an eighth light-emitting layer (EML8), a ninth light-emitting layer (EML9), a tenth light-emitting layer (EML10), an eleventh light-emitting layer (EML11), and a twelfth light-emitting layer (EML12).

[0122] The first pixel electrode PXE1, the first light-emitting layer EML1, and the common electrode CME can together define the first light-emitting element EL1. However, in Figure 9In the diagram, the first pixel electrode PXE1, the first emissive layer EML1, and the common electrode CME are illustrated to define the first light-emitting element EL1. However, a combination of pixel electrodes and emissive layers among the second pixel electrode PXE2 and the second emissive layer EML2, the third pixel electrode PXE3 and the third emissive layer EML3, the fourth pixel electrode PXE4 and the fourth emissive layer EML4, the fifth pixel electrode PXE5 and the fifth emissive layer EML5, the sixth pixel electrode PXE6 and the sixth emissive layer EML6, the seventh pixel electrode PXE7 and the seventh emissive layer EML7, the eighth pixel electrode PXE8 and the eighth emissive layer EML8, the ninth pixel electrode PXE9 and the ninth emissive layer EML9, the tenth pixel electrode PXE10 and the tenth emissive layer EML10, the eleventh pixel electrode PXE11 and the eleventh emissive layer EML11, and the twelfth pixel electrode PXE12 and the twelfth emissive layer EML12 can replace the first pixel electrode PXE1 and the first emissive layer EML1 together with the common electrode CML to define the light-emitting element.

[0123] Further reference Figure 6 The pixel circuit layer PXC may include a first pixel circuit PC1, a second pixel circuit PC2, a third pixel circuit PC3, a fourth pixel circuit PC4, a fifth pixel circuit PC5, a sixth pixel circuit PC6, a seventh pixel circuit PC7, an eighth pixel circuit PC8, a ninth pixel circuit PC9, a tenth pixel circuit PC10, an eleventh pixel circuit PC11, and a twelfth pixel circuit PC12.

[0124] The first pixel circuit PC1, the second pixel circuit PC2, the third pixel circuit PC3, the fourth pixel circuit PC4, the fifth pixel circuit PC5, and the sixth pixel circuit PC6 can be set in the Nth row R (N), and the seventh pixel circuit PC7, the eighth pixel circuit PC8, the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 can be set in the N+1th row R (N+1).

[0125] In one or more embodiments, in a plan view, a second pixel circuit PC2 adjacent to the first pixel circuit PC1 may be disposed in the direction opposite to the first direction DR1 of the first pixel circuit PC1. In one or more embodiments, in a plan view, a third pixel circuit PC3, a fourth pixel circuit PC4, a fifth pixel circuit PC5, and a sixth pixel circuit PC6 may be disposed between the first pixel circuit PC1 and the second pixel circuit PC2 in a row, without being adjacent to each other.

[0126] In one or more embodiments, in a plan view, the eighth pixel circuit PC8, adjacent to the seventh pixel circuit PC7, may be disposed in the direction opposite to the first direction DR1 of the seventh pixel circuit PC7. In one or more embodiments, in a plan view, the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 may be disposed between the seventh pixel circuit PC7 and the eighth pixel circuit PC8 in a row, without being adjacent to each other.

[0127] In one or more embodiments, the pixel circuits arranged in a row can be regularly arranged along a first direction DR1. For example, the pixel circuits arranged in the Nth row R (N) can be arranged in the order of the second pixel circuit PC2, the first pixel circuit PC1, the third pixel circuit PC3, the fourth pixel circuit PC4, the fifth pixel circuit PC5, and the sixth pixel circuit PC6. Furthermore, the pixel circuits arranged in the N+1th row R (N+1) can be arranged in the order of the eighth pixel circuit PC8, the seventh pixel circuit PC7, the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12.

[0128] In one or more embodiments, the arrangement of pixel circuits in the Nth row R(N) and the arrangement of pixel circuits in the N+1th row R(N+1) can be repeated along the second direction DR2. For example, the arrangement of pixel circuits in the Nth row R(N) and the arrangement of pixel circuits in the N+1th row R(N+1) can be alternately arranged along the second direction DR2.

[0129] In one or more embodiments, the pixel circuits arranged in the same column along the second direction DR2 can be substantially identical. For example, each of the pixel circuits arranged in the same column along the second direction DR2 can be electrically connected to a light-emitting element that emits light of the same color and can receive the same type of write gate signal (e.g., a first write gate signal GW1 or a second write gate signal GW2).

[0130] Specifically, each of the first pixel circuit PC1 and the seventh pixel circuit PC7 can be electrically connected to a light-emitting element that emits light of the first color and can receive a first write gate signal GW1. Each of the second pixel circuit PC2 and the eighth pixel circuit PC8 can be electrically connected to a light-emitting element that emits light of the first color and can receive a second write gate signal GW2. Each of the third pixel circuit PC3 and the ninth pixel circuit PC9 can be electrically connected to a light-emitting element that emits light of the second color and can receive the first write gate signal GW1. Each of the fourth pixel circuit PC4 and the tenth pixel circuit PC10 can be electrically connected to a light-emitting element that emits light of the second color and can receive the second write gate signal GW2. Each of the fifth pixel circuit PC5 and the eleventh pixel circuit PC11 is electrically connected to a light-emitting element that emits light of the third color and can receive the first write gate signal GW1. Each of the sixth pixel circuit PC6 and the twelfth pixel circuit PC12 can be electrically connected to a light-emitting element that emits light of the third color and can receive the second write gate signal GW2.

[0131] The first pixel circuit PC1 may be a portion of the first pixel PX1 including transistors (e.g., transistors T1-1, T2-1, T3-1, T4-1, T5-1, and T6-1) for operating and controlling the light-emitting elements (e.g., the first light-emitting element EL1) included in the first pixel PX1.

[0132] The second pixel circuit PC2 may be a portion of the second pixel PX2 that includes transistors (e.g., first-2 transistor T1-2, second-2 transistor T2-2, third-2 transistor T3-2, fourth-2 transistor T4-2, fifth-2 transistor T5-2, and sixth-2 transistor T6-2) for the operation and control of the light-emitting element (e.g., second light-emitting element EL2) included in the second pixel PX2.

[0133] The third pixel circuit PC3 can be a portion of the third pixel PX3 including transistors for operating and controlling the light-emitting elements included in the third pixel PX3. The fourth pixel circuit PC4 can be a portion of the fourth pixel PX4 including transistors for operating and controlling the light-emitting elements included in the fourth pixel PX4. The fifth pixel circuit PC5 can be a portion of the fifth pixel PX5 including transistors for operating and controlling the light-emitting elements included in the fifth pixel PX5. The sixth pixel circuit PC6 can be a portion of the sixth pixel PX6 including transistors for operating and controlling the light-emitting elements included in the sixth pixel PX6.

[0134] In this disclosure, the light-emitting element included in the third pixel PX3 can be referred to as the third light-emitting element, the light-emitting element included in the fourth pixel PX4 can be referred to as the fourth light-emitting element, the light-emitting element included in the fifth pixel PX5 can be referred to as the fifth light-emitting element, and the light-emitting element included in the sixth pixel PX6 can be referred to as the sixth light-emitting element.

[0135] The seventh pixel circuit PC7 can be substantially the same as the first pixel circuit PC1, the eighth pixel circuit PC8 can be substantially the same as the second pixel circuit PC2, the ninth pixel circuit PC9 can be substantially the same as the third pixel circuit PC3, the tenth pixel circuit PC10 can be substantially the same as the fourth pixel circuit PC4, the eleventh pixel circuit PC11 can be substantially the same as the fifth pixel circuit PC5, and the twelfth pixel circuit PC12 can be substantially the same as the sixth pixel circuit PC6.

[0136] Specifically, like the first pixel circuit PC1, the third pixel circuit PC3, and the fifth pixel circuit PC5, the seventh pixel circuit PC7, the ninth pixel circuit PC9, and the eleventh pixel circuit PC11 can be pixel circuits for pixels included in the first pixel group PXG1. Additionally, like the second pixel circuit PC2, the fourth pixel circuit PC4, and the sixth pixel circuit PC6, the eighth pixel circuit PC8, the tenth pixel circuit PC10, and the twelfth pixel circuit PC12 can be pixel circuits for pixels included in the second pixel group PXG2.

[0137] exist Figure 9 In area A2, a cross-section of a portion of the first pixel circuit PC1 is illustrated, and each of the second pixel circuit PC2, the third pixel circuit PC3, the fourth pixel circuit PC4, the fifth pixel circuit PC5, the sixth pixel circuit PC6, the seventh pixel circuit PC7, the eighth pixel circuit PC8, the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 according to this disclosure may have a cross-sectional structure substantially the same as that of the first pixel circuit PC1.

[0138] The substrate SUB can be the base of the display panel 100. The substrate SUB can include transparent or opaque materials. The substrate SUB can be a transparent resin substrate such as polyimide (PI). For example, a substrate SUB including polyimide can include a first organic layer, a first barrier layer, and / or a second organic layer, etc. As another example, the substrate SUB can include a quartz substrate (e.g., a synthetic quartz substrate), a calcium fluoride substrate, and / or an alkali-free glass substrate, etc. These can be used individually or in combination with each other.

[0139] A bottom metal layer (BML) can be disposed on the substrate (SUB). The bottom metal layer (BML) can prevent impurities from diffusing into the active layer (ACT) or prevent static electricity generated in the transistor (TR). In one or more embodiments, the bottom metal layer (BML) may include a conductive material. For example, conductive materials may include molybdenum (Mo), copper (Cu), aluminum (Al), and / or titanium (Ti). These can be used individually or in combination with each other.

[0140] A buffer layer BFL can be disposed on the bottom metal layer BML and the substrate SUB. The buffer layer BFL can prevent impurities such as oxygen and / or moisture from diffusing through the substrate SUB into the upper part of the substrate SUB. The buffer layer BFL can provide a flat upper surface on the upper part of the substrate SUB. The buffer layer BFL may include an inorganic insulating material.

[0141] The active layer (ACT) can be set on the buffer layer (BFL). The active layer (ACT) can include a source region, a drain region, and a channel region between the source region and the drain region.

[0142] In one or more embodiments, the active layer ACT may include an oxide semiconductor. For example, the oxide semiconductor may include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (GE), chromium (Cr), titanium (Ti), and / or zinc (Zn), etc. These may be used individually or in combination with each other. However, the materials included in the active layer ACT according to this disclosure are not necessarily limited thereto, and the active layer ACT may include organic semiconductors and / or silicon semiconductors, etc. For example, the silicon semiconductor may be polycrystalline silicon and / or amorphous silicon, etc.

[0143] A gate insulating layer (GIL) may be disposed on the active layer (ACT). In one or more embodiments, the gate insulating layer (GIL) may comprise an inorganic insulating material. The inorganic insulating material may comprise silicon oxide (SiO2). x Silicon nitride (SiN) x ) and / or silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0144] The gate electrode GE can be disposed on the gate insulating layer GIL. In a plan view, the gate electrode GE can overlap with the channel region of the active layer ACT. In one or more embodiments, the gate electrode GE may include a conductive material.

[0145] The first write gate line GWL1 and the second write gate line GWL2 may be disposed in the pixel circuit layer PXC. In one or more embodiments, each of the first write gate line GWL1 and the second write gate line GWL2 may be disposed in the same layer (or at the same location) as the gate electrode GE. For example, the first write gate line GWL1, the second write gate line GWL2, and the gate electrode GE may comprise the same material and may be formed by the same process. However, the interlayer arrangement of the first write gate line GWL1, the second write gate line GWL2, and the gate electrode GE according to this disclosure is not necessarily limited thereto.

[0146] An insulating layer ISL may be disposed on a buffer layer BFL. For example, the insulating layer ISL may cover the gate electrode GE on the buffer layer BFL. In one or more embodiments, the insulating layer ISL may comprise an inorganic insulating material and / or an organic insulating material. In one or more embodiments, the insulating layer ISL may have a substantially flat upper surface. However, the insulating layer ISL according to this disclosure is not necessarily limited to this, and the insulating layer ISL may have a substantially uniform thickness along the contour of the gate electrode GE.

[0147] The source electrode SE and drain electrode DE can be disposed on the insulating layer ISL. The source electrode SE and drain electrode DE can contact the active layer ACT through contact holes penetrating the insulating layer ISL in the thickness direction (e.g., third direction DR3). For example, the source electrode SE can contact the source region of the active layer ACT, and the drain electrode DE can contact the drain region of the active layer ACT. In one or more embodiments, each of the source electrode SE and drain electrode DE may include a conductive material.

[0148] The first data line DL1, the second data line DL2, and the third data line DL3 may be disposed on the insulating layer ISL. In one or more embodiments, each of the first data line DL1, the second data line DL2, and the third data line DL3 may include a conductive material. In one or more embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 may be disposed in (or at) the same layer as each other. For example, the first data line DL1, the second data line DL2, and the third data line DL3 may include the same material and may be formed by the same process.

[0149] In one or more embodiments, the first data line DL1, the second data line DL2, and the third data line DL3 may be disposed in the same layer (or at the same location) as the source electrode SE and the drain electrode DE. For example, the first data line DL1, the second data line DL2, and the third data line DL3 may comprise the same material as the source electrode SE and the drain electrode DE, and may be formed by the same process. However, the arrangement of each of the first data line DL1, the second data line DL2, and the third data line DL3 according to this disclosure is not necessarily limited thereto, and the first data line DL1, the second data line DL2, and the third data line DL3 may be disposed in different layers from the source electrode SE and the drain electrode DE.

[0150] In one or more embodiments, in a plan view, the first data line DL1 may be disposed between a first pixel circuit PC1 and a second pixel circuit PC2 that are adjacent to each other. In one or more embodiments, in a plan view, the second data line DL2 may be disposed between a third pixel circuit PC3 and a fourth pixel circuit PC4 that are adjacent to each other. In one or more embodiments, in a plan view, the third data line DL3 may be disposed between a fifth pixel circuit PC5 and a sixth pixel circuit PC6 that are adjacent to each other.

[0151] In one or more embodiments, each of the first data line DL1, the second data line DL2, and the third data line DL3 may extend along the second direction DR2 within the pixel circuit layer PXC. Specifically, the first data line DL1, the second data line DL2, and the third data line DL3 may intersect both the Nth row R(N) and the N+1th row R(N+1).

[0152] A first through-hole insulating layer VIA1 may be disposed on the insulating layer ISL. In one or more embodiments, the first through-hole insulating layer VIA1 may have a substantially flat upper surface. In one or more embodiments, the first through-hole insulating layer VIA1 may comprise an organic material such as polyimide.

[0153] The first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, the sixth connecting electrode CNE6, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12 can be disposed on the first through-hole insulating layer VIA1. For example, in a plan view, the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, and the sixth connecting electrode CNE6 can be disposed in the Nth row R (N). Additionally, in a plan view, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12 can be disposed in the N+1th row R (N+1).

[0154] In one or more embodiments, the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, the sixth connecting electrode CNE6, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12 may be disposed on the first data line DL1, the second data line DL2, and the third data line DL3.

[0155] However, the arrangement of the first connecting electrode CNE1, second connecting electrode CNE2, third connecting electrode CNE3, fourth connecting electrode CNE4, fifth connecting electrode CNE5, sixth connecting electrode CNE6, seventh connecting electrode CNE7, eighth connecting electrode CNE8, ninth connecting electrode CNE9, tenth connecting electrode CNE10, eleventh connecting electrode CNE11, and twelfth connecting electrode CNE12 with the first data line DL1, second data line DL2, and third data line DL3 according to this disclosure is not necessarily limited to this. For example, the sixth connecting electrode CNE6, seventh connecting electrode CNE7, eighth connecting electrode CNE8, ninth connecting electrode CNE9, tenth connecting electrode CNE10, eleventh connecting electrode CNE11, and twelfth connecting electrode CNE12, as well as the first data line DL1, second data line DL2, and third data line DL3, can be disposed in the same layer (or at the same location).

[0156] The first connection electrode CNE1 may be included in the first pixel circuit PC1. The first connection electrode CNE1 may be electrically connected to the light-emitting control transistor (e.g., transistor T6-1) included in the first pixel circuit PC1. For example, the first connection electrode CNE1 may contact the source electrode SE of the transistor TR through a contact hole that penetrates the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the first connection electrode CNE1 according to this disclosure is not necessarily limited to this, and the first connection electrode CNE1 may contact the drain electrode DE of the transistor TR through a contact hole that penetrates the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0157] In one or more embodiments, the first connection electrode CNE1 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the first connection electrode CNE1 is arranged in the area of ​​the first pixel circuit PC1 in the Nth row R(N), the first connection electrode CNE1 may be arranged in the area of ​​each of the first pixel circuits PC1 in rows such as the N+2nd row and the N+4th row.

[0158] The second connection electrode CNE2 may be included in the second pixel circuit PC2. The second connection electrode CNE2 may be electrically connected to a light-emitting control transistor (e.g., a 6-2 transistor T6-2) included in the second pixel circuit PC2. For example, the second connection electrode CNE2 may contact the source electrode of the light-emitting control transistor included in the second pixel circuit PC2 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the second connection electrode CNE2 according to this disclosure is not necessarily limited to this, and the second connection electrode CNE2 may also contact the drain electrode of the light-emitting control transistor included in the second pixel circuit PC2 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0159] In one or more embodiments, in a plan view, the second connection electrode CNE2 may be spaced apart from the first connection electrode CNE1 (e.g., spaced apart). In one or more embodiments, the second connection electrode CNE2 may be disposed in the opposite direction to the first connection electrode CNE1 adjacent to the second connection electrode CNE2 in the first direction DR1. In one or more embodiments, in a plan view, the first connection electrode CNE1 and the second connection electrode CNE2 may be symmetrical to each other based on the first data line DL1. However, the first connection electrode CNE1 and the second connection electrode CNE2 according to this disclosure are not necessarily limited to these.

[0160] In one or more embodiments, the second connection electrode CNE2 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the second connection electrode CNE2 is arranged in the area where the second pixel circuit PC2 is arranged in the Nth row R(N), the second connection electrode CNE2 may be arranged in the area where each of the second pixel circuits PC2 is arranged in rows such as the N+2nd row and the N+4th row.

[0161] The third connection electrode CNE3 may be included in the third pixel circuit PC3. The third connection electrode CNE3 may be electrically connected to the light-emitting control transistor (e.g., transistor T6-1) included in the third pixel circuit PC3. For example, the third connection electrode CNE3 may contact the source electrode of the light-emitting control transistor included in the third pixel circuit PC3 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the third connection electrode CNE3 according to this disclosure is not necessarily limited to this, and the third connection electrode CNE3 may also contact the drain electrode of the light-emitting control transistor included in the third pixel circuit PC3 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0162] In one or more embodiments, in a plan view, the third connecting electrode CNE3 may be spaced apart from the first connecting electrode CNE1 (e.g., spaced apart). In one or more embodiments, the third connecting electrode CNE3 may be disposed from the first connecting electrode CNE1 adjacent to the third connecting electrode CNE3 in a first direction DR1.

[0163] In one or more embodiments, the third connecting electrode CNE3 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the third connecting electrode CNE3 is arranged in the area where the third pixel circuit PC3 is arranged in the Nth row R(N), the third connecting electrode CNE3 may be arranged in the area where each of the third pixel circuits PC3 is arranged in rows such as the N+2nd row and the N+4th row.

[0164] A fourth connection electrode CNE4 may be included in a fourth pixel circuit PC4. The fourth connection electrode CNE4 may be electrically connected to a light-emitting control transistor (e.g., transistor T6-2) included in the fourth pixel circuit PC4. For example, the fourth connection electrode CNE4 may contact the source electrode of the light-emitting control transistor included in the fourth pixel circuit PC4 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the fourth connection electrode CNE4 according to this disclosure is not necessarily limited to this, and the fourth connection electrode CNE4 may also contact the drain electrode of the light-emitting control transistor included in the fourth pixel circuit PC4 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0165] In one or more embodiments, in a plan view, the fourth connection electrode CNE4 may be spaced apart from the third connection electrode CNE3 (e.g., spaced apart). In one or more embodiments, in a plan view, the second data line DL2 may be disposed between the third connection electrode CNE3 and the fourth connection electrode CNE4.

[0166] In one or more embodiments, the fourth connection electrode CNE4 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the fourth connection electrode CNE4 is arranged in the area of ​​the fourth pixel circuit PC4 in the Nth row R(N), the fourth connection electrode CNE4 may be arranged in the area of ​​each of the fourth pixel circuits PC4 in rows such as the N+2nd row and the N+4th row.

[0167] A fifth connection electrode CNE5 may be included in a fifth pixel circuit PC5. The fifth connection electrode CNE5 may be electrically connected to a light-emitting control transistor (e.g., transistor T6-1) included in the fifth pixel circuit PC5. For example, the fifth connection electrode CNE5 may contact the source electrode of the light-emitting control transistor included in the fifth pixel circuit PC5 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third-direction DR3). However, the fifth connection electrode CNE5 according to this disclosure is not necessarily limited to this, and the fifth connection electrode CNE5 may contact the drain electrode of the light-emitting control transistor included in the fifth pixel circuit PC5 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third-direction DR3).

[0168] In one or more embodiments, in a plan view, the fifth connecting electrode CNE5 may be spaced apart from the fourth connecting electrode CNE4 (e.g., spaced apart). In one or more embodiments, the fifth connecting electrode CNE5 may be disposed on a first direction DR1 from the fourth connecting electrode CNE4 adjacent to the fifth connecting electrode CNE5.

[0169] In one or more embodiments, the fifth connecting electrode CNE5 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the fifth connecting electrode CNE5 is arranged in the area where the fifth pixel circuit PC5 is arranged in the Nth row R(N), the fifth connecting electrode CNE5 may be arranged in the area where each of the fifth pixel circuits PC5 is arranged in rows such as the N+2nd row and the N+4th row.

[0170] A sixth connection electrode CNE6 may be included in a sixth pixel circuit PC6. The sixth connection electrode CNE6 may be electrically connected to a light-emitting control transistor (e.g., the 6-2nd transistor T6-2) included in the sixth pixel circuit PC6. For example, the sixth connection electrode CNE6 may contact the source electrode of the light-emitting control transistor included in the sixth pixel circuit PC6 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the sixth connection electrode CNE6 according to this disclosure is not necessarily limited to this, and the sixth connection electrode CNE6 may contact the drain electrode of the light-emitting control transistor included in the sixth pixel circuit PC6 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0171] In one or more embodiments, in a plan view, the sixth connection electrode CNE6 may be spaced apart from the fifth connection electrode CNE5 (e.g., spaced apart). In one or more embodiments, in a plan view, the third data line DL3 may be disposed between the fifth connection electrode CNE5 and the sixth connection electrode CNE6.

[0172] In one or more embodiments, the sixth connection electrode CNE6 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the sixth connection electrode CNE6 is placed in the area where the sixth pixel circuit PC6 is placed in the Nth row R(N), the sixth connection electrode CNE6 may be placed in the area where each of the sixth pixel circuits PC6 is placed in rows such as the N+2nd row and the N+4th row.

[0173] A seventh connection electrode CNE7 may be included in a seventh pixel circuit PC7. The seventh connection electrode CNE7 may be electrically connected to a light-emitting control transistor (e.g., transistor T6-1) included in the seventh pixel circuit PC7. For example, the seventh connection electrode CNE7 may contact the source electrode of the light-emitting control transistor included in the seventh pixel circuit PC7 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the seventh connection electrode CNE7 according to this disclosure is not necessarily limited to this, and the seventh connection electrode CNE7 may also contact the drain electrode of the light-emitting control transistor included in the seventh pixel circuit PC7 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0174] In the plan view, the seventh connecting electrode CNE7 may be spaced apart from the first connecting electrode CNE1 on the second direction DR2 (e.g., spaced apart). In the plan view, the seventh connecting electrode CNE7 may be symmetrical to the first connecting electrode CNE1 based on a virtual line adjacent to each of the first pixel circuit PC1 and the seventh pixel circuit PC7 and parallel to the first direction DR1.

[0175] In one or more embodiments, the seventh connecting electrode CNE7 may be repeatedly arranged along the second direction DR2 in two-row units. For example, when the seventh connecting electrode CNE7 is arranged in the area where the seventh pixel circuit PC7 is arranged in the (N+1)th row R (N+1), the seventh connecting electrode CNE7 may be arranged in the area where each of the seventh pixel circuits PC7 is arranged in rows such as the (N+3)th row and the (N+5)th row. In one or more embodiments, in a plan view, the first connecting electrode CNE1 and the seventh connecting electrode CNE7 may be alternately arranged along the second direction DR2.

[0176] An eighth connection electrode CNE8 may be included in an eighth pixel circuit PC8. The eighth connection electrode CNE8 may be electrically connected to a light-emitting control transistor (e.g., transistor T6-2) included in the eighth pixel circuit PC8. For example, the eighth connection electrode CNE8 may contact the source electrode of the light-emitting control transistor included in the eighth pixel circuit PC8 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the eighth connection electrode CNE8 according to this disclosure is not necessarily limited to this, and the eighth connection electrode CNE8 may also contact the drain electrode of the light-emitting control transistor included in the eighth pixel circuit PC8 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0177] In the plan view, the eighth connecting electrode CNE8 may be spaced apart from the second connecting electrode CNE2 on the second direction DR2 (e.g., spaced apart). In the plan view, the eighth connecting electrode CNE8 may be symmetrical with the second connecting electrode CNE2 based on a virtual line adjacent to each of the second pixel circuit PC2 and the eighth pixel circuit PC8 and parallel to the first direction DR1.

[0178] In one or more embodiments, the eighth connection electrode CNE8 may be repeatedly arranged along the second direction DR2 in two-row units. For example, when the eighth connection electrode CNE8 is arranged in the area where the eighth pixel circuit PC8 is arranged in the N+1th row R (N+1), the eighth connection electrode CNE8 may be arranged in the area where each of the eighth pixel circuits PC8 is arranged in rows such as the N+3rd row and the N+5th row. In one or more embodiments, in a plan view, the second connection electrode CNE2 and the eighth connection electrode CNE8 may be alternately arranged along the second direction DR2.

[0179] A ninth connection electrode CNE9 may be included in a ninth pixel circuit PC9. The ninth connection electrode CNE9 may be electrically connected to a light-emitting control transistor (e.g., transistor T6-1) included in the ninth pixel circuit PC9. For example, the ninth connection electrode CNE9 may contact the source electrode of the light-emitting control transistor included in the ninth pixel circuit PC9 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the ninth connection electrode CNE9 according to this disclosure is not necessarily limited to this, and the ninth connection electrode CNE9 may also contact the drain electrode of the light-emitting control transistor included in the ninth pixel circuit PC9 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0180] In the plan view, the ninth connecting electrode CNE9 may be spaced apart from the third connecting electrode CNE3 in the second direction DR2 (e.g., spaced apart). In the plan view, the shape of the ninth connecting electrode CNE9 and the shape of the third connecting electrode CNE3 may be substantially the same. However, the shape of each of the third connecting electrode CNE3 and the ninth connecting electrode CNE9 in the plan view according to this disclosure is not necessarily limited to this.

[0181] In one or more embodiments, the ninth connection electrode CNE9 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the ninth connection electrode CNE9 is arranged in the area where the ninth pixel circuit PC9 is arranged in the N+1th row R (N+1), the ninth connection electrode CNE9 may be arranged in the area where each of the ninth pixel circuits PC9 is arranged in rows such as the N+3rd row and the N+5th row.

[0182] The tenth connection electrode CNE10 may be included in the tenth pixel circuit PC10. The tenth connection electrode CNE10 may be electrically connected to the light-emitting control transistor (e.g., transistor T6-2) included in the tenth pixel circuit PC10. For example, the tenth connection electrode CNE10 may contact the source electrode of the light-emitting control transistor included in the tenth pixel circuit PC10 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the tenth connection electrode CNE10 according to this disclosure is not necessarily limited to this, and the tenth connection electrode CNE10 may also contact the drain electrode of the light-emitting control transistor included in the tenth pixel circuit PC10 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0183] In the plan view, the tenth connecting electrode CNE10 may be spaced apart from the fourth connecting electrode CNE4 in the second direction DR2 (e.g., spaced apart). In the plan view, the shapes of the tenth connecting electrode CNE10 and the fourth connecting electrode CNE4 may differ. For example, in the plan view, the size of the tenth connecting electrode CNE10 may be larger than the size of the fourth connecting electrode CNE4. However, the shapes of each of the fourth connecting electrode CNE4 and the tenth connecting electrode CNE10 in the plan view according to this disclosure are not necessarily limited to this.

[0184] In one or more embodiments, the tenth connecting electrode CNE10 may be repeatedly arranged along the second direction DR2 in two-row units. For example, when the tenth connecting electrode CNE10 is arranged in the area where the tenth pixel circuit PC10 is arranged in the (N+1)th row R (N+1), the tenth connecting electrode CNE10 may be arranged in the area where each of the tenth pixel circuits PC10 is arranged in rows such as the (N+3)th and (N+5)th rows. In one or more embodiments, in a plan view, the fourth connecting electrode CNE4 and the tenth connecting electrode CNE10 may be alternately arranged along the second direction DR2.

[0185] The eleventh connection electrode CNE11 may be included in the eleventh pixel circuit PC11. The eleventh connection electrode CNE11 may be electrically connected to the light-emitting control transistor (e.g., transistor T6-1) included in the eleventh pixel circuit PC11. For example, the eleventh connection electrode CNE11 may contact the source electrode of the light-emitting control transistor included in the eleventh pixel circuit PC11 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the eleventh connection electrode CNE11 according to this disclosure is not necessarily limited to this, and the eleventh connection electrode CNE11 may contact the drain electrode of the light-emitting control transistor included in the eleventh pixel circuit PC11 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0186] In the plan view, the eleventh connecting electrode CNE11 may be spaced apart from the fifth connecting electrode CNE5 in the second direction DR2 (e.g., spaced apart). In the plan view, the shape of the eleventh connecting electrode CNE11 and the shape of the fifth connecting electrode CNE5 may be different. However, the shape of each of the fifth connecting electrode CNE5 and the eleventh connecting electrode CNE11 in the plan view according to this disclosure is not necessarily limited to this.

[0187] In one or more embodiments, the eleventh connecting electrode CNE11 may be repeatedly arranged along the second direction DR2 in two rows. For example, if the eleventh connecting electrode CNE11 is located in the area where the eleventh pixel circuit PC11 is located in the (N+1)th row R(N+1), then the eleventh connecting electrode CNE11 may be located in the areas where each of the eleventh pixel circuits PC11 is located in the (N+3)th row and the (N+5)th row, etc. In one or more embodiments, in a plan view, the fifth connecting electrode CNE5 and the eleventh connecting electrode CNE11 may be alternately arranged along the second direction DR2.

[0188] The twelfth connection electrode CNE12 may be included in the twelfth pixel circuit PC12. The twelfth connection electrode CNE12 may be electrically connected to the light-emitting control transistor (e.g., transistor T6-2) included in the twelfth pixel circuit PC12. For example, the twelfth connection electrode CNE12 may contact the source electrode of the light-emitting control transistor included in the twelfth pixel circuit PC12 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3). However, the twelfth connection electrode CNE12 according to embodiments of this disclosure is not necessarily limited to this, and the twelfth connection electrode CNE12 may also contact the drain electrode of the light-emitting control transistor included in the twelfth pixel circuit PC12 through a contact hole penetrating the first via insulating layer VIA1 in the thickness direction (e.g., third direction DR3).

[0189] In the plan view, the twelfth connecting electrode CNE12 may be spaced apart from the sixth connecting electrode CNE6 in the second direction DR2 (e.g., spaced apart). In the plan view, the shape of the twelfth connecting electrode CNE12 and the shape of the sixth connecting electrode CNE6 may be substantially the same. However, the shape of each of the sixth connecting electrode CNE6 and the twelfth connecting electrode CNE12 in the plan view according to this disclosure is not necessarily limited to this.

[0190] In one or more embodiments, the twelfth connecting electrode CNE12 may be repeatedly arranged along the second direction DR2 in two rows. For example, when the twelfth connecting electrode CNE12 is arranged in the area where the twelfth pixel circuit PC12 is arranged in the N+1th row R (N+1), the twelfth connecting electrode CNE12 may be arranged in the area where each of the twelfth pixel circuits PC12 is arranged in rows such as the N+3rd row and the N+5th row.

[0191] In one or more embodiments, the connecting electrodes arranged in a row can be regularly arranged along a first direction DR1. For example, the connecting electrodes arranged in the Nth row R(N) can be arranged in the order of the second connecting electrode CNE2, the first connecting electrode CNE1, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, and the sixth connecting electrode CNE6. Additionally, the connecting electrodes arranged in the N+1th row R(N+1) can be arranged in the order of the eighth connecting electrode CNE8, the seventh connecting electrode CNE7, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12.

[0192] In one or more embodiments, the arrangement of the connecting electrodes in the Nth row R(N) and the arrangement of the connecting electrodes in the N+1th row R(N+1) can be repeated along the second direction DR2. For example, the arrangement of the connecting electrodes in the Nth row R(N) and the arrangement of the connecting electrodes in the N+1th row R(N+1) can be alternately arranged along the second direction DR2.

[0193] However, the arrangement, shape, and / or size of the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, the sixth connecting electrode CNE6, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12 according to this disclosure may be shown as an example and may not be limited thereto.

[0194] The first auxiliary voltage line AVL1 may be disposed on the first through-hole insulating layer VIA1. In one or more embodiments, the first auxiliary voltage line AVL1 may be disposed in the same layer (or at the same location) as the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, the sixth connecting electrode CNE6, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12. However, the arrangement of the first auxiliary voltage line AVL1 according to this disclosure is not necessarily limited to this.

[0195] In one or more embodiments, the first auxiliary voltage line AVL1 may be electrically connected to the first auxiliary electrode AXE1 to prevent voltage drop of the second power voltage ELVSS. In one or more embodiments, in a plan view, the first auxiliary voltage line AVL1 may be spaced apart from the light-emitting layer EML (e.g., spaced apart).

[0196] A second through-hole insulating layer VIA2 may be disposed on a first through-hole insulating layer VIA1. In one or more embodiments, the second through-hole insulating layer VIA2 may comprise substantially the same material as the first through-hole insulating layer VIA1. For example, the second through-hole insulating layer VIA2 may comprise an organic insulating material.

[0197] The pixel electrode layer PXL can be disposed on the second via insulating layer VIA2. In one or more embodiments, in a plan view, the first pixel electrode PXE1, the second pixel electrode PXE2, the third pixel electrode PXE3, the fourth pixel electrode PXE4, the fifth pixel electrode PXE5, the sixth pixel electrode PXE6, the seventh pixel electrode PXE7, the eighth pixel electrode PXE8, the ninth pixel electrode PXE9, the tenth pixel electrode PXE10, the eleventh pixel electrode PXE11, the twelfth pixel electrode PXE12, the first auxiliary electrode AXE1, and the second auxiliary electrode AXE2 can be spaced apart from each other (e.g., spaced apart).

[0198] The first pixel electrode PXE1 can be electrically connected to the first pixel circuit PC1. For example, the first pixel electrode PXE1 can be electrically connected to the first pixel circuit PC1 through the first connection electrode CNE1. Specifically, the first pixel electrode PXE1 can contact the first connection electrode CNE1 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., on the third direction DR3).

[0199] In one or more embodiments, in a planar view, the first pixel electrode PXE1 may overlap with the first pixel circuit PC1. In one or more embodiments, in a planar view, the first pixel electrode PXE1 may overlap with the third pixel circuit PC3. Specifically, a first portion of the first pixel electrode PXE1 may overlap with the third pixel circuit PC3 in a planar view, and a second portion protruding from the first portion of the first pixel electrode PXE1 in a direction opposite to the first direction DR1 may overlap with the first pixel circuit PC1 in a planar view. Additionally, in a planar view, the first portion of the first pixel electrode PXE1 may overlap with a portion of the third connecting electrode CNE3.

[0200] The second pixel electrode PXE2 can be electrically connected to the second pixel circuit PC2. For example, the second pixel electrode PXE2 can be electrically connected to the second pixel circuit PC2 through the second connection electrode CNE2. Specifically, the second pixel electrode PXE2 can contact the second connection electrode CNE2 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., on the third direction DR3).

[0201] In one or more embodiments, in a planar view, the second pixel electrode PXE2 may overlap with the second pixel circuit PC2. In one or more embodiments, in a planar view, the second pixel electrode PXE2 may overlap with the sixth pixel circuit PC6. Specifically, a first portion of the second pixel electrode PXE2 overlaps with the sixth pixel circuit PC6 in a planar view, and a second portion of the second pixel electrode PXE2 protruding from the first portion in a first direction DR1 may overlap with the second pixel circuit PC2 in a planar view. Additionally, in a planar view, the first portion of the second pixel electrode PXE2 may overlap with a portion of the sixth connecting electrode CNE6.

[0202] In one or more embodiments, in a plan view, a second pixel electrode PXE2 disposed from the first pixel electrode PXE1 in a first direction DR1 may be symmetrical to the first pixel electrode PXE1 based on a virtual line adjacent to the fourth pixel circuit PC4 and the fifth pixel circuit PC5 and parallel to the second direction DR2. In one or more embodiments, in a plan view, a second pixel electrode PXE2 disposed from the first pixel electrode PXE1 in the opposite direction to the first pixel electrode PXE1 in the first direction DR1 may be symmetrical to the first pixel electrode PXE1 based on a first data line DL1.

[0203] The third pixel electrode PXE3 can be electrically connected to the third pixel circuit PC3. For example, the third pixel electrode PXE3 can be electrically connected to the third pixel circuit PC3 via the third connection electrode CNE3. Specifically, the third pixel electrode PXE3 can contact the third connection electrode CNE3 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., on the third direction DR3).

[0204] The third pixel electrode PXE3 may include a first main portion PXE3-1 and a first extension portion PXE3-2. The first main portion PXE3-1 and the first extension portion PXE3-2 may be integrally formed. In one or more embodiments, the first extension portion PXE3-2 may protrude from the first main portion PXE3-1 in a direction opposite to the first direction DR1. In one or more embodiments, in a plan view, the first extension portion PXE3-2 may be bent toward the second direction DR2.

[0205] In one or more embodiments, in a plan view, the first major portion PXE3-1 may overlap with the third pixel circuit PC3. In one or more embodiments, in a plan view, the first major portion PXE3-1 may overlap with a portion of the third connection electrode CNE3. For example, a portion of the first major portion PXE3-1 may contact a portion of the third connection electrode CNE3 through a contact hole in the second via insulating layer VIA2.

[0206] In one or more embodiments, in a plan view, the first extension portion PXE3-2 may overlap with the first pixel circuit PC1 and the second pixel circuit PC2. For example, the first extension portion PXE3-2 may extend in a direction opposite to the first direction DR1 and pass over the upper portion of each of the first pixel circuit PC1 and the second pixel circuit PC2.

[0207] In one or more embodiments, in a plan view, the first extension portion PXE3-2 may extend along a portion of the boundary of the sixth pixel electrode PXE6 adjacent to the first extension portion PXE3-2. For example, the first extension portion PXE3-2 may surround (e.g., around) a portion of the sixth pixel electrode PXE6 adjacent to the first extension portion PXE3-2, while maintaining a constant distance between that portion of the sixth pixel electrode PXE6 and the first extension portion PXE3-2.

[0208] In one or more embodiments, in a plan view, the third pixel electrode PXE3 may be spaced apart from the first pixel electrode PXE1 in the opposite direction of the second direction DR2 (e.g., spaced apart). For example, the first main portion PXE3-1 may be disposed from the first portion of the first pixel electrode PXE1 in the opposite direction of the second direction DR2.

[0209] The fourth pixel electrode PXE4 can be electrically connected to the fourth pixel circuit PC4. For example, the fourth pixel electrode PXE4 can be electrically connected to the fourth pixel circuit PC4 through the fourth connection electrode CNE4. Specifically, the fourth pixel electrode PXE4 can contact the fourth connection electrode CNE4 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0210] The fourth pixel electrode PXE4 may include a second main portion PXE4-1 and a second extension portion PXE4-2. The second main portion PXE4-1 and the second extension portion PXE4-2 may be integrally formed. In one or more embodiments, the second extension portion PXE4-2 may protrude from the second main portion PXE4-1 in a direction opposite to the first direction DR1. In one or more embodiments, in a plan view, the second extension portion PXE4-2 may be bent towards the second direction DR2.

[0211] In one or more embodiments, in a plan view, the second main portion PXE4-1 may overlap with the sixth pixel circuit PC6. In one or more embodiments, in a plan view, the second extension portion PXE4-2 may overlap with the fourth pixel circuit PC4 and the fifth pixel circuit PC5. For example, the second extension portion PXE4-2 may extend in a direction opposite to the first direction DR1 and pass over the upper portion of each of the fourth pixel circuit PC4 and the fifth pixel circuit PC5.

[0212] In one or more embodiments, in a plan view, the second extension portion PXE4-2 may extend along a portion of the boundary of the fifth pixel electrode PXE5 adjacent to the second extension portion PXE4-2. For example, in a plan view, the second extension portion PXE4-2 may surround (e.g., around) a portion of the fifth pixel electrode PXE5 adjacent to the second extension portion PXE4-2, while maintaining a constant distance between that portion of the fifth pixel electrode PXE5 and the second extension portion PXE4-2.

[0213] In one or more embodiments, the second extension portion PXE4-2 can contact the fourth connection electrode CNE4 of the fourth pixel circuit PC4 through the contact hole of the sixth pixel circuit PC6, the fifth pixel circuit PC5, and the second through-hole insulating layer VIA2. Since the second extension portion PXE4-2 contacts the fourth connection electrode CNE4, the fourth pixel electrode PXE4 and the fourth pixel circuit PC4 can be electrically connected to each other.

[0214] In one or more embodiments, in a plan view, the fourth pixel electrode PXE4 may be spaced apart (e.g., spaced apart) from each of the second pixel electrode PXE2 and the third extension portion PXE6-2 of the sixth pixel electrode PXE6 in a direction opposite to the second direction DR2. For example, the second main portion PXE4-1 may be disposed from the first portion of the second pixel electrode PXE2 in a direction opposite to the second direction DR2. In one or more embodiments, in a plan view, the fourth pixel electrode PXE4 may be spaced apart (e.g., spaced apart) from the sixth connecting electrode CNE6.

[0215] The fifth pixel electrode PXE5 can be electrically connected to the fifth pixel circuit PC5. For example, the fifth pixel electrode PXE5 can be electrically connected to the fifth pixel circuit PC5 through the fifth connection electrode CNE5. Specifically, the fifth pixel electrode PXE5 can contact the fifth connection electrode CNE5 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0216] In one or more embodiments, in a plan view, the fifth pixel electrode PXE5 may overlap with the fifth pixel circuit PC5. In one or more embodiments, in a plan view, the fifth pixel electrode PXE5 may overlap with each of the fourth pixel circuit PC4 and the fifth pixel circuit PC5.

[0217] The sixth pixel electrode PXE6 can be electrically connected to the sixth pixel circuit PC6. For example, the sixth pixel electrode PXE6 can be electrically connected to the sixth pixel circuit PC6 through the sixth connection electrode CNE6. Specifically, the sixth pixel electrode PXE6 can contact the sixth connection electrode CNE6 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0218] The sixth pixel electrode PXE6 may include a third main portion PXE6-1 and a third extension portion PXE6-2. The third main portion PXE6-1 and the third extension portion PXE6-2 may be integrally formed. In one or more embodiments, the third extension portion PXE6-2 may protrude from the third main portion PXE6-1 in a direction opposite to the first direction DR1.

[0219] In one or more embodiments, in a plan view, the third main portion PXE6-1 may overlap with the first pixel circuit PC1 and the second pixel circuit PC2. In one or more embodiments, in a plan view, the third extension portion PXE6-2 may overlap with the second pixel circuit PC2 and the sixth pixel circuit PC6. For example, the third extension portion PXE6-2 may extend in a direction opposite to the first direction DR1 and pass over the upper portion of each of the second pixel circuit PC2 and the sixth pixel circuit PC6.

[0220] In one or more embodiments, in a plan view, the third extension portion PXE6-2 may be spaced apart (e.g., spaced apart) from the first portion of the second pixel electrode PXE2 in a direction opposite to the second direction DR2. In one or more embodiments, in a plan view, the third extension portion PXE6-2 may be spaced apart (e.g., spaced apart) from the second main portion PXE4-1 of the fourth pixel electrode PXE4 in the second direction DR2. In other words, in a plan view, the third extension portion PXE6-2 may be located between the first portion of the second pixel electrode PXE2 and the second main portion PXE4-1 of the fourth pixel electrode PXE4.

[0221] In one or more embodiments, the third extension portion PXE6-2 may extend from the upper part of the second pixel circuit PC2 and may contact the sixth connection electrode CNE6 of the sixth pixel circuit PC6 through the contact hole of the second via insulating layer VIA2. Since the third extension portion PXE6-2 contacts the sixth connection electrode CNE6, the sixth pixel electrode PXE6 and the sixth pixel circuit PC6 may be electrically connected to each other.

[0222] The seventh pixel electrode PXE7 can be electrically connected to the seventh pixel circuit PC7. For example, the seventh pixel electrode PXE7 can be electrically connected to the seventh pixel circuit PC7 via the seventh connection electrode CNE7. Specifically, the seventh pixel electrode PXE7 can contact the seventh connection electrode CNE7 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0223] In one or more embodiments, in a planar view, the seventh pixel electrode PXE7 may overlap with the seventh pixel circuit PC7. In one or more embodiments, in a planar view, the seventh pixel electrode PXE7 may overlap with the ninth pixel circuit PC9. Specifically, a first portion of the seventh pixel electrode PXE7 may overlap with the ninth pixel circuit PC9 in a planar view, and a second portion of the seventh pixel electrode PXE7 protruding from the first portion in a direction opposite to the first direction DR1 may overlap with the seventh pixel circuit PC7 in a planar view. Additionally, in a planar view, the first portion of the seventh pixel electrode PXE7 may overlap with a portion of the ninth connecting electrode CNE9.

[0224] The eighth pixel electrode PXE8 can be electrically connected to the eighth pixel circuit PC8. For example, the eighth pixel electrode PXE8 can be electrically connected to the eighth pixel circuit PC8 through the eighth connection electrode CNE8. Specifically, the eighth pixel electrode PXE8 can contact the eighth connection electrode CNE8 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0225] In one or more embodiments, in a planar view, the eighth pixel electrode PXE8 may overlap with the eighth pixel circuit PC8. In one or more embodiments, in a planar view, the eighth pixel electrode PXE8 may overlap with the twelfth pixel circuit PC12. Specifically, a first portion of the eighth pixel electrode PXE8 may overlap with the twelfth pixel circuit PC12 in a planar view, and a second portion of the eighth pixel electrode PXE8 protruding from the first portion in a first direction DR1 may overlap with the eighth pixel circuit PC8 in a planar view. Additionally, in a planar view, the first portion of the eighth pixel electrode PXE8 may overlap with a portion of the twelfth connecting electrode CNE12.

[0226] In one or more embodiments, in a plan view, an eighth pixel electrode PXE8 disposed from the seventh pixel electrode PXE7 on the first direction DR1 can be symmetrical to the seventh pixel electrode PXE7 based on a virtual line adjacent to the tenth pixel circuit PC10 and the eleventh pixel circuit PC11 and parallel to the second direction DR2. In one or more embodiments, in a plan view, an eighth pixel electrode PXE8 disposed from the seventh pixel electrode PXE7 in the opposite direction to the first direction DR1 can be symmetrical to the seventh pixel electrode PXE7 based on the first data line DL1.

[0227] The ninth pixel electrode PXE9 can be electrically connected to the ninth pixel circuit PC9. For example, the ninth pixel electrode PXE9 can be electrically connected to the ninth pixel circuit PC9 through the ninth connection electrode CNE9. Specifically, the ninth pixel electrode PXE9 can contact the ninth connection electrode CNE9 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0228] The ninth pixel electrode PXE9 may include a fourth main portion PXE9-1 and a fourth extension portion PXE9-2. The fourth main portion PXE9-1 and the fourth extension portion PXE9-2 may be integrally formed. In one or more embodiments, the fourth extension portion PXE9-2 may protrude from the fourth main portion PXE9-1 in a direction opposite to the first direction DR1. In one or more embodiments, in a plan view, the fourth extension portion PXE9-2 may be bent towards the second direction DR2.

[0229] In one or more embodiments, in a plan view, the fourth major portion PXE9-1 may overlap with the ninth pixel circuit PC9. In one or more embodiments, in a plan view, the fourth major portion PXE9-1 may overlap with a portion of the ninth connection electrode CNE9. For example, a portion of the fourth major portion PXE9-1 may contact a portion of the ninth connection electrode CNE9 through a contact hole in the second via insulating layer VIA2.

[0230] In one or more embodiments, in a plan view, the fourth extension PXE9-2 may overlap with the ninth pixel circuit PC9 and the seventh pixel circuit PC7. For example, the fourth extension PXE9-2 may extend in a direction opposite to the first direction DR1 and pass over the upper part of the ninth pixel circuit PC9. Alternatively, the fourth extension PXE9-2 may extend in a direction opposite to the first direction DR1 and may bend in the second direction DR2 to pass over the upper part of the seventh pixel circuit PC7.

[0231] In one or more embodiments, the fourth extension PXE9-2 may be adjacent to a portion of the twelfth pixel electrode PXE12. For example, the fourth extension PXE9-2 may be spaced apart from the twelfth pixel electrode PXE12 in the first direction DR1 in a planar view (e.g., spaced apart) while maintaining a constant distance from a portion of the boundary of the twelfth pixel electrode PXE12.

[0232] In one or more embodiments, in a plan view, the ninth pixel electrode PXE9 may be spaced apart from the seventh pixel electrode PXE7 in a direction opposite to the second direction DR2 (e.g., spaced apart). For example, the fourth main portion PXE9-1 may be disposed from the first portion of the seventh pixel electrode PXE7 in a direction opposite to the second direction DR2.

[0233] The tenth pixel electrode PXE10 can be electrically connected to the tenth pixel circuit PC10. For example, the tenth pixel electrode PXE10 can be electrically connected to the tenth pixel circuit PC10 through the tenth connection electrode CNE10. Specifically, the tenth pixel electrode PXE10 can contact the tenth connection electrode CNE10 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0234] The tenth pixel electrode PXE10 may include a fifth main portion PXE10-1 and a fifth extension portion PXE10-2. The fifth main portion PXE10-1 and the fifth extension portion PXE10-2 may be integrally formed. In one or more embodiments, the fifth extension portion PXE10-2 may protrude from the fifth main portion PXE10-1 in a direction opposite to the first direction DR1. In one or more embodiments, in a plan view, the fifth extension portion PXE10-2 may be bent towards the second direction DR2.

[0235] In one or more embodiments, in a plan view, the fifth main portion PXE10-1 may overlap with the twelfth pixel circuit PC12. In one or more embodiments, in a plan view, the fifth extension portion PXE10-2 may overlap with the tenth pixel circuit PC10 and the eleventh pixel circuit PC11. For example, the fifth extension portion PXE10-2 may extend in a direction opposite to the first direction DR1 and pass over the upper portion of each of the tenth pixel circuit PC10 and the eleventh pixel circuit PC11.

[0236] In one or more embodiments, in a plan view, the fifth extension portion PXE10-2 may extend along a portion of the boundary of the eleventh pixel electrode PXE11 adjacent to the fifth extension portion PXE10-2. For example, in a plan view, the fifth extension portion PXE10-2 may surround (e.g., around) a portion of the eleventh pixel electrode PXE11 adjacent to the fifth extension portion PXE10-2, while maintaining a constant distance between that portion of the eleventh pixel electrode PXE11 and the fifth extension portion PXE10-2.

[0237] In one or more embodiments, the fifth extension portion PXE10-2 can contact the tenth connection electrode CNE10 of the tenth pixel circuit PC10 through the contact hole of the eleventh pixel circuit PC11 via the twelfth pixel circuit PC12 and the second through-hole insulating layer VIA2. Since the fifth extension portion PXE10-2 contacts the tenth connection electrode CNE10, the tenth pixel electrode PXE10 and the tenth pixel circuit PC10 can be electrically connected to each other.

[0238] In one or more embodiments, in a plan view, the tenth pixel electrode PXE10 may be spaced apart (e.g., spaced apart) from each of the sixth extension portions PXE12-2 of the eighth pixel electrode PXE8 and the twelfth pixel electrode PXE12 in a direction opposite to the second direction DR2. For example, the fifth main portion PXE10-1 may be disposed from the first portion of the eighth pixel electrode PXE8 in a direction opposite to the second direction DR2. In one or more embodiments, in a plan view, the tenth pixel electrode PXE10 may be spaced apart (e.g., spaced apart) from the twelfth connecting electrode CNE12.

[0239] The eleventh pixel electrode PXE11 can be electrically connected to the eleventh pixel circuit PC11. For example, the eleventh pixel electrode PXE11 can be electrically connected to the eleventh pixel circuit PC11 through the eleventh connection electrode CNE11. Specifically, the eleventh pixel electrode PXE11 can contact the eleventh connection electrode CNE11 through a contact hole that penetrates the second via insulating layer VIA2 in the thickness direction (e.g., the third direction DR3).

[0240] In one or more embodiments, in a plan view, the eleventh pixel electrode PXE11 may overlap with the eleventh pixel circuit PC11. In one or more embodiments, in a plan view, the eleventh pixel electrode PXE11 may overlap with each of the tenth pixel circuit PC10 and the eleventh pixel circuit PC11.

[0241] The twelfth pixel electrode PXE12 may include a sixth main portion PXE12-1 and a sixth extension portion PXE12-2. The sixth main portion PXE12-1 and the sixth extension portion PXE12-2 may be integrally formed. In one or more embodiments, the sixth extension portion PXE12-2 may protrude from the sixth main portion PXE12-1 in a direction opposite to the first direction DR1.

[0242] In one or more embodiments, in a plan view, the sixth main portion PXE12-1 may overlap with the seventh pixel circuit PC7 and the eighth pixel circuit PC8. In one or more embodiments, in a plan view, the sixth extension portion PXE12-2 may overlap with the eighth pixel circuit PC8 and the twelfth pixel circuit PC12. For example, the sixth extension portion PXE12-2 may extend in a direction opposite to the first direction DR1 and pass over the upper portion of each of the eighth pixel circuit PC8 and the twelfth pixel circuit PC12.

[0243] In one or more embodiments, in a plan view, the sixth extension portion PXE12-2 may be spaced apart (e.g., spaced apart) from the first portion of the eighth pixel electrode PXE8 in a direction opposite to the second direction DR2. In one or more embodiments, in a plan view, the sixth extension portion PXE12-2 may be spaced apart (e.g., spaced apart) from the fifth main portion PXE10-1 of the tenth pixel electrode PXE10 in the second direction DR2. In other words, in a plan view, the sixth extension portion PXE12-2 may be located between the first portion of the eighth pixel electrode PXE8 and the fifth main portion PXE10-1 of the tenth pixel electrode PXE10.

[0244] In one or more embodiments, the sixth extension portion PXE12-2 may extend from the top of the eighth pixel circuit PC8 and may contact the twelfth connection electrode CNE12 of the twelfth pixel circuit PC12 through the contact hole of the second via insulating layer VIA2. Since the sixth extension portion PXE12-2 contacts the twelfth connection electrode CNE12, the twelfth pixel electrode PXE12 and the twelfth pixel circuit PC12 may be electrically connected to each other.

[0245] In one or more embodiments, the pixel electrodes disposed in a row can be regularly arranged along a first direction DR1. For example, the pixel electrodes disposed in the Nth row R (N) can be arranged in the order of the second pixel electrode PXE2, the first pixel electrode PXE1, the third pixel electrode PXE3, the fourth pixel electrode PXE4, the fifth pixel electrode PXE5, and the sixth pixel electrode PXE6. Furthermore, the pixel electrodes disposed in the N+1th row R (N+1) can be arranged in the order of the eighth pixel electrode PXE8, the seventh pixel electrode PXE7, the ninth pixel electrode PXE9, the tenth pixel electrode PXE10, the eleventh pixel electrode PXE11, and the twelfth pixel electrode PXE12.

[0246] In one or more embodiments, the arrangement of pixel electrodes in the Nth row R(N) and the arrangement of pixel electrodes in the N+1th row R(N+1) can be repeated along the second direction DR2. For example, the arrangement of pixel electrodes in the Nth row R(N) and the arrangement of pixel electrodes in the N+1th row R(N+1) can be alternately arranged along the second direction DR2.

[0247] In one or more embodiments, in a planar view, the first auxiliary electrode AXE1 may be disposed between the sixth pixel electrode PXE6 and the twelfth pixel electrode PXE12. Specifically, in a planar view, the first auxiliary electrode AXE1 may be disposed between the third main portion PXE6-1 and the sixth main portion PXE12-1. In one or more embodiments, in a planar view, the first auxiliary electrode AXE1 may overlap with the first pixel circuit PC1, the second pixel circuit PC2, the seventh pixel circuit PC7, and the eighth pixel circuit PC8. In one or more embodiments, in a planar view, the first auxiliary electrode AXE1 may overlap with the first data line DL1.

[0248] In one or more embodiments, multiple first auxiliary electrodes AXE1 may be configured along a first direction DR1 and a second direction DR2. A thirteenth hole H13 may be defined in a pixel defining layer PDL covering the upper portion of some of the multiple first auxiliary electrodes AXE1. The thirteenth hole H13 may not be defined in the pixel defining layer PDL covering the upper portion of the remaining first auxiliary electrodes AXE1.

[0249] In one or more embodiments, the second auxiliary electrode AXE2 may be disposed from the fifth pixel electrode PXE5 in the opposite direction to the second direction DR2. For example, the second auxiliary electrode AXE2 may be spaced apart (e.g., spaced apart) from each of the second extension PXE4-2 of the fourth pixel electrode PXE4 and the fifth pixel electrode PXE5 in the opposite direction to the second direction DR2.

[0250] In one or more embodiments, the second auxiliary electrode AXE2 may be disposed on the eleventh pixel electrode PXE11 along the second direction DR2. For example, the second auxiliary electrode AXE2 may be spaced apart from each of the eleventh pixel electrodes PXE11 along the second direction DR2. In one or more embodiments, the second auxiliary electrode AXE2 may be repeatedly disposed along the second direction DR2. For example, the second auxiliary electrode AXE2 may be disposed in multiple rows with one row spaced apart.

[0251] In one or more embodiments, the first auxiliary electrode AXE1 and the second auxiliary electrode AXE2 may have the same shape in a plan view. However, the shapes of the first auxiliary electrode AXE1 and the second auxiliary electrode AXE2 according to this disclosure are not necessarily limited to this, and in a plan view, the shapes of each of the first auxiliary electrode AXE1 and the second auxiliary electrode AXE2 may be different from each other.

[0252] A pixel defining layer (PDL) may be disposed on a pixel electrode layer (PXL). In one or more embodiments, the pixel defining layer (PDL) may include an organic insulating material such as polyimide. A light-emitting layer (EML) may be disposed on the pixel defining layer (PDL). In one or more embodiments, the light-emitting layer (EML) may include a light-emitting material. For example, the light-emitting material may include organic light-emitting materials and / or quantum dots, etc. A common electrode (CME) may be disposed on the light-emitting layer (EML). For example, the common electrode (CME) may be disposed on both the light-emitting layer (EML) and the pixel defining layer (PDL). In one or more embodiments, the common electrode (CME) may include a conductive material.

[0253] At least one hole may be defined in the pixel definition layer (PDL) to expose a portion of the upper surface of each of the first pixel electrode PXE1, the second pixel electrode PXE2, the third pixel electrode PXE3, the fourth pixel electrode PXE4, the fifth pixel electrode PXE5, the sixth pixel electrode PXE6, the seventh pixel electrode PXE7, the eighth pixel electrode PXE8, the ninth pixel electrode PXE9, the tenth pixel electrode PXE10, the eleventh pixel electrode PXE11, the twelfth pixel electrode PXE11, and the first auxiliary electrode AXE1.

[0254] In one or more embodiments, the holes may penetrate the pixel-defining layer (PDL) in the thickness direction (e.g., on the third direction DR3). The holes may include a first hole H1, a second hole H2, a third hole H3, a fourth hole H4, a fifth hole H5, a sixth hole H6, a seventh hole H7, an eighth hole H8, a ninth hole H9, a tenth hole H10, an eleventh hole H11, a twelfth hole H12, and a thirteenth hole H13.

[0255] In one or more embodiments, the first aperture H1 may expose a portion of the upper surface of the first pixel electrode PXE1. For example, the first aperture H1 may expose a first portion of the first pixel electrode PXE1.

[0256] In one or more embodiments, the first light-emitting layer EML1 may fill the first hole H1. As described above, the first light-emitting layer EML1, together with the first pixel electrode PXE1 and the common electrode CME, may define a first light-emitting element EL1 that emits light of a first color. In one or more embodiments, in a plan view, the first light-emitting layer EML1 may overlap with the third pixel circuit PC3.

[0257] In one or more embodiments, the second aperture H2 may expose a portion of the upper surface of the second pixel electrode PXE2. For example, the second aperture H2 may expose a first portion of the second pixel electrode PXE2.

[0258] In one or more embodiments, the second light-emitting layer EML2 may fill the second hole H2. For example, the second light-emitting layer EML2 may define a light-emitting element emitting light of a first color together with the second pixel electrode PXE2 and the common electrode CME. In one or more embodiments, in a plan view, the second light-emitting layer EML2 may overlap with the sixth pixel circuit PC6.

[0259] In one or more embodiments, the third aperture H3 may expose a portion of the upper surface of the third pixel electrode PXE3. For example, the third aperture H3 may expose a first major portion PXE3-1 of the third pixel electrode PXE3.

[0260] In one or more embodiments, the third emissive layer EML3 may fill the third hole H3. For example, the third emissive layer EML3 may define a light-emitting element that emits light of a second color together with the third pixel electrode PXE3 and the common electrode CME. In one or more embodiments, in a plan view, the third emissive layer EML3 may overlap with the third pixel circuit PC3 and the first main portion PXE3-1.

[0261] In one or more embodiments, the fourth aperture H4 may expose a portion of the upper surface of the fourth pixel electrode PXE4. For example, the fourth aperture H4 may expose a second major portion PXE4-1 of the fourth pixel electrode PXE4.

[0262] In one or more embodiments, the fourth light-emitting layer EML4 may fill the fourth hole H4. For example, the fourth light-emitting layer EML4 may define a light-emitting element emitting light of a second color together with the fourth pixel electrode PXE4 and the common electrode CME. In one or more embodiments, in a plan view, the fourth light-emitting layer EML4 may overlap with the sixth pixel circuit PC6 and the second main portion PXE4-1.

[0263] In one or more embodiments, the fifth aperture H5 may expose a portion of the upper surface of the fifth pixel electrode PXE5. In one or more embodiments, the fifth emissive layer EML5 may fill the fifth aperture H5. For example, the fifth emissive layer EML5 may define a light-emitting element emitting light of a third color together with the fifth pixel electrode PXE5 and the common electrode CME. In embodiments, in a plan view, the fifth emissive layer EML5 may overlap with the fourth pixel circuit PC4 and the fifth pixel circuit PC5.

[0264] In one or more embodiments, the sixth aperture H6 may expose a portion of the upper surface of the sixth pixel electrode PXE6. For example, the sixth aperture H6 may expose the third main portion PXE6-1 of the sixth pixel electrode PXE6.

[0265] In one or more embodiments, the sixth emissive layer EML6 may fill the sixth aperture H6. For example, the sixth emissive layer EML6 may define an emissive element emitting light of a third color together with the sixth pixel electrode PXE6 and the common electrode CME. In one or more embodiments, in a plan view, the sixth emissive layer EML6 may overlap with the first pixel circuit PC1 and the second pixel circuit PC2. In one or more embodiments, in a plan view, the sixth emissive layer EML6 may overlap with the third main portion PXE6-1.

[0266] In one or more embodiments, the seventh hole H7 may expose a portion of the upper surface of the seventh pixel electrode PXE7. For example, the seventh hole H7 may expose a first portion of the seventh pixel electrode PXE7.

[0267] In one or more embodiments, the seventh emissive layer EML7 may fill the seventh hole H7. For example, the seventh emissive layer EML7 may define a light-emitting element emitting light of a first color together with the seventh pixel electrode PXE7 and the common electrode CME. In one or more embodiments, in a plan view, the seventh emissive layer EML7 may overlap with the ninth pixel circuit PC9.

[0268] In one or more embodiments, the eighth hole H8 may expose a portion of the upper surface of the eighth pixel electrode PXE8. For example, the eighth hole H8 may expose a first portion of the eighth pixel electrode PXE8.

[0269] In one or more embodiments, the eighth emitting layer EML8 may fill the eighth hole H8. For example, the eighth emitting layer EML8 may define a light-emitting element emitting light of a first color together with the eighth pixel electrode PXE8 and the common electrode CME. In one or more embodiments, in a planar view, the eighth emitting layer EML8 may overlap with the twelfth pixel circuit PC12.

[0270] In one or more embodiments, the ninth aperture H9 may expose a portion of the upper surface of the ninth pixel electrode PXE9. For example, the ninth aperture H9 may expose the fourth major portion PXE9-1 of the ninth pixel electrode PXE9.

[0271] In one or more embodiments, the ninth light-emitting layer EML9 may fill the ninth hole H9. For example, the ninth light-emitting layer EML9 may define a light-emitting element that emits light of a second color together with the ninth pixel electrode PXE9 and the common electrode CME. In one or more embodiments, in a plan view, the ninth light-emitting layer EML9 may overlap with the ninth pixel circuit PC9 and the fourth main portion PXE9-1.

[0272] In one or more embodiments, the tenth aperture H10 may expose a portion of the upper surface of the tenth pixel electrode PXE10. For example, the tenth aperture H10 may expose the fifth major portion PXE10-1 of the tenth pixel electrode PXE10.

[0273] In one or more embodiments, the tenth emitting layer EML10 may fill the tenth aperture H10. For example, the tenth emitting layer EML10 may define a light-emitting element that emits light of a second color together with the tenth pixel electrode PXE10 and the common electrode CME. In one or more embodiments, in a plan view, the tenth emitting layer EML10 may overlap with the twelfth pixel circuit PC12 and the fifth main portion PXE10-1.

[0274] In one or more embodiments, the eleventh aperture H11 may expose a portion of the upper surface of the eleventh pixel electrode PXE11. In one or more embodiments, the eleventh emitting layer EML11 may fill the eleventh aperture H11. For example, the eleventh emitting layer EML11 may define a light-emitting element emitting light of a third color together with the eleventh pixel electrode PXE11 and the common electrode CME. In one or more embodiments, in a plan view, the eleventh emitting layer EML11 may overlap with the tenth pixel circuit PC10 and the eleventh pixel circuit PC11.

[0275] In one or more embodiments, the twelfth aperture H12 may expose a portion of the upper surface of the twelfth pixel electrode PXE12. For example, the twelfth aperture H12 may expose the sixth major portion PXE12-1 of the twelfth pixel electrode PXE12.

[0276] In one or more embodiments, the twelfth emitting layer EML12 may fill the twelfth hole H12. For example, the twelfth emitting layer EML12 may define a light-emitting element emitting light of a third color together with the twelfth pixel electrode PXE12 and the common electrode CME. In one or more embodiments, in a plan view, the twelfth emitting layer EML12 may overlap with the seventh pixel circuit PC7 and the eighth pixel circuit PC8. In one or more embodiments, in a plan view, the twelfth emitting layer EML12 may overlap with the sixth main portion PXE12-1.

[0277] In one or more embodiments, a thirteenth hole H13 may be defined in the pixel-defining film PDL covering the first auxiliary electrode AXE1 to expose a portion of the upper surface of the first auxiliary electrode AXE1. In one or more embodiments, the thirteenth hole H13 may expose a portion of the upper surface of the first auxiliary electrode AXE1.

[0278] In one or more embodiments, the common electrode CME can be electrically connected to the first auxiliary electrode AXE1 via the thirteenth hole H13. Accordingly, a second electrical voltage (e.g., ...) applied to the common electrode CME can be prevented. Figure 3 The voltage drop phenomenon of the second power voltage (ELVSS).

[0279] In one or more embodiments, the thirteenth hole H13 can be formed by a laser drilling process. However, the emissive layer EML and the thirteenth hole H13 according to this disclosure are not necessarily limited thereto. For example, the emissive layer EML can be formed to completely surround the upper portion of the pixel defining layer PDL, and the thirteenth hole H13 can penetrate each of the pixel defining layer PDL and the emissive layer EML in the thickness direction (e.g., third-direction DR3).

[0280] In one or more embodiments, a plurality of first auxiliary electrodes AXE1 may be disposed along a first direction DR1 and a second direction DR2. In one or more embodiments, a plurality of second auxiliary electrodes AXE2 may be disposed along the first direction DR1 and the second direction DR2. In one or more embodiments, a pixel defining layer PDL may cover the entire upper surface of each of the plurality of second auxiliary electrodes AXE2.

[0281] In one or more embodiments, the number of thirteenth holes H13 may be the same as the number of first auxiliary electrodes AXE1. For example, a plurality of first auxiliary electrodes AXE1 may be arranged along a first direction DR1 and a second direction DR2, and the thirteenth holes H13 may be arranged at each location where each of the plurality of first auxiliary electrodes AXE1 is arranged.

[0282] In another embodiment, the number of thirteenth holes H13 may be less than the number of first auxiliary electrodes AXE1. For example, thirteenth holes H13 may be provided at each location of some of the plurality of first auxiliary electrodes AXE1. For example, a thirteenth hole H13 may be provided at each of two or more first auxiliary electrodes AXE1 that are adjacent to each other along the first direction DR1 or the second direction DR2.

[0283] As described above, in the display device 1 according to the present disclosure, the data voltage VDATA can be provided to each of the pixels included in the first pixel group PXG1 in response to a first write gate signal GW1 applied via the first write gate line GWL1. Additionally, the data voltage VDATA can be provided to each of the pixels included in the first pixel group PXG1 and arranged in the second pixel group PXG2 in response to a second write gate signal GW2 applied via the second write gate line GWL2 at a timing different from the application timing of the first write gate signal GW1. Accordingly, the display device 1 can selectively output the data voltage VDATA to one of the plurality of pixels arranged in the same row without the need for a demultiplexing circuit that selectively outputs the data voltage VDATA to one of the plurality of pixels arranged in the same row. Consequently, the power efficiency of the display device 1 is improved, the number of pixels arranged in the display area DA of the display device 1 can be increased, and the display quality can be improved.

[0284] Figure 10 The illustration includes Figure 1 Another example of the layout diagram showing the arrangement of pixels in a display panel.

[0285] In addition to Figure 8 Except for the second auxiliary electrode AXE2, which is omitted in the light-emitting element layer DEL, see reference. Figure 10 The described display device can be compared with the reference. Figure 8 The described display devices are substantially the same or similar.

[0286] In the following text, descriptions and references may be omitted or briefly described. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The content described is repetitive.

[0287] refer to Figure 10The light-emitting element layer DELa may include a pixel electrode layer PXLa, a pixel definition layer PDL, a light-emitting layer EML, and a common electrode CME. The pixel electrode layer PXLa may include a first pixel electrode PXE1, a second pixel electrode PXE2, a third pixel electrode PXE3, a fourth pixel electrode PXE4, a fifth pixel electrode PXE5, a sixth pixel electrode PXE6, a seventh pixel electrode PXE7, an eighth pixel electrode PXE8, a ninth pixel electrode PXE9, a tenth pixel electrode PXE10, an eleventh pixel electrode PXE11, a twelfth pixel electrode PXE12, and a first auxiliary electrode AXE1.

[0288] In one or more embodiments, the auxiliary electrode may not be disposed in the row where the fourth pixel circuit PC4 and the fifth pixel circuit PC5 are disposed. For example, the components of the pixel electrode layer PXLa disposed along the column where the fourth pixel circuit PC4 and the fifth pixel circuit PC5 are disposed may be disposed along the second direction DR2 in the order of the second extension PXE4-2 of the fourth pixel electrode PXE4, the fifth pixel electrode PXE5, the fifth extension PXE10-2 of the tenth pixel electrode PXE10, and the eleventh pixel electrode PXE11. In other words, Figure 8 The second auxiliary electrode AXE2 may not be disposed on the fourth pixel circuit PC4, the fifth pixel circuit PC5, the tenth pixel circuit PC10, and the eleventh pixel circuit PC11. Accordingly, the area on the pixel circuit layer PXC where the second extension PXE4-2 of the fourth pixel electrode PXE4 is disposed can be easily ensured, and the size of the area can be reduced. Figure 1 The time and cost of manufacturing the display device 1.

[0289] Figure 11 and Figure 12 The illustration includes Figure 1 A layout diagram showing another example of the arrangement of pixels in a display panel. Figure 13 This is an explanation Figure 12 A plan view illustrating an example arrangement of pixel electrodes and auxiliary electrodes. For example, Figure 13 It is a diagram. Figure 12 A plan view of the pixel circuit layer PXCb, the fifth pixel electrode PXE5b, the sixth pixel electrode PXE6b, the eleventh pixel electrode PXE11b, the twelfth pixel electrode PXE12b, the first auxiliary electrode AXE1b, and the second auxiliary electrode AXE2b.

[0290] In addition to the arrangement and shape of the components included in the pixel circuit layer PXCb and the light-emitting element layer DELb, reference Figure 11 and Figure 12 The described display device can be compared with the reference. Figure 8 The described display devices are substantially the same or similar.

[0291] In the following text, descriptions and references may be omitted or briefly described. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The description repeats any content.

[0292] refer to Figure 11 , Figure 12 and Figure 13 The pixel circuit layer PXCb may include a first pixel circuit PC1b, a second pixel circuit PC2b, a third pixel circuit PC3b, a fourth pixel circuit PC4b, a fifth pixel circuit PC5b, a sixth pixel circuit PC6b, a seventh pixel circuit PC7b, an eighth pixel circuit PC8b, a ninth pixel circuit PC9b, a tenth pixel circuit PC10b, an eleventh pixel circuit PC11b, and a twelfth pixel circuit PC12b.

[0293] The second pixel circuit PC2b may include a first connection electrode CNE1b. The third pixel circuit PC3b may include a second connection electrode CNE2b. The fourth pixel circuit PC4b may include a third connection electrode CNE3b. The fifth pixel circuit PC5b may include a fourth connection electrode CNE4b. The eighth pixel circuit PC8b may include a fifth connection electrode CNE5b. The ninth pixel circuit PC9b may include a sixth connection electrode CNE6b. The tenth pixel circuit PC10b may include a seventh connection electrode CNE7b. The eleventh pixel circuit PC11b may include an eighth connection electrode CNE8b.

[0294] In one or more embodiments, in a planar view, the fourth connection electrode CNE4b may overlap with each of the fifth pixel circuit PC5b and the eleventh pixel circuit PC11b. In one or more embodiments, in a planar view, the fifth connection electrode CNE5b may overlap with each of the second pixel circuit PC2b and the eighth pixel circuit PC8b (e.g., see...). Figure 11 ).

[0295] The pixel electrode layer PXLb may include a first pixel electrode PXE1b, a second pixel electrode PXE2b, a third pixel electrode PXE3b, a fourth pixel electrode PXE4b, a fifth pixel electrode PXE5b, a sixth pixel electrode PXE6b, a seventh pixel electrode PXE7b, an eighth pixel electrode PXE8b, a ninth pixel electrode PXE9b, a tenth pixel electrode PXE10b, an eleventh pixel electrode PXE11b, a twelfth pixel electrode PXE12b, a first auxiliary electrode AXE1b, and a second auxiliary electrode AXE2b.

[0296] The first pixel electrode PXE1b may include a first main portion PXE1-1b and a first extension portion PXE1-2b. In one or more embodiments, in a plan view, the first main portion PXE1-1b may overlap with each of the first pixel circuit PC1b and the seventh pixel circuit PC7b. In one or more embodiments, the first extension portion PXE1-2b may extend from the first main portion PXE1-1b in a first direction DR1 and may overlap with each of the ninth pixel circuit PC9b and the tenth pixel circuit PC10b in a plan view.

[0297] The second pixel electrode PXE2b may include a second main portion PXE2-1b and a second extension portion PXE2-2b. In one or more embodiments, in a plan view, the second main portion PXE2-1b may overlap with the fifth pixel circuit PC5b and the eleventh pixel circuit PC11b. In one or more embodiments, in a plan view, the second main portion PXE2-1b may overlap with the fourth connection electrode CNE4b.

[0298] In one or more embodiments, the second extension portion PXE2-2b may extend from the second main portion PXE2-1b along the first direction DR1 and may overlap with each of the second pixel circuit PC2b and the sixth pixel circuit PC6b in a plan view. For example, in a plan view, the second extension portion PXE2-2b may overlap with the first connection electrode CNE1b. Specifically, the second extension portion PXE2-2b extending from the second main portion PXE2-1b along the first direction DR1 may penetrate the second via insulating layer (e.g., in the thickness direction, third direction DR3) through the second via insulating layer. Figure 9 The contact hole of the second through-hole insulating layer (VIA2) contacts the first connection electrode CNE1b. Accordingly, the second pixel electrode PXE2b can be electrically connected to the second pixel circuit PC2b via the first connection electrode CNE1b.

[0299] In one or more embodiments, in a planar view, the third pixel electrode PXE3b may overlap with each of the first pixel circuit PC1b and the third pixel circuit PC3b. For example, a first portion of the third pixel electrode PXE3b may overlap with the first pixel circuit PC1b in a planar view, and a second portion extending from the first portion of the third pixel electrode PXE3b in a diagonal direction of the first direction DR1 and the second direction DR2 may overlap with the third pixel circuit PC3b in a planar view.

[0300] The third pixel electrode PXE3b can be electrically connected to the third pixel circuit PC3b via the second connection electrode CNE2b. Specifically, a second portion of the third pixel electrode PXE3b can contact the second connection electrode CNE2b through a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3).

[0301] In one or more embodiments, in a planar view, the fourth pixel electrode PXE4b may overlap with each of the fourth pixel circuit PC4b and the fifth pixel circuit PC5b. For example, a first portion of the fourth pixel electrode PXE4b may overlap with the fifth pixel circuit PC5b in a planar view, and a second portion extending from the first portion of the fourth pixel electrode PXE4b in the opposite direction to the first direction DR1 and the oblique direction of the second direction DR2 may overlap with the fourth pixel circuit PC4b in a planar view.

[0302] The fourth pixel electrode PXE4b can be electrically connected to the fourth pixel circuit PC4b via the third connection electrode CNE3b. Specifically, a second portion of the fourth pixel electrode PXE4b can contact the third connection electrode CNE3b via a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3).

[0303] The fifth pixel electrode PXE5b may include a third main portion PXE5-1b and a third extension portion PXE5-2b. In one or more embodiments, in a plan view, the third main portion PXE5-1b may overlap with each of the third pixel circuit PC3b and the fourth pixel circuit PC4b.

[0304] In one or more embodiments, the third extension portion PXE5-2b may extend from the third main portion PXE5-1b along the diagonal direction of the first direction DR1 and the second direction DR2. In one or more embodiments, in a plan view, the third extension portion PXE5-2b may overlap with each of the tenth pixel circuit PC10b and the eleventh pixel circuit PC11b.

[0305] The fifth pixel electrode PXE5b can be electrically connected to the fifth pixel circuit PC5b via the fourth connection electrode CNE4b. Specifically, the third extension portion PXE5-2b of the fifth pixel electrode PXE5b can contact the fourth connection electrode CNE4b through a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3).

[0306] In one or more embodiments, in a planar view, the sixth pixel electrode PXE6b may overlap with each of the second pixel circuit PC2b and the sixth pixel circuit PC6b. In one or more embodiments, in a planar view, the sixth pixel electrode PXE6b may overlap with the first connection electrode CNE1b.

[0307] In one or more embodiments, in a planar view, the seventh pixel electrode PXE7b may overlap with the first pixel circuit PC1b and the seventh pixel circuit PC7b. In one or more embodiments, in a planar view, the shapes of the first pixel electrode PXE1b and the seventh pixel electrode PXE7b may be different from each other.

[0308] The eighth pixel electrode PXE8b may include a fourth main portion PXE8-1b and a fourth extension portion PXE8-2b. In one or more embodiments, in a plan view, the fourth main portion PXE8-1b may overlap with the fifth pixel circuit PC5b and the eleventh pixel circuit PC11b.

[0309] In one or more embodiments, in a plan view, the fourth extension portion PXE8-2b may overlap with the second pixel circuit PC2b and the sixth pixel circuit PC6b. For example, the fourth extension portion PXE8-2b may extend from the fourth main portion PXE8-1b in the first direction DR1 and may overlap with the second pixel circuit PC2b and the sixth pixel circuit PC6b in a plan view.

[0310] In one or more embodiments, in a plan view, the fourth extension portion PXE8-2b may overlap with the fifth connecting electrode CNE5b. For example, the fourth extension portion PXE8-2b may contact the fifth connecting electrode CNE5b through a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3). Accordingly, the eighth pixel electrode PXE8b may be electrically connected to the eighth pixel circuit PC8b through the fifth connecting electrode CNE5b.

[0311] The ninth pixel electrode PXE9b can be electrically connected to the ninth pixel circuit PC9b via the sixth connection electrode CNE6b. For example, the ninth pixel electrode PXE9b can contact the sixth connection electrode CNE6b via a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3). In one or more embodiments, in a plan view, the shape of the third pixel electrode PXE3b can be substantially the same as the shape of the ninth pixel electrode PXE9b.

[0312] In one or more embodiments, in a planar view, the ninth pixel electrode PXE9b may overlap with each of the seventh pixel circuit PC7b and the ninth pixel circuit PC9b. For example, a first portion of the ninth pixel electrode PXE9b may overlap with the seventh pixel circuit PC7b in a planar view, and a second portion extending from the first portion of the ninth pixel electrode PXE9b in a diagonal direction of the first direction DR1 and the second direction DR2 may overlap with the ninth pixel circuit PC9b in a planar view.

[0313] The tenth pixel electrode PXE10b can be electrically connected to the tenth pixel circuit PC10b via the seventh connection electrode CNE7b. For example, the tenth pixel electrode PXE10b can contact the seventh connection electrode CNE7b via a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3). In one or more embodiments, in a plan view, the shape of the fourth pixel electrode PXE4b can be substantially the same as the shape of the tenth pixel electrode PXE10b.

[0314] In one or more embodiments, the tenth pixel electrode PXE10b may overlap with each of the tenth pixel circuit PC10b and the eleventh pixel circuit PC11b in a planar view. For example, a first portion of the tenth pixel electrode PXE10b may overlap with the eleventh pixel circuit PC11b in a planar view, and a second portion extending from the first portion of the tenth pixel electrode PXE10b in the opposite direction of the first direction DR1 and the oblique direction of the second direction DR2 may overlap with the tenth pixel circuit PC10b in a planar view.

[0315] The eleventh pixel electrode PXE11b may include a fifth main portion PXE11-1b and a fifth extension portion PXE11-2b. In one or more embodiments, in a plan view, the fifth main portion PXE11-1b may overlap with each of the ninth pixel circuit PC9b and the tenth pixel circuit PC10b.

[0316] In one or more embodiments, in a plan view, the fifth extension portion PXE11-2b may overlap with each of the fourth pixel circuit PC4b and the tenth pixel circuit PC10b. For example, in one or more embodiments, the fifth extension portion PXE11-2b may extend from the fifth main portion PXE11-1b in the diagonal direction of the first direction DR1 and the second direction DR2, and may overlap with each of the fourth pixel circuit PC4b and the tenth pixel circuit PC10b in a plan view.

[0317] In an embodiment, in a plan view, the fifth extension portion PXE11-2b may overlap with the eighth connection electrode CNE8b. For example, the fifth extension portion PXE11-2b may contact the eighth connection electrode CNE8b through a contact hole that penetrates the second via insulating layer in the thickness direction (e.g., third direction DR3). Accordingly, the eleventh pixel electrode PXE11b may be electrically connected to the eleventh pixel circuit PC11b via the eighth connection electrode CNE8b.

[0318] In one or more embodiments, in a planar view, the twelfth pixel electrode PXE12b may overlap with each of the twelfth pixel circuit PC12b and the eighth pixel circuit PC8b. In one or more embodiments, in a planar view, the twelfth pixel electrode PXE12b may overlap with the fifth connection electrode CNE5b.

[0319] In one or more embodiments, the fifth pixel electrode PXE5b and the sixth pixel electrode PXE6b may have a zigzag shape along the first direction DR1. Specifically, when the centers of a plurality of fifth pixel electrodes PXE5b and a plurality of sixth pixel electrodes PXE6b disposed along the first direction DR1 are connected in a planar view, the first virtual line LN1 connecting these centers may be zigzag based on the first direction DR1.

[0320] In one or more embodiments, the eleventh pixel electrode PXE11b and the twelfth pixel electrode PXE12b may have a zigzag shape along the first direction DR1. Specifically, when the centers of a plurality of eleventh pixel electrodes PXE11b and a plurality of twelfth pixel electrodes PXE12b disposed along the first direction DR1 are connected in a planar view, the second virtual line LN2 connecting these centers may be zigzag based on the first direction DR1. In one or more embodiments, the first virtual line LN1 and the second virtual line LN2 may be symmetrical based on lines parallel to the first direction DR1 and adjacent to each other at the Nth row R(N) and the (N+1)th row R(N+1).

[0321] In the planar view, the first auxiliary electrode AXE1b can overlap with each of the ninth pixel circuit PC9b and the tenth pixel circuit PC10b. For example, the first auxiliary electrode AXE1b can be disposed on the ninth pixel circuit PC9b and the tenth pixel circuit PC10b along the second direction DR2. Specifically, in the planar view, the first auxiliary electrode AXE1b can be disposed from the fifth pixel electrode PXE5b in the opposite direction to the second direction DR2, and can be disposed from the eleventh pixel electrode PXE11b on the second direction DR2. In other words, the components of the pixel electrode layer PXLb disposed along the column in which the ninth pixel circuit PC9b and the tenth pixel circuit PC10b are disposed can be repeatedly disposed along the second direction DR2 in the order of the first auxiliary electrode AXE1b, the fifth pixel electrode PXE5b, and the eleventh pixel electrode PXE11b.

[0322] In a planar view, the second auxiliary electrode AXE2b may overlap with each of the second pixel circuit PC2b and the sixth pixel circuit PC6b. For example, the second auxiliary electrode AXE2b may be disposed on the second pixel circuit PC2b and the sixth pixel circuit PC6b along the second direction DR2. Specifically, in a planar view, the second auxiliary electrode AXE2b may be disposed on the second direction DR2 from the sixth pixel electrode PXE6b adjacent to the second auxiliary electrode AXE2b, and may be disposed in the opposite direction of the second direction DR2 from the twelfth pixel electrode PXE12b adjacent to the second auxiliary electrode AXE2b. In other words, the components of the pixel electrode layer PXLb disposed along the column in which the second pixel circuit PC2b and the sixth pixel circuit PC6b are disposed may be repeatedly disposed along the second direction DR2 in the order of the sixth pixel electrode PXE6b, the second auxiliary electrode AXE2b, and the twelfth pixel electrode PX12b. In one or more embodiments, the pixel defining layer PDL may completely cover the upper surface of each of the plurality of second auxiliary electrodes AXE2b.

[0323] In one or more embodiments, the shapes of the first auxiliary electrode AXE1b and the second auxiliary electrode AXE2b may be substantially the same in a plan view. In one or more embodiments, the dimensions of the first auxiliary electrode AXE1b and the second auxiliary electrode AXE2b may be substantially the same in a plan view. However, the relationship between the first auxiliary electrode AXE1b and the second auxiliary electrode AXE2b according to this disclosure is not necessarily limited to this.

[0324] However, the arrangement, shape, and / or size of the first connecting electrode CNE1, the second connecting electrode CNE2, the third connecting electrode CNE3, the fourth connecting electrode CNE4, the fifth connecting electrode CNE5, the sixth connecting electrode CNE6, the seventh connecting electrode CNE7, the eighth connecting electrode CNE8, the ninth connecting electrode CNE9, the tenth connecting electrode CNE10, the eleventh connecting electrode CNE11, and the twelfth connecting electrode CNE12 according to this disclosure may be shown as an example and may not be limited thereto.

[0325] However, the number, shape, size, and / or arrangement of the connection electrodes included in the pixel circuit layer PXCb according to this disclosure may be shown as examples and are not necessarily limited thereto. For example, the first pixel circuit PC1b may include a connection electrode that overlaps with and is electrically connected to the first pixel electrode PXE1b in a plan view; the sixth pixel circuit PC6b may include a connection electrode that overlaps with and is electrically connected to the sixth pixel electrode PXE6b in a plan view; the seventh pixel circuit PC7b may include a connection electrode that overlaps with and is electrically connected to the seventh pixel electrode PXE7b in a plan view; and the twelfth pixel circuit PC12b may include a connection electrode that overlaps with and is electrically connected to the twelfth pixel electrode PXE12b in a plan view.

[0326] The light-emitting layer EMLb may include a first light-emitting layer EML1b, a second light-emitting layer EML2b, a third light-emitting layer EML3b, a fourth light-emitting layer EML4b, a fifth light-emitting layer EML5b, a sixth light-emitting layer EML6b, a seventh light-emitting layer EML7b, an eighth light-emitting layer EML8b, a ninth light-emitting layer EML9b, a tenth light-emitting layer EML10b, an eleventh light-emitting layer EML11b, and a twelfth light-emitting layer EML12b.

[0327] Holes penetrating the pixel-defining layer (PDL) in the thickness direction (e.g., third direction DR3) may include a first hole H1b, a second hole H2b, a third hole H3b, a fourth hole H4b, a fifth hole H5b, a sixth hole H6b, a seventh hole H7b, an eighth hole H8b, a ninth hole H9b, a tenth hole H10b, an eleventh hole H11b, a twelfth hole H12b, and a thirteenth hole H13b. Apart from shape, size, and location, the light-emitting layer (EMLb) and the holes can be related to... Figure 8 The light-emitting layer EML and the apertures are basically the same or similar.

[0328] In one or more embodiments, a pixel-defining layer covering the first auxiliary electrode AXE1b (e.g., Figure 9The pixel-defining layer (PDL) can define a thirteenth hole H13b that exposes a portion of the upper surface of the first auxiliary electrode AXE1b.

[0329] In one or more embodiments, the number of thirteenth holes H13b can be equal to the number of first auxiliary electrodes AXE1b. For example, a plurality of first auxiliary electrodes AXE1b can be arranged along a first direction DR1 and a second direction DR2, and the thirteenth holes H13b can be arranged at each location where each of the plurality of first auxiliary electrodes AXE1b is arranged.

[0330] In another embodiment, the number of thirteenth holes H13b may be less than the number of first auxiliary electrodes AXE1b. For example, thirteenth holes H13b may be provided at each location of some of the multiple first auxiliary electrodes AXE1b. For example, a thirteenth hole H13b may be provided at each of two or more first auxiliary electrodes AXE1b that are adjacent to each other along the first direction DR1 or the second direction DR2.

[0331] Figure 14 This is an explanation Figure 12 A plan view of another example of the arrangement of pixel electrodes and auxiliary electrodes.

[0332] In addition to the arrangement of the first auxiliary electrode AXE1c, the fifth pixel electrode PXE5c, the sixth pixel electrode PXE6c, the eleventh pixel electrode PXE11c, and the twelfth pixel electrode PXE12c, refer to Figure 14 The described display device can be compared with the reference. Figure 11 , Figure 12 and Figure 13 The described display devices are substantially the same or similar.

[0333] In the following text, descriptions and references may be omitted or briefly described. Figure 11 , Figure 12 and Figure 13 The description repeats any content.

[0334] refer to Figure 14 The pixel electrode layer PXLc may include a fifth pixel electrode PXE5c, a sixth pixel electrode PXE6c, an eleventh pixel electrode PXE11c, a twelfth pixel electrode PXE12c, and a first auxiliary electrode AXE1c. In this disclosure, the first auxiliary electrode AXE1c or multiple first auxiliary electrodes AXE1c may be referred to as auxiliary electrodes or multiple first auxiliary electrodes.

[0335] In one or more embodiments, the fifth pixel electrode PXE5c and the sixth pixel electrode PXE6c can be arranged in a row along the first direction DR1. Specifically, when the centers of a plurality of fifth pixel electrodes PXE5c and a plurality of sixth pixel electrodes PXE6c arranged along the first direction DR1 are connected in a planar view, the virtual line LN connecting these centers can be parallel to the first direction DR1.

[0336] In one or more embodiments, the eleventh pixel electrode PXE11c and the twelfth pixel electrode PXE12c can be arranged in a row along the first direction DR1. Specifically, when the centers of a plurality of eleventh pixel electrodes PXE11c and a plurality of twelfth pixel electrodes PXE12c arranged along the first direction DR1 are connected in a planar view, the virtual line LN connecting these centers can be parallel to the first direction DR1.

[0337] In one or more embodiments, in a planar view, the first auxiliary electrode AXE1c may overlap with each of the third pixel circuit PC3c, the fourth pixel circuit PC4c, the ninth pixel circuit PC9c, and the tenth pixel circuit PC10c. In one or more embodiments, the first auxiliary electrode AXE1c may be disposed from the fifth pixel electrode PXE5c in the second direction DR2 or in the opposite direction to the second direction DR2. In one or more embodiments, the first auxiliary electrode AXE1c may be disposed from the eleventh pixel electrode PXE11c in the second direction DR2 or in the opposite direction to the second direction DR2.

[0338] In one or more embodiments, the first auxiliary electrode AXE1c can be repeatedly arranged in multiple ways along the second direction DR2. For example, multiple first auxiliary electrodes can be repeatedly arranged along the second direction DR2.

[0339] In one or more embodiments, in a plan view, each of the plurality of first auxiliary electrodes may have substantially the same shape. However, the shape of each of the plurality of first auxiliary electrodes according to this disclosure is not necessarily limited to this.

[0340] In one or more embodiments, the components of the pixel electrode layer PXLc arranged along the column where the third pixel circuit PC3c and the fourth pixel circuit PC4c are disposed can be arranged along the second direction DR2 in the order of the first auxiliary electrode AXE1c, the fifth pixel electrode PXE5c, the first auxiliary electrode AXE1c, and the eleventh pixel electrode PXE11c. In one or more embodiments, in a plan view, the auxiliary electrode may not be disposed between the sixth pixel electrode PXE6c and the twelfth pixel electrode PXE12c. Accordingly, it can be easily ensured that the second extension portion PXE2-2b can pass through the space above each of the second pixel circuit PC2c and the sixth pixel circuit PC6c.

[0341] The emissive layer EMLc may include a fifth emissive layer EML5c, a sixth emissive layer EML6c, an eleventh emissive layer EML11c, and a twelfth emissive layer EML12c. It penetrates the pixel-defining layer (e.g., in the thickness direction, third-direction DR3) in the thickness direction. Figure 9 The apertures in the pixel-defined layer (PDL) may include a fifth aperture H5c, a sixth aperture H6c, an eleventh aperture H11c, a twelfth aperture H12c, and a thirteenth aperture H13c. Aside from shape, size, and position, the emissive layer (EMLc) and the apertures can be related to... Figure 12 The light-emitting layer EMLb and the pores are basically the same or similar.

[0342] In one or more embodiments, the thirteenth hole H13c is defined in a pixel defining layer covering the first auxiliary electrode AXE1c, and the thirteenth hole H13c may expose a portion of the upper surface of the first auxiliary electrode AXE1c.

[0343] In one or more embodiments, the thirteenth hole H13c may be defined in the upper pixel definition layer PDL covering some of the plurality of first auxiliary electrodes. The thirteenth hole H13c may not be defined in the upper pixel definition layer PDL covering the remaining electrodes of the plurality of first auxiliary electrodes.

[0344] In one or more embodiments, the number of thirteenth holes H13c can be equal to the number of first auxiliary electrodes AXE1c. For example, multiple first auxiliary electrodes can be arranged along a first direction DR1 and a second direction DR2, and the thirteenth holes H13c can be arranged at each location where each of the multiple first auxiliary electrodes is arranged.

[0345] In another embodiment, the number of thirteenth holes H13c may be less than the number of first auxiliary electrodes AXE1c. For example, thirteenth holes H13c may be provided at each location of some of the multiple first auxiliary electrodes. For example, one thirteenth hole H13c may be provided at each of two or more auxiliary electrodes that are adjacent to each other along the first direction DR1 or the second direction DR2.

[0346] Figure 15 This is a block diagram illustrating an electronic device according to one or more embodiments. Figure 16 This is a view illustrating an example of an electronic device implemented as a smartphone.

[0347] refer to Figure 15 and Figure 16The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. The display device 1060 included in the electronic device 1000 may be... Figure 1 The display device 1. In addition, the electronic device 1010 may further include several ports that can communicate with video cards, sound cards, memory cards or USB devices, or can communicate with other systems.

[0348] Processor 1010 can control display device 1060. For example, processor 1010 can perform specific calculations or tasks. According to one or more embodiments, processor 1010 can be a microprocessor, central processing unit, or application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, or data bus, etc. According to one or more embodiments, processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. Processor 1010 can process input image data and input control signals (e.g., Figure 1 The input image data (IMG) and the input control signal (CONT) are output to... Figure 1 The drive controller 200.

[0349] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0350] Storage device 1030 may include a solid-state drive (SSD), hard disk drive (HDD), or CD-ROM, etc. Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, or mouse, and output devices such as speakers or printers. According to one or more embodiments, display device 1060 may be included in input / output device 1040. Power supply 1050 may supply the power required for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link. Display device 1060 may be driven based on input image data and input control signals output from processor 1010.

[0351] In one or more embodiments, such as Figure 16 As shown, electronic device 1000 can be implemented as a smartphone. However, a smartphone is just one example of electronic device 1000, and the electronic device 1000 according to embodiments of this disclosure is not limited to this. For example, electronic device 1000 can be implemented as a television, mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle display, computer monitor, laptop computer, or head-mounted display device, etc. Additionally, electronic device 1000 can be a monitor. Furthermore, electronic device 1000 can be a car.

[0352] The display device according to embodiments of the present disclosure can be used as a display device included in a computer (e.g., a laptop computer or a smart tablet), a mobile phone, a smartphone, a PMP, a PDA, or an MP3 player, etc.

[0353] Although apparatuses according to embodiments of the present disclosure have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims and their equivalents.

Claims

1. A display device, comprising: The pixel circuit layer includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged in the same row; A first light-emitting element is configured to emit light of a first color and includes a first pixel electrode and a first light-emitting layer on the first pixel electrode, wherein the first pixel electrode is on the pixel circuit layer and electrically connected to the first pixel circuit. The second light-emitting element is configured to emit light of the first color and includes a second pixel electrode and a second light-emitting layer on the second pixel electrode, wherein the second pixel electrode is on the pixel circuit layer and electrically connected to the second pixel circuit. The third light-emitting element is configured to emit light of a second color different from the first color, and includes a third pixel electrode and a third light-emitting layer on the third pixel electrode. The third pixel electrode is on the pixel circuit layer, electrically connected to the third pixel circuit, and overlaps with each of the first pixel circuit, the second pixel circuit, and the third pixel circuit in a planar view. A first write gate line extends along a first direction in the pixel circuit layer and is configured to provide a first write gate signal to the first pixel circuit and the third pixel circuit. as well as A second write gate line extends along the first direction in the pixel circuit layer and is configured to provide a second write gate signal, applied at a timing different from that of the first write gate signal, to the second pixel circuit.

2. The display device according to claim 1, wherein, The third pixel electrode includes: The first main portion overlaps with the third pixel circuit in the plan view; and The first extension extends from the first main portion and overlaps with each of the first pixel circuit, the second pixel circuit, and the third pixel circuit in the plan view.

3. The display device according to claim 2, wherein, The pixel circuit layer further includes: The fourth pixel circuit is electrically connected to the second write gate line; The fifth pixel circuit is electrically connected to the first write gate line; and The sixth pixel circuit is electrically connected to the second write gate line.

4. The display device according to claim 3, wherein, The second pixel circuit, the first pixel circuit, the third pixel circuit, the fourth pixel circuit, the fifth pixel circuit, and the sixth pixel circuit are arranged repeatedly along the first direction in the order of the second pixel circuit, the first pixel circuit, the third pixel circuit, the fourth pixel circuit, the fifth pixel circuit, and the sixth pixel circuit.

5. The display device according to claim 3, further comprising: A fourth light-emitting element is configured to emit light of the second color and includes a fourth pixel electrode and a fourth light-emitting layer on the fourth pixel electrode, the fourth pixel electrode being on the pixel circuit layer and electrically connected to the fourth pixel circuit; The fifth light-emitting element is configured to emit light of a third color different from the first color and the second color, and includes a fifth pixel electrode and a fifth light-emitting layer on the fifth pixel electrode, the fifth pixel electrode being disposed on the pixel circuit layer and electrically connected to the fifth pixel circuit; as well as A sixth light-emitting element is configured to emit light of the third color and includes a sixth pixel electrode and a sixth light-emitting layer on the sixth pixel electrode, the sixth pixel electrode being on the pixel circuit layer and electrically connected to the sixth pixel circuit.

6. The display device according to claim 5, wherein, The fourth pixel electrode includes: The second main part overlaps with the sixth pixel circuit in the plan view; and The second extension extends from the second main portion and overlaps with each of the fourth and fifth pixel circuits.

7. The display device according to claim 3, further comprising: A first data line extends in the pixel circuit layer along a second direction intersecting the first direction and is electrically connected to each of the first pixel circuit and the second pixel circuit; The second data line extends along the second direction in the pixel circuit layer and is electrically connected to the third pixel circuit and the fourth pixel circuit; as well as The third data line extends along the second direction in the pixel circuit layer and is electrically connected to the fifth pixel circuit and the sixth pixel circuit. In the plan view, the first data line is located between the adjacent first pixel circuit and the second pixel circuit. In the plan view, the second data line is located between the adjacent third pixel circuit and the fourth pixel circuit, and In the plan view, the third data line is located between the fifth pixel circuit and the sixth pixel circuit, which are adjacent to each other.

8. A display device, comprising: The pixel circuit layer includes a first pixel circuit, a second pixel circuit spaced apart from the first pixel circuit in a first direction, and a third pixel circuit, a fourth pixel circuit, a fifth pixel circuit, and a sixth pixel circuit located between the first pixel circuit and the second pixel circuit and arranged sequentially along the first direction. A first light-emitting element is configured to emit light of a first color and includes a first pixel electrode and a first light-emitting layer on the first pixel electrode, wherein the first pixel electrode is on the pixel circuit layer and electrically connected to the first pixel circuit. The second light-emitting element is configured to emit light of the first color and includes a second pixel electrode and a second light-emitting layer on the second pixel electrode. The second pixel electrode is on the pixel circuit layer, electrically connected to the second pixel circuit, and overlaps with each of the second pixel circuit, the fifth pixel circuit, and the sixth pixel circuit in a plan view. as well as A third light-emitting element is configured to emit light of a second color different from the first color, and includes a third pixel electrode and a third light-emitting layer on the third pixel electrode, the third pixel electrode being on the pixel circuit layer and electrically connected to the third pixel circuit.

9. The display device according to claim 8, wherein, The second pixel electrode includes: The main part overlaps with the fifth pixel circuit in the plan view; and The extension portion extends from the main portion along the first direction and overlaps with each of the second pixel circuit and the sixth pixel circuit in the plan view.

10. An electronic device comprising: The processor is configured to output input image data and input control signals; as well as The display device according to any one of claims 1 to 9 is configured to be driven based on the input image data and the input control data.

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