Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device, the display panel comprises a substrate, a metal wire, a first electrode layer and a packaging layer, the metal wire is located on one side of the substrate, and at least part of the metal wire is located in a packaging area; the first electrode layer is located on the side, away from the substrate, of the metal wire, and the first electrode layer covers the exposed face, located in the packaging area, of the metal wire; the packaging layer is located on the side, deviating from the substrate, of the first electrode layer and covers the exposed face of the first electrode layer, and the exposed face, located in the packaging area, of the metal wire is covered with the first electrode layer. The corrosion influence of a developing solution and a first electrode layer anode etching solution on the side wall of the metal wire in the patterning process of the first electrode layer and / or the pixel limiting layer and / or the supporting column can be blocked without increasing extra Mask cost, it is ensured that the flatness of the wall of the metal wire is good, and the water and oxygen blocking capacity is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] AMOLED (Active-matrix organic light-emitting diode) display technology is one of the most mainstream display technologies currently available. Compared to traditional LCD displays, it is favored by many display terminal manufacturers due to its superior performance, including lower power consumption, higher contrast ratio, more vibrant colors, thinner and lighter screen, and flexibility. However, OLED device materials are particularly sensitive to water and oxygen, which can easily diffuse through organic materials or non-dense inorganic metals. If water and oxygen invade the OLED material, the OLED will malfunction and fail to emit light properly. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to provide a display panel and its manufacturing method, as well as a display device, which can better improve the display effect of the display panel.

[0004] For the purposes described above, this disclosure discloses a display panel including a display area and an encapsulation area located on one side of the display area. The display panel includes:

[0005] substrate;

[0006] Metal traces are located on one side of the substrate, and at least a portion of the metal traces are located in the packaging area;

[0007] A first electrode layer is located on the side of the metal trace away from the substrate, and the first electrode layer covers the exposed surface of the metal trace located within the packaging area;

[0008] An encapsulation layer is located on the side of the first electrode layer away from the substrate and covers the exposed surface of the first electrode layer.

[0009] In one embodiment, the metal trace includes a first sublayer, a second sublayer, and a third sublayer stacked together, wherein the second sublayer is located on the side of the first sublayer facing away from the substrate, and the third sublayer is located on the side of the second sublayer facing away from the first sublayer.

[0010] Preferably, the second sublayer is made of a different material than the first sublayer, and / or the second sublayer is made of a different material than the third sublayer;

[0011] Preferably, the first sublayer and the third sublayer are made of titanium, and the second sublayer is made of aluminum;

[0012] Preferably, the metal traces located in the packaging area include a first metal trace and a second metal trace, the first metal trace and the second metal trace are spaced apart, and the first metal trace and the second metal trace extend in the same direction;

[0013] Preferably, the first metal trace is used to transmit a first power supply voltage signal, the second metal trace is used to transmit a second power supply voltage signal, and the voltage value of the second power supply voltage signal is greater than the voltage value of the first power supply voltage signal.

[0014] In one embodiment, the first electrode layer covers the side surface of the metal trace located in the packaging region away from the substrate and the sidewall surface adjacent to the surface;

[0015] Preferably, in a cross-section perpendicular to the plane of the substrate and parallel to the extension direction of the metal trace located in the packaging area, the distance between the edge of the orthogonal projection of the side surface of the metal trace away from the substrate on the substrate and the edge of the orthogonal projection of the first electrode layer on the substrate is greater than or equal to 5 micrometers.

[0016] In one embodiment, the display panel further includes a first insulating layer located on the side of the metal trace closer to the substrate;

[0017] Preferably, the material of the first insulating layer includes inorganic materials;

[0018] Preferably, the display panel further includes at least one organic layer, the at least one organic layer being provided with a first via, and the orthographic projection of the encapsulation area on the substrate is located within the orthographic projection range of the first via on the substrate;

[0019] Preferably, at least one organic layer is stacked on the side of the first via near the display area to form a dam;

[0020] Preferably, the sidewall of the dam near the first through hole is stepped.

[0021] In one embodiment, at least one organic layer includes a first planarization layer, wherein the first planarization layer is located on the side of the first insulating layer away from the substrate and on the side of the metal trace close to the substrate, the first planarization layer is provided with a first sub-via, and the metal trace located in the packaging area overlaps with the first insulating layer through the first sub-via.

[0022] Preferably, at least one organic layer further includes a second planarization layer, the second planarization layer being located on the side of the first planarization layer away from the substrate and covering at least a portion of the metal traces located on the periphery of the packaging area, the second planarization layer being provided with a second sub-via communicating with the first sub-via, the orthographic projection of the first sub-via on the substrate being located within the orthographic projection range of the second sub-via on the substrate;

[0023] Preferably, the orthographic projection of the second planarization layer on the substrate near the edge of the second sub-via is recessed relative to the orthographic projection of the first planarization layer on the substrate near the edge of the first sub-via;

[0024] Preferably, the first electrode layer covers the exposed surface of the metal trace through the second sub-via;

[0025] Preferably, at least one organic layer further includes a pixel defining layer, the pixel defining layer being located on the side of the second planarization layer opposite to the substrate and covering at least a portion of the first electrode layer located on the periphery of the encapsulation region, the pixel defining layer being provided with a third sub-via communicating with the second sub-via, the orthographic projection of the second sub-via on the substrate being located within the orthographic projection range of the third sub-via on the substrate;

[0026] Preferably, the orthographic projection of the pixel defining layer on the substrate near the edge of the third sub-via is recessed relative to the orthographic projection of the second planarization layer on the substrate near the edge of the second sub-via;

[0027] Preferably, in a cross section perpendicular to the plane of the substrate and perpendicular to the extension direction of the metal trace located in the packaging area, the distance between the edge of the orthographic projection of the pixel defining layer on the substrate near the third sub-via and the edge of the orthographic projection of the surface of the first electrode layer on the side away from the substrate on the substrate is greater than or equal to 5 micrometers.

[0028] Preferably, the display panel further includes a support pillar located on the side of the pixel defining layer opposite to the substrate, and the support pillar is at least partially disposed around the third sub-via.

[0029] Preferably, the orthographic projection of the support post on the substrate near the edge of the third sub-via is recessed relative to the orthographic projection of the pixel defining layer on the substrate near the edge of the third sub-via.

[0030] In one embodiment, the encapsulation layer is located on the side of the support pillar opposite to the substrate, and at least a portion of the encapsulation layer extends into the encapsulation region and covers the first electrode layer located in the encapsulation region.

[0031] Preferably, at least a portion of the encapsulation layer extends to the side of the encapsulation region away from the display region and covers the first electrode layer on the side of the encapsulation region away from the display region;

[0032] Preferably, the material of the encapsulation layer includes inorganic materials.

[0033] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel, which includes the following steps:

[0034] Provide substrate;

[0035] Metal traces are formed on one side of the substrate, with a portion of the metal traces located in the packaging area.

[0036] A first electrode layer is formed on the side of the metal trace away from the substrate, and the first electrode layer covers the exposed surface of the metal trace located within the packaging area;

[0037] An encapsulation layer is formed on the side of the first electrode layer away from the substrate, and the encapsulation layer covers the exposed surface of the first electrode layer.

[0038] In one embodiment, the step of forming a metal trace on one side of the substrate further includes:

[0039] A first insulating layer is formed on one side of the substrate;

[0040] Preferably, after the step of forming the first insulating layer on one side of the substrate, the method further includes:

[0041] A first planarization layer is formed on one side of the substrate. The first planarization layer includes a first sub-via, through which the metal trace located in the packaging area overlaps with the first insulating layer.

[0042] Preferably, the step of forming a first planarization layer on one side of the substrate includes:

[0043] A first organic material layer is deposited on the substrate, and the first organic material layer is patterned using photolithography to form the first planarization layer.

[0044] In one embodiment, the step of forming a first electrode layer on the side of the metal trace away from the substrate further includes:

[0045] A second planarization layer is formed on the side of the metal trace away from the substrate. The second planarization layer is provided with a second sub-via. The orthogonal projection of the second sub-via on the substrate is located within the packaging area.

[0046] Preferably, the step of forming a second planarization layer on the side of the metal trace opposite to the substrate includes:

[0047] A second organic material layer is formed on the side of the metal trace that is away from the substrate;

[0048] The second organic material layer is patterned using photolithography to form an organic protective layer. The organic protective layer includes a first organic protective layer and a second organic protective layer. The thickness of the first organic protective layer is greater than the thickness of the second organic protective layer. The second organic protective layer covers the exposed surfaces of the metal traces located in the encapsulation area and a portion of the exposed surfaces of the metal traces located around the encapsulation area.

[0049] The organic protective layer is ashed to remove the second organic protective layer and part of the first organic protective layer, forming a second planarization layer;

[0050] Preferably, the thickness of the removed portion of the first organic protective layer is equal to the thickness of the second organic protective layer;

[0051] Preferably, in the direction perpendicular to the plane of the substrate, the thickness of the first organic protective layer is greater than or equal to 2 micrometers;

[0052] Preferably, the thickness of the second organic protective layer is between 0.3 micrometers and 0.6 micrometers in the direction perpendicular to the plane of the substrate.

[0053] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel as described above.

[0054] Compared with the prior art, the display panel provided in this disclosure, by setting a first electrode layer to cover the exposed surface of the metal traces located in the packaging area, can block the corrosive effects of the developing solution and the first electrode layer anolyte on the sidewalls of the metal traces during the patterning process of the first electrode layer and / or pixel limiting layer and / or support pillar without increasing the additional mask cost, ensuring the flatness of the sidewalls of the metal traces and improving the ability to block water and oxygen. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram illustrating anomalies in the metal and inorganic encapsulation of the lower bezel of an OLED screen in existing technology.

[0057] Figure 2 This is a schematic diagram illustrating OLED pixel failure in the black spot region in existing technology;

[0058] Figure 3 The OLED pixel failure black spots are caused by water and oxygen intrusion paths created by the inorganic metal encapsulation of the lower bezel.

[0059] Figure 4 A top view of the display panel is provided for an embodiment of this application;

[0060] Figure 5 A partial cross-sectional schematic diagram of the display panel is provided for an embodiment of this application;

[0061] Figure 6 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 1 ;

[0062] Figure 7 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 2 ;

[0063] Figure 8 for Figure 7 A partial cross-sectional diagram of the corresponding display panel at point BB;

[0064] Figure 9 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 3

[0065] Figure 10 for Figure 9 A partial cross-sectional diagram of the corresponding display panel at point BB;

[0066] Figure 11 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 4 ;

[0067] Figure 12 for Figure 11 A partial cross-sectional diagram of the corresponding display panel at point BB;

[0068] Figure 13 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 5 ;

[0069] Figure 14 for Figure 13 A partial cross-sectional diagram of the corresponding display panel at point BB;

[0070] Figure 15 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 6 ;

[0071] Figure 16A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 7 ;

[0072] Figure 17 A partial cross-sectional schematic diagram of the display panel at point AA is provided for embodiments of this application. Figure 8 ;

[0073] Figure 18 for Figure 17 A partial cross-sectional diagram of the corresponding display panel at point BB; Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0075] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0076] refer to Figure 1 In related technologies, the metal traces M4 (TiAlTi) of the VSS and VDD bottom bezels of OLED display panels are easily affected by corrosion from developing solutions and anodic etching solutions during the array backplane fabrication process, resulting in poor flatness of the metal trace sidewalls. Therefore, there is poor coverage between the VSS and VDD metal traces of the OLED screen bottom bezel and the upper TFE CVD inorganic encapsulation area film layer, creating water and oxygen intrusion paths (such as...). Figure 1 The location indicated by the middle arrow) causes pixel failure at the bottom edge of the screen, resulting in black spots (such as...). Figure 2 As shown in M ​​and Figure 3As shown, the bottom bezel metal packaging structure typically uses ILD inorganic film + M4 metal + TFE CVD inorganic film. This packaging structure cannot improve the corrosion problem of the M4 metal sidewall of the metal traces, which is the root cause of water and oxygen path generation, especially serious in narrow bezel products. At the same time, extending the bottom bezel metal and inorganic packaging area will lead to an increase in the screen bezel, which is not conducive to narrow bezels and reduces product competitiveness.

[0077] For the reasons stated above, this application provides a display panel and a method for manufacturing the same, and a display device. The display panel includes a display area and an encapsulation area located on one side of the display area. The display panel includes a substrate 10, metal traces 40, a first electrode layer 50, and an encapsulation layer 60. The metal traces 40 are located on one side of the substrate 10, and at least a portion of the metal traces 40 are located in the encapsulation area B1. The first electrode layer 50 is located on the side of the metal traces 40 away from the substrate 10, and the first electrode layer 50 covers the exposed surface of the metal traces 40 located in the encapsulation area B1. The encapsulation layer 60... Located on the side of the first electrode layer 50 away from the substrate 10 and covering the exposed surface of the first electrode layer 50, this application, by setting the first electrode layer 50 to cover the exposed surface of the metal trace 40 located in the packaging area B1, can block the corrosive effects of the developing solution and the anodic etching solution of the first electrode layer 50 and / or the pixel limiting layer 33 and / or the support pillar 34 on the sidewall of the metal trace 40 during the patterning process without increasing the additional mask cost, ensuring the flatness of the sidewall of the metal trace 40 is intact and improving the ability to block water and oxygen.

[0078] Next, combine Figures 4-18 This application describes the display panel provided in the embodiments of the present application.

[0079] The display panel includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes an encapsulation area B1 located on one side of the display area AA. Furthermore, the display panel also includes a dam area B2. If two dams are provided in the dam area B2, the encapsulation area B1 is located in the dam area B2. At the same time, in order to achieve a narrow bezel design, one dam is provided in the dam area B2, and the encapsulation area B1 is located on the side of the dam area B2 away from the display area AA. This embodiment is described using the example of one dam being provided in the dam area B2.

[0080] refer to Figures 5-18 The display panel includes a substrate 10, wherein the substrate 10 includes a substrate layer, a barrier layer and a buffer layer located on the substrate layer.

[0081] In some specific embodiments, the substrate 10 may include a first substrate layer (Polyimide 1), a first barrier layer (Barrier 1), a second substrate layer (Polyimide 2), and a second barrier layer (Barrier 2) stacked sequentially. The first substrate layer (Polyimide 1) and the second substrate layer (Polyimide 2) are collectively referred to as substrate layers, and the first barrier layer (Barrier 1) and the second barrier layer (Barrier 2) are collectively referred to as barrier layers. In the embodiments, the substrate 10 may adopt a double-layer substrate structure to improve water and oxygen barrier and load-bearing capacity.

[0082] For example, the substrate layer is a flexible material, allowing the display panel to be bent, thereby enabling functions such as curved display, foldable display, or rollable display. The flexible substrate layer can be made of any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC). The substrate layer can also be a rigid material, such as glass or plastic.

[0083] For example, the materials used for the first barrier layer (Barrier1) and the second barrier layer (Barrier2) include silicon oxide (SiOx).

[0084] Exemplarily, a buffer layer is located on the barrier layer, and exemplaryly, the buffer layer includes an inorganic layer or an organic layer. For example, the buffer layer may be formed from an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride, or an organic material such as acrylic, polyimide, or polyester. For example, the buffer layer in this embodiment may include a silicon nitride (SiNx) buffer layer and a silicon oxide (SiOx) buffer layer disposed sequentially.

[0085] refer to Figures 5-18 The display panel also includes a driving circuit layer 20 located in the display area AA. The driving circuit layer 20 is located on one side of the substrate 10. The driving circuit layer 20 includes a pixel driving circuit. The display panel can be an LTPS (Low Temperature Poly-Silicon) display panel or an LTPO (Low Temperature Poly Oxide) display panel. The film structure of the driving circuit layer 20 will be described below using an LTPS (Low Temperature Poly-Silicon) display panel as an example.

[0086] In the direction perpendicular to the plane of substrate 10, the driving circuit layer 20 includes a TFT channel layer Poly Si, a gate insulating layer GI, a gate layer M1, a capacitor dielectric layer CI, a capacitor electrode layer M2, a first insulating layer 21 (also known as an interlayer insulating layer ILD), a source / drain layer, and an interconnect third metal layer M3. The interconnect metal layer provides the screen-required signals such as VDD, Vdata, and VSS required for pixel circuit driving.

[0087] For example, the material of the gate insulating layer GI includes silicon oxide (SiOx); the material of the gate layer M1 includes molybdenum (Mo); the material of the capacitor dielectric layer CI includes silicon nitride (SiNx); the material of the capacitor plate layer M2 includes molybdenum (Mo); the material of the first insulating layer 21 includes inorganic materials, such as the first insulating layer 21 including a silicon oxide (SiOx) buffer layer and a silicon nitride (SiNx) buffer layer stacked sequentially, and the third metal layer M3 includes a Ti / Al / Ti composite structure.

[0088] refer to Figures 6-18 The display panel also includes at least one organic layer 30, and the at least one organic layer 30 is provided with a first via 310, wherein the orthographic projection of the encapsulation area B1 on the substrate 10 is outside the orthographic projection range of the first via 310 on the substrate 10, that is, no organic layer is provided in the encapsulation area B1 of the display panel. This design prevents the formation of water and oxygen intrusion paths.

[0089] Continue to refer to Figures 6-18 Specifically, at least one organic layer 30 may include a first planarization layer 31. The first planarization layer 31 is located on the side of the driving circuit layer 20 away from the substrate 10. The first planarization layer 31 is provided with a first sub-via 311. The orthogonal projection of the first sub-via 311 on the substrate 10 is located in the encapsulation area B1. In this embodiment, by providing the first sub-via 311, part of the first insulating layer 21 is exposed, mainly the first insulating layer 21 in the encapsulation area B1 is exposed. At the same time, it can also prevent the formation of water and oxygen intrusion paths. During the manufacturing process, the first organic material layer located in the encapsulation area B1 is removed by photolithography to form the first sub-via 311.

[0090] The material of the exemplary first planarization layer 31 includes organic materials, such as resin materials.

[0091] refer to Figures 7-18 The display panel also includes metal traces 40 located on the side of the first planarization layer 31 away from the substrate 10. At least a portion of the metal traces 40 are located in the encapsulation area B1. The metal traces 40 located in the encapsulation area B1 are connected to the first insulating layer 21 through the first sub-via 311, that is, the first insulating layer 21 wraps the bottom of the metal traces 40 in the encapsulation area B1.

[0092] In an optional embodiment, the metal trace 40 includes a first sublayer 43, a second sublayer 44, and a third sublayer 45 stacked together. The first sublayer 43 is located on the side of the second sublayer 44 away from the substrate 10, and the third sublayer 45 is located on the side of the second sublayer 44 close to the substrate 10. The second sublayer 44 is made of a different material than the first sublayer 43, and / or the second sublayer 44 is made of a different material than the third sublayer 45.

[0093] For example, the first sublayer 43 and the third sublayer 45 may be made of titanium, and the second sublayer 44 may be made of aluminum.

[0094] In an optional embodiment, the metal trace 40 located in the package region B1 includes a first metal trace 41 and a second metal trace 42, wherein the first metal trace 41 and the second metal trace 42 are spaced apart, and the first metal trace 41 and the second metal trace 42 extend in the same direction. The first metal trace 41 is used to transmit a first power supply voltage signal, and the second metal trace 42 is used to transmit a second power supply voltage signal. The first power supply voltage signal and the second power supply voltage signal are different voltage signals. One of the second power supply voltage signal and the first power supply voltage signal is a high voltage (e.g., ELVDD), and the other is a low voltage (e.g., ELVSS). For example, the voltage value of the second power supply voltage signal is greater than the voltage value of the first power supply voltage signal, that is, the first metal trace 41 transmits the first power supply voltage signal with a smaller voltage value, and the second metal trace 42 transmits the second power supply voltage signal with a larger voltage value.

[0095] refer to Figures 9-18 At least one organic layer 30 also includes a second planarization layer 32. The second planarization layer 32 is located on the side of the first planarization layer 31 away from the substrate 10 and covers at least part of the metal traces 40 located around the packaging area B1. The second planarization layer 32 is provided with a second sub-via 321 communicating with the first sub-via 311. The orthographic projection of the first sub-via 311 on the substrate 10 is within the orthographic projection range of the second sub-via 321 on the substrate 10. It can also be understood that the edge of the orthographic projection of the second planarization layer 32 on the substrate 10 near the second sub-via 321 is recessed relative to the edge of the orthographic projection of the first planarization layer 31 on the substrate 10 near the first sub-via 311, forming a step buffer zone, which is beneficial to the coverage of the subsequent packaging layer 60.

[0096] refer to Figures 9-12During the fabrication process, a second organic adhesive material (resin material) is first deposited on the side of the first metal trace 41 facing away from the substrate 10. Then, a halftone mask is used to pattern the second organic adhesive material using photolithography to form an organic protective layer 320. This organic protective layer 320 includes a first organic protective layer 322 and a second organic protective layer 323. The thickness D1 of the first organic protective layer 322 is greater than the thickness D2 of the second organic protective layer 323. For example, in the direction perpendicular to the surface of the substrate 10 (Z direction), the thickness D1 of the first protective layer is greater than or equal to 2 micrometers (μm). The thickness D2 of the second protective layer is between 0.3 and 0.6 micrometers (μm). The second organic protective layer 323 covers the exposed surfaces of the metal traces 40 located in the encapsulation region B1 and a portion of the metal traces 40 located around the periphery of the encapsulation region B1. By setting the organic protective layer 320, the sidewalls of the metal traces 40 can be protected during the fabrication of the second planarization layer 32, preventing the developer (TMAH tetramethylammonium hydroxide) from corroding the sidewalls of the second sublayer 44 (aluminum layer) of the metal traces 40, ensuring the smoothness of the sidewalls of the second sublayer 44 (aluminum layer) of the metal traces 40. Finally, the organic protective layer is ashed. 320. Remove the second organic protective layer 323 and part of the first organic protective layer 322 adhesive layer to form a second planarization layer. In this step, the thickness of the part of the first organic protective layer 322 adhesive layer removed is equal to the thickness of the second organic protective layer 323, that is, the thickness of the part of the first organic protective layer 322 adhesive layer removed is between 0.3-0.6 micrometers (µm). For example, oxygen (O2) or oxygen (O2) + sulfur hexafluoride (SF6) is used to ashed the organic protective layer 320, and the second organic protective layer 323 is completely removed in this process to avoid the presence of the second organic protective layer 323 in the encapsulation area B1.

[0097] refer to Figures 13-18The display panel also includes a first electrode layer 50, which is located on the side of the second planarization layer 32 away from the substrate 10. The first electrode layer 50 covers the exposed surface of the metal trace 40 through the second sub-via 321. Since the orthographic projection of the first sub-via 311 on the substrate 10 is within the orthographic projection range of the second sub-via 321 on the substrate 10, the metal trace 40 located in the second sub-via 321 has an exposed surface, and the first electrode layer 50 will cover the exposed surface of this part of the metal trace 40. In this embodiment, the metal traces 40 in the encapsulation area B1 are protected by setting a first electrode layer 50. The first electrode layer 50 can cover the exposed second sub-layer 44 (aluminum layer) of the metal traces 40, thereby preventing the developer or etching solution from laterally etching the second sub-layer 44 (aluminum layer) when the first electrode layer 50 is made. Therefore, water and oxygen channels will not be formed in the second sub-layer 44 (aluminum layer), and the occurrence of water vapor and oxygen channels outside the display panel entering the effective display area AA of the display panel is prevented, thus solving the black spot problem of the display panel.

[0098] refer to Figure 14 and Figure 18 In an optional embodiment, in a cross-section perpendicular to the plane of substrate 10 and parallel to the extension direction of the metal trace 40 within the packaging region B1 (e.g., at BB), the distance H1 between the edge of the orthogonal projection of the side surface of the metal trace 40 facing away from substrate 10 onto substrate 10 and the edge of the orthogonal projection of the first electrode layer 50 onto substrate 10 is greater than or equal to 5 micrometers (μm). This design prevents the development solution and anolyte (a mixture of phosphoric acid / nitric acid / acetic acid) from corroding the sidewalls of the metal trace 40 (aluminum layer) during the patterning process of the anode or pixel defining layer 33 or support pillar 34. This ensures the smoothness of the sidewalls of the metal trace 40 (aluminum layer).

[0099] refer to Figures 15-18 At least one organic layer 30 also includes a pixel defining layer 33. The pixel defining layer 33 is located on the side of the second planarization layer 32 away from the substrate 10 and covers at least a portion of the first electrode layer 50 located around the packaging region B1. The pixel defining layer 33 is provided with a third sub-via 331 communicating with the second sub-via 321. The orthographic projection of the second sub-via 321 on the substrate 10 is within the orthographic projection range of the third sub-via 331 on the substrate 10. It can also be understood that the edge of the orthographic projection of the pixel defining layer 33 on the substrate 10 near the third sub-via 331 is recessed relative to the edge of the orthographic projection of the second planarization layer 32 on the substrate 10 near the second sub-via 321. This design makes the pixel planarization layer recessed relative to the second planarization layer, forming a step buffer zone, which is beneficial to the coverage of the subsequent packaging layer 60.

[0100] The material of the exemplary pixel defining layer 33 includes organic materials, such as resin materials.

[0101] refer to Figure 17 In an optional embodiment, in a cross-section perpendicular to the plane of substrate 10 and parallel to the extension direction of the metal trace 40 within the packaging region B1 (e.g., the cross-section at AA), the distance H2 between the edge of the orthogonal projection of the pixel defining layer 33 on substrate 10 near the edge of the third sub-via 331 and the edge of the orthogonal projection of the surface of the first electrode layer 50 on the side facing away from substrate 10 on substrate 10 is greater than or equal to 5 micrometers. This design prevents the development solution and anolyte (a mixture of phosphoric acid / nitric acid / acetic acid) from corroding the sidewalls of the metal trace 40 (aluminum layer) during the SPC patterning process of the support pillar 34. This ensures the integrity of the metal sidewall flatness of the metal trace 40 (aluminum layer).

[0102] refer to Figures 16-18 At least one organic layer 30 also includes a support post 34 (SPC) located on the side of the pixel defining layer 33 away from the substrate 10. The support post 34 is at least partially disposed around the third sub-via 331. The edge of the orthographic projection of the support post 34 on the substrate 10 near the encapsulation region B1 is recessed relative to the edge of the orthographic projection of the pixel defining layer 33 on the substrate 10 near the third sub-via 331. This design forms a stepped buffer zone to facilitate the coverage of subsequent film layers.

[0103] The exemplary support column 34 (SPC) is made of organic materials, such as resin materials.

[0104] In one embodiment, at least one organic layer 30 located on the side of the first via 310 near the display area AA is stacked to form a dam 70. It can also be understood that the second planarization layer, the pixel limiting layer 33 and the support pillar 34 located in the dam area B2 are stacked to form a dam. The side wall of the dam 70 near the first via 310 is stepped, which is beneficial to improving the coverage of the encapsulation layer 60.

[0105] refer to Figures 17-18The display panel also includes an encapsulation layer 60 (TFE CVD), which is located on the side of the support pillar 34 away from the substrate 10. At least a portion of the encapsulation layer 60 extends to the encapsulation region B1 and covers the first electrode layer 50 located in the encapsulation region B1. Furthermore, at least a portion of the encapsulation layer 60 extends to the side of the encapsulation region B1 away from the display region AA and covers the first electrode layer 50 on the side of the encapsulation region B1 away from the display region AA. In this embodiment, the inward shrinkage between the multiple organic layers forms a buffer step, ensuring good coverage of the encapsulation layer 60 in the Dam region. At the same time, due to the protection of the metal trace 40 by the second protective layer, namely the first electrode layer 50, during the fabrication of the second planarization layer 32, the corrosion of the sidewalls of the metal trace 40 by the developer and anodic etching solution during the process is blocked, ensuring good coverage of the sidewalls of the metal trace 40 by the encapsulation layer 60.

[0106] For example, the material of the encapsulation layer 60 includes inorganic materials, such as silicon nitride (SiN) with good density.

[0107] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel, which includes the following steps:

[0108] refer to Figure 5 S10: Provide substrate 10;

[0109] In this step, a first substrate layer (Polyimide1), a first barrier layer (Barrier1), a second substrate layer (Polyimide2), a second barrier layer (Barrier1), and a buffer layer are sequentially formed on the glass substrate 10.

[0110] refer to Figure 5 S20: A driving circuit layer 20 is formed on one side of the substrate 10;

[0111] In this step, a channel layer, a gate insulating layer, a gate layer, a capacitor dielectric layer, a capacitor electrode layer, and a first insulating layer 21 are sequentially formed on the substrate 10.

[0112] refer to Figure 6 S30: A first planarization layer 31 is formed on the layer of the driving circuit layer 20 that is opposite to the substrate 10;

[0113] In this step, a first organic material layer is deposited on the side of the driving circuit layer 20 away from the substrate 10 (or, in other words, a first organic material layer is deposited on the side of the first insulating layer 21 away from the substrate 10); the exemplary first organic material layer may be a first resin material.

[0114] The first organic material layer is then patterned using photolithography to form the first planarization layer 31. In this step, the first organic material layer located in the encapsulation area B1 is removed by photolithography to form the first sub-via 311. This design prevents the formation of water and oxygen intrusion paths.

[0115] refer to Figures 7-8 S40: A metal trace 40 is formed on the side of the first planarization layer 31 away from the substrate 10;

[0116] In this step, a first titanium material layer, an aluminum material layer, and a second titanium material layer are sequentially stacked on the side of the first planarization layer 31 facing away from the substrate 10. Photolithography and dry etching are used to form the first titanium material layer, aluminum material layer, and second titanium material layer to create metal traces 40. It should be noted that the metal traces 40 located in the packaging region B1 overlap with the first insulating layer 21 through a first sub-via 311. The metal traces 40 located in the packaging region B1 include a first metal trace 41 and a second metal trace 42, and the first metal trace 41 and the second metal trace 42 extend in the same direction. The first metal trace 41 and the second metal trace 42 are spaced apart. The first metal trace 41 is used to transmit a first power supply voltage signal, and the second metal trace 42 is used to transmit a second power supply voltage signal. The first power supply voltage signal and the second power supply voltage signal are different voltage signals. One of the second power supply voltage signal and the first power supply voltage signal is a high voltage (e.g., ELVDD), and the other is a low voltage (e.g., ELVSS). For example, the voltage value of the second power supply voltage signal is greater than the voltage value of the first power supply voltage signal. That is, the first metal trace 41 transmits the first power supply voltage signal with a smaller voltage value, and the second metal trace 42 transmits the second power supply voltage signal with a larger voltage value.

[0117] refer to Figures 9-12 S50: A second planarization layer 32 is formed on the side of the first planarization layer 31 away from the substrate 10, wherein the second planarization layer 32 covers at least part of the metal trace 40 located on the periphery of the package area B1, wherein the second planarization layer 32 is provided with a second sub-via 321 communicating with the first sub-via 311, and the orthographic projection of the first sub-via 311 on the substrate 10 is located within the orthographic projection range of the second sub-via 321 on the substrate 10.

[0118] In this step, a second organic material layer is formed on the first planarization layer 31 and the layer of metal trace 40 that is away from the substrate 10. An exemplary second organic material layer may be a second resin material.

[0119] The second organic material layer is patterned using photolithography to form an organic protective layer 320. The organic protective layer 320 includes a first organic protective layer 322 and a second organic protective layer 323. The thickness D1 of the first organic protective layer 322 is greater than the thickness D1 of the second organic protective layer 323. For example, in the direction perpendicular to the plane of the substrate 10 (Z direction), the thickness of the first organic protective layer 322 is greater than or equal to 2 μm, and the thickness D2 of the second organic protective layer is based on 0.3-0.6 μm. The second organic protective layer covers the exposed surfaces of the metal traces 40 located in the packaging area B1 and some of the metal traces 40 located around the packaging area B1. By setting the organic protective layer 320, the sidewalls of the metal traces 40 can be protected during the fabrication of the second planarization layer 32, preventing the developer (TMAH tetramethylammonium hydroxide) from corroding the sidewalls of the second sublayer 44 (aluminum layer) of the metal traces 40, and ensuring the flatness of the sidewalls of the second sublayer 44 (aluminum layer) of the metal traces 40.

[0120] The organic protective layer 320 is ashed to remove the second organic protective layer 323 and part of the first organic protective layer 322 adhesive layer, forming a second planarization layer. In this step, the thickness of the removed part of the first organic protective layer 322 adhesive layer is equal to the thickness of the second organic protective layer 323, that is, the thickness of the removed part of the first organic protective layer 322 adhesive layer is between 0.3-0.6 micrometers (µm). For example, oxygen (O2) or oxygen (O2) + sulfur hexafluoride (SF6) is used to ashed the organic protective layer 320, and the second organic protective layer 323 is completely removed during this process, thereby forming a second sub-via 321 to avoid the presence of the second organic protective layer 323 in the encapsulation area B1.

[0121] In an optional embodiment, further, in order to improve the coverage of the subsequent encapsulation layer 60, the edge of the orthographic projection of the second planarization layer 32 on the substrate 10 near the second sub-via 321 is recessed relative to the edge of the orthographic projection of the first planarization layer 31 on the substrate 10 near the first sub-via 311, forming a step buffer zone, which is beneficial to the coverage of the subsequent encapsulation layer 60.

[0122] refer to Figures 13-14 S60: A first electrode layer 50 is formed on the side of the second planarization layer 32 away from the substrate 10;

[0123] In this step, a conductive material layer is formed on the side of the second planarization layer 32 away from the substrate 10. The conductive material layer includes, for example, a stacked indium tin oxide material layer, a silver material layer, and an indium tin oxide material layer (ITO / Ag / ITO).

[0124] A patterned conductive material layer is formed to create a first conductive layer. This first conductive layer covers the exposed surface of the metal trace 40 located in the packaging region B1. Specifically, it covers the surface of the metal trace 40 located in the packaging region B1 facing away from the substrate 10 and the sidewall adjacent to that surface. This can be understood as the first conductive layer completely encapsulating the first trace located in the packaging region B1. In this step, by using the first electrode layer 50 as a protective film layer for the metal trace 40, the fabrication process is simplified by eliminating the need for a new mask.

[0125] refer to Figure 15 S70: A pixel defining layer 33 is formed on the side of the second planarization layer 32 away from the substrate 10. The pixel defining layer 33 at least covers the first electrode layer 50 located outside the packaging region B1.

[0126] In this step, a third organic material layer is formed on the side of the second planarization layer 32 and the first electrode layer 50 away from the substrate 10. An exemplary third organic material layer includes a third resin material.

[0127] The third organic material layer is patterned using photolithography to form a pixel defining layer 33. In this step, the third organic material layer located in the packaging area B1 and the periphery of the packaging area B1 is removed by photolithography to form a third sub-via 331. In this step, the third organic material layer located on the periphery of the packaging area B1 cannot be removed too much; it must cover at least a portion of the first conductive layer on the periphery of the packaging area B1. For example, in a cross section perpendicular to the plane of the substrate 10 and perpendicular to the direction of the metal trace 40, the distance between the edge of the orthogonal projection of the pixel defining layer 33 on the substrate 10 near the third sub-via 331 and the edge of the orthogonal projection of the surface of the first electrode layer 50 on the side facing away from the substrate 10 on the substrate 10 is greater than or equal to 5 micrometers. This design is to prevent the developer and anodic etchant (a mixture of phosphoric acid / nitric acid / acetic acid) from corroding the sidewall of M4 (TiAlTi)Al during the SPC patterning process of the support pillar 34, ensuring the integrity of the flatness of the M4 metal sidewall.

[0128] In an optional embodiment, further, in order to improve the coverage of the subsequent encapsulation layer 60, the edge of the orthographic projection of the pixel defining layer 33 on the substrate 10 near the third sub-via 331 is recessed relative to the edge of the orthographic projection of the second planarization layer 32 on the substrate 10 near the second sub-via 321, forming a step buffer zone, which is beneficial to the coverage of the subsequent encapsulation layer 60.

[0129] refer to Figure 16 S80: A support post 34 is formed on the side of the pixel limiting layer 33 facing away from the substrate 10, and the support post 34 is at least partially disposed around the third sub-via 331.

[0130] In this step, a fourth organic material layer is formed on the side of the pixel defining layer 33 facing away from the substrate 10. An exemplary fourth organic material layer includes a fourth resin layer. The fourth organic material layer is patterned using photolithography, such as removing portions of the fourth organic material layer located in the encapsulation region B1 and around the encapsulation region B1, to form a support pillar 34. Further, to improve the coverage of the subsequent encapsulation layer 60, the orthographic projection of the support pillar 34 onto the substrate 10 near the edge of the encapsulation region B1 is recessed relative to the orthographic projection of the pixel defining layer 33 onto the substrate 10 near the edge of the third sub-via 331, forming a step buffer zone to facilitate the coverage of subsequent film layers.

[0131] refer to Figures 17-18 S90: An encapsulation layer 60 (TFE CVD) is formed on the side of the support pillar 34 away from the substrate 10, wherein at least a portion of the encapsulation layer 60 extends to the encapsulation region B1 and covers the first electrode layer 50 located in the encapsulation region B1. Further, at least a portion of the encapsulation layer 60 extends to the side of the encapsulation region B1 away from the display region AA and covers the first electrode layer 50 on the side of the encapsulation region B1 away from the display region AA.

[0132] In this step, a second inorganic material layer is deposited on the side of the support pillar 34 away from the substrate 10 using plasma-enhanced chemical vapor deposition (PECVD). For example, the second inorganic material layer can be a silicon nitride (SiN) material layer with good density. PECVD is used in this step because it has good water and oxygen barrier capabilities. At the same time, because the multilayer organic film layers are stacked and formed into buffer steps in the previous steps, TFE CVD has good coverage in the Dam region. In addition, the second protective layer, namely the first electrode layer 50, protects the metal trace 40 during the fabrication of the second planarization layer 32, preventing the developer and anolyte from corroding the sidewalls of the metal trace 40 during the process, thus ensuring good coverage of the sidewalls of the metal trace 40 by TFE CVD.

[0133] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel described in this application or a display panel manufactured using the above-described manufacturing method. This display device may include devices with image processing capabilities, such as servers, personal computers, laptops, etc. Because this display device includes the display panel described in this application, the display quality of this electronic device is better.

[0134] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0135] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a display area and an encapsulation area located on one side of the display area. The display panel includes: substrate; Metal traces are located on one side of the substrate, and at least a portion of the metal traces are located in the packaging area; A first electrode layer is located on the side of the metal trace away from the substrate, and the first electrode layer covers the exposed surface of the metal trace located within the packaging area; An encapsulation layer is located on the side of the first electrode layer away from the substrate and covers the exposed surface of the first electrode layer.

2. The display panel as described in claim 1, characterized in that, The metal trace includes a first sublayer, a second sublayer, and a third sublayer stacked together, wherein the second sublayer is located on the side of the first sublayer facing away from the substrate, and the third sublayer is located on the side of the second sublayer facing away from the first sublayer. Preferably, the second sublayer is made of a different material than the first sublayer, and / or the second sublayer is made of a different material than the third sublayer; Preferably, the first sublayer and the third sublayer are made of titanium, and the second sublayer is made of aluminum; Preferably, the metal traces located in the packaging area include a first metal trace and a second metal trace, the first metal trace and the second metal trace are spaced apart, and the first metal trace and the second metal trace extend in the same direction; Preferably, the first metal trace is used to transmit a first power supply voltage signal, the second metal trace is used to transmit a second power supply voltage signal, and the voltage value of the second power supply voltage signal is greater than the voltage value of the first power supply voltage signal.

3. The display panel as described in claim 1, characterized in that, The first electrode layer covers the side surface of the metal trace located in the packaging area away from the substrate and the side wall surface adjacent to the surface; Preferably, in a cross-section perpendicular to the plane of the substrate and parallel to the extension direction of the metal trace located in the packaging area, the distance between the edge of the orthogonal projection of the side surface of the metal trace away from the substrate on the substrate and the edge of the orthogonal projection of the first electrode layer on the substrate is greater than or equal to 5 micrometers.

4. The display panel as described in claim 1, characterized in that, The display panel further includes a first insulating layer, which is located on the side of the metal trace closer to the substrate; Preferably, the material of the first insulating layer includes inorganic materials; Preferably, the display panel further includes at least one organic layer, the at least one organic layer being provided with a first via, and the orthographic projection of the encapsulation area on the substrate is located within the orthographic projection range of the first via on the substrate; Preferably, at least one organic layer is stacked on the side of the first via near the display area to form a dam; Preferably, the sidewall of the dam near the first through hole is stepped.

5. The display panel as described in claim 4, characterized in that, At least one organic layer includes a first planarization layer, wherein the first planarization layer is located on the side of the first insulating layer away from the substrate and on the side of the metal trace close to the substrate. The first planarization layer is provided with a first sub-via, and the metal trace located in the packaging area overlaps with the first insulating layer through the first sub-via. Preferably, at least one organic layer further includes a second planarization layer, the second planarization layer being located on the side of the first planarization layer away from the substrate and covering at least a portion of the metal traces located on the periphery of the packaging area, the second planarization layer being provided with a second sub-via communicating with the first sub-via, the orthographic projection of the first sub-via on the substrate being located within the orthographic projection range of the second sub-via on the substrate; Preferably, the orthographic projection of the second planarization layer on the substrate near the edge of the second sub-via is recessed relative to the orthographic projection of the first planarization layer on the substrate near the edge of the first sub-via; Preferably, the first electrode layer covers the exposed surface of the metal trace through the second sub-via; Preferably, at least one organic layer further includes a pixel defining layer, the pixel defining layer being located on the side of the second planarization layer opposite to the substrate and covering at least a portion of the first electrode layer located on the periphery of the encapsulation region, the pixel defining layer being provided with a third sub-via communicating with the second sub-via, the orthographic projection of the second sub-via on the substrate being located within the orthographic projection range of the third sub-via on the substrate; Preferably, the orthographic projection of the pixel defining layer on the substrate near the edge of the third sub-via is recessed relative to the orthographic projection of the second planarization layer on the substrate near the edge of the second sub-via; Preferably, in a cross section perpendicular to the plane of the substrate and perpendicular to the extension direction of the metal trace located in the packaging area, the distance between the edge of the orthographic projection of the pixel defining layer on the substrate near the third sub-via and the edge of the orthographic projection of the surface of the first electrode layer on the side away from the substrate on the substrate is greater than or equal to 5 micrometers. Preferably, the display panel further includes a support pillar located on the side of the pixel defining layer opposite to the substrate, and the support pillar is at least partially disposed around the third sub-via. Preferably, the orthographic projection of the support post on the substrate near the edge of the third sub-via is recessed relative to the orthographic projection of the pixel defining layer on the substrate near the edge of the third sub-via.

6. The display panel as described in claim 5, characterized in that, The encapsulation layer is located on the side of the support pillar opposite to the substrate, and at least a portion of the encapsulation layer extends into the encapsulation region and covers the first electrode layer located in the encapsulation region. Preferably, at least a portion of the encapsulation layer extends to the side of the encapsulation region away from the display region and covers the first electrode layer on the side of the encapsulation region away from the display region; Preferably, the material of the encapsulation layer includes inorganic materials.

7. A method for manufacturing a display panel, characterized in that, Includes the following steps: Provide substrate; Metal traces are formed on one side of the substrate, with a portion of the metal traces located in the packaging area. A first electrode layer is formed on the side of the metal trace away from the substrate, and the first electrode layer covers the exposed surface of the metal trace located within the packaging area; An encapsulation layer is formed on the side of the first electrode layer away from the substrate, and the encapsulation layer covers the exposed surface of the first electrode layer.

8. The manufacturing method as described in claim 7, characterized in that, The step of forming a metal trace on one side of the substrate includes the following prior to the step of forming a metal trace on one side of the substrate: A first insulating layer is formed on one side of the substrate; Preferably, after the step of forming the first insulating layer on one side of the substrate, the method further includes: A first planarization layer is formed on one side of the substrate. The first planarization layer includes a first sub-via, through which the metal trace located in the packaging area overlaps with the first insulating layer. Preferably, the step of forming a first planarization layer on one side of the substrate includes: A first organic material layer is deposited on the substrate, and the first organic material layer is patterned using photolithography to form the first planarization layer.

9. The manufacturing method as described in claim 7, characterized in that, The step of forming the first electrode layer on the side of the metal trace away from the substrate includes: A second planarization layer is formed on the side of the metal trace away from the substrate. The second planarization layer is provided with a second sub-via. The orthogonal projection of the second sub-via on the substrate is located within the packaging area. Preferably, the step of forming a second planarization layer on the side of the metal trace opposite to the substrate includes: A second organic material layer is formed on the side of the metal trace that is away from the substrate; The second organic material layer is patterned using photolithography to form an organic protective layer. The organic protective layer includes a first organic protective layer and a second organic protective layer. The thickness of the first organic protective layer is greater than the thickness of the second organic protective layer. The second organic protective layer covers the exposed surfaces of the metal traces located in the encapsulation area and a portion of the exposed surfaces of the metal traces located around the encapsulation area. The organic protective layer is ashed to remove the second organic protective layer and part of the first organic protective layer, forming a second planarization layer; Preferably, the thickness of the removed portion of the first organic protective layer is equal to the thickness of the second organic protective layer; Preferably, in the direction perpendicular to the plane of the substrate, the thickness of the first organic protective layer is greater than or equal to 2 micrometers; Preferably, the thickness of the second organic protective layer is between 0.3 micrometers and 0.6 micrometers in the direction perpendicular to the plane of the substrate.

10. A display device comprising a display panel as described in any one of claims 1-9.

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