Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel and a preparation method thereof and a display device, the display panel comprises a display area and a non-display area, the display panel comprises a substrate, a circuit structure layer, an isolation structure, a light emitting unit and a protection layer, the circuit structure layer is arranged on one side of the substrate, and the isolation structure is arranged on the other side of the substrate; the circuit structure layer comprises a pixel circuit structure located in the display area, a test terminal part located in the non-display area and a wiring part electrically connected with the test terminal part; the protection layer is arranged on the side, away from the substrate, of the circuit structure layer, at least part of the orthographic projection of the wiring part on the substrate is located within the orthographic projection range of the protection layer on the substrate, and at least part of the orthographic projection of the test terminal part on the substrate is located outside the orthographic projection range of the protection layer on the substrate. By adding the protective layer, the pins of the test circuit board can be prevented from being in contact with the wiring parts corresponding to other test terminal parts in the subsequent test process, so that the risk of abnormal display and burn of the display panel caused by short circuit in the test process is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, current display products are prone to display abnormalities and screen burn-in during subsequent testing. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a display panel and its preparation method, as well as a display device, to reduce the risk of display abnormalities and burns during testing.

[0005] For the purposes described above, this application provides a display panel, which includes:

[0006] Substrate;

[0007] A circuit structure layer is disposed on one side of the substrate. The circuit structure layer includes a pixel circuit structure located in the display area, a test terminal portion located in the non-display area, and a trace portion electrically connected to the test terminal portion.

[0008] An isolation structure is located in the display area and disposed on the side of the circuit structure layer away from the substrate, and the isolation structure encloses and forms a plurality of isolation openings;

[0009] A light-emitting unit, wherein the light-emitting unit is at least partially located in the isolation opening;

[0010] A protective layer is disposed on the side of the circuit structure layer away from the substrate, wherein the orthographic projection of the trace portion on the substrate is at least partially within the orthographic projection range of the protective layer on the substrate, and the orthographic projection of the test terminal portion on the substrate is at least partially outside the orthographic projection range of the protective layer on the substrate.

[0011] In one embodiment, the display panel includes:

[0012] A planarization layer is located at least in the non-display area and disposed between the trace portion and the protective layer. The orthographic projection of the trace portion on the substrate is at least partially within the orthographic projection range of the planarization layer on the substrate, and the orthographic projection of the terminal portion on the substrate is at least partially outside the orthographic projection range of the planarization layer on the substrate.

[0013] In one embodiment, the trace portion includes a strip-shaped portion extending along a first direction, and the test terminal portion includes a strip-shaped portion extending along a second direction; wherein the first direction and the second direction intersect; the orthographic projection of the virtual extension of the strip-shaped portion of the test terminal portion along the second direction and the overlapping area of ​​the non-electrically connected trace portion on the substrate is located within the orthographic projection range of the protective layer on the substrate.

[0014] Preferably, a plurality of test terminals are provided, and the plurality of test terminals are arranged at intervals along the first direction;

[0015] Preferably, there are multiple wiring portions, and the multiple wiring portions are arranged at intervals along the second direction; preferably, the first direction is perpendicular to the second direction.

[0016] In one embodiment, the light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked along a direction away from the substrate;

[0017] Preferably, the light-emitting layer and the second electrode are located in the isolation opening;

[0018] Preferably, the isolation structure includes a support portion and a crown portion, the crown portion being located on the side of the support portion away from the substrate, and the orthographic projection of the support portion on the substrate being located within the orthographic projection of the crown portion on the substrate;

[0019] Preferably, the first electrode is the anode and the second electrode is the cathode;

[0020] Preferably, the protective layer includes a light-emitting material layer and a cathode material layer, wherein the light-emitting material layer is located in the same layer as the light-emitting layer and is made of the same material, and the cathode material layer is located in the same layer as the second electrode and is made of the same material.

[0021] In one embodiment, the display panel includes a first encapsulation layer, the first encapsulation layer including a first encapsulation portion located in the display area and a second encapsulation portion located in the non-display area, the first encapsulation portion being disposed on the side of the light-emitting unit away from the substrate, and the orthographic projection of the light-emitting unit on the substrate being located within the orthographic projection range of the first encapsulation portion on the substrate;

[0022] The second encapsulation portion is disposed on the side of the wiring portion away from the substrate, and the protective layer includes the second encapsulation portion;

[0023] Preferably, the first encapsulation layer includes a first inorganic encapsulation layer;

[0024] Preferably, the display panel further includes a second encapsulation layer and a third encapsulation layer, wherein the second encapsulation layer is located on the side of the first encapsulation layer away from the substrate, and the third encapsulation layer is located on the side of the second encapsulation layer away from the first encapsulation layer.

[0025] In one embodiment, the circuit structure layer includes a fifth metal layer, the terminal portion includes a fifth terminal portion located on the fifth metal layer, and the trace portion includes a fifth trace portion located on the fifth metal layer; preferably, the orthographic projection of the fifth trace portion on the substrate is located within the orthographic projection of the protective layer on the substrate, and the display panel includes a fourth planarization layer disposed between the fifth trace portion and the protective layer.

[0026] In one embodiment, the circuit structure layer further includes a fourth metal layer disposed between the substrate and the fifth metal layer;

[0027] The test terminal portion includes a fourth terminal portion located on the fourth metal layer, and the trace portion includes a fourth trace portion located on the fourth metal layer; the fourth terminal portion is electrically connected to the fifth terminal portion;

[0028] Preferably, the orthographic projection of the fourth terminal portion on the substrate is located within the orthographic projection of the fifth terminal portion on the substrate;

[0029] Preferably, the orthographic projection of the fourth trace on the substrate is located within the orthographic projection of the fifth trace on the substrate;

[0030] Preferably, the display panel further includes a third planarization layer, which is disposed between the fourth trace portion and the fifth trace portion.

[0031] In one embodiment, the circuit structure layer further includes a third metal layer disposed between the substrate and the fourth metal layer;

[0032] The test terminal portion includes a third terminal portion located on the third metal layer, and the trace portion includes a third trace portion located on the third metal layer; the third terminal portion is electrically connected to the fourth terminal portion;

[0033] Preferably, the orthographic projection of the third terminal portion on the substrate is located within the orthographic projection of the fourth terminal portion on the substrate;

[0034] Preferably, the orthographic projection of the third trace on the substrate is located within the orthographic projection of the fourth trace on the substrate;

[0035] Preferably, the display panel further includes a second planarization layer, which is disposed between the third wiring portion and the fourth wiring portion.

[0036] In one embodiment, the circuit structure layer further includes a second metal layer and a first metal layer, the second metal layer being disposed between the first metal layer and the third metal layer, the first metal layer being disposed between the substrate and the second metal layer, and the first metal layer and the second metal layer being located at least in the display area;

[0037] Preferably, the display panel further includes a first planarization layer disposed between the second metal layer and the third metal layer.

[0038] In one embodiment, the non-display area includes a test pad area, and the protective layer is located in the test pad area.

[0039] Based on the same inventive concept, this application also provides a method for manufacturing a display panel, the display panel including a display area and a non-display area, the method for manufacturing the display panel including:

[0040] A circuit structure layer is formed on one side of the substrate, and the circuit structure layer is processed to form a pixel circuit structure located in the display area, a test terminal portion located in the non-display area, and a trace portion electrically connected to the test terminal portion.

[0041] An isolation structure and a first pixel light-emitting unit are formed on the side of the circuit structure layer away from the substrate, located in the display area, and a first encapsulation layer is formed in the display area and the non-display area. The first encapsulation layer includes a first encapsulation portion located in the display area that covers the first pixel light-emitting unit and a second encapsulation portion formed simultaneously with the first encapsulation portion located in the non-display area. The second encapsulation portion forms a protective layer. The orthographic projection of the trace portion on the substrate is at least partially located within the orthographic projection range of the protective layer on the substrate. The protective layer covers at least a portion of the trace portion and exposes at least a portion of the test terminal portion.

[0042] In one embodiment, the step of forming an isolation structure and a first pixel light-emitting unit located in the display area on the side of the circuit structure layer away from the substrate, and a first encapsulation layer located in the display area and the non-display area, includes:

[0043] A first electrode is formed on the side of the circuit structure layer away from the substrate;

[0044] A light-emitting material layer, a second electrode material layer, and a first encapsulation layer corresponding to the first pixel are formed on the side of the isolation structure away from the substrate;

[0045] The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the first pixel are processed to form the first encapsulation part, the light-emitting layer, and the second electrode of the first pixel light-emitting unit. At the same time, the protective layer is also formed, which includes a first sub-protective part formed by the light-emitting material layer, a second sub-protective part formed by the second electrode material layer, and a third sub-protective part formed by the first encapsulation layer.

[0046] In one embodiment, after the step of forming a circuit structure layer on one side of the substrate, the method for fabricating the display panel further includes:

[0047] A planarization layer is formed on the side of the circuit structure away from the substrate, such that the planarization layer covers at least a portion of the trace portion and exposes at least a portion of the test terminal portion;

[0048] The protective layer is formed on the side of the planarization layer away from the substrate.

[0049] In one embodiment, after processing the light-emitting material layer, the second electrode material layer, and the first encapsulation layer corresponding to the first pixel, the method for manufacturing the display panel further includes:

[0050] A light-emitting material layer, a second electrode material layer, and a first encapsulation layer are formed corresponding to the second pixel; wherein, the first encapsulation layer corresponding to the second pixel is located in the display area;

[0051] The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the second pixel are processed to form a second pixel light-emitting unit and a first encapsulation part covering the second pixel light-emitting unit; wherein the emitted light color of the second pixel light-emitting unit and the first pixel light-emitting unit is different.

[0052] In one embodiment, after processing the first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the second pixel, the method for manufacturing the display panel further includes:

[0053] A light-emitting material layer, a second electrode material layer, and a first encapsulation layer corresponding to the third pixel are formed; wherein, the first encapsulation layer corresponding to the third pixel is located in the display area;

[0054] The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the third pixel are processed to form a third pixel light-emitting unit and a first encapsulation part covering the third pixel light-emitting unit; wherein the emitted light color of the third pixel light-emitting unit is different from that of the first pixel light-emitting unit and the second pixel light-emitting unit.

[0055] Based on the same inventive concept, this application also provides a display device, which includes the above-described display panel.

[0056] Compared with the prior art, the display panel provided in this application protects the circuit structure layer by adding a protective layer on the side of the circuit structure layer away from the substrate. During the pixel patterning etching process, the protective layer located in the non-display area can effectively protect the underlying traces, preventing metal exposure caused by etching. In subsequent testing, it can prevent the pins of the test circuit board from contacting the traces corresponding to other test terminals, thereby reducing the risk of short circuits causing abnormal display and burns to the display panel during testing. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of the structure of a related display panel;

[0059] Figure 2 This is a schematic cross-sectional view of a related display panel before the formation of light-emitting units;

[0060] Figure 3 This is a schematic diagram of the cross-sectional structure of a related display panel after the light-emitting unit is formed;

[0061] Figure 4 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0062] Figure 5 For this application Figure 4 Sectional view at point AA;

[0063] Figure 6 A cross-sectional structural diagram of a display panel during testing, provided in another embodiment of this application;

[0064] Figure 7 This is a partial structural diagram of the non-display area of ​​a display panel provided in another embodiment of this application;

[0065] Figure 8 A partial structural diagram of a display panel during testing, provided in another embodiment of this application;

[0066] Figure 9 A cross-sectional structural diagram of a display panel during testing, provided in another embodiment of this application;

[0067] Figure 10 This is a cross-sectional structural diagram of the non-display area of ​​a display panel provided in another embodiment of this application;

[0068] Figure 11 A cross-sectional structural diagram of the display area of ​​a display panel provided in another embodiment of this application;

[0069] Figure 12 A schematic flowchart illustrating a method for fabricating a display panel according to another embodiment of this application;

[0070] Figure 13 This is a schematic diagram of the structure during the fabrication process of a display panel according to another embodiment of this application;

[0071] Figure 14 This is a schematic diagram of the manufacturing process of a display panel provided in another embodiment of this application.

[0072] Marker explanation:

[0073] 100. Display panel; 101. Display area; 102. Non-display area;

[0074] 1. Substrate;

[0075] 2. Circuit structure layer; 201. Test terminal section; 202. Routing section; 21. First metal layer; 22. Second metal layer; 23. Third metal layer; 231. Third terminal section; 232. Third routing section; 24. Fourth metal layer; 241. Fourth terminal section; 242. Fourth routing section; 25. Fifth metal layer; 251. Fifth terminal section; 252. Fifth routing section;

[0076] 3. Planarization layer; 31. First planarization layer; 32. Second planarization layer; 33. Third planarization layer; 34. Fourth planarization layer;

[0077] 4. Protective layer; 41. First encapsulation layer; 42. Second encapsulation layer; 43. Third encapsulation layer;

[0078] 5. Test the circuit board;

[0079] 6. Isolation structure; 60. Isolation opening; 61. Support; 62. Crown;

[0080] 7. Light-emitting unit; 71. First electrode; 72. Light-emitting layer; 73. Second electrode. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0082] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0083] Reference Figure 1 , Figure 2 and Figure 3 This refers to a related display panel 100, which includes a display area 101 and a non-display area 102. The display panel 100 includes a substrate 1 and a circuit structure layer 2 and a planarization layer 3 sequentially stacked on the substrate 1, with the planarization layer 3 covering the circuit structure layer 2.

[0084] During the fabrication of the display panel 100, repeated etching is required to form light-emitting units in the display area 101. The inventors discovered that in the process of forming the light-emitting units, firstly, a full-area vapor deposition is performed to complete the deposition of the first color OLED light-emitting layer and functional layer. Then, a full-area thin-film encapsulation is performed. Next, through processes such as coating, exposure, development, etching, and stripping, the unwanted portions of the substrate are selectively removed, thus completing the patterning of the first color pixel. This process is then repeated twice more to complete the patterning of full-color pixels for the three primary colors (red, green, and blue, RGB). However, during the etching process for pixel patterning in the display area 101, referring to… Figure 3 As shown, this will cause etching loss to the planarization layer 3 in the non-display area 102, resulting in the metal traces in the circuit structure layer 2 below the planarization layer 3 being exposed. During subsequent aging and screen testing, the pins of the test circuit board may come into contact with metal traces at locations where they should not be overlapped, which may cause short circuits between different pins, resulting in abnormal display or screen burn-out.

[0085] Based on this, this application provides a display panel solution, as detailed in the following embodiments.

[0086] Reference Figure 4 , Figure 5 As shown, one embodiment of this application provides a display panel 100, which includes a display area 101 and a non-display area 102. The display panel 100 includes a substrate 1, a circuit structure layer 2, an isolation structure 6, a light-emitting unit 7, and a protective layer 4. The circuit structure layer 2 is disposed on one side of the substrate 1 and includes a pixel circuit structure located in the display area 101 and a test terminal portion 201 and a wiring portion 202 located in the non-display area 102. The wiring portion 202 is electrically connected to the test terminal portion 201. The pixel circuit structure can be a driving circuit that provides driving current to the light-emitting unit 7 to drive the light-emitting unit 7 to emit light.

[0087] The isolation structure 6 and the light-emitting unit 7 are located in the display area 101, and the isolation structure 6 is disposed on the side of the circuit structure layer 2 away from the substrate 1. The isolation structure 6 encloses and forms a plurality of isolation openings 60, and at least a portion of the structure of the light-emitting unit 7 is located in the isolation openings 60, and the light-emitting unit 7 is electrically connected to the pixel circuit structure. The protective layer 4 is disposed on the side of the circuit structure layer 2 away from the substrate 1. The orthographic projection of the trace portion 202 on the substrate 1 is at least partially within the orthographic projection range of the protective layer 4 on the substrate 1, and the orthographic projection of the test terminal portion 201 on the substrate 1 is at least partially outside the orthographic projection range of the protective layer 4 on the substrate 1.

[0088] Specifically, the protective layer 4 covers at least a portion of the trace portion 202 of the circuit structure layer 2, and exposes at least a portion of the test terminal portion 201. The trace portion 202 can be a metal trace led out from the display area 101, such as a power line or signal line. (Refer to...) Figure 6 As shown, during the test, the test terminal portion 201 of the circuit structure layer 2 is electrically connected to the pins of the test circuit board 5 to achieve signal transmission. The test circuit board 5 can be a flexible printed circuit board (FPC). By covering the parts of the trace portion 202 that are prone to short circuits with the protective layer 4, the trace portion 202 of the circuit structure layer 2 and the pins of the test circuit board 5 are kept insulated to prevent short circuits between different pins.

[0089] The display panel 100 provided in this embodiment increases the protection of the circuit structure layer 2 by adding a protective layer 4 on the side of the circuit structure layer 2 away from the substrate 1. During the patterning etching process of the display area 101, the protective layer 4 located in the non-display area 102 can effectively protect the underlying trace portion 202, preventing metal exposure caused by etching. In subsequent testing, it can prevent the pins of the test circuit board from contacting the trace portion 202 corresponding to other test terminal portions 201, thereby avoiding short circuits during testing and reducing the risk of abnormal display and burns to the display panel.

[0090] Reference Figure 5 , Figure 6 As shown, in one embodiment, the display panel 100 includes a planarization layer 3. The planarization layer 3 is located at least in the non-display area 102 and is disposed between the trace portion 202 and the protective layer 4. The orthographic projection of the trace portion 202 on the substrate 1 is at least partially within the orthographic projection range of the planarization layer 3 on the substrate 1, and the orthographic projection of the test terminal portion 201 on the substrate 1 is at least partially outside the orthographic projection range of the planarization layer 3 on the substrate 1. That is, the planarization layer 3 covers at least a portion of the trace portion 202 and exposes at least a portion of the test terminal portion 201.

[0091] Optionally, the planarization layer 3 may also be partially located in the non-display area 102 and partially located in the display area 101.

[0092] Reference Figure 7 , Figure 8 As shown, in one embodiment, the trace portion 202 includes a strip-shaped portion extending along a first direction (X direction in the figure), and the test terminal portion 201 includes a strip-shaped portion extending along a second direction (Y direction in the figure). The first and second directions intersect, and the strip-shaped portion of the test terminal portion 201 has a virtual extension along the second direction. The virtual extension overlaps with the orthographic projection of the non-electrically connected trace portion 202 onto the substrate 1. The orthographic projection of the overlapping area of ​​the virtual extension of the test terminal portion 201 and the non-electrically connected trace portion 202 onto the substrate 1 is located within the orthographic projection range of the protective layer 4 onto the substrate 1.

[0093] Specifically, the test terminal portion 201 is cross-connected with the corresponding trace portion 202. The virtual extension of the test terminal portion 201 corresponds to the pin of the test circuit board 5, and thus overlaps with the orthographic projection of other trace portions 202 on the substrate 1. In other words, during the test, the position where the pin of the test circuit board 5 connected to a test terminal portion 201 overlaps with the trace portion 202 corresponding to other test terminal portions 201 is prone to short circuit, resulting in burns. By covering these overlapping areas with the protective layer 4, abnormal display or burns caused by short circuits can be avoided.

[0094] Optionally, multiple test terminal portions 201 are provided, and the multiple test terminal portions 201 are arranged at intervals along the first direction.

[0095] Optionally, multiple wiring sections 202 are provided, and the multiple wiring sections 202 are arranged at intervals along the second direction.

[0096] Optionally, the first direction is perpendicular to the second direction.

[0097] Optionally, the number of wiring sections 202 is less than or equal to the number of test terminal sections 201. The wiring sections 202 and test terminal sections 201 can be connected one-to-one or many-to-one. The specific design can be customized according to the testing requirements.

[0098] Specifically, the protective layer 4 and the circuit structure layer 2 are stacked along a third direction (Z direction in the figure). During testing, the test circuit board 5 is stacked on the test terminal section 201 along the third direction, so that the multiple test terminal sections 201 are electrically connected to the corresponding pins of the test circuit board 5. Each trace section 202 needs to be insulated from the pins of the test circuit board 5 to prevent short circuits.

[0099] Reference Figure 11 As shown, in one embodiment, the light-emitting unit 7 includes a first electrode 71, a light-emitting layer 72, and a second electrode 73 sequentially stacked along a direction away from the substrate 1.

[0100] Optionally, the light-emitting layer 72 and the second electrode 73 are located in the isolation opening 60.

[0101] Optionally, the isolation structure 6 includes a support portion 61 and a crown portion 62. The crown portion 62 is located on the side of the support portion 61 away from the substrate 1, and the orthographic projection of the support portion 61 on the substrate 1 is within the orthographic projection of the crown portion 62 on the substrate 1. The support portion 61 is a conductive structure, and the second electrode 73 is electrically connected to the support portion 61.

[0102] Optionally, the first electrode 71 is the anode and the second electrode 73 is the cathode.

[0103] Optionally, the protective layer 4 includes a light-emitting material layer and a cathode material layer. The light-emitting material layer and the light-emitting layer 72 are located in the same layer and have the same material. The cathode material layer and the second electrode 73 are located in the same layer and have the same material.

[0104] Specifically, the isolation structure 6 can block the light-emitting layer 72 of adjacent light-emitting units 7 to reduce the current crosstalk problem between adjacent light-emitting units 7. The second electrode 73 is connected to the isolation structure 6 to form a common electrode for driving.

[0105] The composition and preparation of the isolation structure 6 (or partition structure or isolation column) are specified in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 09. Further descriptions are provided in CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, and CN117500332A for reference.

[0106] Reference Figure 5 , Figure 11 As shown, in one embodiment, the display panel 100 includes a first encapsulation layer 41. The first encapsulation layer 41 includes a first encapsulation portion located in the display area 101 and a second encapsulation portion located in the non-display area 102. The first encapsulation portion is disposed on the side of the light-emitting unit 7 away from the substrate 1, and the orthographic projection of the light-emitting unit 7 on the substrate 1 is within the orthographic projection range of the first encapsulation portion on the substrate 1. The second encapsulation portion is disposed on the side of the wiring portion 202 away from the substrate 1, and the protective layer 4 includes the second encapsulation portion.

[0107] Optionally, the first encapsulation layer 41 includes a first inorganic encapsulation layer. Specifically, the first encapsulation layer 41 is prepared from inorganic materials by chemical vapor deposition (CVD).

[0108] In this process, the second encapsulation portion in the protective layer 4 is disposed on the same layer as the first encapsulation portion, both located in the first encapsulation layer 41. Therefore, while the first encapsulation layer 41 is patterned to form the first encapsulation portion in the display area 101, the second encapsulation portion covering the wiring portion 202 can be retained to form the protective layer 4, thus simplifying the process.

[0109] Optionally, the display panel 100 further includes a second encapsulation layer 42 and a third encapsulation layer 43. The second encapsulation layer 42 is located on the side of the first encapsulation layer 41 away from the substrate 1, and the third encapsulation layer 43 is located on the side of the second encapsulation layer 42 away from the first encapsulation layer 41. Specifically, the second encapsulation layer 42 covers the first encapsulation layer 41 and the isolation structure 6, and the third encapsulation layer 43 covers the second encapsulation layer 42. The first encapsulation layer 41 and the third encapsulation layer 43 are inorganic layers. The high density of the inorganic layers helps to isolate water and oxygen. The second encapsulation layer 42 is an organic layer, thus having a larger thickness to flatten the surface of the display panel, achieving an inorganic-organic-inorganic three-layer encapsulation.

[0110] Reference Figures 9 to 11 As shown, in one embodiment, the circuit structure layer 2 includes a fifth metal layer 25, the test terminal portion 201 includes a fifth terminal portion 251 located on the fifth metal layer 25, and the wiring portion 202 includes a fifth wiring portion 252 located on the fifth metal layer 25. The orthographic projection of the fifth wiring portion 252 onto the substrate 1 is within the orthographic projection range of the protective layer 4 onto the substrate 1.

[0111] Optionally, the display panel 100 includes a fourth planarization layer 34, which is disposed between the fifth trace portion 252 and the protective layer 4.

[0112] Reference Figures 9 to 11 As shown, in one embodiment, the circuit structure layer 2 further includes a fourth metal layer 24, which is disposed between the substrate 1 and the fifth metal layer 25. The test terminal portion 201 includes a fourth terminal portion 241 located on the fourth metal layer 24, and the wiring portion 202 includes a fourth wiring portion 242 located on the fourth metal layer 24. The fourth terminal portion 241 and the fifth terminal portion 251 are electrically connected.

[0113] Optionally, the orthographic projection of the fourth terminal portion 241 on the substrate 1 is located within the orthographic projection of the fifth terminal portion 251 on the substrate 1.

[0114] Optionally, the orthographic projection of the fourth trace 242 on the substrate 1 is located within the orthographic projection of the fifth trace 252 on the substrate 1.

[0115] Optionally, the display panel 100 further includes a third planarization layer 33, which is disposed between the fourth wiring portion 242 and the fifth wiring portion 252.

[0116] Reference Figures 9 to 11 As shown, in one embodiment, the circuit structure layer 2 further includes a third metal layer 23, which is disposed between the substrate 1 and the fourth metal layer 24. The test terminal portion 201 includes a third terminal portion 231 located on the third metal layer 23, and the wiring portion 202 includes a third wiring portion 232 located on the third metal layer 23. The third terminal portion 231 is electrically connected to the fourth terminal portion 241.

[0117] Optionally, the orthographic projection of the third terminal portion 231 on the substrate 1 is located within the orthographic projection of the fourth terminal portion 241 on the substrate 1.

[0118] Optionally, the orthographic projection of the third trace 232 on the substrate 1 is located within the orthographic projection of the fourth trace 242 on the substrate 1.

[0119] Optionally, the display panel 100 further includes a second planarization layer 32, which is disposed between the third wiring portion 232 and the fourth wiring portion 242.

[0120] Reference Figure 11 As shown, in one embodiment, the circuit structure layer 2 further includes a second metal layer 22 and a first metal layer 21. The second metal layer 22 is disposed between the first metal layer 21 and the third metal layer 23, and the first metal layer 21 is disposed between the substrate 1 and the second metal layer 22. The first metal layer 21 and the second metal layer 22 are located at least in the display area 101.

[0121] Optionally, the display panel 100 further includes a first planarization layer 31 disposed between the second metal layer 22 and the third metal layer 23.

[0122] Optionally, an interlayer insulating layer is provided between the second metal layer 22 and the first metal layer 21.

[0123] The circuit structure layer 2 employs multi-layered metal electrical connections, which reduces voltage drop, thereby improving current transmission efficiency and minimizing energy loss during transmission. Furthermore, it enables more stable and faster signal transmission, extending circuit lifespan and enhancing reliability. A planarization layer between adjacent metal layers provides insulation.

[0124] Reference Figure 4 As shown, in one embodiment, the non-display area 102 includes a test pad area (CT Pad), and the protective layer 4 is located in the test pad area.

[0125] For example, in the display area 101, the pixel circuit structure may include an active layer, a third metal layer 23, and a fourth metal layer 24. The active layer, the first metal layer 21, the second metal layer 22, the third metal layer 23, and the fourth metal layer 24 are sequentially stacked on one side of the substrate 1. The source and drain of the driving transistor may be disposed in the third metal layer 23. The third metal layer 23 may be electrically connected to the active layer via, and the fourth metal layer 24 may be electrically connected to the third metal layer 23 via. The first electrode 71 of the light-emitting unit may be electrically connected to the fourth metal layer 24 via. Some special display areas, such as light-transmitting display areas, may exist in the display area 101, and their signal lines may be disposed in the fifth metal layer 25.

[0126] Reference Figure 12 As shown, another embodiment of this application provides a method for manufacturing a display device, which can produce the display panel in the above embodiment. The display panel 100 includes a display area 101 and a non-display area 102. The method for manufacturing the display panel includes the following steps:

[0127] Step S1: A circuit structure layer 2 is formed on one side of the substrate 1. The circuit structure layer 2 is processed, and a pixel circuit structure located in the display area 101, a test terminal portion 201 located in the non-display area 102, and a trace portion 202 are formed simultaneously. The trace portion 202 is electrically connected to the test terminal portion 201. (Refer to...) Figure 13 ;

[0128] Step S2: An isolation structure 6 and a first pixel light-emitting unit are formed on the side of the circuit structure layer 2 away from the substrate 1, located in the display area 101, and a first encapsulation layer 41 is formed in the display area 101 and the non-display area 102. The first encapsulation layer 41 includes a first encapsulation portion in the display area 101 covering the first pixel light-emitting unit, and a second encapsulation portion formed simultaneously with the first encapsulation portion in the non-display area 102. The second encapsulation portion forms a protective layer 4. The orthographic projection of the trace portion 202 on the substrate 1 is at least partially within the orthographic projection range of the protective layer 4 on the substrate 1. The protective layer 4 covers at least a portion of the trace portion 202 and exposes at least a portion of the test terminal portion 201. (See reference...) Figure 14 .

[0129] Specifically, the circuit structure layer 2 is located in the display area 101 and the non-display area 102. The portion of the circuit structure layer 2 in the display area 101 is used to form a pixel circuit structure. The circuit structure layer 2 also includes a test terminal portion 201 and a wiring portion 202 located in the non-display area 102. The isolation structure 6 encloses and forms a plurality of isolation openings 60, and at least a portion of the structure of the light-emitting unit 7 is located in the isolation openings 60. The orthographic projection of the wiring portion 202 on the substrate 1 is at least partially within the orthographic projection range of the protective layer 4 on the substrate 1, and the orthographic projection of the test terminal portion 201 on the substrate 1 is at least partially outside the orthographic projection range of the protective layer 4 on the substrate 1.

[0130] The method for fabricating the display panel 100 provided in this embodiment adds a protective layer 4 to the side of the circuit structure layer 2 away from the substrate 1, thereby increasing the protection of the circuit structure layer 2. During the patterning etching process of the display area 101, the protective layer 4 located in the non-display area 102 can effectively protect the underlying traces 202, preventing metal exposure caused by etching. In subsequent testing, it can prevent the pins of the test circuit board from contacting the traces 202 corresponding to other test terminals 201, thus avoiding short circuits during testing and reducing the risk of abnormal display and burn-in of the display panel. In addition, using the same layer for fabrication can simplify the manufacturing process and improve production efficiency.

[0131] In one embodiment, step S2 includes:

[0132] Step S21: Form a first electrode 71 on the side of the circuit structure layer 2 away from the substrate 1;

[0133] Step S22: Form a light-emitting material layer, a second electrode material layer and a first encapsulation layer 41 corresponding to the first pixel on the side of the isolation structure 6 away from the substrate 1;

[0134] Step S23: Process the first encapsulation layer 41, the second electrode material layer and the light-emitting material layer corresponding to the first pixel to form the light-emitting layer 72, the second electrode 73 and the first encapsulation part covering the first pixel light-emitting unit of the first encapsulation part, and at the same time form a protective layer 4, which includes a first sub-protective part formed by the light-emitting material layer, a second sub-protective part formed by the second electrode material layer and a third sub-protective part formed by the first encapsulation layer 41.

[0135] Specifically, a portion of the light-emitting material layer, the second electrode material layer, and the first encapsulation layer 41 corresponding to the first pixel are located in the isolation opening 60, and a portion are located on the side of the isolation structure 6 away from the substrate 1. The first encapsulation layer 41, the second electrode material layer, and the light-emitting material layer corresponding to the first pixel are patterned to form a first pixel light-emitting unit, a first encapsulation portion covering the first pixel light-emitting unit, and a second encapsulation portion covering the wiring portion 202. The second encapsulation portion together with the lower second electrode material layer and the light-emitting material layer form a protective layer 4. The first encapsulation portion and the second encapsulation portion are located in the first encapsulation layer 41.

[0136] In one embodiment, after step S1, the method for manufacturing the display panel further includes:

[0137] A planarization layer 3 is formed on the side of the circuit structure layer 2 away from the substrate 1, such that the planarization layer 3 covers at least a portion of the trace portion 202 and exposes at least a portion of the test terminal portion 201; wherein, the planarization layer 3 is located at least in the non-display area 102, and is disposed between the trace portion 202 and the protective layer 4, the orthographic projection of the trace portion 202 on the substrate 1 is within the orthographic projection range of the planarization layer 3 on the substrate 1, and the orthographic projection of the test terminal portion 201 on the substrate 1 is outside the orthographic projection range of the planarization layer 3 on the substrate 1;

[0138] A protective layer 4 is formed on the side of the planarization layer 3 away from the substrate 1.

[0139] In one embodiment, after step S23, the method for manufacturing the display panel further includes:

[0140] Step S31: Form a light-emitting material layer, a second electrode material layer, and a first encapsulation layer 41 corresponding to the second pixel; wherein, the first encapsulation layer 41 corresponding to the second pixel is located in the display area 101;

[0141] Step S32: Process the first encapsulation layer 41, the second electrode material layer and the light-emitting material layer corresponding to the second pixel to form a second pixel light-emitting unit and a first encapsulation part covering the second pixel light-emitting unit; wherein the emitted light color of the second pixel light-emitting unit and the first pixel light-emitting unit is different.

[0142] In one embodiment, after step S32, the method for manufacturing the display panel further includes:

[0143] Step S41: Form a light-emitting material layer, a second electrode material layer, and a first encapsulation layer 41 corresponding to the third pixel; wherein, the first encapsulation layer 41 corresponding to the third pixel is located in the display area 101;

[0144] Step S42: Process the first encapsulation layer 41, the second electrode material layer and the light-emitting material layer corresponding to the third pixel to form a third pixel light-emitting unit and a first encapsulation part covering the third pixel light-emitting unit; wherein the emitted light color of the third pixel light-emitting unit is different from that of the first pixel light-emitting unit and the second pixel light-emitting unit.

[0145] Specifically, during the first pixel patterning process, a portion of the corresponding first encapsulation layer 41 located in the non-display area 102 can be retained as a protective layer 4 to protect the underlying circuit structure layer 2, so as to prevent over-etching and exposure of metal traces during the subsequent pixel patterning etching process.

[0146] Another embodiment of this application provides a display device that includes the display panel 100 described in the above embodiments. This display device can be located in a smart device (such as a mobile phone, VR device, computer, television, in-vehicle display, etc.).

[0147] The display device provided in this application has a display panel 100 with an added protective layer 4 on the side of the circuit structure layer 2 away from the substrate 1, which increases the protection of the circuit structure layer 2. During the patterning etching process of the display area 101, the protective layer 4 located in the non-display area 102 can effectively protect the underlying trace portion 202, avoiding metal exposure caused by etching. In subsequent testing, it can prevent the pins of the test circuit board from contacting the trace portion 202 corresponding to other test terminal portions 201, thereby reducing the risk of short circuits causing abnormal display and burns to the display panel during testing.

[0148] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0149] It should be noted that the above description describes one embodiment of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0150] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area, and the display panel includes: Substrate; A circuit structure layer is disposed on one side of the substrate. The circuit structure layer includes a pixel circuit structure located in the display area, a test terminal portion located in the non-display area, and a trace portion electrically connected to the test terminal portion. An isolation structure is located in the display area and disposed on the side of the circuit structure layer away from the substrate, and the isolation structure encloses and forms a plurality of isolation openings; A light-emitting unit, wherein the light-emitting unit is at least partially located in the isolation opening; A protective layer is disposed on the side of the circuit structure layer away from the substrate, wherein the orthographic projection of the trace portion on the substrate is at least partially within the orthographic projection range of the protective layer on the substrate, and the orthographic projection of the test terminal portion on the substrate is at least partially outside the orthographic projection range of the protective layer on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel includes: A planarization layer is located at least in the non-display area and disposed between the trace portion and the protective layer. The orthographic projection of the trace portion on the substrate is at least partially within the orthographic projection range of the planarization layer on the substrate, and the orthographic projection of the terminal portion on the substrate is at least partially outside the orthographic projection range of the planarization layer on the substrate.

3. The display panel according to claim 1, characterized in that, The trace portion includes a strip-shaped portion extending along a first direction, and the test terminal portion includes a strip-shaped portion extending along a second direction; wherein the first direction and the second direction intersect; the orthographic projection of the virtual extension of the strip-shaped portion of the test terminal portion along the second direction and the overlapping area of ​​the trace portion that is not electrically connected to the test terminal portion on the substrate is located within the orthographic projection range of the protective layer on the substrate. Preferably, a plurality of test terminals are provided, and the plurality of test terminals are arranged at intervals along the first direction; Preferably, there are multiple wiring portions, and the multiple wiring portions are arranged at intervals along the second direction; preferably, the first direction is perpendicular to the second direction.

4. The display panel according to claim 1, characterized in that, The light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode that are sequentially stacked along a direction away from the substrate; Preferably, the light-emitting layer and the second electrode are located in the isolation opening; Preferably, the isolation structure includes a support portion and a crown portion, the crown portion being located on the side of the support portion away from the substrate, and the orthographic projection of the support portion on the substrate being located within the orthographic projection of the crown portion on the substrate; Preferably, the first electrode is the anode and the second electrode is the cathode; Preferably, the protective layer includes a light-emitting material layer and a cathode material layer, wherein the light-emitting material layer is located in the same layer as the light-emitting layer and is made of the same material, and the cathode material layer is located in the same layer as the second electrode and is made of the same material.

5. The display panel according to claim 4, characterized in that, The display panel includes a first encapsulation layer, which includes a first encapsulation portion located in the display area and a second encapsulation portion located in the non-display area. The first encapsulation portion is disposed on the side of the light-emitting unit away from the substrate, and the orthographic projection of the light-emitting unit on the substrate is located within the orthographic projection range of the first encapsulation portion on the substrate. The second encapsulation portion is disposed on the side of the wiring portion away from the substrate, and the protective layer includes the second encapsulation portion; Preferably, the first encapsulation layer includes a first inorganic encapsulation layer; Preferably, the display panel further includes a second encapsulation layer and a third encapsulation layer, wherein the second encapsulation layer is located on the side of the first encapsulation layer away from the substrate, and the third encapsulation layer is located on the side of the second encapsulation layer away from the first encapsulation layer.

6. The display panel according to claim 1, characterized in that, The circuit structure layer includes a fifth metal layer, the test terminal portion includes a fifth terminal portion located on the fifth metal layer, and the trace portion includes a fifth trace portion located on the fifth metal layer; preferably, the orthographic projection of the fifth trace portion on the substrate is located within the orthographic projection of the protective layer on the substrate, and the display panel includes a fourth planarization layer, which is disposed between the fifth trace portion and the protective layer.

7. The display panel according to claim 6, characterized in that, The circuit structure layer further includes a fourth metal layer, which is disposed between the substrate and the fifth metal layer; The test terminal portion includes a fourth terminal portion located on the fourth metal layer, and the trace portion includes a fourth trace portion located on the fourth metal layer; the fourth terminal portion is electrically connected to the fifth terminal portion; Preferably, the orthographic projection of the fourth terminal portion on the substrate is located within the orthographic projection of the fifth terminal portion on the substrate; Preferably, the orthographic projection of the fourth trace on the substrate is located within the orthographic projection of the fifth trace on the substrate; Preferably, the display panel further includes a third planarization layer, which is disposed between the fourth trace portion and the fifth trace portion.

8. The display panel according to claim 7, characterized in that, The circuit structure layer further includes a third metal layer, which is disposed between the substrate and the fourth metal layer; The test terminal portion includes a third terminal portion located on the third metal layer, and the trace portion includes a third trace portion located on the third metal layer; the third terminal portion is electrically connected to the fourth terminal portion; Preferably, the orthographic projection of the third terminal portion on the substrate is located within the orthographic projection of the fourth terminal portion on the substrate; Preferably, the orthographic projection of the third trace on the substrate is located within the orthographic projection of the fourth trace on the substrate; Preferably, the display panel further includes a second planarization layer, which is disposed between the third wiring portion and the fourth wiring portion.

9. The display panel according to claim 8, characterized in that, The circuit structure layer further includes a second metal layer and a first metal layer, the second metal layer being disposed between the first metal layer and the third metal layer, the first metal layer being disposed between the substrate and the second metal layer, and the first metal layer and the second metal layer being located at least in the display area; Preferably, the display panel further includes a first planarization layer disposed between the second metal layer and the third metal layer.

10. The display panel as claimed in claim 1, characterized in that, The non-display area includes a test pad area, and the protective layer is located in the test pad area.

11. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area, and the method for manufacturing the display panel includes: A circuit structure layer is formed on one side of the substrate, and the circuit structure layer is processed to form a pixel circuit structure located in the display area, a test terminal portion located in the non-display area, and a trace portion electrically connected to the test terminal portion. An isolation structure and a first pixel light-emitting unit are formed on the side of the circuit structure layer away from the substrate, located in the display area, and a first encapsulation layer is formed in the display area and the non-display area. The first encapsulation layer includes a first encapsulation portion located in the display area that covers the first pixel light-emitting unit and a second encapsulation portion formed simultaneously with the first encapsulation portion located in the non-display area. The second encapsulation portion forms a protective layer. The orthographic projection of the trace portion on the substrate is at least partially located within the orthographic projection range of the protective layer on the substrate. The protective layer covers at least a portion of the trace portion and exposes at least a portion of the test terminal portion.

12. The method for manufacturing a display panel according to claim 11, characterized in that, The step of forming an isolation structure and a first pixel light-emitting unit located in the display area on the side of the circuit structure layer away from the substrate, and a first encapsulation layer located in the display area and the non-display area, includes: A first electrode is formed on the side of the circuit structure layer away from the substrate; A light-emitting material layer, a second electrode material layer, and a first encapsulation layer corresponding to the first pixel are formed on the side of the isolation structure away from the substrate; The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the first pixel are processed to form the first encapsulation part, the light-emitting layer, and the second electrode of the first pixel light-emitting unit. At the same time, the protective layer is also formed, which includes a first sub-protective part formed by the light-emitting material layer, a second sub-protective part formed by the second electrode material layer, and a third sub-protective part formed by the first encapsulation layer.

13. The method for manufacturing a display panel according to claim 11, characterized in that, Following the step of forming a circuit structure layer on one side of the substrate, the method for fabricating the display panel further includes: A planarization layer is formed on the side of the circuit structure away from the substrate, such that the planarization layer covers at least a portion of the trace portion and exposes at least a portion of the test terminal portion; The protective layer is formed on the side of the planarization layer away from the substrate.

14. The method for manufacturing a display panel according to claim 12, characterized in that, After processing the first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the first pixel, the method for manufacturing the display panel further includes: A light-emitting material layer, a second electrode material layer, and a first encapsulation layer are formed corresponding to the second pixel; wherein, the first encapsulation layer corresponding to the second pixel is located in the display area; The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the second pixel are processed to form a second pixel light-emitting unit and a first encapsulation part covering the second pixel light-emitting unit; wherein the emitted light color of the second pixel light-emitting unit and the first pixel light-emitting unit is different.

15. The method for manufacturing a display panel according to claim 14, characterized in that, After processing the first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the second pixel, the method for manufacturing the display panel further includes: A light-emitting material layer, a second electrode material layer, and a first encapsulation layer corresponding to the third pixel are formed; wherein, the first encapsulation layer corresponding to the third pixel is located in the display area; The first encapsulation layer, the second electrode material layer, and the light-emitting material layer corresponding to the third pixel are processed to form a third pixel light-emitting unit and a first encapsulation part covering the third pixel light-emitting unit; wherein the emitted light color of the third pixel light-emitting unit is different from that of the first pixel light-emitting unit and the second pixel light-emitting unit.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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