Semiconductor test structures and methods

Abstract

The application provides a semiconductor testing structure and method, which belongs to the technical field of semiconductors. The semiconductor testing structure is located on a wafer to be detected and comprises a drain region, a source region and a trench isolation structure in the wafer to be detected. The trench isolation structure is located between the drain region and the source region to isolate the drain region and the source region. The source region comprises at least one first interdigital electrode, the drain region comprises at least one second interdigital electrode, the first interdigital electrode and the second interdigital electrode are interpenetrated to make the first interdigital electrode have an effective part overlapping the second interdigital electrode, and a gate structure is located on the source region and extends along the intersection line of the effective part and the trench isolation structure. The application can solve the problem that it is difficult for a Fab to effectively detect the bulk microdefects of a wafer to be detected.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor testing structure and method. Background Technology

[0002] Bulk micro-defect density (BMD) is an important physical parameter of wafers, and its density should not be too high or too low. A certain concentration of BMD can adsorb impurities from the silicon wafer surface into the wafer, forming a clean surface area; however, excessive BMD density can cause wafer warping during processing, such as heat treatment. Too much BMD can also cause leakage current in the pn junction of components, reducing minority carrier lifetime. Accurately quantifying the maximum BMD density that a wafer can form during wafer production and device fabrication is crucial for evaluating the characteristics of heavily doped substrates and guiding the development of appropriate downstream processing techniques.

[0003] Currently, for BMD inspection of incoming wafers, wafer suppliers conduct BMD testing before shipment using specific instruments (such as optical inspection instruments, microscopes, etc.) after dicing (slicing, destructive testing). However, there is no effective and quick way for fabs (integrated circuit factories) to conduct BMD inspection, making it impossible to confirm the accuracy of the BMD data in the incoming inspection report. Often, the accuracy can only be estimated backward based on the actual yield of the finished product after the incoming wafers have been produced. Therefore, there is always a risk that the yield will be abnormal due to the distortion of BMD data in the incoming inspection report. Summary of the Invention

[0004] In view of this, this application aims to provide a semiconductor testing structure and method to solve the problem that existing technologies cannot effectively detect bulk micro-defects in fabs.

[0005] This application provides a semiconductor test structure formed on a wafer to be tested, comprising: The drain region, source region, and trench isolation structure are all located within the wafer to be tested. The trench isolation structure is located between the drain region and the source region to isolate the drain region and the source region. The source region includes at least one first interdigitated finger, and the drain region includes at least one second interdigitated finger. The first interdigitated finger and the second interdigitated finger interpenetrate each other so that the first interdigitated finger has an effective portion overlapping with the second interdigitated finger. A gate structure is located on the source region, and the gate structure extends at least along the boundary line between the effective portion and the trench isolation structure.

[0006] Optionally, the gate structure extends along the boundary line between the source region and the trench isolation structure.

[0007] Optionally, the source region is a closed ring, and a portion of the inner ring surface of the source region protrudes towards the center of the source region to form the first interdigitated finger, and the drain region is located within the inner ring surface of the source region.

[0008] Optionally, the width of the groove isolation structure between the overlapping portions of the first interdigitated finger and the second interdigitated finger is smaller than the width outside the overlapping portion of the first interdigitated finger and the second interdigitated finger.

[0009] Optionally, the edge of the leak area is in direct contact with the edge of the trench isolation structure or has a gap; and / or, The edge of the source region is in direct contact with or has a gap with the trench isolation structure.

[0010] Optionally, the conductivity type of the wafer to be tested is P-type, the conductivity type of the drain region and the source region is N-type, the drain region is located in the N-type well region of the wafer to be tested, and the source region is located in the first P-type well region of the wafer to be tested.

[0011] Optionally, the depth of the first P-type well region and the N-type well region is greater than the depth of the trench isolation structure.

[0012] Based on another aspect of this application, a semiconductor testing method is also provided, comprising: A semiconductor test structure as described above is formed on the wafer to be tested; The source region of the semiconductor test structure is grounded, and a detection voltage is applied to the drain region of the semiconductor test structure. The detection voltage is gradually increased while the current change in the gate structure is detected simultaneously until the gate structure undergoes complete tunneling. Based on the detection voltage corresponding to when the gate structure is completely tunneled, it is determined whether the bulk micro-defects of the wafer to be tested are qualified.

[0013] Optionally, after a batch of incoming wafers arrives but before formal production begins, at least one wafer is sampled from the batch of incoming wafers as the wafer to be tested; and, If the micro-defects of the wafer under test are deemed acceptable, the batch of incoming wafers will be put into formal production. If the micro-defects of the wafer under test are deemed unacceptable, the batch of incoming wafers will be stopped from being put into formal production.

[0014] Optionally, the method for determining whether the bulk micro-defects of the wafer to be inspected are qualified further includes: Based on the preset specification range of the bulk micro-defects in the wafer to be tested and the specification parameters of the semiconductor test structure, determine the ideal detection voltage range corresponding to when the gate structure is completely tunneled. If the detection voltage corresponding to the complete tunneling of the gate structure is within the ideal detection voltage range, the wafer to be tested is deemed qualified; otherwise, the wafer to be tested is deemed unqualified.

[0015] In summary, this application provides a semiconductor testing structure and method. The semiconductor testing structure includes a drain region, a source region, and a trench isolation structure, all located within the wafer to be tested. The trench isolation structure is located between the drain region and the source region to isolate them. The source region includes at least one first interdigit, and the drain region includes at least one second interdigit. The first interdigit and the second interdigit intersect each other, so that the first interdigit has an effective portion overlapping with the second interdigit. A gate structure is located on the source region, and the gate structure extends at least along the boundary line between the effective portion and the trench isolation structure. An unexpected effect of this application is that after forming the semiconductor testing structure on the wafer to be tested, the quantity of bulk micro-defects on the wafer can be quickly determined through electrical testing. This allows integrated circuit manufacturers to independently, timely, accurately, and non-destructively detect the quantity of bulk micro-defects in the wafer, avoiding significant yield losses caused by wafers with abnormal bulk micro-defects being put into normal production. Moreover, the channel in the above structure includes the interface between the trench isolation structure and the wafer under test, that is, the channel extends into the interior of the wafer under test, so that the number of bulk micro-defects inside the wafer under test can be confirmed by the electrical parameters inside the wafer under test, thereby improving the effectiveness and accuracy of bulk micro-defect detection. Attached Figure Description

[0016] Figure 1 This is a top view schematic diagram of a semiconductor test structure provided in an embodiment of this application.

[0017] Figure 2 This is a cross-sectional view along the dashed line of a semiconductor test structure provided in an embodiment of this application.

[0018] Figure 3 This is a top view schematic diagram of another structure of drain region, source region and trench isolation structure provided in an embodiment of this application.

[0019] Figure 4 A flowchart of a semiconductor testing method provided in an embodiment of this application.

[0020] Figure 5 This is a schematic diagram showing how the current changes with increasing detection voltage in the gate structure provided in this application embodiment.

[0021] Figure 6 This is a flowchart illustrating a semiconductor testing method provided in an embodiment of this application.

[0022] The attached figures are labeled as follows: 100 - Wafer to be tested; 110 - Effective region; 200 - Drain region; 210 - Second interdigit; 220 - Palm; 230 - N-type well region; 300 - Source region; 310 - First interdigit; 320 - First P-type well region; 330 - Second P-type well region; 400 - Trench isolation structure; 500 - Gate structure; 510 - Gate oxide layer; 520 - Gate conductive layer; X - First direction; Y - Second direction; U1 - First voltage; U2 - Second voltage. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] This application provides a semiconductor test structure.

[0025] Figure 1 This is a top view schematic diagram of a semiconductor test structure provided in an embodiment of this application. Figure 2 This is a cross-sectional view along the dashed line of a semiconductor test structure provided in an embodiment of this application.

[0026] like Figure 1 and Figure 2 As shown in the embodiment of this application, the semiconductor test structure is formed on the wafer 100 to be tested, including a drain region 200, a source region 300, a trench isolation structure 400 and a gate structure 500.

[0027] Specifically, the material of the wafer 100 to be tested can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art.

[0028] The wafer to be tested 100 can be a bare wafer, and its conductivity type can be P-type or N-type. For example, at least one wafer can be selected from a batch of incoming wafers as the wafer to be tested 100. The drain region 200, source region 300, trench isolation structure 400 and gate structure 500 can be disposed, for example, in the test area of ​​the wafer to be tested, that is, without affecting the production line of the wafer to be tested (without affecting the device area). Of course, this application is not limited to this, and it is also feasible to dispose of some or all of the above-mentioned structures in the device area of ​​the wafer to be tested.

[0029] Please continue to refer to Figure 1 and Figure 2 In some embodiments, the conductivity type of the wafer 100 to be tested can be P-type. The drain region 200, the source region 300, and the trench isolation structure 400 are all located in the wafer 100 to be tested. The drain region 200 and the source region 300 are respectively disposed on both sides of the trench isolation structure 400. The trench isolation structure 400 can be closed into a ring shape, and the drain region 200 and the source region 300 are isolated (defined) by the trench isolation structure 400. The contour shapes of the source region 300 and the drain region 200 can each match the contour shape of the corresponding side of the trench isolation structure 400. Figure 1 As shown in the top view, the drain area 200 is located inside the trench isolation structure 400 (within the inner annular surface). The edge of the drain area 200 can contact the edge of the trench isolation structure 400. It has an isolated shape. The drain area 200 may include a palm portion 220 and four second interdigitates 210. The four second interdigitates 210 extend along a first direction X and are spaced apart along a second direction Y, and are connected to one end of the palm portion 220 (i.e., extend from that end). The width of the palm portion 220 is greater than the width of each second interdigitate 210 to facilitate the electrical outgoing of each second interdigitate 210 (drain area 200). Figure 2 As shown in the cross-sectional view, the drain region 200 includes an N-type well region 230 disposed in the wafer 100 to be tested and a first heavily doped N-type region disposed in the N-type well region 230. The first heavily doped N-type region serves as the drain region 200. The doping concentration of the N-type well region 230 is less than that of the drain region 200, and the doping depth (junction depth) of the N-type well region 230 is greater than or equal to the depth of the trench isolation structure 400. In other embodiments of this application, the drain region 200 may also be spaced apart from the edge adjacent to the trench isolation structure 400, that is, a portion of the wafer 100 to be tested (i.e., a wafer region) is also provided between the drain region 200 and the trench isolation structure 400.

[0030] like Figure 1As shown in the top view, the source region 300 is located outside the trench isolation structure 400, forming a closed ring around the trench isolation structure 400. The edge of the source region 300 is spaced apart from the adjacent edge (i.e., the outer edge) of the trench isolation structure 400, meaning there is a portion of the wafer region between the source region 300 and the trench isolation structure 400. A portion of the inner ring surface of the source region 300 protrudes towards the center of the source region 300, forming three first interdigitated fingers 310. These three first interdigitated fingers 310 intersect with four second interdigitated fingers 210. Figure 2 As shown in the cross-sectional view, the source region 300 may include a second P-type well region 330, a first P-type well region 320, and a second N-type heavily doped region arranged sequentially. The doping depth of the second P-type well region 330 is greater than the doping depth of the first P-type well region 320, and the doping depth of the first P-type well region 320 is greater than the doping depth of the second N-type heavily doped region. The second P-type well region 330 covers the first P-type well region 320 from the bottom and sidewalls, and the first P-type well region 320 covers the second N-type heavily doped region from the bottom and sidewalls. That is, the second N-type heavily doped region is located in the first P-type well region 320, and the first P-type well region 320 is located in the second P-type well region 330. The second N-type heavily doped region can serve as the source region 300. The doping concentration of the second N-type heavily doped region is greater than the doping concentration of the first P-type well region 320, and the doping concentration of the first P-type well region 320 is greater than the doping concentration of the second P-type well region 330. In other examples of this application, it is also feasible to provide only one P-type well region (e.g., only the first P-type well region 320) or multiple P-type well regions below the source region 300 to improve the breakdown voltage.

[0031] Please continue. Figure 1 In the top view, three first interdigitated fingers 310 and four second interdigitated fingers 210 intersect each other. The groove isolation structure 400 is disposed between the second interdigitated fingers 210 and the first interdigitated fingers 310. The overlapping portion of the three first interdigitated fingers 310 and the four second interdigitated fingers 210 and the groove isolation structure 400 therein constitute the effective area 110 of the test structure of this application. The width of the groove isolation structure 400 within the effective area 110 is smaller than the width of the groove isolation structure 400 outside the overlapping portion. In other words, the width of the groove isolation structure 400 located at the overlapping portion of the second interdigitated fingers 210 and the first interdigitated fingers 310 is the minimum width of the groove isolation structure 400.

[0032] Please continue to refer to Figure 1 and Figure 2The gate structure 500 is located on the source region 300 on the wafer 100 to be tested, and extends in a ring shape along the boundary line between the source region 300 and the trench isolation structure 400. Specifically, the gate structure 500 includes a gate oxide layer 510 and a gate conductive layer 520. The gate oxide layer 510 covers the wafer surface between the source region 300 and the trench isolation structure 400, and covers part of the surface of the source region 300. That is, one side of the gate oxide layer 510 is in contact with or spaced from the trench isolation structure 400, and the other side of the gate oxide layer 510 is located on the surface of the source region 300. The gate conductive layer 520 is located on the gate oxide layer 510, and the gate oxide layer 510 covers the gate conductive layer 520 from the bottom and sidewalls of the gate conductive layer 520.

[0033] It is understood that in other examples, any other suitable number of second interdigits 210 and first interdigits 310 can be provided, such as five second interdigits 210 and six first interdigits 310. This application is not limited to the number of second interdigits 210 and first interdigits 310. In addition, an insulating dielectric layer (e.g., an oxide layer) may also be provided on the wafer 100 to be tested. The insulating dielectric layer covers the drain region 200, the source region 300, the trench isolation structure 400, and the gate structure 500. Interconnect structures are provided in the insulating dielectric layer for electrically leading out the drain region 200, the source region 300, and the gate structure 500 to facilitate electrical testing, such as plugs provided in the insulating dielectric layer and pads connected to the plugs.

[0034] In such Figure 2 In the cross-sectional schematic diagram shown, the longitudinal cross-sectional shape of the trench isolation structure 400 can be an inverted trapezoidal shape (wider at the top and narrower at the bottom). The doping depth (junction depth) of the N-type well region 230 can be greater than or equal to the depth of the trench isolation structure 400. The doping depth (junction depth) of the first P-type well region 320 can be greater than the depth of the trench isolation structure 400. The doping depth of the first P-type well region 320 can be greater than the doping depth of the N-type well region 230.

[0035] Figure 3 This is a top view of a drain region 200, a source region 300, and a trench isolation structure 400, provided as an embodiment of this application. Figure 3As shown, the drain region 200 includes a palm portion 220 and two sets of second interdigitated fingers 210. The two sets of second interdigitated fingers 210 are respectively disposed on both sides of the palm portion 220 along the first direction X. Each set of second interdigitated fingers 210 includes multiple second interdigitated fingers 210. A trench isolation structure 400 surrounds the drain region 200, a source region 300 surrounds the trench isolation structure 400, and a gate structure 500 (not shown in the figure) is disposed on the source region 300. The specific arrangement of the drain region 200, the trench isolation structure 400, the source region 300, and the gate structure 500 can be referred to the aforementioned embodiment. Furthermore... In other examples of this application, the drain region 200 may also include a palm portion 220 and three sets of second interdigitates 210, wherein two sets of second interdigitates 210 are respectively disposed on both sides of the palm portion 220 along the first direction X, and another set of second interdigitates 210 is disposed on one side of the palm portion 220 along the second direction Y. Each set of second interdigitates 210 includes multiple second interdigitates 210. The groove isolation structure 400 surrounds the drain region 200, and the source region 300 surrounds the groove isolation structure 400.

[0036] Based on this, one embodiment of this application also provides a semiconductor testing method. Figure 4 A flowchart of a semiconductor testing method provided in an embodiment of this application is shown below. Figure 4 As shown, semiconductor testing methods include: S100: Form the semiconductor test structure as described above on the wafer to be tested; S200: Ground the source region of the semiconductor test structure and apply a detection voltage to the drain region of the semiconductor test structure; S300: Gradually increase the detection voltage while simultaneously detecting the current change in the gate structure until the gate structure undergoes complete tunneling; S400: Determine whether the bulk micro-defects of the wafer to be tested are qualified based on the detection voltage corresponding to when the gate structure is completely tunneled.

[0037] In step S100, a corresponding test structure as described above can be formed on the wafer to be tested. The configuration of the drain region, source region, trench isolation structure and gate structure in the test structure can be referred to the aforementioned embodiments.

[0038] In step S200, the source region is grounded, a detection voltage is applied to the drain region (i.e., the drain region), and the gate structure (gate conductive layer) is connected to the current meter.

[0039] In step S300, the detection voltage is gradually increased, for example from 0 to 300V, while the current change in the gate structure (gate conductive layer) is detected simultaneously. The detection voltage is increased until the gate structure undergoes complete tunneling (carriers completely tunnel through the gate oxide layer). This application uses the contact surface between the overlapping portion of the first and second interdigitates and the trench isolation structure (the interface between the trench isolation structure and the wafer in the effective region) as the detection point for bulk micro-defects. Under normal circumstances, when the source region is grounded and a high voltage is applied to the drain region, electrons will flow from the source region to the drain region. When the detection voltage gradually increases until the channel between the source and drain regions (the wafer surface between the two and the interface between the wafer and the trench isolation structure) is burned out, an abnormality occurs. Electrons can only reach the gate structure from the source region through the tunneling effect, which causes a drastic change in the current in the gate structure. Therefore, the change in the current in the gate structure can reflect whether the channel between the source and drain regions has been burned out. At the same time, bulk micro-defects are essentially oxygen precipitates. The number of bulk micro-defects is negatively correlated with the conductivity of the wafer under test. It can be inferred that the more bulk micro-defects there are, the greater the detection voltage required to burn out the channel between the source and drain regions. That is, the detection voltage corresponding to the drastic change in the current in the gate structure is positively correlated with the number of bulk micro-defects. In this way, the number of bulk micro-defects in the wafer under test can be quickly determined through electrical testing. Furthermore, setting a trench isolation structure between the drain and source regions not only enables the semiconductor test structure to withstand higher detection voltages, reaching the high voltage required to burn out the channel, but also allows the channel to extend into the wafer. This allows the number of bulk micro-defects inside the wafer to be identified by examining the electrical parameters inside the wafer, thereby improving the effectiveness and accuracy of bulk micro-defect detection.

[0040] Figure 5 This is a schematic diagram illustrating how the current changes with increasing detection voltage in the gate structure provided in an embodiment of this application. Figure 5 As shown, when the detection voltage is less than the first voltage U1, the channel between the drain and source regions is normal and not burned out, so no current is detected in the gate structure. When the detection voltage is greater than the first voltage U1, part of the channel between the drain and source regions is burned out, causing soft breakdown of the gate oxide layer, that is, tunneling begins in the gate oxide layer, and current is detected in the gate structure. This current increases with the increase of the detection voltage. When the detection voltage is greater than the second voltage U2 (the second voltage U2 is greater than the first voltage U1), the channel is completely burned out, causing hard breakdown of the gate structure, that is, complete tunneling of the gate oxide layer, causing the current in the gate structure to increase sharply. Therefore, the above electrical test can be stopped after confirming the second voltage U2, that is, the minimum voltage at which the charge carriers completely tunnel through the gate oxide layer.

[0041] In step S400, the method for determining whether the bulk micro-defects of the wafer under test are qualified may include: determining the ideal detection voltage range corresponding to the qualified (within the preset specification range) bulk micro-defects of the wafer under test based on the preset specification range of the bulk micro-defects in the wafer under test and the specification parameters of the test structure formed on the wafer under test; determining whether the detection voltage (e.g., the second voltage) with the smallest absolute value when the gate structure undergoes complete tunneling is within the ideal detection voltage range; if so, the number of bulk micro-defects of the wafer under test is qualified; if not, the number of bulk micro-defects of the wafer under test is unqualified. It should be understood that for high-quality (qualified) wafers, the number of bulk micro-defects (especially the number of bulk micro-defects inside the wafer) needs to be precisely controlled within a preset specification range. Too many or too few bulk micro-defects will have an adverse effect on the quality of the wafer. In this application, the interface between the trench isolation structure and the wafer under test is used as part of the channel between the drain region and the source region, so that the channel extends into the interior of the wafer under test, thereby confirming the number of bulk micro-defects in the wafer under test through the electrical parameters inside the wafer under test. Compared to using only the electrical parameters of the wafer surface (the channel is only located on the wafer surface) to detect the number of bulk micro-defects in the wafer (actually on the wafer surface), this application can detect the number of bulk micro-defects inside the wafer to be tested, thereby improving the effectiveness and accuracy of the detection.

[0042] In addition to the number of bulk micro-defects, the variables affecting the second voltage (first voltage) mainly include the trench isolation structure and the gate oxide layer. The longer the trench, for example, the greater the width and depth of the trench isolation structure, the larger the first and second voltages will be. The thicker the gate oxide layer, the larger the first and second voltages will also be. Therefore, in some examples, the above-mentioned electrical tests can be performed on a wafer with a determined number of bulk micro-defects to obtain the relationship between the parameters of the bulk micro-defects, the above-mentioned test structure (e.g., trench isolation structure and gate oxide layer), and the second voltage. Then, using the above relationship, the ideal detection voltage range corresponding to the bulk micro-defects of the wafer under test being qualified (within the preset specification range) can be determined from the preset specification range of the bulk micro-defects in the wafer under test and the parameters of the formed test structure.

[0043] Figure 6 This is a flowchart illustrating a semiconductor testing method provided in an embodiment of this application. Figure 6 As shown, after a batch of incoming wafers is fed into the production line, but before the batch of incoming wafers is put into formal production, at least one wafer can be sampled from the batch of incoming wafers as a wafer to be tested. The above-mentioned test structure is formed in the test area of ​​the wafer to be tested, and the above-mentioned electrical test is performed to determine whether the bulk micro-defects of the wafer to be tested are qualified. If yes, the batch of incoming wafers is put into formal production (offline production). If no, the batch of incoming wafers is stopped from being put into formal production, and the batch of incoming wafers is returned for re-feeding.

[0044] In summary, this application provides a semiconductor testing structure and method. The semiconductor testing structure includes a drain region, a source region, and a trench isolation structure, all located within the wafer to be tested. The trench isolation structure is located between the drain region and the source region to isolate them. The source region includes at least one first interdigit, and the drain region includes at least one second interdigit. The first interdigit and the second interdigit intersect each other, so that the first interdigit has an effective portion overlapping with the second interdigit. A gate structure is located on the source region, and the gate structure extends at least along the boundary line between the effective portion and the trench isolation structure. An unexpected effect of this application is that after forming the semiconductor testing structure on the wafer to be tested, electrical testing can quickly determine whether the number of bulk micro-defects on the wafer is acceptable. This allows integrated circuit manufacturers to independently, timely, accurately, and non-destructively detect the number of bulk micro-defects in the wafer, avoiding significant yield losses caused by wafers with abnormal bulk micro-defects being put into normal production. Moreover, the channel in the aforementioned semiconductor testing structure includes the interface between the trench isolation structure and the wafer, that is, the channel extends into the interior of the wafer to be tested. This allows the number of bulk micro-defects inside the wafer to be tested to be confirmed by the electrical parameters inside the wafer, thereby improving the effectiveness and accuracy of bulk micro-defect detection.

[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0046] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0047] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0048] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor test structure formed on a wafer to be tested, characterized in that, The semiconductor test structure is used to detect the number of bulk micro-defects inside the wafer under test, including: The drain region, source region, and trench isolation structure are all located within the wafer to be tested. The trench isolation structure is located between the drain region and the source region to isolate the drain region and the source region. The source region includes at least one first interdigitated finger, and the drain region includes at least one second interdigitated finger. The first interdigitated finger and the second interdigitated finger interpenetrate each other so that the first interdigitated finger has an effective portion overlapping with the second interdigitated finger. A gate structure is located on the source region, and the gate structure extends at least along the boundary line between the effective portion and the trench isolation structure.

2. The semiconductor test structure according to claim 1, characterized in that, The gate structure extends along the boundary line between the source region and the trench isolation structure.

3. The semiconductor test structure according to claim 1 or 2, characterized in that, The source region is a closed ring, and a portion of the inner ring surface of the source region protrudes towards the center of the source region to form the first interdigitated finger. The drain region is located within the inner ring surface of the source region.

4. The semiconductor test structure according to claim 1, characterized in that, The width of the groove isolation structure between the overlapping portions of the first interdigitated finger and the second interdigitated finger is less than the width outside the overlapping portion of the first interdigitated finger and the second interdigitated finger.

5. The semiconductor test structure according to claim 1, characterized in that, The edge of the leak area is in direct contact with the edge of the trench isolation structure or has a gap; and / or, The edge of the source region is in direct contact with or has a gap with the trench isolation structure.

6. The semiconductor test structure according to claim 1, characterized in that, The wafer under test is of P-type conductivity, the drain region and the source region are of N-type conductivity, the drain region is located in the N-type well region of the wafer under test, and the source region is located in the first P-type well region of the wafer under test.

7. The semiconductor test structure according to claim 6, characterized in that, The depths of the first P-type well region and the N-type well region are greater than the depth of the trench isolation structure.

8. A semiconductor testing method, characterized in that, include: A semiconductor test structure as described in any one of claims 1 to 7 is formed on the wafer to be tested; The source region of the semiconductor test structure is grounded, and a detection voltage is applied to the drain region of the semiconductor test structure. The detection voltage is gradually increased while the current change in the gate structure is detected simultaneously until the gate structure undergoes complete tunneling. Based on the detection voltage corresponding to when the gate structure is completely tunneled, it is determined whether the bulk micro-defects of the wafer to be tested are qualified.

9. The semiconductor testing method according to claim 8, characterized in that, After a batch of incoming wafers arrives but before formal production begins, at least one wafer is sampled from that batch as the wafer to be tested; and... If the micro-defects of the wafer under test are deemed acceptable, the batch of incoming wafers will be put into formal production. If the micro-defects of the wafer under test are deemed unacceptable, the batch of incoming wafers will be stopped from being put into formal production.

10. The semiconductor testing method according to claim 8, characterized in that, The method for determining whether the bulk micro-defects of the wafer to be inspected are acceptable further includes: Based on the preset specification range of the bulk micro-defects in the wafer to be tested and the specification parameters of the semiconductor test structure, determine the ideal detection voltage range corresponding to when the gate structure is completely tunneled. If the detection voltage corresponding to the complete tunneling of the gate structure is within the ideal detection voltage range, the wafer to be tested is deemed qualified; otherwise, the wafer to be tested is deemed unqualified.

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