System and method for generating inference information on modifiable models on a storage device

Abstract

A system and related method includes a memory and processing circuitry that receives a plurality of weights from a host device to implement instantiation of a model on the memory device. The instantiation of the model includes a plurality of weights, and each weight is determined using another instantiation of the model trained on the host device. The processing circuitry then generates inference information using instantiation of the model implemented on the storage device. The processing circuitry further receives the plurality of updated weights from the host device and updates the instantiation of the model based on the plurality of updated weights to implement an updated instantiation of the model on the storage device. The processing circuitry then generates updated inference information on the storage device using update instantiation of the model based on the at least one signal to be processed by the processing circuitry.

Description

Technical Field

[0001] This disclosure relates to systems and methods for generating inferred information using a model on a storage device based on at least one signal received by a host system. Summary of the Invention

[0002] According to this disclosure, systems and methods are provided for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) based on at least one signal to be processed using a modifiable instantiation of a model. The systems and methods disclosed herein enable a model instantiation on a host (e.g., a first instantiation of the model) to be trained by the host without communicating with the storage device, and then updated with an instantiation of the model implemented on the storage device (e.g., a second instantiation of the model). This allows the first instantiation of the model to be trained by a centralized host while at least one storage device is using the implemented instantiation of the model (e.g., the second instantiation of the model), which can be updated at any time by receiving updated data. When the storage device receives a signal to be processed, the storage device generates inference information based on the received at least one signal, using the model instantiation on the storage device. The systems and methods disclosed herein use a modifiable instantiation of the model on the storage device so that a centralized host can maintain the instantiation of the trained model and then distribute updated weights to at least one storage device to implement the updated instantiation on the storage device. The system and method disclosed in this paper offload the task of instantiating the training model from each storage device. This allows each storage device to focus on the execution of operations, rather than the training of firmware or the system, which would require a minimal amount of bandwidth and power from each storage device. This improves the overall access efficiency and power consumption of the processing circuitry of storage devices (e.g., solid-state drive devices).

[0003] In some embodiments, the system (e.g., a storage device) is provided with memory and processing circuitry communicatively coupled to each other. In some embodiments, the system may be distributed between the storage device and another device separate from the storage device (e.g., a host, such as a storage controller device), such that the host provides control circuitry to implement at least some of the functions described herein. In some embodiments, the processing circuitry receives updated weights from the host device. In some embodiments, the processing circuitry updates the instantiation of the model on the storage device based on the updated weights to implement an updated instantiation of the model on the storage device. The processing circuitry then generates inference information on the storage device based on at least one signal to be processed using the updated instantiation of the model. Attached Figure Description

[0004] The following description includes a discussion of the figures, illustrating examples of implementations of embodiments of this disclosure. The figures should be understood by way of example and not by way of limitation. As used herein, references to one or more “embodiments” are to be understood as describing a particular feature, structure, and / or characteristic included in at least one implementation. Therefore, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0005] Figure 1 A schematic diagram of a system including a host device and a storage device having processing circuitry and memory, according to some embodiments of the present disclosure, is shown. Figure 2 A schematic diagram of a system including a host device communicating with multiple storage devices is shown according to some embodiments of the present disclosure; Figure 3 A schematic diagram of a host device instantiated with a training model according to some embodiments of the present disclosure is shown; Figure 4 A flowchart illustrating illustrative steps of instantiating a model on a storage device and updating the model instantiation on the storage device based on at least one signal, according to some embodiments of the present disclosure, is shown; and Figure 5 Some embodiments of the present disclosure are shown for use as follows Figure 4 The flowchart illustrates the steps of the sub-process of instantiating a model implemented on a storage device to generate inferred information on the storage device. Detailed Implementation

[0006] According to this disclosure, a system and method are provided for generating inference information on a storage device (e.g., a solid-state drive (SSD) device) based on at least one signal to be processed, using a modifiable instantiation of a model (e.g., a neural network, a machine learning neural network, or any other suitable neural network with a training / learning framework). The SSD device can implement a model to aid instruction execution, wherein the model is trained on the SSD device, and wherein operations processed by the SSD are used as training data. However, if the SSD's processing circuitry undertakes the task of training the model, the processing circuitry has limited available bandwidth to process instructions and execute operations (e.g., reads and writes). Furthermore, in systems with more than one storage device, each storage device trains an instantiation of its corresponding model. In such systems, each SSD training its own instantiation of its corresponding model degrades the system's limited bandwidth. This results in inefficiency in the processing circuitry of each storage device.

[0007] If the processing circuitry of an SSD device can offload the training of model instantiation to another device (e.g., a host), the available bandwidth of each storage device is improved. To improve the efficiency of the SSD device, the processing circuitry can instantiate the model based on the instantiation of the model trained on the host device in order to process the received signals. Therefore, the host's task is to train the model instantiation and then send updated data (e.g., updated weights of the model) to update the model instantiation on the storage device.

[0008] The processing circuitry generates inference information on the storage device by instantiating a model implemented on the storage device. Each instantiation of the model includes multiple weights, each of which is determined using another instantiation of the model trained on a host coupled to the storage device. At some point after the model is instantiated on the storage device, the processing circuitry can receive multiple updated weights from the host. Once the processing circuitry receives the multiple updated weights, it implements an updated instantiation of the model on the storage device based on these updated weights. When the processing circuitry receives a signal to be processed, it uses the updated instantiation of the model, at least based on the received signal to be processed, to generate updated inference information on the storage device. In some embodiments, the processing circuitry can continuously update the instantiation of the model on the storage device by receiving further updated weights from the host.

[0009] In some embodiments, the memory of the system disclosed herein may include any of the following memory densities: single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), five-level cell (PLC), and any suitable memory density with more than five bits per memory cell.

[0010] For the purposes of brevity and clarity, the features of the disclosure described herein are in the context of a storage device having processing circuitry and memory. However, the principles of this disclosure can be applied to any other suitable context in which inferred information is generated on the storage device using a modifiable instantiation of a model based on at least one signal to be processed. The storage device may include processing circuitry and memory, and the processing circuitry and memory are communicatively coupled via a network bus or interface. In some embodiments, the processing circuitry receives data (e.g., updated weights) signaled to be updated, which may be driven from a source (e.g., a host) outside the storage device on the network bus or interface, or may be transferred from within the storage device (e.g., from memory).

[0011] In some embodiments, the processor of the processing circuit can be a highly parallelized processor capable of rapidly processing high-bandwidth incoming data. For example, the processing circuit can initiate the generation of inference information for the signal to be processed before completing the generation of inference information for the previously received signal to be processed.

[0012] In some embodiments, the systems and methods disclosed herein may refer to a storage device system (e.g., an SSD storage system) that includes a storage device such as a solid-state drive device that is communicatively coupled to processing circuitry via a network bus or interface.

[0013] An SSD is a data storage device that uses integrated circuit components as memory to permanently store data. SSDs have no moving mechanical parts, a feature that distinguishes them from traditional electromechanical disks, such as hard disk drives (HDDs) or floppy disks, which contain spinning disks and removable read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shocks, operate quietly, have lower access times, and less latency.

[0014] Many types of SSDs use NAND-based flash memory, which retains data without power, and include non-volatile storage technology types. The Quality of Service (QoS) of an SSD can be related to the predictability of low latency and the consistency of high input / output operations per second (IOPS) when serving read / write input / output (I / O) workloads. This means that latency or I / O command completion times need to be within specified ranges without unexpected outliers. Throughput or I / O rates may also need to be tightly tuned to avoid sudden drops in performance levels.

[0015] refer to Figure 1-5 This will allow for a better understanding of the subject matter of this disclosure.

[0016] Figure 1 A schematic diagram of a system 100 according to some embodiments of the present disclosure is shown. The system 100 includes a host device (e.g., host 108) and a storage device 102 having processing circuitry 104 and memory 106. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive (SSD) device). In some embodiments, the processing circuitry 104 may include a processor or any suitable processing unit. In some embodiments, the memory 106 may be non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, in addition to or instead of an SSD, the storage device 102 may include a hard disk drive (HDD) device. In some embodiments, the system 100 includes a host 108 communicating with the storage device 102.

[0017] Host 108 includes a first instantiation of model 112, which may be implemented on the control circuitry of host 108. In some embodiments, the control circuitry trains the first instantiation of model 112 using analog signals. The first instantiation of model 112 is used to determine weights (e.g., updated weights 110) based on training by host 108. Each weight of the model contributes to decision-making regarding outcomes or results determined based on inputs (e.g., received signals to be processed). Once processing circuitry 104 receives weights from host 108, it implements a second instantiation of model 114 on storage device 102. Processing circuitry 104 then generates inference information on the storage device using the second instantiation of model 114 based on at least one signal to be processed. The second instantiation of model 114 may be updated when processing circuitry 104 receives updated weights 110 from host 108. In some embodiments, the second instantiation of model 114 may be updated at any time by receiving updated data (e.g., updated weights 110) via any suitable firmware update request.

[0018] In some embodiments, processing circuitry 104 is configured to generate inference information on storage device 102 using a second instantiation of model 114 implemented on storage device 102. In some embodiments, the second instantiation of model 114 is implemented based on weights received from host 108, which determines the weights by training a first instantiation of model 112. Processing circuitry further receives multiple updated weights from host 108 and then updates the second instantiation of model 114 based on these updated weights to implement the updated instantiation on storage device 102. Once the second instantiation of model 114 is updated to the updated instantiation of the model, processing circuitry 104 then uses the updated instantiation of the model to determine updated inference information on storage device 102 based on at least one signal to be processed. In some embodiments, the garbage collection request includes a destination memory address corresponding to potentially invalid or expired destination data. In some embodiments, the garbage collection request and weights (e.g., updated weights 110) are transmitted to processing circuitry 104 on a network bus or interface. In some embodiments, the garbage collection request and weights (e.g., updated weights 110) are transmitted from an external source (e.g., host 108). In some embodiments, the processing circuit 104 receives signals from both internal and external sources of the storage device 102 (e.g., garbage collection requests and updated weights 110). A temporary memory (e.g., a cache or queue) may also be present within the processing circuit 104, configured to store any unfinished requests to be processed by the processing circuit 104.

[0019] Additionally, storage device 102 includes memory 106. In some embodiments, memory 106 includes any one or more non-volatile memories such as phase-change memory (PCM), PCM and switching (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), memristor, spin-transfer torque random access memory (STT-RAM) and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, memory 106 may include volatile memory in the form of a cache. In some embodiments, memory 106 may include any one of single-cell (SLC) memory, multi-cell (MLC) memory, three-cell (TLC) memory, four-cell (QLC) memory, five-cell (PLC) memory, or any other suitable memory having a memory density greater than 5 bits per memory cell. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data for executing signals / requests. In some embodiments, a data bus between memory 106 and processing circuitry 104 provides a network bus for accessing memory 106 or writing data to memory 106. In some embodiments, the processor or processing unit of processing circuitry 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor (also referred to herein as processing circuitry 104) may include any suitable software, hardware, or both for controlling memory 106 and processing circuitry 104. In some embodiments, storage device 102 may further include a multi-core processor. Memory 106 may also include hardware elements for non-transitory storage of instructions, commands, or requests.

[0020] Processing circuitry 104 is configured to generate inference information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed, wherein the instantiation of the model is implemented on the storage device using weights received from a host device, and another instantiation of the model has already been trained on the host device. Furthermore, processing circuitry 104 can receive updated weights 110 from host 108. The updated weights 110 are determined using a first instantiation of model 112 trained on host 108. The updated weights 110 are used to implement a second instantiation of model 114 on storage device 102. Each weight of the model contributes to decision-making regarding the outcome or result determined based on the input (e.g., the received signal to be processed). Once processing circuitry 104 receives the updated weights 110 from host 108, it updates the second instantiation of model 114 on storage device 102. Processing circuitry 104 then generates updated inference information on the storage device using the updated second instantiation of the model based on at least one signal to be processed. These processes enable the instantiation of a model on host 108 (e.g., the first instantiation of model 112) to be trained by host 108 without communicating with storage device 102, and then the instantiation of the model implemented on storage device 102 (e.g., the second instantiation of model 114) to be updated. This allows the instantiation of the model to be trained by centralized host 108 while at least one storage device (e.g., storage device 102) is using the implemented instantiation of the model (e.g., the second instantiation of model 114), which can be updated at any time by receiving updated data (e.g., updated weights 110) via any suitable firmware update request.

[0021] Storage devices (e.g., SSD devices) may include one or more memory die packages (e.g., including memory 106), wherein each die includes a storage cell. In some embodiments, storage cells are organized into pages, and pages are organized into blocks. Each storage cell may store one or more bits of information.

[0022] It will be understood that although system 100 depicts an embodiment according to this disclosure in which storage device 102 is configured to have the ability to generate inferred information on the storage device based on a modifiable instantiation of a model using at least one signal to be processed, any other suitable device may be implemented in a similar manner.

[0023] For the purposes of clarity and brevity, and not by way of limitation, this disclosure is provided in the context of generating inferred information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed, which provides the features and functions disclosed herein. The process of generating inferred information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed can be configured by any suitable software, hardware, or both for implementing such features and functions. The generation of inferred information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed can be implemented at least partially in, for example, storage device 102 (e.g., as part of processing circuitry 104, or any other suitable device). For example, for a solid-state storage device (e.g., storage device 102), the generation of inferred information on a storage device using a modifiable instantiation of a model based on at least one signal to be processed can be implemented in processing circuitry 104.

[0024] Figure 2 A schematic diagram of a system 200 comprising a host device 108 communicating with a plurality of storage devices (e.g., storage device_1202, storage device_2204, storage device_3206 and storage device_N208) is shown according to some embodiments of the present disclosure.

[0025] Host 108 includes a first instantiation of model 112, which can be implemented on and trained by the control circuitry of host 108. Host 108 is communicatively coupled to each of the storage devices (e.g., 202, 204, 206, and 208) via a network interface or data bus. Each corresponding storage device (e.g., 202, 204, 206, and 208) has a corresponding instantiation of the model implemented on the corresponding storage device (e.g., a second instantiation of model 203, a third instantiation of model 205, a fourth instantiation of model 207, and an Nth instantiation of model 209). Host 108 is configured to train the first instantiation of model 112 to determine updated weights 110, which are sent to each of the storage devices (e.g., storage device_1 202, storage device_2 204, storage device_3, and storage device_N 208) via a network interface or data bus. Once the corresponding storage device receives the updated weight 110 from the host 108, the corresponding storage device 102 updates the corresponding instantiation of the model using the updated weight 110. This system 200 enables a distributed system with multiple storage devices to have model instantiation, where model instantiation can be updated simultaneously.

[0026] Figure 3A schematic diagram of a host 108 for training model instantiation (e.g., a first instantiation of model 112) according to some embodiments of the present disclosure is shown. Host 108 includes control circuitry 302, a first instantiation of model 112 implemented on control circuitry 302, and a training module 304. Training module 304 is configured to send an analog signal 306 to the first instantiation of model 112 to train the first instantiation of model 112. The first instantiation of model 112 generates a training result 308 based on the analog signal 306 and sends the training result 308 to training module 304. In some embodiments, training module 304 further compares the expected training result corresponding to the analog signal 306 with the training result 308 generated by the first instantiation of model 112. The weights of the first instantiation of model 112 can be adjusted based on the comparison between the training result 308 and the expected training result corresponding to the analog signal 306. In some embodiments, the comparison between the training result 308 and the expected training result can also be used to determine the effectiveness of the first instantiation of model 112 and whether the first instantiation of the model needs further training.

[0027] At any time, the control circuitry 302 of host 108 can send updated weights 310 to storage device 102. In some embodiments, processing circuitry 104 receives the updated weights 310 and uses them to implement a second instantiation of model 114. In some embodiments, the updated weights 310 are sent to storage device 102 via a data bus or network interface that is communicatively coupled from host 108 to storage device 102. In some embodiments, a first instantiation of model 112 is trained by control circuitry 302 without communicating with storage device 102, and then the instantiation of the model implemented on storage device 102 (e.g., the second instantiation of model 114) is updated.

[0028] Figure 4 A flowchart 400 illustrates illustrative steps according to some embodiments of the present disclosure for generating inference information on a storage device based on the instantiation of a model using at least one signal and updating the instantiation of the model on the storage device. In some embodiments, the referenced storage device, processing circuitry, memory, host, updated weights, first instantiation of the model, second instantiation of the model, control circuitry, training module, and analog signal may be implemented as storage device 102, processing circuitry 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, second instantiation of the model 114, control circuitry 302, training module 304, and analog signal 306, respectively. In some embodiments, process 400 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0029] At step 402, the processing circuitry uses an instantiation of a model implemented on the storage device to generate inference information on the storage device, wherein the instantiation of the model includes multiple weights, each of which is determined using another instantiation of a model trained on a host device coupled to the storage device. In some embodiments, the processing circuitry implements an instantiation of the model on the storage device (e.g., a second instantiation of the model) using multiple weights received from the host. In some embodiments, the host includes control circuitry to train another instantiation of the model (e.g., a first instantiation of the model) using an analog signal similar to the expected signal that the processing circuitry will receive and process. Furthermore, the host's control circuitry may include a training module to create an analog signal and send it to the other instantiation of the model (e.g., the first instantiation of the model), and then compare the expected result of the analog signal with a test result received from the other instantiation of the model (e.g., the first instantiation of the model). In some embodiments, when the host is not communicatively coupled to the storage device, the host trains the other instantiation of the model based on the analog signal. Weights are determined by the host and sent to the processing circuitry of the storage device to implement the instantiation of the model (e.g., a second instantiation of the model). In some embodiments, the processing circuitry generates inference information based on at least one signal received by the processing circuitry, using an instantiation of the model's implementation. In some embodiments, the generated inference information includes a prediction operation performed by the processing circuitry based on at least one received signal. In some embodiments, the prediction operation may be any one of a workload detection operation, a hot operation, a storage device optimization operation, or a storage device arbitration operation. Once inference information is generated on the storage device, at step 404, the processing circuitry can receive multiple updated weights from the host device.

[0030] At step 404, the processing circuitry receives multiple updated weights from the host device at the storage device. In some embodiments, the processing circuitry receives the multiple updated weights from a firmware update request sent from the host. In some embodiments, the processing circuitry receives the updated weights from a network interface or data bus that communicatively couples the storage device to the host. At step 406, when the processing circuitry of the storage device receives the multiple updated weights from the host device, the processing circuitry then updates the instantiation of the model based on the multiple updated weights to implement updated instantiation of the model on the storage device.

[0031] At step 406, the processing circuitry updates the model instantiation based on multiple updated weights to implement the updated instantiation of the model on the storage device. In some embodiments, the number of updated weights may be the same as the number of weights in the original instantiation of the model implemented on the storage device. At step 408, once the updated instantiation of the model is implemented on the storage device, the processing circuitry uses the updated instantiation of the model to generate updated interference information on the storage device based on at least one signal to be processed.

[0032] At step 408, the processing circuit generates updated inference information on the storage device using the updated model instantiation based on at least one signal to be processed. In some embodiments, the generated updated inference information is a prediction operation performed by the processing circuit based on at least one signal. In some embodiments, given the same signal received by the processing circuit, the updated inference information generated using the updated model instantiation may differ from the inference information generated using a previous version of the instantiation. In some embodiments, the updated model instantiation may be updated when the processing circuit receives any other updated weights from the host.

[0033] Figure 5 The instantiation of a model implemented on a storage device according to some embodiments of this disclosure is illustrated (e.g., as shown in the example). Figure 4 The flowchart illustrates the steps of the subprocess 500 that generates inferred information on a storage device (shown at 402). In some embodiments, the referenced storage device, processing circuitry, memory, host, updated weights, first instantiation of the model, and second instantiation of the model may be implemented as storage device 102, processing circuitry 104, memory 106, host 108, updated weights 110, first instantiation of the model 112, and second instantiation of the model 114, respectively. In some embodiments, subprocess 500 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0034] At step 502, the processing circuitry determines a running average from at least one signal to be processed and generates inference information based on the determined running average. In some embodiments, the running average may be determined based on a predetermined number of signals received by the processing circuitry. For example, instantiation of a model implemented on a storage device may be used to generate inference information for workload detection. In such an example, the processing circuitry of the storage device may receive signals such as instructions or operations to be processed by the processing circuitry and then predict the expected instructions or operations based on the running average of previously received signals. In some embodiments, the running average is continuously adjusted based on the most recently received signals at the storage device.

[0035] The terms “an embodiment,” “an embodiment,” “multiple embodiments,” “the embodiment,” “the multiple embodiments,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments”, unless otherwise expressly stated.

[0036] The terms “including,” “comprise,” “have,” and their variations mean “including but not limited to,” unless otherwise expressly stated.

[0037] The list of items does not imply that any or all items are mutually exclusive, unless otherwise expressly stated.

[0038] The terms “a,” “an,” and “the” mean “one or more” unless otherwise explicitly stated.

[0039] Devices that communicate with each other do not need to communicate continuously unless otherwise explicitly stated. Furthermore, devices that communicate with each other may communicate directly or indirectly through one or more intermediaries.

[0040] The description of an embodiment having several interconnected components does not imply that all such components are required. Instead, a variety of optional components are described to illustrate a wide range of possible embodiments. Furthermore, although process steps, method steps, algorithms, etc., may be described in sequential order, such processes, methods, and algorithms can be configured to operate in an alternative order. In other words, any order or sequence of steps that may be described does not necessarily indicate that the steps must be performed in that order. The steps of the process described herein can be performed in any actual order. Moreover, some steps may be performed simultaneously.

[0041] When a single device or item is described herein, it will be apparent that more than one device / item (whether or not they cooperate) may be used in place of the single device / item. Similarly, when more than one device or item is described herein (whether or not they cooperate), it will be apparent that a single device / item may be used in place of more than one device or item, or that a different number of devices / items may be used in place of the number of devices or programs shown. The functionality and / or features of a device are alternatively embodied by one or more other devices that are not explicitly described as having such functionality / features. Therefore, other embodiments do not need to include the device itself.

[0042] The diagrams may have illustrated at least some of the operations, showing events occurring in a certain order. In alternative embodiments, some operations may be performed, modified, or removed in a different order. Furthermore, steps may be added to the logic described above, and these steps still conform to the described embodiments. Additionally, the operations described herein may occur sequentially, or some operations may be processed in parallel. Moreover, the operations may be performed by a single processing unit or by distributed processing units.

[0043] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in accordance with the above teachings.

Claims

1. A method for processing at least one signal on a storage device, the method comprising: Inference information is generated on the storage device using an instantiation of a model implemented on the storage device, the instantiation of the model including multiple weights, wherein the multiple weights are determined using another instantiation of a model trained on a host device coupled to the storage device; Receive multiple updated weights from the host device at the storage device; The instantiation of the model is updated based on the multiple updated weights to achieve the updated instantiation of the model; and Based on the at least one signal, updated inference information is generated on the storage device using the updated instantiation of the model.

2. The method according to claim 1, wherein, When the host device is not communicatively coupled to the storage device, other instantiations of the model are trained on the host device based on simulated data.

3. The method according to claim 2, wherein, The additional instantiated simulation data used to train the model is determined by the host device based on a subset of the expected signals to be processed by the instantiation of the model on the storage device.

4. The method according to claim 1, wherein, Inference information includes prediction operations from multiple operations.

5. The method according to claim 4, wherein, The plurality of operations include any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) device power optimization operation, or (d) device bandwidth arbitration operation.

6. The method according to claim 1, wherein, Using the instantiation of the model to generate inference information on the storage device includes: Determining the operating average from the at least one signal, wherein generating inference information includes generating inference information based on the operating average.

7. A storage device, comprising: Memory; and The processing circuit is used to: Multiple weights are received from a host device to instantiate a model on the storage device, wherein the instantiation of the model includes multiple weights, each of which is determined using another instantiation of the model trained on the host device. Inference information is generated using an instantiation of the model implemented on the storage device. Receive multiple updated weights from the host device. The instantiation of the model is updated based on the multiple updated weights to achieve the updated instantiation of the model, and Based on at least one signal to be processed, updated inference information is generated on the storage device using the updated instantiation of the model.

8. The storage device according to claim 7, wherein, When the host device is not communicatively coupled to the storage device, other instantiations of the model are trained on the host device based on simulated data.

9. The storage device according to claim 8, wherein, The additional instantiated simulation data used to train the model is determined by the host device based on a subset of the expected signals to be processed by the instantiation of the model on the storage device.

10. The storage device according to claim 7, wherein, Inference information includes prediction operations from multiple operations.

11. The storage device according to claim 10, wherein, The plurality of operations include any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) device power optimization operation, or (d) device bandwidth arbitration operation.

12. The storage device according to claim 7, wherein, In order to generate inference information on the storage device using the instantiation of the model, the processing circuitry is used to: Determining the operating average from the at least one signal, wherein generating inference information includes generating inference information based on the operating average.

13. A system comprising: The host includes: The control circuit coupled to the communication bus is used to: The first instantiation of the trained model provides inference output, and this first instantiation includes multiple weights. The multiple weights are communicated to the storage device using a communication bus, and The communication bus is used to transmit multiple updated weights to the storage device, and A storage device coupled to the communication bus, the storage device comprising: Memory; and The processing circuit is used to: Receive multiple weights, The second instantiation of the model is implemented on the storage device based on the multiple weights. Based on at least one signal to be processed, inference information is generated using a second instantiation of the model. Receive multiple updated weights from the host. The second instantiation of the model is updated based on the multiple updated weights to achieve the updated second instantiation of the model, and The updated second instantiation of the model is used to generate updated inference information.

14. The system according to claim 13, wherein, The first instantiation of a trained model is performed on the host when the host is not communicatively coupled to the storage device.

15. The system according to claim 14, wherein, The first instantiation of the simulated data used to train the trained model is determined by the control circuit based on a subset of the expected signals to be processed by the second instantiation of the model.

16. The system according to claim 14, wherein, The control circuit is further used to: The simulation data is passed to the first instantiation of the model. Receive training results from the first instantiation of the model. In response to a comparison of the training results with the expected training results corresponding to the simulated data, modified simulated data is determined, and Transmit the modified simulation data.

17. The system according to claim 13, wherein, Inference information includes prediction operations from multiple operations.

18. The system according to claim 17, wherein, The plurality of operations include any one or more of the following: (a) workload detection operation, (b) thermal arbitration operation, (c) power optimization operation, or (d) bandwidth arbitration operation.

19. The system according to claim 13, wherein, In order to generate inference information using the instantiation of the trained model, the processing circuitry is used to: Determining the operating average from the at least one signal, wherein generating inference information includes generating inference information based on the operating average.

20. The system of claim 13, further comprising a plurality of storage devices, wherein, The storage device is one of the plurality of storage devices, and each storage device is coupled to the host via the communication bus.

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