Driving circuit, driving method, driving module and display device

Abstract

The invention discloses a driving circuit, a driving method, a driving module and a display device. The drive circuit comprises a carry output circuit (10) and a drive reset circuit (11). The driving reset circuit (11) controls the connection or disconnection between the nth-stage driving output end (Gn) and the first voltage end (V1) under the control of a driving control signal (GD); the carry output circuit (10) controls connection or disconnection between an output clock signal end (CLK) and an nth-level carry output end (OCn) under the control of the potential of a first node (PU); n is a positive integer; the drive control end (GD) is an (n-j) th-level carry output end or an (n-j) th-level output clock signal end, and j is an integer greater than or equal to 1. According to the circuit, the driving reset circuit is additionally arranged, pre-charging of the nth-stage driving output end is removed, that is, pre-charging of pixels is removed, and the purpose of removing pre-charging of all the pixels is achieved.

Description

Drive circuit, drive method, drive module and display device

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving method, driving module and display device.

[0002] In related technologies, Z-architecture Single Gate or Dual Gate display products exhibit a situation where some pixels are pre-charged while others are not in mixed-color scenes. This charging difference leads to defects such as horizontal or vertical stripes or color variations in the mixed-color image, known as Fine Pitch defects. Currently, there are two main directions for improvement regarding Fine Pitch defects: First, increasing the charging rate. However, when the display product size is large and the refresh rate is high, the improvement in the charging rate is limited and cannot completely improve Fine Pitch. Second, eliminating pixel pre-charging. Related technologies eliminate pixel pre-charging by removing clock signal pre-charging, but this is not suitable for high refresh rate and high-resolution display products and has a significant impact on the reliability of the GOA (Gate On Array) circuit.

[0003]

[0004] In one aspect, embodiments of this disclosure provide a driving circuit, including a carry output circuit and a drive reset circuit;

[0005] The drive reset circuit is electrically connected to the drive control terminal, the nth stage drive output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the first voltage terminal under the control of the drive control signal provided by the drive control terminal.

[0006] The carry output circuit is electrically connected to the first node, the output clock signal terminal, and the nth level carry output terminal, and is used to control the connection or disconnection between the output clock signal terminal and the nth level carry output terminal under the control of the potential of the first node; n is a positive integer;

[0007] The drive control terminal is either the carry output terminal of the njth stage or the output clock signal terminal of the njth stage, where j is an integer greater than or equal to 1.

[0008] The driving circuit described in at least one embodiment of this disclosure further includes a driving output circuit;

[0009] The drive output circuit is electrically connected to the first node, the nth stage drive output terminal, and the output clock signal terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the first node.

[0010] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive output circuit is greater than or equal to 0.5 and less than or equal to 2.

[0011] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0012] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the nth stage drive output terminal; or...

[0013] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0014] The driving circuit described in at least one embodiment of this disclosure further includes a driving control circuit;

[0015] The drive control circuit is electrically connected to the output control node and the nth stage drive output terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the output control node.

[0016] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive control circuit is greater than or equal to 0.2 and less than or equal to 1.

[0017] The driving circuit described in at least one embodiment of this disclosure further includes a node control circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0018] The node control circuit is electrically connected to the first node, the second node, the output control node, the output clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the output control node and the second voltage terminal under the control of the potential of the second node.

[0019] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node included in the node control circuit is greater than or equal to 0.5 and less than or equal to 2.

[0020] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node in the node control circuit and the channel width-to-length ratio of the transistor in the drive control circuit is greater than or equal to 0.1 and less than or equal to 0.3.

[0021] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0022] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the output control node; or...

[0023] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0024] The driving circuit described in at least one embodiment of this disclosure further includes a node control circuit and a drive setting circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0025] The node control circuit is electrically connected to the first node, the output control node, and the output clock signal terminal, respectively, and is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node.

[0026] The drive setting circuit is electrically connected to the second node, the nth stage drive output terminal, and the third voltage terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the third voltage terminal under the control of the potential of the second node.

[0027] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0028] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the output control node; or...

[0029] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0030] In at least one embodiment of this disclosure, the drive reset circuit is disposed on the side of the carry output circuit away from the drive output circuit.

[0031] In at least one embodiment of this disclosure, the drive reset circuit is disposed on the side of the carry output circuit away from the transistor whose gate is electrically connected to the first node, which is included in the node control circuit.

[0032] The driving circuit described in at least one embodiment of this disclosure further includes a driving set circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0033] The drive setting circuit is electrically connected to the second node, the nth stage drive output terminal, and the fourth voltage terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the fourth voltage terminal under the control of the potential of the second node.

[0034] The driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit; the driving circuit includes a second node, or the driving circuit includes a first second node and a second second node;

[0035] The first node control circuit is electrically connected to the first node, the input terminal, the reset terminal, and the second node, respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal, the reset signal provided by the reset terminal, and the potential of the second node.

[0036] In at least one embodiment of this disclosure, the drive reset circuit includes a first transistor;

[0037] The gate of the first transistor is electrically connected to the drive control terminal, the first electrode of the first transistor is electrically connected to the nth drive output terminal, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0038] The carry-out circuit includes a second transistor;

[0039] The gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the output clock signal terminal, and the second terminal of the second transistor is electrically connected to the nth carry output terminal.

[0040] In at least one embodiment of this disclosure, the drive output circuit includes a third transistor;

[0041] The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the output clock signal terminal, and the second terminal of the third transistor is electrically connected to the nth stage drive output terminal.

[0042] In at least one embodiment of this disclosure, the drive control circuit includes a fourth transistor;

[0043] The gate of the fourth transistor is electrically connected to the output control node, the first terminal of the fourth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fourth transistor is electrically connected to the nth stage drive output terminal.

[0044] In at least one embodiment of this disclosure, the node control circuit includes a fifth transistor and a sixth transistor; the driving circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; or,

[0045] The node control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the driving circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the first second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; the gate of the seventh transistor is electrically connected to the second second node, the first terminal of the seventh transistor is electrically connected to the output control node, and the second terminal of the seventh transistor is electrically connected to the second voltage terminal.

[0046] In at least one embodiment of this disclosure, the node control circuit includes a fifth transistor, and the drive set circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a third voltage terminal; or...

[0047] The node control circuit includes a fifth transistor, and the drive setting circuit includes an eighth transistor and a ninth transistor; the drive circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the third voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal.

[0048] In at least one embodiment of this disclosure, the drive setting circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a fourth voltage terminal; or,

[0049] The drive setting circuit includes an eighth transistor and a ninth transistor; the drive circuit includes a first second node and a second second node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the fourth voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to the fourth voltage terminal.

[0050] In a second aspect, embodiments of this disclosure provide a driving method applied to a driving circuit as described above, the driving method comprising:

[0051] Under the control of the drive control signal, the drive reset circuit controls the connection or disconnection between the nth stage drive output terminal and the first voltage terminal;

[0052] The carry output circuit, under the control of the potential of the first node, controls whether the output clock signal terminal is connected or disconnected from the carry output terminal of the nth stage;

[0053] n is a positive integer.

[0054] In at least one embodiment of this disclosure, the display cycle includes a reset phase; the driving method includes:

[0055] During the reset phase, the drive reset circuit, under the control of the drive control signal, controls the connection between the nth stage drive output terminal and the first voltage terminal.

[0056] In at least one embodiment of this disclosure, the display cycle includes an output phase disposed after the reset phase, and the pixel circuit further includes a drive output circuit; the driving method includes:

[0057] During the output phase, the drive output circuit, under the control of the potential of the first node, controls the connection between the nth stage drive output terminal and the output clock signal terminal.

[0058] In a third aspect, embodiments of this disclosure provide a driving module including multiple levels of the aforementioned driving circuits.

[0059] The driving module described in at least one embodiment of this disclosure includes 2m clock signal lines; m is a positive integer; the driving circuit includes a carry output terminal, an input terminal, and a reset terminal;

[0060] The carry output terminal of the a-th stage driving circuit is electrically connected to the input terminal of the a+i-th stage driving circuit.

[0061] The reset terminal of the a-th stage driving circuit is electrically connected to the carry output terminal of the a+p-th stage driving circuit.

[0062] a is a positive integer; i is not equal to j; i, j and p are positive integers.

[0063] In a fourth aspect, embodiments of this disclosure provide a display device including the driving module described above.

[0064] Figure 1A is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0065] Figure 1B is a structural diagram of the relevant pixel module;

[0066] Figure 1C is a timing diagram of the pixel module shown in Figure 1B;

[0067] Figure 2 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0068] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0069] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0070] Figure 5 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0071] Figure 6 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0072] Figure 7 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0073] Figure 8 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0074] Figure 9 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0075] Figure 10 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0076] Figure 11 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0077] Figure 12 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0078] Figure 13 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0079] Figure 14 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0080] Figure 15 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0081] Figure 16 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0082] Figure 17 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0083] Figure 18 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0084] Figure 19 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0085] Figure 20 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 17;

[0086] Figure 21 is a timing diagram of the operation of the drive module according to at least one embodiment of the present disclosure;

[0087] Figure 22 is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 17) according to at least one embodiment of the present disclosure;

[0088] Figure 23A is a layout diagram of the gate metal layer in Figure 22;

[0089] Figure 23B is a layout diagram of the semiconductor layer in Figure 22;

[0090] Figure 23C is a layout diagram of the source and drain metal layers in Figure 22;

[0091] Figure 23D is a layout diagram of the conductive layer in Figure 22;

[0092] Figure 23E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 22;

[0093] Figure 23F is a stack-up diagram of the source / drain metal layer and the conductive layer in Figure 22.

[0094] Figure 24 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0095] Figure 25A is a layout diagram of a portion of the driving circuit according to at least one embodiment of the present disclosure;

[0096] Figure 25B is a layout diagram of the gate metal layer in Figure 25A;

[0097] Figure 25C is a layout diagram of the semiconductor layer in Figure 25A;

[0098] Figure 25D is a layout diagram of the source and drain metal layers in Figure 25A;

[0099] Figure 25E is a layout diagram of the conductive layer in Figure 25A;

[0100] Figure 25F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 25A;

[0101] Figure 25G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 25A;

[0102] Figure 26 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0103] Figure 27A is a layout diagram of a portion of the driving circuit according to at least one embodiment of the present disclosure;

[0104] Figure 27B is a layout diagram of the gate metal layer in Figure 27A;

[0105] Figure 27C is a layout diagram of the semiconductor layer in Figure 27A;

[0106] Figure 27D is a layout diagram of the source and drain metal layers in Figure 27A;

[0107] Figure 27E is a layout diagram of the conductive layer in Figure 27A;

[0108] Figure 27F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 27A;

[0109] Figure 27G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 27A;

[0110] Figure 28 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0111] Figure 29A is a layout diagram of a portion of the driving circuit according to at least one embodiment of the present disclosure;

[0112] Figure 29B is a layout diagram of the gate metal layer in Figure 29A;

[0113] Figure 29C is a layout diagram of the semiconductor layer in Figure 29A;

[0114] Figure 29D is a layout diagram of the source and drain metal layers in Figure 29A;

[0115] Figure 29E is a layout diagram of the conductive layer in Figure 29A;

[0116] Figure 29F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 29A;

[0117] Figure 29G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 29A;

[0118] Figure 30 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0119] Figure 31A is a layout diagram of a portion of the driving circuit according to at least one embodiment of the present disclosure;

[0120] Figure 31B is a layout diagram of the gate metal layer in Figure 31A;

[0121] Figure 31C is a layout diagram of the semiconductor layer in Figure 31A;

[0122] Figure 31D is a layout diagram of the source and drain metal layers in Figure 31A;

[0123] Figure 31E is a layout diagram of the conductive layer in Figure 31A;

[0124] Figure 31F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 31A;

[0125] Figure 31G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 31A;

[0126] Figure 32 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0127] Figure 33A is a layout diagram of a portion of the driving circuit according to at least one embodiment of the present disclosure;

[0128] Figure 33B is a layout diagram of the gate metal layer in Figure 33A;

[0129] Figure 33C is a layout diagram of the semiconductor layer in Figure 33A;

[0130] Figure 33D is a layout diagram of the source and drain metal layers in Figure 33A;

[0131] Figure 33E is a layout diagram of the conductive layer in Figure 33A;

[0132] Figure 33F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 33A;

[0133] Figure 33G is a stack-up diagram of the source / drain metal layer and the conductive layer in Figure 33A.

[0134] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0135] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0136] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0137] As shown in Figure 1A, the driving circuit described in this embodiment includes a carry output circuit 10 and a drive reset circuit 11;

[0138] The drive reset circuit 11 is electrically connected to the drive control terminal GD, the nth stage drive output terminal Gn and the first voltage terminal V1 respectively, and is used to control the connection or disconnection between the nth stage drive output terminal Gn and the first voltage terminal V1 under the control of the drive control signal provided by the drive control terminal GD.

[0139] The carry output circuit 10 is electrically connected to the first node PU, the output clock signal terminal CLK, and the nth carry output terminal OCn. It is used to control the connection or disconnection between the output clock signal terminal CLK and the nth carry output terminal OCn under the control of the potential of the first node PU; n is a positive integer.

[0140] The drive control terminal GD is the carry output terminal of the njth stage or the output clock signal terminal of the njth stage, where j is an integer greater than or equal to 1.

[0141] In at least one embodiment of this disclosure, the example is given with j equal to 1.

[0142] In related technologies, Z-architecture Single Gate or Dual Gate display products exhibit a situation where some pixels are pre-charged while others are not in mixed-color scenes. This charging difference leads to defects such as horizontal or vertical stripes or color variations in the mixed-color image, known as Fine Pitch defects. Currently, there are two main directions for improvement regarding Fine Pitch defects: First, increasing the charging rate. However, when the display product size is large and the refresh rate is high, the improvement in the charging rate is limited and cannot completely improve Fine Pitch. Second, eliminating pixel pre-charging. Related technologies eliminate pixel pre-charging by removing clock signal pre-charging, but this is not suitable for high refresh rate and high-resolution display products and has a significant impact on the reliability of the GOA (Gate On Array) circuit.

[0143] As shown in Figure 1B, taking a single-grid display product as an example, for instance, the grid line labeled G1 is the first row, the grid line labeled G2 is the second row, and so on, with the grid line labeled G6 being the sixth row.

[0144] For example, the data line labeled D1 is the first column, the data line labeled D2 is the second column, and so on, with the data line labeled D7 being the seventh column.

[0145] The row labeled Ga represents the a-th grid line, where a is a positive integer less than or equal to 6; the column labeled Db represents the b-th data line, where b is a positive integer less than or equal to 7; and the row labeled Pab represents the a-th pixel in the b-th column.

[0146] For example, the pixel labeled P11 is the first pixel in the first row and first column, the pixel labeled P12 is the first pixel in the second column, and so on, with the pixel labeled P16 being the first pixel in the sixth column.

[0147] For example, the pixel labeled P21 is the first pixel in the second row, the pixel labeled P22 is the second pixel in the second row, the pixel labeled P26 is the sixth pixel in the second row;

[0148] For example, the pixel labeled P31 is the first pixel in the third row, and the pixel labeled P32 is the second pixel in the third row.

[0149] The pixel labeled P41 is the first pixel in the fourth row, and the pixel labeled P42 is the second pixel in the fourth row.

[0150] The pixel labeled P51 is the first pixel in the fifth row, and the pixel labeled P52 is the second pixel in the fifth row.

[0151] The first column of pixels consists of red sub-pixels, the second column consists of green sub-pixels, and the third column consists of blue sub-pixels.

[0152] As shown in Figure 1C, if GB127 (a mixed grayscale image of green and blue 127) is displayed, at least one embodiment of the pixel module shown in Figure 1B has the following working timing: for example, the opening time of each row of gate lines is 3H, and the opening timing of adjacent gate lines overlaps by 1H, which is equivalent to a precharge of 2H. The data voltages on D2 are L127, L0, L127, L0. P32 is charged with L127 during the third row scan time H3. Since the data voltage of the previous row is L0, when G4 is turned on, the data signal of P32 needs to be charged from L0 to L127. That is, P32 is not precharged before actual charging. Due to the actual RC delay of the data voltage and the limitation of the pixel charging capacity, the pixel voltage cannot be charged to the target value within 1H charging time, so the pixel display is dark. The data voltages on D3 are L127, L127, L127, and L127 respectively. When the G5 grid line of P42 is open, since the data voltages of its first two rows are both L27, P42 has a 2-hour pre-charging time before actual charging, allowing the pixel voltage to reach the target value, and P42 displays normal brightness. Similarly, P12, P23, P32, P43, and P52 have no pre-charging and display a darker image, while P13, P22, P33, P42, and P53 have pre-charging and display normal brightness. This results in a display structure where odd-numbered rows of green pixels are darker and odd-numbered rows of blue pixels are normal, and even-numbered rows of green pixels are normal and even-numbered rows of blue pixels are darker. This leads to differences in brightness and color between odd and even rows, resulting in fine pitch.

[0153] In Figure 1C, L127 is the data voltage corresponding to grayscale 127, and L0 is the data voltage corresponding to grayscale 0.

[0154] At least one embodiment of this disclosure proposes a new driving circuit. By adding a driving reset circuit 11, the effective pulse width of the output terminal Gn of the nth stage driving stage is less than the effective pulse width of the clock signal. The pre-charging of the Gn terminal is removed, so that the charging time of the pixel rows in the display area tends to be consistent or has a small difference, thereby improving the poor fine pitch caused by the different pre-charging times of the pixels in the AA area.

[0155] Optionally, the first voltage terminal can be a first low voltage terminal or a second low voltage terminal.

[0156] In at least one embodiment of this disclosure, the voltage value of the second low voltage signal provided by the second low voltage terminal may be less than the voltage value of the first low voltage signal provided by the first low voltage terminal;

[0157] When the voltage corresponding to the leakage current of the transistor whose gate in the pixel is electrically connected to the nth driving output terminal is high, the first voltage terminal can be the first low voltage terminal.

[0158] When the voltage corresponding to the leakage current of the transistor whose gate in the pixel is electrically connected to the nth stage drive output terminal is low, the first voltage terminal can be the second low voltage terminal.

[0159] At least one embodiment of the drive circuit shown in FIG1 of this disclosure, when in operation, displays a reset phase in the display cycle;

[0160] For example, referring to Figures 18 and 21, the OC terminal of this stage driver circuit precharges the first node PU of the next stage driver circuit. The OC of the nth stage is connected to the I1 terminal of the (n+i)th stage. In this case, i is not equal to j. The figure shows i = 3 and j = 1, that is, the OC of the first stage provides a signal to the I1 terminal of the fourth stage. The OCn of the nth stage is connected to the RST terminal of the nmth stage, where m can be equal to i or not equal to i. This case exemplifies that i and m are not equal, that is, i = 3 and m = 4, that is, the OC terminal of the fifth stage provides a signal to the RST terminal of the first stage. This example demonstrates how the OC terminal of the first-stage driver circuit pre-charges the first node of the fourth stage. When the corresponding fourth-stage driver circuit needs to output a signal from the OC terminal or the GN terminal, transistors M2 and M3 can be fully turned on. Due to the presence of transistor M1, whose gate is connected to the OC terminal of the upper-stage driver circuit or the clock signal of the upper-stage driver circuit, the overlapping of the effective levels of the upper-stage clock signal and the current-stage clock signal causes transistor M1 to turn on. Ultimately, the effective pulse width of the GN output is less than the effective pulse width of the OC terminal output. For example, in this example, the effective pulse width of the OC terminal is 3H, and the effective pulse width of the GN terminal is 1H.

[0161] During the reset phase, the drive reset circuit, under the control of the drive control signal, controls the connection between the nth stage drive output terminal and the first voltage terminal.

[0162] In at least one embodiment of this disclosure, the pre-charging phase refers to a period in which the effective levels of the output clock signals corresponding to adjacent driving circuits overlap for at least 1H (1H being the charging time of one row of pixels). This application exemplifies an overlap of 2H between the effective levels of adjacent clock signals.

[0163] The driving circuit described in at least one embodiment of this disclosure further includes a driving output circuit;

[0164] The drive output circuit is electrically connected to the first node, the nth stage drive output terminal, and the output clock signal terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the first node.

[0165] In a specific implementation, the driving circuit may further include a driving output circuit, which controls the connection or disconnection between the nth stage driving output terminal and the output clock signal terminal under the control of the potential of the first node.

[0166] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this disclosure further includes a driving output circuit 21;

[0167] The drive output circuit 21 is electrically connected to the first node PU, the nth stage drive output terminal Gn, and the output clock signal terminal CLK, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal Gn and the output clock signal terminal CLK under the control of the potential of the first node PU.

[0168] When at least one embodiment of the driving circuit shown in FIG2 of this disclosure is in operation, the display cycle may include an output phase set after the reset phase;

[0169] During the output phase, the drive output circuit 21, under the control of the potential of the first node PU, controls the connection between the nth stage drive output terminal Gn and the output clock signal terminal CLK, so as to control the nth drive output terminal Gn to output the nth drive signal.

[0170] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive output circuit is greater than or equal to 0.5 and less than or equal to 2.

[0171] In specific implementation, the ratio between the channel width-to-length ratio of the transistors included in the drive reset circuit and the channel width-to-length ratio of the transistors included in the drive output circuit can be greater than or equal to 0.5 and less than or equal to 2. The larger the channel width-to-length ratio of the transistors included in the drive reset circuit, the more fully the voltage of the nth-stage drive signal provided by the nth-stage drive output terminal is pulled down during the reset phase. However, considering that some display products have layout space limitations, the channel width-to-length ratio of the transistors included in the drive reset circuit can also be smaller than the channel width-to-length ratio of the transistors included in the drive output circuit. It is only necessary to ensure that the potential of the nth-stage drive signal is pulled low during the reset phase, so that the working state of the transistor whose gate in the pixel is connected to the nth-stage drive signal is in the pre-threshold region or saturation region. At this time, the leakage current is small and the pixel is not easy to charge voltage.

[0172] Taking a driver module with six clock signal lines as an example, when the nth output clock signal arrives, the related driver circuit charges the nth driver output terminal through the transistors included in the driver output circuit. The nth driver signal provided by the nth driver output terminal has a total of 3H high level. However, the driver control terminal in the driver circuit described in at least one embodiment of this disclosure is 1H ahead of the nth driver signal. When the driver control terminal provides a high voltage signal, the transistors included in the driver reset circuit turn on. During the first row scan time, the second row scan time, and the third row scan time H3, the nth driver output terminal is discharged. During the fourth row scan time, the transistors included in the driver reset circuit turn off, and the nth driver output terminal normally outputs the nth level drive signal. At this time, the nth driver output terminal has no pre-charge. Since the gate, source, and drain of the transistors included in the driver reset circuit are not connected to the first node and the nth level carry output terminal, the carry-reset relationship in the driver circuit described in at least one embodiment of this disclosure is not affected, the pre-charge time is consistent with the related driver circuit, and the reliability of the GOA architecture is not affected. Furthermore, in at least one embodiment of this disclosure, the nth-level drive output terminal is not pre-charged, the transistor whose gate in the pixel is connected to the nth-level drive signal is turned on for 1H time, and the brightness of pixels located in different rows is the same.

[0173] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0174] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the nth stage drive output terminal; or...

[0175] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0176] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 2, the driving circuit of at least one embodiment of this disclosure further includes an energy storage circuit 40;

[0177] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the nth stage drive output terminal Gn.

[0178] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the driving circuit of at least one embodiment of this disclosure further includes an energy storage circuit 40;

[0179] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the nth carry output terminal OCn.

[0180] The driving circuit described in at least one embodiment of this disclosure further includes a driving control circuit;

[0181] The drive control circuit is electrically connected to the output control node, the output clock signal terminal, and the nth stage drive output terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the output control node.

[0182] In a specific implementation, the driving circuit may further include a driving control circuit, which controls the connection or disconnection between the nth stage driving output terminal and the output clock signal terminal under the control of the potential of the output control node.

[0183] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive control circuit is greater than or equal to 0.2 and less than or equal to 1.

[0184] The driving circuit described in at least one embodiment of this disclosure further includes a node control circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0185] The node control circuit is electrically connected to the first node, the second node, the output control node, the output clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the output control node and the second voltage terminal under the control of the potential of the second node.

[0186] In a specific implementation, the driving circuit may further include a node control circuit. Under the control of the potential of the first node, the node control circuit controls the connection or disconnection between the output control node and the output clock signal terminal. Under the control of the potential of the second node, the node control circuit controls the connection or disconnection between the output control node and the second voltage terminal.

[0187] Optionally, the second voltage terminal can be the first low voltage terminal.

[0188] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node included in the node control circuit is greater than or equal to 0.5 and less than or equal to 2.

[0189] In at least one embodiment of this disclosure, the ratio between the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node in the node control circuit and the channel width-to-length ratio of the transistor in the drive control circuit is greater than or equal to 0.1 and less than or equal to 0.3.

[0190] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this disclosure further includes a driving control circuit 61 and a node control circuit 62.

[0191] The drive control circuit 61 is electrically connected to the output control node S0, the output clock signal terminal CLK, and the nth stage drive output terminal Gn, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal Gn and the output clock signal terminal CLK under the control of the potential of the output control node S0.

[0192] The node control circuit 62 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the output control node S0, the output clock signal terminal CLK, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the output control node S0 and the output clock signal terminal CLK under the control of the potential of the first node PU, to control the connection or disconnection between the output control node S0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the output control node S0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0193] In at least one embodiment shown in Figure 5, in the node control circuit, the transistor whose gate is electrically connected to the second node is electrically connected to the output control node S0 to prevent the transistor included in the drive control circuit 61 from turning on when noise is generated, thus charging the nth-stage drive output terminal Gn with an incorrect signal. Since the voltage of the first node is relatively high after two boosts, the gate voltage of the transistor whose gate is electrically connected to the first node in the node control circuit 62 is relatively large, and the corresponding conduction current is relatively large. The gate voltage of the transistor included in the drive control circuit 61 is the same as the voltage of the nth output clock signal, which is much lower than the second-order boost voltage of the first node. The nth drive signal is provided by the transistor included in the drive control circuit 61, and the channel width-to-length ratio of the transistor included in the drive reset circuit can be reduced. To ensure low-temperature driving capability, the ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive control circuit can be set to be greater than or equal to 0.2 and less than or equal to 1. The ratio between the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node in the node control circuit and the channel width-to-length ratio of the transistor included in the drive control circuit can be set to be greater than or equal to 0.1 and less than or equal to 0.3.

[0194] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0195] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the output control node; or...

[0196] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0197] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 5, the driving circuit of at least one embodiment of this disclosure further includes an energy storage circuit 40;

[0198] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the output control node S0.

[0199] As shown in Figure 7, based on at least one embodiment of the driving circuit shown in Figure 5, the driving circuit of at least one embodiment of this disclosure further includes an energy storage circuit 40;

[0200] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the nth carry output terminal OCn.

[0201] The driving circuit described in at least one embodiment of this disclosure further includes a node control circuit and a drive setting circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0202] The node control circuit is electrically connected to the first node, the output control node, and the output clock signal terminal, respectively, and is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node.

[0203] The drive setting circuit is electrically connected to the second node, the nth stage drive output terminal, and the third voltage terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the third voltage terminal under the control of the potential of the second node.

[0204] In a specific implementation, the driving circuit may include a node control circuit and a drive setting circuit. The node control circuit controls the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node. The drive setting circuit controls the connection or disconnection between the nth stage drive output terminal and the third voltage terminal under the control of the potential of the second node.

[0205] Optionally, the third voltage terminal can be the first low voltage terminal.

[0206] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 1, the driving circuit described in at least one embodiment of this disclosure further includes a driving control circuit 61, a node control circuit 62, and a driving set circuit 63.

[0207] The drive control circuit 61 is electrically connected to the output control node S0, the output clock signal terminal CLK, and the nth stage drive output terminal Gn, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal Gn and the output clock signal terminal CLK under the control of the potential of the output control node S0.

[0208] The node control circuit 62 is electrically connected to the first node PU, the output control node S0, and the output clock signal terminal CLK, respectively, and is used to control the connection or disconnection between the output control node S0 and the output clock signal terminal CLK under the control of the potential of the first node PU.

[0209] The drive setting circuit 63 is electrically connected to the first second node PD1, the second second node PD2, the nth stage drive output terminal Gn, and the third voltage terminal V3, respectively. It is used to control the connection or disconnection between the nth stage drive output terminal Gn and the third voltage terminal V3 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth stage drive output terminal Gn and the third voltage terminal V3 under the control of the potential of the second second node PD2.

[0210] The driving circuit described in at least one embodiment of this disclosure further includes an energy storage circuit;

[0211] The first terminal of the energy storage circuit is electrically connected to the first node, and the second terminal of the energy storage circuit is electrically connected to the output control node; or...

[0212] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth carry output terminal.

[0213] As shown in FIG9, based on at least one embodiment of the driving circuit shown in FIG8, the driving circuit of at least one embodiment of the present disclosure further includes an energy storage circuit 40;

[0214] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the output control node S0.

[0215] As shown in Figure 10, based on at least one embodiment of the driving circuit shown in Figure 8, the driving circuit of at least one embodiment of this disclosure further includes an energy storage circuit 40;

[0216] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the nth carry output terminal OCn.

[0217] In at least one embodiment of this disclosure, the drive reset circuit is disposed on the side of the carry output circuit away from the drive output circuit.

[0218] In at least one embodiment of this disclosure, the drive reset circuit is disposed on the side of the carry output circuit away from the transistor whose gate is electrically connected to the first node, which is included in the node control circuit.

[0219] In specific implementation, when the gate of the transistor included in the drive reset circuit is electrically connected to the carry output terminal of the njth stage, the drive reset circuit is laid out close to the cascade line electrically connected to the carry output circuit to facilitate signal connection and shorten the connection line between the drive reset circuit and the carry output terminal of the njth stage, which is beneficial to the layout.

[0220] The driving circuit described in at least one embodiment of this disclosure further includes a driving set circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node;

[0221] The drive setting circuit is electrically connected to the second node, the nth stage drive output terminal, and the fourth voltage terminal, respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the fourth voltage terminal under the control of the potential of the second node.

[0222] Optionally, the fourth voltage terminal can be the first low voltage terminal.

[0223] In a specific implementation, the driving circuit may further include a driving setting circuit, wherein the driving setting line, under the control of the potential of the second node, controls the connection or disconnection between the nth stage driving output terminal and the fourth voltage terminal.

[0224] The driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit; the driving circuit includes a second node, or the driving circuit includes a first second node and a second second node;

[0225] The first node control circuit is electrically connected to the first node, the input terminal, the reset terminal, and the second node, respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal, the reset signal provided by the reset terminal, and the potential of the second node.

[0226] In a specific implementation, the driving circuit may further include a first node control circuit, which controls the potential of the first node under the control of the input signal, the reset signal and the potential of the second node.

[0227] In at least one embodiment of this disclosure, the first node control circuit may also be electrically connected to the frame reset terminal, and is used to control the potential of the first node under the control of the frame reset signal provided by the frame reset terminal.

[0228] In a specific implementation, the first node control circuit can also control the potential of the first node under the control of the frame reset signal.

[0229] The driving circuit described in at least one embodiment of this disclosure may further include a second node control circuit;

[0230] The driving circuit includes a second node, or the driving circuit includes a first second node and a second second node;

[0231] The second node control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node according to the potential of the first node.

[0232] In a specific implementation, the driving circuit may further include a second node control circuit, which controls the potential of the second node according to the potential of the first node.

[0233] As shown in Figure 11, based on at least one embodiment of the driving circuit shown in Figure 3, the driving circuit of at least one embodiment of this disclosure further includes a driving set circuit 63.

[0234] The drive setting circuit 63 is electrically connected to the first second node PD1, the second second node PD2, the nth stage drive output terminal Gn, and the fourth voltage terminal V4, respectively. It is used to control the connection or disconnection between the nth stage drive output terminal Gn and the fourth voltage terminal V4 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth stage drive output terminal Gn and the fourth voltage terminal V4 under the control of the potential of the second second node PD2.

[0235] The driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit 71;

[0236] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0237] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0238] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0239] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0240] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0241] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0242] Optionally, the fifth voltage terminal can be a second low voltage terminal.

[0243] As shown in Figure 12, based on at least one embodiment of the driving circuit shown in Figure 4, the driving circuit of at least one embodiment of this disclosure further includes a driving set circuit 63.

[0244] The drive setting circuit 63 is electrically connected to the first second node PD1, the second second node PD2, the nth stage drive output terminal Gn, and the fourth voltage terminal V4, respectively. It is used to control the connection or disconnection between the nth stage drive output terminal Gn and the fourth voltage terminal V4 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth stage drive output terminal Gn and the fourth voltage terminal V4 under the control of the potential of the second second node PD2.

[0245] The driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit 71;

[0246] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0247] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0248] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0249] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0250] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0251] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0252] As shown in Figure 13, based on at least one embodiment of the driving circuit shown in Figure 6, the driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit 71;

[0253] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0254] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0255] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0256] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0257] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0258] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0259] As shown in Figure 14, based on at least one embodiment of the driving circuit shown in Figure 7, the driving circuit described in at least one embodiment of this disclosure further includes a first node control circuit 71;

[0260] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0261] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0262] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0263] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0264] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0265] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0266] As shown in Figure 15, based on at least one embodiment of the driving circuit shown in Figure 9, the driving circuit of at least one embodiment of this disclosure further includes a first node control circuit 71;

[0267] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0268] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0269] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0270] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0271] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0272] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0273] As shown in FIG16, based on at least one embodiment of the driving circuit shown in FIG10, the driving circuit of at least one embodiment of the present disclosure further includes a first node control circuit 71.

[0274] The first node control circuit 71 is electrically connected to the first node PU, the input terminal I1, the reset terminal RST, the first second node PD1, and the second second node PD2, respectively, and is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1, the reset signal provided by the reset terminal RST, the potential of the first second node PD1, and the potential of the second second node PD2.

[0275] The first node control circuit 71 is also electrically connected to the frame reset terminal STV, and is used to control the potential of the first node PU under the control of the frame reset signal provided by the frame reset terminal STV.

[0276] The driving circuit described in at least one embodiment of this disclosure further includes a second node control circuit 72;

[0277] The second node control circuit 72 is electrically connected to the first node PU, the first second node PD1 and the second second node PD2 respectively, and is used to control the potential of the first second node PD1 according to the potential of the first node PU, and to control the potential of the second second node PD2 according to the potential of the first node PU.

[0278] The driving circuit described in at least one embodiment of this disclosure further includes a carry-reset circuit 73;

[0279] The carry-reset circuit 73 is electrically connected to the first second node PD1, the second second node PD2, the nth carry output terminal OCn, and the fifth voltage terminal V5, respectively. It is used to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the nth carry output terminal OCn and the fifth voltage terminal V5 under the control of the potential of the second second node PD2.

[0280] In at least one embodiment of this disclosure, the drive reset circuit includes a first transistor;

[0281] The gate of the first transistor is electrically connected to the drive control terminal, the first electrode of the first transistor is electrically connected to the nth drive output terminal, and the second electrode of the first transistor is electrically connected to the first voltage terminal.

[0282] The carry-out circuit includes a second transistor;

[0283] The gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the output clock signal terminal, and the second terminal of the second transistor is electrically connected to the nth carry output terminal.

[0284] In at least one embodiment of this disclosure, the drive output circuit includes a third transistor;

[0285] The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the output clock signal terminal, and the second terminal of the third transistor is electrically connected to the nth stage drive output terminal.

[0286] In at least one embodiment of this disclosure, the drive control circuit includes a fourth transistor;

[0287] The gate of the fourth transistor is electrically connected to the output control node, the first terminal of the fourth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fourth transistor is electrically connected to the nth stage drive output terminal.

[0288] In at least one embodiment of this disclosure, the node control circuit includes a fifth transistor and a sixth transistor; the driving circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; or,

[0289] The node control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the driving circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the first second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; the gate of the seventh transistor is electrically connected to the second second node, the first terminal of the seventh transistor is electrically connected to the output control node, and the second terminal of the seventh transistor is electrically connected to the second voltage terminal.

[0290] In at least one embodiment of this disclosure, the node control circuit includes a fifth transistor, and the drive set circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a third voltage terminal; or...

[0291] The node control circuit includes a fifth transistor, and the drive setting circuit includes an eighth transistor and a ninth transistor; the drive circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the third voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal.

[0292] In at least one embodiment of this disclosure, the drive setting circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a fourth voltage terminal; or,

[0293] The drive setting circuit includes an eighth transistor and a ninth transistor; the drive circuit includes a first second node and a second second node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the fourth voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to the fourth voltage terminal.

[0294] As shown in Figure 17, based on at least one embodiment of the driving circuit shown in Figure 11, the driving reset circuit includes a first transistor M1;

[0295] The gate of the first transistor M1 is electrically connected to the drive control terminal GD, the source of the first transistor M1 is electrically connected to the nth stage drive output terminal Gn, and the drain of the first transistor M1 is electrically connected to the first low voltage terminal VGL.

[0296] The carry-out circuit includes a second transistor M2;

[0297] The gate of the second transistor M2 is electrically connected to the first node PU, the source of the second transistor M2 is electrically connected to the output clock signal terminal CLK, and the drain of the second transistor M2 is electrically connected to the nth carry output terminal OCn.

[0298] The drive output circuit includes a third transistor M3;

[0299] The gate of the third transistor M3 is electrically connected to the first node PU, the source of the third transistor M3 is electrically connected to the output clock signal terminal CLK, and the drain of the third transistor M3 is electrically connected to the nth stage drive output terminal Gn.

[0300] The drive set circuit includes an eighth transistor M8 and a ninth transistor M9;

[0301] The gate of the eighth transistor M8 is electrically connected to the first second node PD1, the source of the eighth transistor M8 is electrically connected to the nth stage drive output terminal Gn, and the drain of the eighth transistor M8 is electrically connected to the first low voltage terminal VGL.

[0302] The gate of the ninth transistor M9 is electrically connected to the second node PD2; the source of the ninth transistor M9 is electrically connected to the nth stage drive output terminal Gn; and the drain of the ninth transistor M9 is electrically connected to the first low voltage terminal VGL.

[0303] The first node control circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14;

[0304] The gate and source of M10 are both electrically connected to the input terminal I1, and the drain of M10 is electrically connected to the first node PU.

[0305] The gate of M11 is electrically connected to the reset terminal RST, the source of M11 is electrically connected to the first node PU, and the drain of M11 is electrically connected to the second low voltage terminal LVGL.

[0306] The gate of M12 is electrically connected to the first second node PD1, the source of M12 is electrically connected to the first node PU, and the drain of M12 is electrically connected to the second low voltage terminal LVGL.

[0307] The gate of M13 is electrically connected to the second node PD2, the source of M13 is electrically connected to the first node PU, and the drain of M13 is electrically connected to the second low voltage terminal LVGL.

[0308] The gate of M14 is electrically connected to the frame reset terminal STV, the source of M14 is electrically connected to the first node PU, and the drain of M14 is electrically connected to the second low voltage terminal LVGL.

[0309] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22;

[0310] The gate and source of M15 are both electrically connected to the first control voltage terminal VDDO, and the drain of M15 is electrically connected to the first pull-down control node PD_CN1.

[0311] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the first pull-down control node PD_CN1, and the drain of M16 is electrically connected to the second low voltage terminal LVGL.

[0312] The gate of M17 is electrically connected to the first pull-down control node PD_CN1, the source of M17 is electrically connected to the first control voltage terminal VDDO, and the drain of M17 is electrically connected to the first second node PD1.

[0313] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the first second node PD1, and the drain of M18 is electrically connected to the second low voltage terminal LVGL.

[0314] The gate and source of M19 are electrically connected to the second control voltage terminal VDDE, and the drain of M19 is electrically connected to the second pull-down control node PD_CN2.

[0315] The gate of M20 is electrically connected to the first node PU, the source of M20 is electrically connected to the second pull-down control node PD_CN2, and the drain of M20 is electrically connected to the second low voltage terminal LVGL.

[0316] The gate of M21 is electrically connected to the second pull-down control node PD_CN2, the source of M21 is electrically connected to the second control voltage terminal VDDE, and the drain of M21 is electrically connected to the second node PD2.

[0317] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the second node PD2, and the drain of M22 is electrically connected to the second low voltage terminal LVGL.

[0318] The carry-reset terminal includes the twenty-third transistor M23 and the twenty-fourth transistor M24;

[0319] The gate of M23 is electrically connected to the first second node PD1, the source of M23 is electrically connected to the nth carry output terminal OCn, and the drain of M23 is electrically connected to the second low voltage terminal LVGL.

[0320] The gate of M24 is electrically connected to the second node PD2, the source of M24 is electrically connected to the nth carry output terminal OCn, and the drain of M24 is electrically connected to the second low voltage terminal LVGL.

[0321] The energy storage circuit includes a storage capacitor C1;

[0322] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the nth stage drive output terminal Gn.

[0323] In at least one embodiment of the drive circuit shown in Figure 17, all transistors are n-type transistors.

[0324] In at least one embodiment of the driving circuit shown in Figure 17, the first voltage terminal is the first low voltage terminal VGL; GD can be electrically connected to the carry output terminal of the (n-1)th stage, or GD can be electrically connected to the output clock signal terminal of the (n-1)th stage.

[0325] The driving circuit described in at least one embodiment of this disclosure removes the pre-charge of the driving signal provided at the driving output terminal without changing the duty cycle of the output clock signal or the lifespan of the driving circuit, thereby achieving the purpose of removing the pre-charge of all pixels.

[0326] In at least one embodiment of the driving circuit shown in Figure 17 of this disclosure, the gate of M1 is electrically connected to GD, the source of M1 is electrically connected to the nth stage driving output terminal Gn, and the drain of M1 is electrically connected to the first low voltage terminal VGL. The ratio of the channel width-to-length ratio of M1 to that of M3 can be greater than or equal to 0.5 and less than or equal to 2. The larger the channel width-to-length ratio of M1, the more fully the voltage of the nth stage driving output terminal is pulled down during the pre-charging stage. However, considering that some display products have layout space limitations, the channel width-to-length ratio of M1 can also be smaller than that of M3. It is only necessary to ensure that the potential of the signal provided by Gn is pulled low during the pre-charging stage so that the pixel TFT (thin-film transistor) is in the pre-threshold region or saturation region. At this time, the leakage current is small and the pixel is not easy to charge voltage.

[0327] Figure 18 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0328] Figure 19 is a structural diagram of the drive module according to at least one embodiment of the present disclosure.

[0329] Figure 20 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 17.

[0330] Figure 21 is a timing diagram of the operation of the drive module according to at least one embodiment of the present disclosure.

[0331] Figure 22 is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 17) according to at least one embodiment of the present disclosure.

[0332] As shown in Figure 18, at least the first row or the first few rows of driving circuits are electrically connected to the starting voltage terminal. For example, the input terminal of the driving circuit in the first three rows is shown to be electrically connected to the starting voltage terminal. Additionally, the GD terminal of the first row or the first few rows is electrically connected to the starting voltage terminal. Optionally, the first row or the first few rows of driving circuits may not have an M1 transistor, while other stages of driving circuits may have an M1 transistor. The GD terminal of the M1 transistors in other stages is connected to the OCn terminal of the previous stage driving circuit. This embodiment illustrates that the GD terminal of the M1 transistors in other stages is connected to the OCn terminal of the previous stage driving circuit. The driving module described in at least one embodiment of this disclosure may include the first... The circuit consists of a first-stage driver circuit GA1, a second-stage driver circuit GA2, a third-stage driver circuit GA3, a fourth-stage driver circuit GA4, a fifth-stage driver circuit GA5, and a sixth-stage driver circuit GA6. The OCn of the nth stage is connected to the I1 terminal of the (n+i)th stage. In this case, i is not equal to j. The diagram illustrates i=3 and j=1, meaning the first-stage OC provides a signal to the I1 terminal of the fourth stage. The OCn of the nth stage is connected to the RST terminal of the nmth stage, where m can be equal to or not equal to i. This case illustrates i and m not being equal, i=3 and m=4, meaning the OC terminal of the fifth stage provides a signal to the RST terminal of the first stage.

[0333] The input terminal of GA1 is electrically connected to the starting voltage terminal STV1, and the first drive output terminal G1 of GA1 is electrically connected to the first row gate line GL1.

[0334] The output clock signal terminal of GA1 is electrically connected to the first clock signal line CLK1;

[0335] The reset terminal of GA1 is electrically connected to the fifth carry output terminal OC5 of GA5;

[0336] The input terminal of GA2 is electrically connected to the starting voltage terminal STV1, and the second drive output terminal G2 of GA2 is electrically connected to the second row gate line GL2.

[0337] The output clock signal terminal of GA2 is electrically connected to the second clock signal line CLK2;

[0338] The reset terminal of GA2 is electrically connected to the sixth-stage carry output terminal OC6 of GA6;

[0339] The output clock signal terminal of GA3 is electrically connected to the third clock signal line CLK3;

[0340] The input terminal of GA3 is electrically connected to the starting voltage terminal STV1, and the third drive output terminal G3 of GA3 is electrically connected to the third row of gate lines GL3.

[0341] The reset terminal of GA3 is electrically connected to the seventh-stage carry output terminal OC7;

[0342] The input terminal of GA4 is electrically connected to the first carry output terminal OC1 of GA1, and the fourth drive output terminal G4 of GA4 is electrically connected to the fourth row gate line GL4.

[0343] The output clock signal terminal of GA4 is electrically connected to the fourth clock signal line CLK4;

[0344] The reset terminal of GA4 is electrically connected to the eighth-stage carry output terminal OC8;

[0345] The input terminal of GA5 is electrically connected to the second carry output terminal OC2 of GA2, and the fifth drive output terminal G5 of GA5 is electrically connected to the fifth row gate line GL5.

[0346] The output clock signal terminal of GA5 is electrically connected to the fifth clock signal line CLK5;

[0347] The reset terminal of GA5 is electrically connected to the ninth-stage carry output terminal OC9;

[0348] The input terminal of GA6 is electrically connected to the third carry output terminal OC3 of GA3, and the sixth drive output terminal G6 of GA6 is electrically connected to the sixth row gate line GL6.

[0349] The output clock signal terminal of GA6 is electrically connected to the sixth clock signal line CLK6;

[0350] The reset terminal of GA6 is electrically connected to the tenth-stage carry output terminal OC10;

[0351] The drive control terminal of GA1 is electrically connected to the starting voltage terminal STV1;

[0352] The drive control terminal of GA2 is electrically connected to the first-stage carry output terminal OC1;

[0353] The drive control terminal of GA3 is electrically connected to the second-stage carry output terminal OC2;

[0354] The drive control terminal of GA4 is electrically connected to the third-stage carry output terminal OC3;

[0355] The drive control terminal of GA5 is electrically connected to the fourth-stage carry output terminal OC4;

[0356] The drive control terminal of GA6 is electrically connected to the fifth-stage carry output terminal OC5.

[0357] In at least one embodiment of this disclosure, when the driving module includes six clock signal lines, the 6n-5th stage driving circuit can be electrically connected to the first clock signal line, the 6n-4th stage driving circuit can be electrically connected to the second clock signal line, the 6n-3rd stage driving circuit can be electrically connected to the third clock signal line, the 6n-2nd stage driving circuit can be electrically connected to the fourth clock signal line, the 6n-1st stage driving circuit can be electrically connected to the fifth clock signal line, and the 6nth stage driving circuit can be electrically connected to the sixth clock signal line, where n is a positive integer.

[0358] As shown in Figure 19, the driving module described in at least one embodiment of this disclosure may include a first-level driving circuit GA1, a second-level driving circuit GA2, a third-level driving circuit GA3, a fourth-level driving circuit GA4, a fifth-level driving circuit GA5, and a sixth-level driving circuit GA6.

[0359] The input terminal of GA1 is electrically connected to the starting voltage terminal STV1, and the first drive output terminal G1 of GA1 is electrically connected to the first row gate line GL1.

[0360] The output clock signal terminal of GA1 is electrically connected to the first clock signal line CLK1;

[0361] The reset terminal of GA1 is electrically connected to the fifth carry output terminal OC5 of GA5;

[0362] The input terminal of GA2 is electrically connected to the starting voltage terminal STV1, and the second drive output terminal G2 of GA2 is electrically connected to the second row gate line GL2.

[0363] The output clock signal terminal of GA2 is electrically connected to the second clock signal line CLK2;

[0364] The reset terminal of GA2 is electrically connected to the sixth-stage carry output terminal OC6 of GA6;

[0365] The output clock signal terminal of GA3 is electrically connected to the third clock signal line CLK3;

[0366] The input terminal of GA3 is electrically connected to the starting voltage terminal STV1, and the third drive output terminal G3 of GA3 is electrically connected to the third row of gate lines GL3.

[0367] The reset terminal of GA3 is electrically connected to the seventh-stage carry output terminal OC7;

[0368] The input terminal of GA4 is electrically connected to the first carry output terminal OC1 of GA1, and the fourth drive output terminal G4 of GA4 is electrically connected to the fourth row gate line GL4.

[0369] The output clock signal terminal of GA4 is electrically connected to the fourth clock signal line CLK4;

[0370] The reset terminal of GA4 is electrically connected to the eighth-stage carry output terminal OC8;

[0371] The input terminal of GA5 is electrically connected to the second carry output terminal OC2 of GA2, and the fifth drive output terminal G5 of GA5 is electrically connected to the fifth row gate line GL5.

[0372] The output clock signal terminal of GA5 is electrically connected to the fifth clock signal line CLK5;

[0373] The reset terminal of GA5 is electrically connected to the ninth-stage carry output terminal OC9;

[0374] The input terminal of GA6 is electrically connected to the third carry output terminal OC3 of GA3, and the sixth drive output terminal G6 of GA6 is electrically connected to the sixth row gate line GL6.

[0375] The output clock signal terminal of GA6 is electrically connected to the sixth clock signal line CLK6;

[0376] The reset terminal of GA6 is electrically connected to the tenth-stage carry output terminal OC10;

[0377] The drive control terminal of GA1 is electrically connected to the starting voltage terminal STV1;

[0378] The drive control terminal of GA2 is electrically connected to CLK1;

[0379] The drive control terminal of GA3 is electrically connected to CLK2;

[0380] The drive control terminal of GA4 is electrically connected to CLK3;

[0381] The drive control terminal of GA5 is electrically connected to CLK4;

[0382] The drive control terminal of GA6 is electrically connected to CLK5.

[0383] As shown in Figure 20, in at least one embodiment of the driving circuit shown in Figure 18 of this disclosure, when GD is electrically connected to the carry output terminal OCn-1 of the (n-1)th stage,

[0384] During the first row scan time H1, the second row scan time H2, and the third row scan time H3, the carry output terminal OCn-1 of the (n-1)th row outputs a high voltage signal; during the second row scan time H2, the third row scan time H3, and the fourth row scan time H4, CLK provides a high voltage signal.

[0385] During the first scan time H1, the second scan time H2, and the third scan time, M1 is turned on, Gn is connected to VGL, and Gn outputs a low voltage signal.

[0386] During the fourth scan time H4, M3 is turned on, Gn and CLK are connected, Gn outputs a high voltage signal, and the nth drive signal output by Gn has no pre-charge;

[0387] As shown in Figure 20, when the pixel circuit is connected to the first data voltage Vdata, there is no difference between the first pixel voltage Vp1 and the second pixel voltage Vp2 when the pixel circuit is connected to the second data voltage Vdata2.

[0388] As shown in Figure 21, in at least one embodiment of the drive module shown in Figure 18 of this disclosure, CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6 sequentially output corresponding clock signals during operation.

[0389] PU1 is the first node in GA1, PU2 is the first node in GA2, PU3 is the first node in GA3, PU4 is the first node in GA4, PU5 is the first node in GA5, and PU6 is the first node in GA6.

[0390] During the first row scan time H1, the second row scan time H2, and the third row scan time H3, OC1 outputs a high voltage signal;

[0391] During the second row scan time H2, the third row scan time H3, and the fourth row scan time H4, OC2 outputs a high voltage signal;

[0392] During the third row scan time H3, the fourth row scan time H4, and the fifth row scan time H5, OC3 outputs a high voltage signal;

[0393] During the fourth row scan time H4, the fifth row scan time H5, and the sixth row scan time H6, OC4 outputs a high voltage signal;

[0394] At the fifth scan time H5, the sixth scan time H6 and the seventh scan time H7, OC5 outputs a high voltage signal;

[0395] At the sixth scan time H6, the seventh scan time H7 and the eighth scan time H8, OC6 outputs a high voltage signal;

[0396] During the third row scan time H3, G1 outputs a high voltage signal;

[0397] During the fourth scan time H4, G2 outputs a high voltage signal;

[0398] During the fifth row scan time H5, G3 outputs a high voltage signal;

[0399] During the sixth line scan time H6, G4 outputs a high voltage signal;

[0400] During the seventh line scan time H7, G5 outputs a high voltage signal;

[0401] At scan time H8 of the eighth line, G6 outputs a high voltage signal.

[0402] As shown in Figure 22, M1 is located on the side of M2 away from M3. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0403] Figure 23A is a layout diagram of the gate metal layer in Figure 22, Figure 23B is a layout diagram of the semiconductor layer in Figure 22, Figure 23C is a layout diagram of the source and drain metal layers in Figure 22, and Figure 23D is a layout diagram of the conductive layer in Figure 22.

[0404] Figure 23E is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 22, and Figure 23F is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 22.

[0405] In Figure 23D, the part labeled L1 is the first connection part, and the drain of M2 is electrically connected to OCn through L1.

[0406] In Figure 23A, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, the gate labeled GT2 is the gate of M2, the gate labeled GT3 is the gate of M3, and the first plate labeled C1a is the first plate of C1.

[0407] In Figure 23B, the active pattern labeled A10 is M10, the active pattern labeled A1 is M1, the active pattern labeled A2 is M2, and the active pattern labeled A3 is M3.

[0408] In Figure 23C, the plate labeled C1b is the second plate of C1.

[0409] In Figure 23D, the part labeled L1 is the first connecting part.

[0410] The differences between at least one embodiment of the driving circuit shown in Figure 24 and at least one embodiment of the driving circuit shown in Figure 18 are as follows:

[0411] The second terminal of C1 is electrically connected to the nth carry-out output terminal OCn.

[0412] In at least one embodiment of the driving circuit shown in Figure 24 of this disclosure, the two plates of C1 are configured to be electrically connected to the first node PU and the nth carry output terminal OCn, respectively. When the potential of PU rises in the first order, M2 is turned on, and the output clock signal provided by CLK charges OCn. At this time, the potential of PU is raised a second time through coupling with C1.

[0413] Figure 25A is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 24) according to at least one embodiment of the present disclosure.

[0414] Figure 25B is a layout diagram of the gate metal layer in Figure 25A, Figure 25C is a layout diagram of the semiconductor layer in Figure 25A, Figure 25D is a layout diagram of the source and drain metal layers in Figure 25A, and Figure 25E is a layout diagram of the conductive layer in Figure 25A.

[0415] Figure 25F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 25A, and Figure 25G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 25A.

[0416] As shown in Figure 25A, M1 is located on the side of M2 away from M3. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0417] In Figure 25B, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, the gate labeled GT2 is the gate of M2, the gate labeled GT3 is the gate of M3, and the first plate labeled C1a is the first plate of C1.

[0418] In Figure 25C, the active pattern labeled A10 is M10, the active pattern labeled A1 is M1, the active pattern labeled A2 is M2, and the active pattern labeled A3 is M3.

[0419] In Figure 25D, the plate labeled C1b is the second plate of C1.

[0420] In Figure 25E, the part labeled L1 is the first connecting part.

[0421] As shown in Figure 26, based on at least one embodiment of the driving circuit shown in Figure 14, the driving reset circuit includes a first transistor M1;

[0422] The gate of the first transistor M1 is electrically connected to the drive control terminal GD, the source of the first transistor M1 is electrically connected to the nth stage drive output terminal Gn, and the drain of the first transistor M1 is electrically connected to the first low voltage terminal VGL.

[0423] The carry-out circuit includes a second transistor M2;

[0424] The gate of the second transistor M2 is electrically connected to the first node PU, the source of the second transistor M2 is electrically connected to the output clock signal terminal CLK, and the drain of the second transistor M2 is electrically connected to the nth carry output terminal OCn.

[0425] The drive control circuit includes a fourth transistor M4;

[0426] The gate of the fourth transistor M4 is electrically connected to the output control node S0, the source of the fourth transistor M4 is electrically connected to the output clock signal terminal CLK, and the drain of the fourth transistor M4 is electrically connected to the nth stage drive output terminal Gn.

[0427] The node control circuit includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.

[0428] The gate of the fifth transistor M5 is electrically connected to the first node PU, the source of the fifth transistor M5 is electrically connected to the output clock signal terminal CLK, and the drain of the fifth transistor M5 is electrically connected to the output control node S0.

[0429] The gate of the sixth transistor M6 is electrically connected to the first second node PD1, the source of the sixth transistor M6 is electrically connected to the output control node S0, and the drain of the sixth transistor M6 is electrically connected to the second low voltage terminal LVGL.

[0430] The gate of the seventh transistor M7 is electrically connected to the second node PD2, the source of the seventh transistor M7 is electrically connected to the output control node S0, and the outlet of the seventh transistor M7 is electrically connected to the second low voltage terminal LVGL.

[0431] The first node control circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14;

[0432] The gate and source of M10 are both electrically connected to the input terminal I1, and the drain of M10 is electrically connected to the first node PU.

[0433] The gate of M11 is electrically connected to the reset terminal RST, the source of M11 is electrically connected to the first node PU, and the drain of M11 is electrically connected to the second low voltage terminal LVGL.

[0434] The gate of M12 is electrically connected to the first second node PD1, the source of M12 is electrically connected to the first node PU, and the drain of M12 is electrically connected to the second low voltage terminal LVGL.

[0435] The gate of M13 is electrically connected to the second node PD2, the source of M13 is electrically connected to the first node PU, and the drain of M13 is electrically connected to the second low voltage terminal LVGL.

[0436] The gate of M14 is electrically connected to the frame reset terminal STV, the source of M14 is electrically connected to the first node PU, and the drain of M14 is electrically connected to the second low voltage terminal LVGL.

[0437] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22;

[0438] The gate and source of M15 are both electrically connected to the first control voltage terminal VDDO, and the drain of M15 is electrically connected to the first pull-down control node PD_CN1.

[0439] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the first pull-down control node PD_CN1, and the drain of M16 is electrically connected to the second low voltage terminal LVGL.

[0440] The gate of M17 is electrically connected to the first pull-down control node PD_CN1, the source of M17 is electrically connected to the first control voltage terminal VDDO, and the drain of M17 is electrically connected to the first second node PD1.

[0441] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the first second node PD1, and the drain of M18 is electrically connected to the second low voltage terminal LVGL.

[0442] The gate and source of M19 are electrically connected to the second control voltage terminal VDDE, and the drain of M19 is electrically connected to the second pull-down control node PD_CN2.

[0443] The gate of M20 is electrically connected to the first node PU, the source of M20 is electrically connected to the second pull-down control node PD_CN2, and the drain of M20 is electrically connected to the second low voltage terminal LVGL.

[0444] The gate of M21 is electrically connected to the second pull-down control node PD_CN2, the source of M21 is electrically connected to the second control voltage terminal VDDE, and the drain of M21 is electrically connected to the second node PD2.

[0445] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the second node PD2, and the drain of M22 is electrically connected to the second low voltage terminal LVGL.

[0446] The carry-reset terminal includes the twenty-third transistor M23 and the twenty-fourth transistor M24;

[0447] The gate of M23 is electrically connected to the first second node PD1, the source of M23 is electrically connected to the nth carry output terminal OCn, and the drain of M23 is electrically connected to the second low voltage terminal LVGL.

[0448] The gate of M24 is electrically connected to the second node PD2, the source of M24 is electrically connected to the nth carry output terminal OCn, and the drain of M24 is electrically connected to the second low voltage terminal LVGL.

[0449] The energy storage circuit includes a storage capacitor C1;

[0450] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the output control node S0.

[0451] In at least one embodiment of the driving circuit shown in Figure 26, all transistors are n-type transistors.

[0452] In at least one embodiment of the driving circuit shown in Figure 26 of this disclosure, M4 is added; the gate of M4 is electrically connected to the drain of M5, the source of M4 is electrically connected to CLK, the drain of M4 is electrically connected to Gn, the source of M1 is electrically connected to the drain of M4, and M6 and M7 are electrically connected to the gate of M4. This prevents M4 from being turned on when noise occurs, thus avoiding the charging of Gn with an incorrect signal. Since the gate of M5 is electrically connected to PU, the potential of PU is higher after two boosts, resulting in a larger gate voltage Vg5 of M5 and a larger corresponding on-current. In at least one embodiment of the driving circuit shown in Figure 18, M1 directly discharges to the drain (Gn) of M3, requiring M1 to have a larger size and a larger layout space. However, in at least one embodiment of the driving circuit shown in Figure 26 below, the gate voltage of M4 is the same as the voltage of CLK, which is significantly lower than the second-order boost voltage of PU. M4 provides the nth-stage driving signal, allowing the size of M1 to be reduced. To ensure low-temperature driving capability, the ratio of the channel width-to-length ratio of M5 to that of M4 can be set to greater than or equal to 0.1 and less than or equal to 0.3, and the ratio of the channel width-to-length ratio of M1 to that of M4 can be greater than or equal to 0.2 and less than or equal to 1.

[0453] Figure 27A is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 26) according to at least one embodiment of the present disclosure.

[0454] Figure 27B is a layout diagram of the gate metal layer in Figure 27A, Figure 27C is a layout diagram of the semiconductor layer in Figure 27A, Figure 27D is a layout diagram of the source and drain metal layers in Figure 27A, and Figure 27E is a layout diagram of the conductive layer in Figure 27A.

[0455] Figure 27F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 27A, and Figure 27G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 27A.

[0456] As shown in Figure 27A, M1 is located on the side of M2 away from M5. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0457] In Figure 27B, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, and the gate labeled GT4 is the gate of M4.

[0458] In Figure 27C, the active pattern labeled A10 is M10, the active pattern labeled A1 is M1, the active pattern labeled A2 is M2, the active pattern labeled A5 is M5, and the active pattern labeled A4 is M4.

[0459] In Figure 27D, the plate labeled C1b is the second plate of C1.

[0460] In Figure 27E, the part labeled L1 is the first connecting part.

[0461] The differences between at least one embodiment of the driving circuit shown in Figure 28 of this disclosure and at least one embodiment of the driving circuit shown in Figure 26 of this disclosure are as follows:

[0462] The second terminal of C1 is electrically connected to the nth carry-out output terminal OCn.

[0463] In at least one embodiment of the driving circuit shown in Figure 28 of this disclosure, the two plates of C1 are electrically connected to PU and OCn respectively, to ensure that the potential of PU rises normally in the second order and to avoid noise coupling of PU to M4, which would indirectly affect Gn.

[0464] Figure 29A is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 28) according to at least one embodiment of the present disclosure.

[0465] Figure 29B is a layout diagram of the gate metal layer in Figure 29A, Figure 29C is a layout diagram of the semiconductor layer in Figure 29A, Figure 29D is a layout diagram of the source and drain metal layers in Figure 29A, and Figure 29E is a layout diagram of the conductive layer in Figure 29A.

[0466] Figure 29F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 29A, and Figure 29G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 29A.

[0467] As shown in Figure 29A, M1 is located on the side of M2 away from M5. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0468] In Figure 29B, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, and the gate labeled GT4 is the gate of M4.

[0469] In Figure 29C, the active pattern labeled A10 is M10, the active pattern labeled A1 is M1, the active pattern labeled A2 is M2, the active pattern labeled A5 is M5, and the active pattern labeled A4 is M4.

[0470] In Figure 29E, the part labeled L1 is the first connecting part.

[0471] As shown in Figure 30, based on at least one embodiment of the driving circuit shown in Figure 16,

[0472] The gate of the first transistor M1 is electrically connected to the drive control terminal GD, the source of the first transistor M1 is electrically connected to the nth stage drive output terminal Gn, and the drain of the first transistor M1 is electrically connected to the first low voltage terminal VGL.

[0473] The carry-out circuit includes a second transistor M2;

[0474] The gate of the second transistor M2 is electrically connected to the first node PU, the source of the second transistor M2 is electrically connected to the output clock signal terminal CLK, and the drain of the second transistor M2 is electrically connected to the nth carry output terminal OCn.

[0475] The drive control circuit includes a fourth transistor M4;

[0476] The gate of the fourth transistor M4 is electrically connected to the output control node S0, the source of the fourth transistor M4 is electrically connected to the output clock signal terminal CLK, and the drain of the fourth transistor M4 is electrically connected to the nth stage drive output terminal Gn.

[0477] The node control circuit includes a fifth transistor M5, and the drive setting circuit includes an eighth transistor M8 and a ninth transistor M9.

[0478] The gate of the fifth transistor M5 is electrically connected to the first node PU, the source of the fifth transistor M5 is electrically connected to the output clock signal terminal CLK, and the drain of the fifth transistor M5 is electrically connected to the output control node S0.

[0479] The gate of the eighth transistor M8 is electrically connected to the first second node PD1, the source of the eighth transistor M8 is electrically connected to the nth stage drive output terminal Gn, and the drain of the eighth transistor M8 is electrically connected to the first low voltage terminal VGL.

[0480] The gate of the ninth transistor M9 is electrically connected to the second node PD2, the source of the ninth transistor M9 is electrically connected to the nth stage drive output terminal Gn, and the drain of the ninth transistor M9 is electrically connected to the first low voltage terminal VGL.

[0481] The first node control circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14;

[0482] The gate and source of M10 are both electrically connected to the input terminal I1, and the drain of M10 is electrically connected to the first node PU.

[0483] The gate of M11 is electrically connected to the reset terminal RST, the source of M11 is electrically connected to the first node PU, and the drain of M11 is electrically connected to the second low voltage terminal LVGL.

[0484] The gate of M12 is electrically connected to the first second node PD1, the source of M12 is electrically connected to the first node PU, and the drain of M12 is electrically connected to the second low voltage terminal LVGL.

[0485] The gate of M13 is electrically connected to the second node PD2, the source of M13 is electrically connected to the first node PU, and the drain of M13 is electrically connected to the second low voltage terminal LVGL.

[0486] The gate of M14 is electrically connected to the frame reset terminal STV, the source of M14 is electrically connected to the first node PU, and the drain of M14 is electrically connected to the second low voltage terminal LVGL.

[0487] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22;

[0488] The gate and source of M15 are both electrically connected to the first control voltage terminal VDDO, and the drain of M15 is electrically connected to the first pull-down control node PD_CN1.

[0489] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the first pull-down control node PD_CN1, and the drain of M16 is electrically connected to the second low voltage terminal LVGL.

[0490] The gate of M17 is electrically connected to the first pull-down control node PD_CN1, the source of M17 is electrically connected to the first control voltage terminal VDDO, and the drain of M17 is electrically connected to the first second node PD1.

[0491] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the first second node PD1, and the drain of M18 is electrically connected to the second low voltage terminal LVGL.

[0492] The gate and source of M19 are electrically connected to the second control voltage terminal VDDE, and the drain of M19 is electrically connected to the second pull-down control node PD_CN2.

[0493] The gate of M20 is electrically connected to the first node PU, the source of M20 is electrically connected to the second pull-down control node PD_CN2, and the drain of M20 is electrically connected to the second low voltage terminal LVGL.

[0494] The gate of M21 is electrically connected to the second pull-down control node PD_CN2, the source of M21 is electrically connected to the second control voltage terminal VDDE, and the drain of M21 is electrically connected to the second node PD2.

[0495] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the second node PD2, and the drain of M22 is electrically connected to the second low voltage terminal LVGL.

[0496] The carry-reset terminal includes the twenty-third transistor M23 and the twenty-fourth transistor M24;

[0497] The gate of M23 is electrically connected to the first second node PD1, the source of M23 is electrically connected to the nth carry output terminal OCn, and the drain of M23 is electrically connected to the second low voltage terminal LVGL.

[0498] The gate of M24 is electrically connected to the second node PD2, the source of M24 is electrically connected to the nth carry output terminal OCn, and the drain of M24 is electrically connected to the second low voltage terminal LVGL.

[0499] The energy storage circuit includes a storage capacitor C1;

[0500] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the output control node S0.

[0501] In at least one embodiment of the driving circuit shown in FIG30 of this disclosure, M8, M9 and M4 are changed to be electrically connected to Gn, and Gn is directly denoised through M8 and M9. When the gate of M5 or the gate of M4 has noise affecting Gn, the noise signal can be directly released through M8 and M9.

[0502] Figure 31A is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 30) according to at least one embodiment of the present disclosure.

[0503] Figure 31B is a layout diagram of the gate metal layer in Figure 31A, Figure 31C is a layout diagram of the semiconductor layer in Figure 31A, Figure 31D is a layout diagram of the source and drain metal layers in Figure 31A, and Figure 31E is a layout diagram of the conductive layer in Figure 31A.

[0504] Figure 31F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 31A, and Figure 31G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 31A.

[0505] As shown in Figure 31A, M1 is located on the side of M2 away from M5. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0506] In Figure 31B, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, and the gate labeled GT4 is the gate of M4.

[0507] In Figure 31C, the active pattern labeled A10 is M10, the active pattern labeled A1 is M1, the active pattern labeled A2 is M2, the active pattern labeled A5 is M5, and the active pattern labeled A4 is M4.

[0508] In Figure 31E, the part labeled L1 is the first connecting part.

[0509] The difference between at least one embodiment of the driving circuit shown in Figure 32 of this disclosure and at least one embodiment of the driving circuit shown in Figure 30 of this disclosure is as follows: the second terminal of C1 is electrically connected to the nth carry output terminal OCn.

[0510] In at least one embodiment of the driving circuit shown in FIG32 of this disclosure, M8, M9 and M4 are changed to be electrically connected to Gn, and Gn is directly denoised through M8 and M9. When the gate of M5 or the gate of M4 has noise affecting Gn, the noise signal can be directly released through M8 and M9.

[0511] Figure 33A is a partial layout diagram of a driving circuit (the structure of which is shown in Figure 32) according to at least one embodiment of the present disclosure.

[0512] Figure 33B is a layout diagram of the gate metal layer in Figure 33A, Figure 33C is a layout diagram of the semiconductor layer in Figure 33A, Figure 33D is a layout diagram of the source and drain metal layers in Figure 33A, and Figure 33E is a layout diagram of the conductive layer in Figure 33A.

[0513] Figure 33F is a stack-up diagram of the gate metal layer and semiconductor layer in Figure 33A, and Figure 33G is a stack-up diagram of the source / drain metal layer and conductive layer in Figure 33A.

[0514] As shown in Figure 33A, M1 is located on the side of M2 away from M5. When M1 is connected to OCn-1, M1 can be close to the cascade line of M2, making signal connection easier and the signal connection length shorter, which is beneficial for layout.

[0515] In Figure 33B, the gate labeled GT10 is the gate of M10, the gate labeled GT1 is the gate of M1, and the gate labeled GT4 is the gate of M4.

[0516] In Figure 33C, the active graphic labeled A10 is M10, the active graphic labeled A1 is M1, the active graphic labeled A2 is M2, the active graphic labeled A5 is M5, and the active graphic labeled A4 is M4.

[0517] In Figure 33E, the part labeled L1 is the first connecting part.

[0518] The driving method described in this embodiment is applied to the above-mentioned driving circuit, and the driving method includes:

[0519] Under the control of the drive control signal, the drive reset circuit controls the connection or disconnection between the nth stage drive output terminal and the first voltage terminal;

[0520] The carry output circuit, under the control of the potential of the first node, controls whether the output clock signal terminal is connected or disconnected from the carry output terminal of the nth stage;

[0521] n is a positive integer.

[0522] In at least one embodiment of this disclosure, the display cycle includes a reset phase; the driving method includes:

[0523] During the reset phase, the drive reset circuit, under the control of the drive control signal, controls the connection between the nth stage drive output terminal and the first voltage terminal.

[0524] In at least one embodiment of this disclosure, the display cycle includes an output phase disposed after the reset phase, and the pixel circuit further includes a drive output circuit; the driving method includes:

[0525] During the output phase, the drive output circuit, under the control of the potential of the first node, controls the connection between the nth stage drive output terminal and the output clock signal terminal.

[0526] The driving module described in this embodiment includes multiple stages of the aforementioned driving circuits.

[0527] The driving module described in at least one embodiment of this disclosure includes a driving circuit comprising a carry output terminal, an input terminal, and a reset terminal;

[0528] The carry output terminal of the a-th stage driving circuit is electrically connected to the input terminal of the a+i-th stage driving circuit.

[0529] The reset terminal of the a-th stage driving circuit is electrically connected to the carry output terminal of the a+p-th stage driving circuit.

[0530] a is a positive integer; i is not equal to j; i, j and p are positive integers.

[0531] In at least one embodiment of this disclosure, the carry output terminal of the a-th stage driving circuit is electrically connected to the input terminal of the (a+i)-th stage driving circuit, where i is not equal to j. For example, i can be equal to 3 and j can be equal to 1, so that the first node in the (a+i)-th stage driving circuit can be pre-charged. In at least one embodiment of this disclosure, the pre-charging of the driving output terminal is removed.

[0532] The display device described in this disclosure includes the driving module described above.

[0533] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

A driving circuit includes a carry-out output circuit and a driving reset circuit. The driving reset circuit is electrically connected to a driving control terminal, an nth-stage driving output terminal, and a first voltage terminal, respectively, and is used to control the connection or disconnection between the nth-stage driving output terminal and the first voltage terminal under the control of the driving control signal provided by the driving control terminal. The carry-out output circuit is electrically connected to a first node, an output clock signal terminal, and the nth-stage carry-out output terminal, and is used to control the connection or disconnection between the output clock signal terminal and the nth-stage carry-out output terminal under the control of the potential of the first node. n is a positive integer. The driving control terminal is the nj-th stage carry-out output terminal or the nj-th stage output clock signal terminal, and j is an integer greater than or equal to 1. The driving circuit as described in claim 1, wherein, It also includes a drive output circuit; the drive output circuit is electrically connected to the first node, the nth stage drive output terminal and the output clock signal terminal respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the first node. The driving circuit as described in claim 2, wherein, The ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive output circuit is greater than or equal to 0.5 and less than or equal to 2. The driving circuit as described in claim 2, wherein, It also includes an energy storage circuit; the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth stage drive output terminal; or, the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth stage carry output terminal. The driving circuit as described in claim 1, wherein, It also includes a drive control circuit; the drive control circuit is electrically connected to the output control node and the nth stage drive output terminal respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the output control node. The driving circuit as described in claim 5, wherein, The ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor included in the drive control circuit is greater than or equal to 0.2 and less than or equal to 1. The driving circuit as described in claim 5, wherein, It also includes a node control circuit; the driving circuit includes a second node; or, the driving circuit includes a first second node and a second second node; the node control circuit is electrically connected to the first node, the second node, the output control node, the output clock signal terminal and the second voltage terminal respectively, and is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the output control node and the second voltage terminal under the control of the potential of the second node. The driving circuit as described in claim 7, wherein, The ratio between the channel width-to-length ratio of the transistor included in the drive reset circuit and the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node included in the node control circuit is greater than or equal to 0.5 and less than or equal to 2. The driving circuit as described in claim 7, wherein, The ratio between the channel width-to-length ratio of the transistor whose gate is electrically connected to the first node in the node control circuit and the channel width-to-length ratio of the transistor in the drive control circuit is greater than or equal to 0.1 and less than or equal to 0.

3. The driving circuit as described in claim 7, wherein, It also includes an energy storage circuit; the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the output control node; or, the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth level carry output terminal. The driving circuit as described in claim 5, wherein, It also includes a node control circuit and a drive setting circuit; the drive circuit includes a second node; or, the drive circuit includes a first second node and a second second node; the node control circuit is electrically connected to the first node, the output control node, and the output clock signal terminal respectively, and is used to control the connection or disconnection between the output control node and the output clock signal terminal under the control of the potential of the first node; the drive setting circuit is electrically connected to the second node, the nth stage drive output terminal, and the third voltage terminal respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the third voltage terminal under the control of the potential of the second node. The driving circuit as described in claim 11, wherein, It also includes an energy storage circuit; the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the output control node; or, the first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the nth level carry output terminal. The driving circuit as described in claim 4, wherein, The drive reset circuit is located on the side of the carry output circuit away from the drive output circuit. The driving circuit as described in claim 10 or 12, wherein, The drive reset circuit is located on the side of the carry output circuit away from the transistor whose gate is electrically connected to the first node, which is part of the node control circuit. The driving circuit as described in any one of claims 2 to 6, wherein, It also includes a drive setting circuit; the drive circuit includes a second node; or, the drive circuit includes a first second node and a second second node; the drive setting circuit is electrically connected to the second node, the nth stage drive output terminal and the fourth voltage terminal respectively, and is used to control the connection or disconnection between the nth stage drive output terminal and the fourth voltage terminal under the control of the potential of the second node. The driving circuit according to any one of claims 1 to 12, wherein, It also includes a first node control circuit; the driving circuit includes a second node, or the driving circuit includes a first second node and a second second node; the first node control circuit is electrically connected to the first node, the input terminal, the reset terminal and the second node respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal, the reset signal provided by the reset terminal and the potential of the second node. The driving circuit as described in claim 1, wherein, The drive reset circuit includes a first transistor; the gate of the first transistor is electrically connected to the drive control terminal, the first electrode of the first transistor is electrically connected to the nth stage drive output terminal, and the second electrode of the first transistor is electrically connected to the first voltage terminal; the carry output circuit includes a second transistor; the gate of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the output clock signal terminal, and the second electrode of the second transistor is electrically connected to the nth stage carry output terminal. The driving circuit as described in claim 2, wherein, The drive output circuit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is electrically connected to the output clock signal terminal, and the second terminal of the third transistor is electrically connected to the nth stage drive output terminal. The driving circuit as described in claim 5, wherein, The drive control circuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the output control node, the first terminal of the fourth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fourth transistor is electrically connected to the nth stage drive output terminal. The driving circuit as described in claim 7, wherein, The node control circuit includes a fifth transistor and a sixth transistor; the driving circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; or, the node control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; the driving circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the sixth transistor is electrically connected to the first second node, the first terminal of the sixth transistor is electrically connected to the output control node, and the second terminal of the sixth transistor is electrically connected to a second voltage terminal; the gate of the seventh transistor is electrically connected to the second second node, the first terminal of the seventh transistor is electrically connected to the output control node, and the second terminal of the seventh transistor is electrically connected to a second voltage terminal. The driving circuit as described in claim 11, wherein, The node control circuit includes a fifth transistor, and the drive setting circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the third voltage terminal; or, the node control circuit includes a fifth transistor, and the drive setting circuit includes an eighth transistor and a ninth transistor; the drive... The circuit includes a first second node and a second second node; the gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the output control node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to the third voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to the third voltage terminal. The driving circuit as described in claim 15, wherein, The drive setting circuit includes an eighth transistor; the drive circuit includes a second node; the gate of the eighth transistor is electrically connected to the second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a fourth voltage terminal; or, the drive setting circuit includes an eighth transistor and a ninth transistor; the drive circuit includes a first second node and a second second node; the gate of the eighth transistor is electrically connected to the first second node, the first terminal of the eighth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the eighth transistor is electrically connected to a fourth voltage terminal; the gate of the ninth transistor is electrically connected to the second second node, the first terminal of the ninth transistor is electrically connected to the nth stage drive output terminal, and the second terminal of the ninth transistor is electrically connected to a fourth voltage terminal. A driving method, applied to a driving circuit as described in any one of claims 1 to 22, the driving method comprising: Under the control of the drive control signal, the drive reset circuit controls the connection or disconnection between the nth stage drive output terminal and the first voltage terminal; The carry-out circuit, under the control of the potential of the first node, controls whether the output clock signal terminal is connected or disconnected from the carry-out terminal of the nth stage; n is a positive integer. The driving method as described in claim 23, wherein, The display cycle includes a reset phase; the driving method includes: during the reset phase, the driving reset circuit, under the control of the driving control signal, controls the connection between the nth stage driving output terminal and the first voltage terminal. The driving method as described in claim 24, wherein, The display cycle includes an output phase set after the reset phase, and the pixel circuit further includes a drive output circuit; the driving method includes: in the output phase, the drive output circuit controls the connection between the nth stage drive output terminal and the output clock signal terminal under the control of the potential of the first node. A driving module includes multiple driving circuits as described in any one of claims 1 to 22. The drive module as described in claim 26, wherein, The driving circuit includes a carry output terminal, an input terminal, and a reset terminal; the carry output terminal of the a-th stage driving circuit is electrically connected to the input terminal of the (a+i)-th stage driving circuit; the reset terminal of the a-th stage driving circuit is electrically connected to the carry output terminal of the (a+p)-th stage driving circuit; a is a positive integer; i is not equal to j; i, j, and p are positive integers. A display device comprising the driving module as described in claim 26 or 27.

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