Display panel, manufacturing method thereof and display device

Abstract

The invention discloses a display panel and a manufacturing method thereof, and a display device. In the display panel, a gate drive circuit comprises multiple stages of cascaded shift registers; the shift register comprises a first output node (Q3), a second node (Q2), a first output sub-circuit (10) and a first output node control sub-circuit (11), the first output sub-circuit (10) is respectively coupled with a gate drive signal output end (OUT), a first output node (Q3) and a clock signal input end (GCK) of the shift register, and the clock signal input end (GCK) is coupled with a corresponding clock signal line; the first output node control sub-circuit (11) is respectively coupled with a second node (Q2), a first output node (Q3) and a first first level signal line (VGL11); the orthographic projection of the first first level signal line (VGL11) on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit (11) on the substrate and the orthographic projection of the clock signal line on the substrate.

Description

Display panel and its manufacturing method, display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411194864.1, filed in China on August 28, 2024, the entire contents of which are incorporated herein by reference.

[0003] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device.

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly wide, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. That is, the gate driving circuit is directly fabricated on the array substrate. The sub-pixel rows of the display area are driven by the shift registers of each level included in the gate driving circuit, thereby realizing the display function of the display product.

[0005] The purpose of this disclosure is to provide a display panel, a method for manufacturing the same, and a display device.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a display panel, comprising: a substrate, a gate driving circuit disposed on the substrate, a clock signal line, and a first level signal line; the gate driving circuit includes cascaded multi-stage shift registers; the shift registers include: a first output node, a second node, a first output sub-circuit, and a first output node control sub-circuit;

[0008] The first output sub-circuit is coupled to the gate drive signal output terminal of the shift register, the first output node and the first clock signal input terminal respectively, and the first clock signal input terminal is coupled to the corresponding clock signal line;

[0009] The first output node control sub-circuit is coupled to the second node, the first output node and the first first level signal line respectively;

[0010] The orthographic projection of the first level signal line on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit on the substrate and the orthographic projection of the clock signal line on the substrate.

[0011] Optionally, the shift register further includes: a first node, a fourth node, a fifth node, and a fourth node control sub-circuit; the display panel further includes a third level signal line;

[0012] The fourth node control sub-circuit is coupled to the first node, the fourth node, the fifth node, the fourth clock signal input terminal, and the third level signal line, respectively.

[0013] The fourth node control sub-circuit includes a transistor whose orthogonal projection on the substrate is located between the orthogonal projection of the third level signal line on the substrate and the orthogonal projection of the clock signal line on the substrate.

[0014] Optionally, the shift register further includes a second output node and a second output node control sub-circuit; the second output node control sub-circuit is coupled to the second output node and the fifth node respectively; at least a portion of the orthographic projection of the transistor included in the second output node control sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line on the substrate.

[0015] Optionally, the shift register further includes a second output sub-circuit; the display panel further includes a second level signal line;

[0016] The second output sub-circuit is coupled to the second output node, the second level signal line and the gate drive signal output terminal, respectively;

[0017] The orthographic projection of the transistor included in the second output sub-circuit on the substrate overlaps at least partially with the orthographic projection of the second level signal line on the substrate; the second level signal line is located on the side of the third level signal line closer to the display area of ​​the display panel.

[0018] Optionally, the shift register further includes a seventh node and a third isolation control sub-circuit; the third isolation control sub-circuit is coupled to the first first level signal line, the fifth node, and the seventh node respectively; at least a portion of the orthographic projection of the transistors included in the third isolation control sub-circuit on the substrate is located between the orthographic projection of the first first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate.

[0019] Optionally, the shift register further includes a sixth node and a second input sub-circuit; the display panel further includes a second first level signal line;

[0020] The second input sub-circuit is coupled to the third clock signal input terminal, the second first level signal line, the sixth node, and the seventh node, respectively; at least a portion of the orthographic projection of the transistor included in the second input sub-circuit onto the substrate is located between the orthographic projection of the second first level signal line onto the substrate and the orthographic projection of the third level signal line onto the substrate, and the second first level signal line is located on the side of the third level signal line away from the display area.

[0021] Optionally, the shift register further includes a seventh node control sub-circuit, which is coupled to the first node, the third clock signal input terminal and the seventh node respectively;

[0022] The display panel includes a first group of clock signal lines and a second group of clock signal lines. The first group of clock signal lines includes at least one clock signal line, and the second group of clock signal lines includes at least one clock signal line. The third level signal line is located between the first group of clock signal lines and the second group of clock signal lines. The clock signal line coupled to the first clock signal input terminal belongs to the second group of clock signal lines. The clock signal line coupled to the third clock signal input terminal belongs to the first group of clock signal lines.

[0023] The orthographic projection of the transistors included in the seventh node control sub-circuit onto the substrate overlaps at least partially with the orthographic projection of the clock signal lines in the first group of clock signal lines onto the substrate.

[0024] Optionally, the shift register further includes a cascaded output sub-circuit, which is coupled to the sixth node and the second node in the shift register, the third level signal line and the second clock signal input terminal in the display panel, respectively; the orthographic projection of the transistor included in the cascaded output sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line coupled to the first clock signal input terminal on the substrate.

[0025] Optionally, the cascaded output sub-circuit includes a first capacitor and a second capacitor; the first plate of the first capacitor is coupled to a sixth node, and the second plate of the first capacitor is coupled to a third-level signal line; the first plate of the second capacitor is coupled to a second node, and the second plate of the second capacitor is coupled to the cascaded signal output terminal; the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the third-level signal line on the substrate; and / or, the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the third-level signal line on the substrate.

[0026] Optionally, the cascaded output sub-circuit further includes a seventh transistor and an eighth transistor, wherein the first terminal of the seventh transistor is coupled to the third level signal line, and the second terminal of the seventh transistor is coupled to the cascaded signal output terminal; the first terminal of the eighth transistor is coupled to the second clock signal input terminal, and the second terminal of the eighth transistor is coupled to the cascaded signal output terminal.

[0027] The gate of the seventh transistor is multiplexed to at least a portion of the first plate of the first capacitor; and / or, the gate of the eighth transistor is multiplexed to at least a portion of the first plate of the second capacitor.

[0028] Optionally, the fourth node control sub-circuit includes a third capacitor, the first plate of the third capacitor being coupled to the fifth node, and the second plate of the third capacitor being coupled to the fourth node; the orthographic projection of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the first first level signal line on the substrate.

[0029] Optionally, the fourth node control sub-circuit further includes a twelfth transistor, the gate of which is coupled to the fifth node, and the first terminal of which is coupled to the fourth clock signal input terminal; and / or, the second output node control sub-circuit includes a fourteenth transistor, the gate of which is coupled to the fifth node, the first terminal of which is coupled to the fifth node, and the second terminal of which is coupled to the second output node;

[0030] The gate of the twelfth transistor is multiplexed to at least a portion of the first plate of the third capacitor; and / or, the gate of the fourteenth transistor is multiplexed to at least a portion of the first plate of the third capacitor.

[0031] Optionally, the shift register further includes a first input sub-circuit; the display panel further includes a start signal line; the first input sub-circuit is coupled to a third clock signal input terminal, a start signal input terminal, and a first node respectively; the start signal input terminal coupled to the first-stage shift register is coupled to the start signal line;

[0032] The orthographic projection of the transistor in the first input sub-circuit onto the substrate is located between the orthographic projection of the start signal line onto the substrate and the orthographic projection of the second first level signal line onto the substrate.

[0033] Optionally, the shift register further includes a first isolation control sub-circuit, which is coupled to the second first level signal line in the display panel, the first node and the second node of the shift register, respectively; the orthographic projection of the transistor included in the first isolation control sub-circuit on the substrate is located between the orthographic projection of the start signal line on the substrate and the orthographic projection of the second first level signal line on the substrate.

[0034] Optionally, the shift register further includes a sixth node control sub-circuit, which is coupled to the third clock signal input terminal, the first node and the sixth node in the shift register respectively; the orthographic projection of the transistor included in the sixth node control sub-circuit on the substrate is located between the orthographic projection of the start signal line on the substrate and the orthographic projection of the second first level signal line on the substrate.

[0035] Optionally, the cascaded signal output of the Nth stage shift register is used as the start signal input of the first input sub-circuit in the (N+2)th stage shift register; N is an integer greater than or equal to 1.

[0036] Optionally, the shift register further includes a first node control sub-circuit, which is coupled to the first node, the sixth node, the second clock signal input terminal, and the third level signal line in the display panel, respectively.

[0037] The orthographic projection of the transistor in the first node control sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line coupled to the second clock signal input terminal on the substrate.

[0038] Optionally, the shift register further includes a second isolation control sub-circuit and a fourth isolation control sub-circuit. The second isolation control sub-circuit is coupled to the first first-level signal line, the sixth node and the second output node in the shift register, respectively. The fourth isolation control sub-circuit is coupled to the first first-level signal line, the first node and the first output node in the shift register, respectively.

[0039] The orthographic projection of the transistor in the second isolation control sub-circuit onto the substrate overlaps with the orthographic projection of the clock signal line coupled to a portion of the first clock signal input terminal onto the substrate; and / or, the orthographic projection of the transistor in the fourth isolation control sub-circuit onto the substrate overlaps with the orthographic projection of the clock signal line coupled to a portion of the first clock signal input terminal onto the substrate.

[0040] Optionally, in the shift register, each sub-circuit includes a transistor, at least a portion of which includes a top gate layer, a bottom gate layer, and an active layer; the bottom gate layer, the active layer, and the top gate layer are sequentially stacked along a direction away from the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the bottom gate layer on the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the top gate layer on the substrate.

[0041] Optionally, in the same transistor, the bottom gate layer is coupled to the top gate layer.

[0042] Optionally, in the same transistor, the top gate layer and the bottom gate layer are independent of each other; the bottom gate layers of at least two transistors are coupled together, and the at least two transistors are coupled to a fixed potential signal terminal.

[0043] Optionally, the display panel includes a display area and a non-display area surrounding the display area, the display area including a light-shielding layer; in the same transistor, the top gate layer and the bottom gate layer are independent of each other, the bottom gate layers of at least two transistors are coupled together, and the bottom gate layers of the at least two transistors are coupled to the light-shielding layer.

[0044] Optionally, in the display panel, the second first-level signal line, the third level signal line, the first first-level signal line, and the second level signal line are arranged sequentially along the direction close to the display area of ​​the display panel.

[0045] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel.

[0046] Based on the above-described technical solution for the display panel, a third aspect of this disclosure provides a method for manufacturing a display panel, the method comprising:

[0047] A gate driving circuit, a clock signal line, and a first first-level signal line are fabricated on a substrate. The gate driving circuit includes cascaded multi-stage shift registers. The shift registers include a first output node, a second node, a first output sub-circuit, and a first output node control sub-circuit. The first output sub-circuit is coupled to the gate driving signal output terminal of the shift register, the first output node, and the clock signal input terminal, respectively. The clock signal input terminal is coupled to the corresponding clock signal line. The first output node control sub-circuit is coupled to the second node, the first output node, and the first first-level signal line, respectively. The orthographic projection of the first first-level signal line on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit on the substrate and the orthographic projection of the clock signal line on the substrate.

[0048] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0049] Figure 1 is a circuit schematic diagram of a shift register provided in an embodiment of this disclosure;

[0050] Figure 2 is a schematic cross-sectional view of the film layer of the display panel provided in an embodiment of this disclosure;

[0051] Figure 3 is a timing diagram of the shift register provided in an embodiment of this disclosure;

[0052] Figure 4 is a schematic diagram of the cascaded gate drive circuit provided in an embodiment of this disclosure;

[0053] Figure 5 is a schematic diagram of the layout of the bottom gate layer of the shift register according to the first embodiment of the present disclosure;

[0054] Figure 6 is a schematic diagram of the layout of the bottom gate layer of the shift register in the second embodiment provided in this disclosure;

[0055] Figure 7 is a schematic diagram of the layout of the bottom gate layer and active layer of the shift register in the second embodiment provided in this disclosure.

[0056] Figure 8 is a schematic diagram of the layout with the first gate metal layer added based on Figure 7;

[0057] Figure 9 is a schematic diagram of the layout of the first gate metal layer added in Figure 8;

[0058] Figure 10 is a schematic diagram of the layout with a second gate metal layer added to Figure 8;

[0059] Figure 11 is a schematic diagram of the layout of the second gate metal layer added in Figure 10;

[0060] Figure 12 is a schematic diagram of the layout with a third gate metal layer added based on Figure 10;

[0061] Figure 13 is a schematic diagram of the layout of the third gate metal layer added in Figure 12;

[0062] Figure 14 is a schematic diagram of the layout of adding vias through the interlayer insulation layer based on Figure 12;

[0063] Figure 15 is a schematic diagram of the layout of the vias that penetrate the interlayer insulation layer added in Figure 14;

[0064] Figure 16 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 14;

[0065] Figure 17 is a schematic diagram of the layout of the first source / drain metal layer added in Figure 16;

[0066] Figure 18 is a schematic diagram of the layout of adding vias through the passivation layer and the first planarization layer based on Figure 16;

[0067] Figure 19 is a schematic diagram of the layout of the vias added in Figure 18 that penetrate the passivation layer and the first planarization layer;

[0068] Figure 20 is a schematic diagram of the layout with a second source / drain metal layer added in Figure 18;

[0069] Figure 21 is a schematic diagram of the layout of the second source / drain metal layer added in Figure 20;

[0070] Figure 22 is a schematic diagram of the layout of the second gate metal layer of the shift register in the third embodiment provided in this disclosure;

[0071] Figure 23 is a schematic diagram of the layout of the source layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer in the shift register of the third embodiment provided in this disclosure;

[0072] Figure 24 is a schematic diagram of the layout of the bottom gate layer of the shift register in the fourth embodiment provided in this disclosure;

[0073] Figure 25 is a schematic diagram of the layout of the active layer of the shift register in the fourth embodiment provided in this disclosure;

[0074] Figure 26 is a schematic diagram of the layout of the first gate metal layer of the shift register in the fourth embodiment provided in this disclosure;

[0075] Figure 27 is a schematic diagram of the layout of the third gate metal layer and the first source / drain metal layer of the shift register in the fourth embodiment of the present disclosure.

[0076] Figure 28 is a schematic diagram of the layout of the bottom gate layer and the first source / drain metal layer of the shift register in the fourth embodiment provided in this disclosure.

[0077] Figure 29 is a schematic diagram of the layout of the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer of the shift register in the fourth embodiment of the present disclosure.

[0078] Figure 30 is a schematic diagram of the via layout of the shift register through the passivation layer and the first planarization layer in the fourth embodiment of the present disclosure.

[0079] Figure 31 is a schematic diagram of the layout of the second source-drain metal layer of the shift register in the fourth embodiment provided in this disclosure;

[0080] Figure 32 is a schematic diagram of the layout of the display area and non-display area of ​​the display panel provided in an embodiment of this disclosure.

[0081] To further illustrate the display panel, its manufacturing method, and the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0082] This disclosure provides a display panel, including a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes cascaded multi-stage shift registers. As shown in Figures 1 and 2, the shift registers adopt a 19T3C circuit structure, including first transistors T1 to nineteenth transistors T19, and first capacitor C1, second capacitor C2, and third capacitor C3. The shift registers can better maintain the stability of the signal output at the gate driving signal output terminal OUT. However, when arranging the above-mentioned shift registers, how to better achieve narrow bezels in display products has become an urgent technical problem to be solved.

[0083] As shown in Figures 1, 6 to 21, an embodiment of the present invention provides a display panel, including: a substrate, a gate driving circuit disposed on the substrate, a clock signal line and a first level signal line VGL11; the gate driving circuit includes cascaded multi-stage shift registers; the shift registers include: a first output node Q3, a second node Q2, a first output sub-circuit 10 and a first output node control sub-circuit 11;

[0084] The first output sub-circuit 10 is coupled to the gate drive signal output terminal OUT of the shift register, the first output node Q3 and the first clock signal input terminal GCK respectively. The first clock signal input terminal GCK is coupled to the corresponding clock signal line (e.g., GCK1 / GCK2 / GCK3 / GCK4).

[0085] The first output node control sub-circuit 11 is coupled to the second node Q2, the first output node Q3 and the first first level signal line VGL11 respectively;

[0086] The orthographic projection of the first first level signal line VGL11 on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit 11 on the substrate and the orthographic projection of the clock signal line on the substrate.

[0087] For example, the first output sub-circuit 10 is used to control the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK under the control of the potential of the first output node Q3. For example, the first output sub-circuit 10 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is coupled to the first output node Q3, the first terminal of the eleventh transistor T11 is coupled to the first clock signal input terminal GCK, and the second terminal of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT.

[0088] For example, at least a portion of the orthographic projection of the first output sub-circuit 10 onto the substrate is located on the side where the orthographic projection of the clock signal line onto the substrate is away from the orthographic projection of the third level signal line VGH onto the substrate.

[0089] For example, the first output node control sub-circuit 11, under the control of the second node Q2, controls the electrical connection between the first output node Q3 and the first first-level signal line VGL11 to be turned on or off. For example, the first output node control sub-circuit 11 includes a nineteenth transistor T19, the gate of the nineteenth transistor T19 is coupled to the second node Q2, the first terminal of the nineteenth transistor T19 is coupled to the first first-level signal line VGL11, and the second terminal of the nineteenth transistor T19 is coupled to the first output node Q3.

[0090] For example, the first first-level signal line VGL11 is used to transmit the first-level signal.

[0091] For example, along the direction close to the display area of ​​the display panel, the orthographic projections of the transistors included in the first output node control sub-circuit 11 on the substrate, the orthographic projections of the first first level signal line VGL11 on the substrate, and the orthographic projections of the clock signal line on the substrate are arranged in sequence.

[0092] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, the orthographic projection of the first first-level signal line VGL11 on the substrate is located between the orthographic projection of the transistors included in the first output node control sub-circuit 11 on the substrate and the orthographic projection of the clock signal line on the substrate. This not only makes the first output node control sub-circuit 11 closer to the first first-level signal line VGL11, which helps to reduce the connection difficulty between the first output node control sub-circuit 11 and the first first-level signal line VGL11, but also helps to narrow the overall layout space occupied by the shift register. Moreover, since the first first-level signal line VGL11 is used to transmit stable signals, this arrangement helps to shield the influence of clock signal changes transmitted by the clock signal line on the transistors included in the first output node control sub-circuit 11, ensuring the stability of the characteristics of the transistors included in the first output node control sub-circuit 11.

[0093] At the same time, at least a portion of the orthographic projection of the first output sub-circuit 10 on the substrate is located on the side where the orthographic projection of the clock signal line on the substrate is far from the orthographic projection of the third level signal line VGH on the substrate, so that the first output sub-circuit 10 can be arranged adjacent to the clock signal line coupled to it, which is beneficial to further narrow the layout space occupied by the shift register as a whole.

[0094] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes: a first node Q1, a fourth node GD, a fifth node QB3, and a fourth node control sub-circuit 15; the display panel further includes a third level signal line VGH; the fourth node control sub-circuit 15 is coupled to the first node Q1, the fourth node GD, the fifth node QB3, the fourth clock signal input terminal CKA2, and the third level signal line VGH, respectively;

[0095] The fourth node control sub-circuit 15 includes a transistor whose orthogonal projection on the substrate is located between the orthogonal projection of the third level signal line VGH on the substrate and the orthogonal projection of the clock signal line on the substrate.

[0096] For example, the fourth node control sub-circuit 15 is used to control the electrical connection between the fourth node GD and the third level signal line VGH under the control of the potential of the first node Q1; to control the potential of the fifth node QB3 according to the potential of the fourth node GD; and to control the electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 under the control of the potential of the fifth node QB3. For example, the fourth node control sub-circuit 15 includes a twelfth transistor T12, a thirteenth transistor T13, and a third capacitor C3. The gate of the twelfth transistor T12 is coupled to the fifth node QB3, the first terminal of the twelfth transistor T12 is coupled to the fourth clock signal input terminal CKA2, and the second terminal of the twelfth transistor T12 is coupled to the fourth node GD. The gate of the thirteenth transistor T13 is coupled to the first node Q1, the first terminal of the thirteenth transistor T13 is coupled to the third level signal line VGH, and the second terminal of the thirteenth transistor T13 is coupled to the fourth node GD. The first plate of the third capacitor C3 is coupled to the gate of the twelfth transistor T12, and the second plate of the third capacitor C3 is coupled to the fourth node GD.

[0097] For example, the third-level signal line VGH is used to transmit a third-level signal, and the clock signal line is used to transmit a corresponding clock signal.

[0098] In the display panel provided in the above embodiment, the orthographic projection of the transistors (twelfth transistor T12 and / or thirteenth transistor T13) included in the fourth node control sub-circuit 15 onto the substrate is located between the orthographic projection of the third level signal line VGH onto the substrate and the orthographic projection of the clock signal line onto the substrate. This makes the fourth node control sub-circuit 15 closer to the third level signal line VGH, which not only helps to reduce the connection difficulty between the fourth node control sub-circuit 15 and the third level signal line VGH, but also helps to narrow the overall layout space occupied by the shift register.

[0099] For example, the orthographic projection of the transistors included in the first output node control sub-circuit 11 onto the substrate is located between the orthographic projection of the third level signal line VGH onto the substrate and the orthographic projection of the first first level signal line VGL11 onto the substrate. For example, the orthographic projection of the first first level signal line VGL11 onto the substrate is located between the orthographic projection of the third level signal line VGH onto the substrate and the orthographic projection of the clock signal line onto the substrate. This arrangement allows the first output node control sub-circuit 11 to be centrally located with the fourth node control sub-circuit 15, which helps to reduce the overall layout space occupied by the shift register; simultaneously, it makes the first output node control sub-circuit 11 and its coupled first first level signal line VGL11 closer together, reducing the difficulty of connecting them.

[0100] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a second output node QB2 and a second output node control sub-circuit 16; the second output node control sub-circuit 16 is coupled to the second output node QB2 and the fifth node QB3 respectively; at least a portion of the orthographic projection of the transistors included in the second output node control sub-circuit 16 onto the substrate is located between the orthographic projection of the third level signal line VGH onto the substrate and the orthographic projection of the clock signal line onto the substrate.

[0101] For example, the second output node control sub-circuit 16 is used to control the electrical connection between the second output node QB2 and the fifth node QB3 under the control of the potential of the fifth node QB3. For example, the second output node control sub-circuit 16 includes a fourteenth transistor T14, the gate of the fourteenth transistor T14 is coupled to the fifth node QB3, the first terminal of the fourteenth transistor T14 is coupled to the fifth node QB3, and the second terminal of the fourteenth transistor T14 is coupled to the second output node QB2.

[0102] The above configuration allows the second output node control sub-circuit 16 to be centrally located with the fourth node control sub-circuit 15, which helps to reduce the overall layout space occupied by the shift register.

[0103] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a second output sub-circuit 14; the display panel further includes a second level signal line VGL2;

[0104] The second output sub-circuit 14 is coupled to the second output node QB2, the second level signal line VGL2 and the gate drive signal output terminal OUT, respectively;

[0105] The orthographic projection of the transistor included in the second output sub-circuit 14 on the substrate overlaps at least partially with the orthographic projection of the second level signal line VGL2 on the substrate; the second level signal line VGL2 is located on the side of the third level signal line VGH that is close to the display area of ​​the display panel.

[0106] For example, the second output sub-circuit 14 is used to control the electrical connection between the second level signal line VGL2 and the gate drive signal output terminal OUT under the control of the second output node QB2. The second output sub-circuit 14 includes a tenth transistor T10, the gate of which is coupled to the second output node QB2, the first terminal of which is coupled to the second level signal line VGL2, and the second terminal of which is coupled to the gate drive signal output terminal OUT.

[0107] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled signal lines, which is conducive to the development of narrow bezels in display panels.

[0108] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a seventh node QB4 and a third isolation control sub-circuit 18; the third isolation control sub-circuit 18 is coupled to the first first level signal line VGL11, the fifth node QB3 and the seventh node QB4 respectively; at least a portion of the orthographic projection of the transistors included in the third isolation control sub-circuit 18 onto the substrate is located between the orthographic projection of the first first level signal line VGL11 onto the substrate and the orthographic projection of the second level signal line VGL2 onto the substrate.

[0109] For example, at least a portion of the orthographic projection of the third isolation control sub-circuit 18 onto the substrate is located between the orthographic projection of the first first level signal line VGL11 onto the substrate and the orthographic projection of the clock signal line onto the substrate.

[0110] For example, the entire orthographic projection of the third isolation control sub-circuit 18 onto the substrate is located between the orthographic projection of the first first level signal line VGL11 onto the substrate and the orthographic projection of the clock signal line onto the substrate.

[0111] For example, the third isolation control sub-circuit 18 is used to control the electrical connection between the fifth node QB3 and the seventh node QB4 to be turned on or off under the control of the first level signal input to the first level signal line VGL11. For example, the third isolation control sub-circuit 18 includes a fifteenth transistor T15, the gate of the fifteenth transistor T15 is coupled to the first level signal line VGL11, the first terminal of the fifteenth transistor T15 is coupled to the seventh node QB4, and the second terminal of the fifteenth transistor T15 is coupled to the fifth node QB3.

[0112] The above arrangement allows the third isolation control sub-circuit 18 to be centrally located between the first first level signal line VGL11 and the second level signal line VGL2. The distance between the third isolation control sub-circuit 18 and the first first level signal line VGL11 is relatively short, which not only reduces the difficulty of connecting the third isolation control sub-circuit 18 to the first first level signal line VGL11, but also helps to narrow the overall layout space occupied by the shift register.

[0113] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a sixth node QB1 and a second input sub-circuit 19; the display panel further includes a second first level signal line VGL12.

[0114] The second input sub-circuit 19 is coupled to the third clock signal input terminal CKA, the second first level signal line VGL12, the sixth node QB1, and the seventh node QB4, respectively. At least a portion of the orthographic projection of the transistor included in the second input sub-circuit 19 onto the substrate is located between the orthographic projection of the second first level signal line VGL12 onto the substrate and the orthographic projection of the third level signal line VGH onto the substrate. The second first level signal line VGL12 is located on the side of the third level signal line VGH away from the display area.

[0115] For example, the second input sub-circuit 19 is used to control the electrical connection between the sixth node QB1 and the second first level signal line VGL12 under the control of the third clock signal input at the third clock signal input terminal CKA, and to control the electrical connection between the seventh node QB4 and the second first level signal line VGL12 under the control of the third clock signal input at the third clock signal input terminal CKA.

[0116] For example, the second input sub-circuit 19 includes a second transistor T2 and a seventeenth transistor T17; the gate of the second transistor T2 is coupled to the third clock signal input terminal CKA, the first terminal of the second transistor T2 is coupled to the second first level signal line VGL12, and the second terminal of the second transistor T2 is coupled to the sixth node QB1; the gate of the seventeenth transistor T17 is coupled to the third clock signal input terminal CKA, the first terminal of the seventeenth transistor T17 is coupled to the second first level signal line VGL12, and the second terminal of the seventeenth transistor T17 is coupled to the seventh node QB4.

[0117] For example, the orthographic projection of the seventeenth transistor T17 on the substrate at least partially overlaps with the orthographic projection of the second first level signal line VGL12 on the substrate; the orthographic projection of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the clock signal line coupled to the third clock signal input terminal CKA on the substrate.

[0118] The above arrangement makes the second input sub-circuit 19 adjacent to the second first level signal line VGL12 and the clock signal line coupled to the third clock signal input terminal CKA. This not only reduces the connection difficulty between the second input sub-circuit 19 and the second first level signal line VGL12 and the clock signal line coupled to the third clock signal input terminal CKA, but also helps to further narrow the overall layout space occupied by the shift register and its coupled signal lines, which is conducive to realizing the narrow bezel of the display panel.

[0119] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a seventh node control sub-circuit 112, which is coupled to the first node Q1, the third clock signal input terminal CKA and the seventh node QB4 respectively.

[0120] The display panel includes a first group of clock signal lines and a second group of clock signal lines. The first group of clock signal lines includes at least one clock signal line, and the second group of clock signal lines includes at least one clock signal line. The third level signal line VGH is located between the first group of clock signal lines and the second group of clock signal lines. The clock signal line coupled to the first clock signal input terminal GCK belongs to the second group of clock signal lines. The clock signal line coupled to the third clock signal input terminal CKA belongs to the first group of clock signal lines.

[0121] The orthographic projection of the transistors included in the seventh node control sub-circuit 112 onto the substrate overlaps at least partially with the orthographic projection of the clock signal lines in the first group of clock signal lines onto the substrate.

[0122] For example, the seventh node control sub-circuit 112 is used to control the electrical connection between the third clock signal input terminal CKA and the seventh node QB4 under the control of the potential of the first node Q1. For example, the seventh node control sub-circuit 112 includes an eighteenth transistor T18, the gate of which is coupled to the first node Q1, the first terminal of which is coupled to the third clock signal input terminal CKA, and the second terminal of which is coupled to the seventh node QB4.

[0123] For example, the second group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, a third clock signal line GCK3, and a fourth clock signal line GCK4; the first group of clock signal lines includes a fifth clock signal line CKA', a sixth clock signal line CKA2', a seventh clock signal line CKB', and an eighth clock signal line CKB2'. The inclusion of multiple clock signal lines in each group helps reduce RC loading on the clock signal lines.

[0124] For example, the line width of the clock signal lines included in the first group of clock signal lines may be the same as or different from the line width of the clock signal lines included in the second group of clock signal lines.

[0125] For example, the clock signal lines included in the first group of clock signal lines have the same line width.

[0126] For example, the clock signal lines included in the second set of clock signal lines have the same line width.

[0127] For example, the orthographic projection of the seventh node control sub-circuit 112 on the substrate overlaps at least partially with the orthographic projection of the fifth clock signal line CKA' on the substrate.

[0128] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0129] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a cascaded output sub-circuit 12, which is coupled to the sixth node QB1 and the second node Q2 in the shift register, the third level signal line VGH in the display panel, and the second clock signal input terminal CKB. The orthographic projection of the transistor included in the cascaded output sub-circuit 12 on the substrate is located between the orthographic projection of the third level signal line VGH on the substrate and the orthographic projection of the clock signal line coupled to the first clock signal input terminal GCK on the substrate.

[0130] For example, the cascaded output sub-circuit 12 includes a first capacitor C1 and a second capacitor C2; the first plate of the first capacitor C1 is coupled to a sixth node QB1, and the second plate of the first capacitor C1 is coupled to a third level signal line VGH; the first plate of the second capacitor C2 is coupled to a second node Q2, and the second plate of the second capacitor C2 is coupled to the cascaded signal output terminal CR; the orthographic projection of the second plate of the first capacitor C1 on the substrate at least partially overlaps with the orthographic projection of the third level signal line VGH on the substrate; and / or, the orthographic projection of the second plate of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the third level signal line VGH on the substrate.

[0131] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0132] For example, the cascaded output sub-circuit 12 further includes a seventh transistor T7 and an eighth transistor T8. The first terminal of the seventh transistor T7 is coupled to the third level signal line VGH, and the second terminal of the seventh transistor T7 is coupled to the cascaded signal output terminal CR. The first terminal of the eighth transistor T8 is coupled to the second clock signal input terminal CKB, and the second terminal of the eighth transistor T8 is coupled to the cascaded signal output terminal CR. The gate of the seventh transistor T7 is multiplexed to at least a portion of the first plate of the first capacitor C1. And / or, the gate of the eighth transistor T8 is multiplexed to at least a portion of the first plate of the second capacitor C2.

[0133] For example, the top gate layer g7 of the seventh transistor T7 is multiplexed as at least a portion of the first plate C11 of the first capacitor C1.

[0134] For example, the second plate C12 of the first capacitor C1 is coupled to the thirteenth adapter pattern 313 through the eightieth via V80, thereby achieving coupling with the third level signal line.

[0135] For example, the first plate C11 of the first capacitor C1 includes a first plate portion and a second plate portion, the top gate layer g7 of the seventh transistor T7 is multiplexed as at least a portion of the first plate portion, and the orthographic projection of the second plate portion on the substrate overlaps at least partially with the orthographic projection of the thirteenth transition pattern 313 on the substrate.

[0136] The above-mentioned configuration, in which the top gate layer g7 of the seventh transistor T7 is reused as at least a portion of the first plate C11 of the first capacitor C1, is beneficial to reducing the overall layout space occupied by the first capacitor C1 and the seventh transistor T7.

[0137] For example, the top gate layer g8 of the eighth transistor T8 is multiplexed as at least a portion of the first plate C21 of the second capacitor C2.

[0138] For example, the second plate C22 of the second capacitor C2 is coupled to the third adapter pattern 33 through the eighty-first via V81, and the third adapter pattern 33 serves as the cascaded signal output terminal CR of the shift register.

[0139] For example, the first output node control sub-circuit 11 includes a nineteenth transistor T19, the shift register further includes a first output node Q3, the first terminal of the nineteenth transistor T19 is coupled to a first first level signal line, the second terminal of the nineteenth transistor T19 is coupled to the first output node Q3; the top gate layer g19 of the nineteenth transistor T19 is multiplexed as at least a portion of the first plate C21 of the second capacitor C2.

[0140] For example, the first plate C21 of the second capacitor C2 includes a third plate portion, a fourth plate portion and a fifth plate portion, the top gate layer g8 of the eighth transistor T8 is multiplexed as at least a portion of the fourth plate portion, and the top gate layer g19 of the nineteenth transistor T19 is multiplexed as at least a portion of the fifth plate portion.

[0141] The above-mentioned configuration, in which the top gate layer g8 of the eighth transistor T8 is multiplexed as at least a portion of the first plate C21 of the second capacitor C2, and / or the top gate layer g19 of the nineteenth transistor T19 is multiplexed as at least a portion of the first plate C21 of the second capacitor C2, is beneficial to reducing the overall layout space occupied by the second capacitor C2, the eighth transistor T8, and the nineteenth transistor T19.

[0142] As shown in Figures 1, 6 to 21, in some embodiments, the fourth node control sub-circuit 15 includes a third capacitor C3, the first plate of the third capacitor C3 is coupled to the fifth node QB3, and the second plate of the third capacitor C3 is coupled to the fourth node GD; the orthographic projection of the second plate of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the first first level signal line VGL11 on the substrate.

[0143] For example, the fourth node control sub-circuit 15 further includes a twelfth transistor T12, the gate of which is coupled to the fifth node QB3, the first terminal of which is coupled to the fourth clock signal input terminal CKA2, and the first terminal of which is coupled to the fourth node GD; and / or, the second output node control sub-circuit 16 includes a fourteenth transistor T14, the gate of which is coupled to the fifth node QB3, the first terminal of which is coupled to the fifth node QB3, and the second terminal of which is coupled to the second output node QB2; the gate of the twelfth transistor T12 is multiplexed to at least a portion of the first plate of the third capacitor C3; and / or, the gate of the fourteenth transistor T14 is multiplexed to at least a portion of the first plate of the third capacitor C3.

[0144] For example, the top gate layer g12 of the twelfth transistor T12 is multiplexed as at least a portion of the first plate C31 of the third capacitor C3. For example, the second plate C32 of the third capacitor C3 is coupled to the fourteenth transition pattern 314 through the eighty-second via V82, the fourteenth transition pattern 314 serving as the fourth node GD.

[0145] For example, the second output node control sub-circuit 16 includes a fourteenth transistor T14, the first terminal of which is coupled to the fifth node QB3, and the second terminal of which is coupled to the second output node QB2; the top gate layer g14 of the fourteenth transistor T14 is multiplexed as at least a portion of the first plate C31 of the third capacitor C3.

[0146] For example, the first plate C31 of the third capacitor C3 includes a sixth plate portion, a seventh plate portion and an eighth plate portion, the top gate layer g12 of the twelfth transistor T12 is multiplexed as at least a portion of the sixth plate portion, and the top gate layer g14 of the fourteenth transistor T14 is multiplexed as at least a portion of the eighth plate portion.

[0147] For example, along the first direction, the seventh electrode portion is located between the sixth electrode portion and the eighth electrode portion, and along the second direction, the width of the seventh electrode portion is greater than the width of the sixth electrode portion and the width of the eighth electrode portion.

[0148] The above-mentioned configuration, in which the top gate layer g12 of the twelfth transistor T12 is multiplexed as at least a portion of the first plate C31 of the third capacitor C3, and / or the top gate layer g14 of the fourteenth transistor T14 is multiplexed as at least a portion of the first plate C31 of the third capacitor C3, is beneficial to reducing the overall layout space occupied by the third capacitor C3, the twelfth transistor T12, and the fourteenth transistor T14.

[0149] The above-mentioned arrangement of the second plate of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the first level signal line VGL11 on the substrate, which is beneficial to further narrow the layout space occupied by the shift register and its coupled clock signal line, and is beneficial to realizing the narrow bezel of the display panel.

[0150] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a first input sub-circuit 110; the display panel further includes a start signal line STV'; the first input sub-circuit 110 is coupled to the third clock signal input terminal CKA, the start signal input terminal STV, and the first node Q1, respectively; the start signal input terminal STV of the first-stage shift register is coupled to the start signal line STV'; the orthographic projection of the transistor included in the first input sub-circuit 110 on the substrate is located between the orthographic projection of the start signal line STV' on the substrate and the orthographic projection of the second first level signal line VGL12 on the substrate.

[0151] For example, the first input sub-circuit 110 is used to control the electrical connection between the start signal input terminal STV and the first node Q1 under the control of the third clock signal input terminal CKA. The first input sub-circuit 110 includes a first transistor T1, the gate of the first transistor T1 is coupled to the third clock signal input terminal CKA, the first terminal of the first transistor T1 is coupled to the start signal input terminal STV, and the second terminal of the first transistor T1 is coupled to the first node Q1.

[0152] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0153] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a first isolation control sub-circuit 13, which is coupled to the second first level signal line VGL12 in the display panel, the first node Q1 and the second node Q2 of the shift register, respectively; the orthographic projection of the transistor included in the first isolation control sub-circuit 13 on the substrate is located between the orthographic projection of the start signal line STV' on the substrate and the orthographic projection of the second first level signal line VGL12 on the substrate.

[0154] For example, the first isolation control sub-circuit 13 is used to control the electrical connection between the first node Q1 and the second node Q2 to be turned on or off under the control of the second first level signal line VGL12. The first isolation control sub-circuit 13 includes a sixth transistor T6, the gate of the sixth transistor T6 is coupled to the second first level signal line VGL12, the first terminal of the sixth transistor T6 is coupled to the first node Q1, and the second terminal of the sixth transistor T6 is coupled to the second node Q2.

[0155] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0156] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a sixth node control sub-circuit 111, which is coupled to the third clock signal input terminal CKA, the first node Q1 and the sixth node QB1 in the shift register, respectively. The orthographic projection of the transistor included in the sixth node control sub-circuit 111 on the substrate is located between the orthographic projection of the start signal line STV' on the substrate and the orthographic projection of the second first level signal line VGL12 on the substrate.

[0157] For example, the sixth node control sub-circuit 111 is used, under the control of the first node Q1, to control the electrical connection between the sixth node QB1 and the third clock signal input terminal CKA to be turned on or off. The sixth node control sub-circuit 111 includes a third transistor T3, the gate of the third transistor T3 is coupled to the first node Q1, the first terminal of the third transistor T3 is coupled to the third clock signal input terminal CKA, and the second terminal of the third transistor T3 is coupled to the sixth node QB1.

[0158] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0159] As shown in Figures 1, 6 to 21, in some embodiments, the cascaded signal output terminal CR of the Nth stage shift register is used as the start signal input terminal STV coupled to the first input sub-circuit 110 in the N+2th stage shift register; N is an integer greater than or equal to 1.

[0160] For example, the display panel further includes a first source-drain metal layer and a second source-drain metal layer; the first terminal of the first transistor T1 in the N+2th stage shift register is coupled to the cascaded signal output terminal CR of the Nth stage shift register in sequence through a first transition pattern 31 and a second transition pattern 32; the first transition pattern 31 extends along a first direction, the second transition pattern 32 extends along a second direction, and the second direction intersects with the first direction; the first transition pattern 31 and the first source-drain metal layer are disposed in the same layer and with the same material, and / or the second transition pattern 32 and the second source-drain metal layer are disposed in the same layer and with the same material.

[0161] The above configuration not only avoids short circuits between the second transition pattern 32 and the functional structures located in the first source flow metal layer, but also helps to reduce the layout difficulty of the shift register in a limited layout space.

[0162] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a first node control sub-circuit 113, which is coupled to the first node Q1, the sixth node QB1, the second clock signal input terminal CKB, and the third level signal line VGH in the display panel, respectively. The orthographic projection of the transistor included in the first node control sub-circuit 113 on the substrate is located between the orthographic projection of the third level signal line VGH on the substrate and the orthographic projection of the clock signal line coupled to the second clock signal input terminal CKB on the substrate.

[0163] For example, the first node control sub-circuit 113 is used to control the electrical connection between the third level signal line VGH and the first node Q1 under the control of the sixth node QB1 and the second clock signal input terminal CKB. The first node control sub-circuit 113 includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is coupled to the sixth node QB1, the first terminal of the fourth transistor T4 is coupled to the third level signal line VGH, the second terminal of the fourth transistor T4 is coupled to the first terminal of the fifth transistor T5, the second terminal of the fifth transistor T5 is coupled to the first node Q1, and the gate of the fifth transistor T5 is coupled to the second clock signal input terminal CKB.

[0164] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0165] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a second isolation control sub-circuit 17 and a fourth isolation control sub-circuit 114. The second isolation control sub-circuit 17 is coupled to the first first level signal line VGL11, the sixth node QB1 and the second output node QB2 in the shift register, respectively; the fourth isolation control sub-circuit 114 is coupled to the first first level signal line VGL11, the first node Q1 and the first output node Q3 in the shift register, respectively.

[0166] The orthographic projection of the transistors included in the second isolation control sub-circuit 17 onto the substrate overlaps with the orthographic projection of a portion of the clock signal line coupled to the first clock signal input terminal GCK onto the substrate; and / or, the orthographic projection of the transistors included in the fourth isolation control sub-circuit 114 onto the substrate overlaps with the orthographic projection of a portion of the clock signal line coupled to the first clock signal input terminal GCK onto the substrate.

[0167] For example, the second isolation control sub-circuit 17 is used to control the electrical connection between the sixth node QB1 and the second output node QB2 under the control of the first level signal line VGL11. The second isolation control sub-circuit 17 includes a ninth transistor T9, the gate of the ninth transistor T9 is coupled to the first level signal line VGL11, the first terminal of the ninth transistor T9 is coupled to the sixth node QB1, and the second terminal of the ninth transistor T9 is coupled to the second output node QB2.

[0168] For example, the fourth isolation control sub-circuit 114 is used to control the electrical connection between the first node Q1 and the first output node Q3 to be turned on or off under the control of the first first level signal line VGL11. The fourth isolation control sub-circuit 114 includes a sixteenth transistor T16, the gate of the sixteenth transistor T16 is coupled to the first first level signal line VGL11, the first terminal of the sixteenth transistor T16 is coupled to the first node Q1, and the second terminal of the sixteenth transistor T16 is coupled to the first output node Q3.

[0169] The above configuration helps to further reduce the overall layout space occupied by the shift register and its coupled clock signal line, which is beneficial to achieving a narrow bezel for the display panel.

[0170] In the display field, especially in OLED displays, LTPS (Low-Temperature Polycrystalline Silicon) PMOS transistors remain the primary transistor type used in GOA (Gate of Array) design due to their higher mobility compared to Oxide transistors. The development of LTPO+ is becoming increasingly urgent. In the sub-pixel driving circuit of LTPO+ products, the transistor controlling the gate of the driving transistor to write data signals is an oxide transistor. This oxide transistor requires a high-voltage pulse with a pulse width of less than 1H or around 1.5H as the shift voltage (i.e., the voltage of the gate drive signal output by the shift register) as the control signal. The shift register that outputs this shift voltage is called NGate GOA. How to use a P-type transistor to output the high-voltage shift pulse is crucial, and maintaining a stable low potential in the output waveform is equally important. However, the stability of the gate drive signal output by existing shift registers is poor. Improving the stability of the gate drive signal output by the shift register has become a pressing technical problem.

[0171] As shown in Figures 1, 6 to 21, in some embodiments, each sub-circuit in the shift register includes a transistor, and at least some of the transistors include a top gate layer, a bottom gate layer, and an active layer; the bottom gate layer, the active layer, and the top gate layer are stacked sequentially along a direction away from the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the bottom gate layer on the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the top gate layer on the substrate.

[0172] In the display panel provided in the above embodiments, by setting at least some transistors in the shift register to include a top gate layer and a bottom gate layer, not only can the bottom gate layer shield the influence of induced charges on the substrate on the transistor channel, but it can also improve the characteristic performance of the transistor after reliability testing, making the transistor characteristics more stable. This effectively improves the stability of the gate drive signal output by the shift register, thereby further improving the display effect of the display panel.

[0173] As shown in Figures 1, 6 to 21, in some embodiments, the bottom gate layer and the top gate layer are coupled in the same transistor.

[0174] For example, the transistor includes an LTPS PMOS transistor, but is not limited to this.

[0175] For example, at least a portion of the transistor employs a dual-gate structure, including a top gate layer, a bottom gate layer, and an active layer; the active layer includes a channel portion, the orthographic projection of the channel portion on the substrate being located inside the orthographic projection of the top gate layer on the substrate, and the orthographic projection of the channel portion on the substrate being located inside the orthographic projection of the bottom gate layer on the substrate.

[0176] In the display panel provided in the above embodiments, by setting at least some transistors in the shift register to include a top gate layer and a bottom gate layer, and the top gate layer and the bottom gate layer being coupled together, not only can the bottom gate layer shield the influence of induced charges on the substrate on the transistor channel, but it can also improve the characteristic performance of the transistor after reliability testing, making the transistor characteristics more stable. This effectively improves the stability of the gate drive signal output by the shift register, thereby further improving the display effect of the display panel.

[0177] As shown in Figures 1, 6 to 21, in some embodiments, the bottom gate layer is coupled to the top gate layer through a conductive connection portion, the conductive connection portion and the bottom gate layer are disposed on different layers, the conductive connection portion is coupled to the bottom gate layer through a first via structure, the conductive connection portion and the top gate layer are disposed on different layers, the conductive connection portion is coupled to the top gate layer through a second via structure, and the orthographic projection of the first via structure on the substrate and the orthographic projection of the second via structure on the substrate do not overlap.

[0178] As shown in Figure 2, exemplarily, the display panel includes, sequentially stacked along a direction away from the substrate 70, a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc. The display panel may also include a passivation layer PVX, but is not limited to this.

[0179] For example, the bottom gate layer may be located between the buffer layer BF and the active layer poly.

[0180] For example, the conductive connection portion is disposed in the same layer and with the same material as the first source / drain metal layer SD1, but is not limited thereto.

[0181] The conductive connection portion is coupled to the bottom gate layer through a first via structure and to the top gate layer through a second via structure. The orthographic projection of the first via structure on the substrate and the orthographic projection of the second via structure on the substrate do not overlap, which not only enables the bottom gate layer and the top gate layer of the transistor to be coupled together, but also ensures the reliability of the via connection.

[0182] As shown in Figures 1, 6 to 21, in some embodiments... In the shift register, the first The first terminal of transistor T1 is coupled to the start signal input terminal STV, and the second terminal of the first transistor is coupled to the first node Q1; the first terminal of the second transistor T2 is coupled to the second first level signal line, and the second terminal of the second transistor T2 is coupled to the sixth node QB1; the bottom gate layer b1 of the first transistor T1 is coupled to the bottom gate layer b2 of the second transistor T2, and / or, the top gate layer g1 of the first transistor T1 is coupled to the top gate layer g2 of the second transistor T2.

[0183] For example, the bottom gate layer b1 of the first transistor T1 and the bottom gate layer b2 of the second transistor T2 are formed as an integral structure, and / or the top gate layer g1 of the first transistor T1 and the top gate layer g2 of the second transistor T2 are formed as an integral structure.

[0184] For example, the start signal input terminal STV coupled to the first transistor T1 in the first-stage shift register and the second-stage shift register can be selected as the start signal line, and the start signal input terminal STV coupled to the first transistor T1 in the Nth-stage shift register can be selected as the cascaded signal output terminal CR of the (N-2)th-stage shift register, where N is an integer greater than 2.

[0185] In the Nth stage shift register, the first terminal of the first transistor T1 is coupled to the first transition pattern 31 through the fourth via V4. The first transition pattern 31 is coupled to the second transition pattern 32 through the fifth via V5. The second transition pattern 32 is coupled to the third transition pattern 33 through the sixth via V6. The third transition pattern 33 serves as the cascade signal output terminal CR of the (N-2)th stage shift register. The cascade signal output terminal CR of the (N-2)th stage shift register serves as the start signal input terminal STV of the Nth stage shift register. The second terminal of the first transistor T1 is coupled to the fourth transition pattern 34 through the eighth via V8. The fourth transition pattern 34 serves as the first node Q1.

[0186] The first terminal of the second transistor T2 is coupled to the fifth transition pattern 35 through the ninth via V9. The fifth transition pattern 35 is coupled to the first level signal line through the tenth via V10. The first level signal line can be selected as the first low level signal line. The second terminal of the second transistor T2 is coupled to the sixth transition pattern 36 through the eleventh via V11. The sixth transition pattern 36 serves as the sixth node QB1.

[0187] For example, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are arranged along a first direction. The active layer 21 of the first transistor T1 is formed into a U-shaped structure, forming two channel portions arranged along the first direction. The active layer 22 of the second transistor T2 includes strips extending along a second direction. By setting the active layer 21 of the first transistor T1 into a U-shaped structure, the channels of the two sub-transistors formed by the first transistor T1 are in the same direction, that is, the channel directions of the two sub-transistors are the same. In this way, the electric field direction and the carrier movement direction are consistent during current conduction. This consistency can reduce the difference in carrier mobility caused by electric fields in different directions in the channel, thereby effectively improving the uniformity of the channel in the same direction.

[0188] The above-mentioned configuration couples the bottom gate layer b1 of the first transistor T1 with the bottom gate layer b2 of the second transistor T2, and / or couples the top gate layer g1 of the first transistor T1 with the top gate layer g2 of the second transistor T2, so that the first transistor T1 and the second transistor T2 can share a single conductive connection. This helps to reduce the number of conductive connections and the number of vias required, thereby reducing the overall layout space occupied by the shift register and better adapting to the narrow bezel requirements of the display panel.

[0189] As shown in Figures 1, 6 to 21, in some embodiments, the bottom gate layer b1 of the first transistor T1 and the bottom gate layer b2 of the second transistor T2 are formed as a first bottom gate portion of an integral structure; the top gate layer g1 of the first transistor T1 and the top gate layer g2 of the second transistor T2 are formed as a first top gate portion of an integral structure; the shift register includes a first conductive connection portion 41, and the first bottom gate portion is coupled to the first top gate portion through the first conductive connection portion 41; the first conductive connection portion 41 is also coupled to a third clock signal input terminal CKA.

[0190] For example, the first conductive connection portion 41 is coupled to the first bottom gate portion through the second via V2 and to the first top gate portion through the first via V1.

[0191] For example, in some shift registers, the first conductive connection portion 41 is also coupled to the third clock signal input terminal CKA via a third via V3. In some shift registers, the first top gate portion is coupled to the twenty-sixth transition pattern 326 via an eighty-fifth via V85, and the twenty-sixth transition pattern 326 is coupled to the third clock signal input terminal CKA via an eighty-fourth via V84.

[0192] For example, the first bottom gate portion includes at least a portion extending along a first direction, and the first bottom gate portion includes a widened portion; the first top gate portion includes at least a portion extending along the first direction, and the first top gate portion includes a narrowed portion and first top gate portions located on both sides of the narrowed portion, the width of the first top gate portions along a second direction is greater than the width of the narrowed portion, and the second direction intersects the first direction; the orthographic projection of the widened portion on the substrate and the orthographic projection of the narrowed portion on the substrate are arranged along the second direction; the first conductive connection portion 41 is coupled to the widened portion and one of the first top gate portions respectively.

[0193] The above configuration can minimize the layout space occupied by the first transistor T1, the second transistor T2 and the first conductive connection portion 41, while ensuring the connection performance between the first conductive connection portion 41 and the first bottom gate portion and the first top gate portion.

[0194] As shown in Figures 1, 6 to 21, and 25, in some embodiments, in the shift register, the first terminal of the seventeenth transistor T17 is coupled to the second first level signal line, the second terminal of the seventeenth transistor T17 is coupled to the seventh node QB4, the bottom gate layer b17 of the seventeenth transistor T17 is coupled to the bottom gate layer b2 of the second transistor T2; and / or, the top gate layer g17 of the seventeenth transistor T17 is coupled to the top gate layer g2 of the second transistor T2.

[0195] For example, the first terminal of the seventeenth transistor T17 is coupled to the fifth transition pattern 35 through the twelfth via V12, thereby achieving coupling with the first level signal line; the second terminal of the seventeenth transistor T17 is coupled to the seventh transition pattern 37 through the thirteenth via V13, and the seventh transition pattern 37 serves as the seventh node QB4.

[0196] For example, the bottom gate layer b17 of the seventeenth transistor T17 and the bottom gate layer b2 of the second transistor T2 are formed as an integral structure; and / or, the top gate layer g17 of the seventeenth transistor T17 and the top gate layer g2 of the second transistor T2 are formed as an integral structure.

[0197] For example, the active layer 217 of the seventeenth transistor T17, the active layer 22 of the second transistor T2, and the active layer 21 of the first transistor T1 are arranged sequentially along a first direction. For example, the active layer 217 of the seventeenth transistor T17 includes a strip extending along the second direction.

[0198] The above configuration allows the first transistor T1, the second transistor T2, and the seventeenth transistor T17 to share a first conductive connection portion 41, which helps to reduce the number of conductive connections and the number of vias required, thereby reducing the overall layout space occupied by the shift register and better adapting to the narrow bezel requirements of the display panel.

[0199] As shown in Figures 1, 6 to 21, in some embodiments, in the shift register, the first terminal of the third transistor T3 is coupled to the first conductive connection 41, and the second terminal of the third transistor T3 is coupled to the sixth node QB1; the first terminal of the eighteenth transistor T18 is coupled to the first conductive connection 41, and the second terminal of the eighteenth transistor T18 is coupled to the seventh node QB4; the bottom gate layer b3 of the third transistor T3 is coupled to the bottom gate layer b18 of the eighteenth transistor T18, and / or, the top gate layer g3 of the third transistor T3 is coupled to the top gate layer g18 of the eighteenth transistor T18.

[0200] For example, the first terminal of the third transistor T3 is coupled to the first conductive connection portion 41 through the fourteenth via V14, and the second terminal of the third transistor T3 is coupled to the sixth transition pattern 36 through the fifteenth via V15, the sixth transition pattern 36 serving as the sixth node QB1; the first terminal of the eighteenth transistor T18 is coupled to the first conductive connection portion 41 through the sixteenth via V16, and the second terminal of the eighteenth transistor T18 is coupled to the seventh transition pattern 37 through the seventeenth via V17, the seventh transition pattern 37 serving as the seventh node QB4.

[0201] For example, the active layer 23 of the third transistor T3 includes a strip extending along a second direction, the active layer 218 of the eighteenth transistor T18 includes a strip extending along a second direction, and the active layer 23 of the third transistor T3 and the active layer 218 of the eighteenth transistor T18 are arranged along a first direction.

[0202] The above configuration allows the third transistor T3 and the eighteenth transistor T18 to share a single conductive connection, which helps reduce the number of conductive connections and the number of vias required. This, in turn, helps to reduce the overall layout space occupied by the shift register and better adapt to the narrow bezel requirements of the display panel.

[0203] As shown in Figures 1, 6 to 21, in some embodiments, the bottom gate layer b3 of the third transistor T3 and the bottom gate layer b18 of the eighteenth transistor T18 are formed as a second bottom gate portion of an integral structure; the top gate layer g3 of the third transistor T3 and the top gate layer g18 of the eighteenth transistor T18 are formed as a second top gate portion of an integral structure; the shift register includes a second conductive connection portion 42, the second bottom gate portion is coupled to the second top gate portion through the second conductive connection portion 42; the second conductive connection portion 42 is also coupled to the first node Q1.

[0204] For example, the second conductive connection portion 42 is coupled to the second top gate portion through the eighteenth via V18 and to the second bottom gate portion through the nineteenth via V19; the second conductive connection portion 42 is reused as the fourth transition pattern 34, serving as the first node Q1.

[0205] For example, the second bottom gate portion includes at least a portion extending along the first direction, and the second top gate portion includes at least a portion extending along the first direction.

[0206] The above configuration can minimize the layout space occupied by the third transistor T3, the eighteenth transistor T18 and the second conductive connection part 42, while ensuring the connection performance between the second conductive connection part 42 and the second bottom gate part and the second top gate part, and facilitating the connection between the third transistor T3 and the eighteenth transistor T18 and the first node Q1.

[0207] As shown in Figures 1, 6 to 21, in some embodiments, in the shift register, the first terminal of the sixth transistor T6 is coupled to the first node Q1, the second terminal of the sixth transistor T6 is coupled to the second node Q2; the bottom gate layer b6 of the sixth transistor T6 is coupled to the top gate layer g6 of the sixth transistor T6.

[0208] For example, the shift register further includes a third conductive connection portion 43, through which the bottom gate layer b6 of the sixth transistor T6 is coupled to the top gate layer g6 of the sixth transistor T6, and the third conductive connection portion 43 is also coupled to a first level signal line.

[0209] For example, the third conductive connection portion 43 is coupled to the top gate layer g6 of the sixth transistor T6 through the twentieth via V20, the third conductive connection portion 43 is coupled to the bottom gate layer b6 of the sixth transistor T6 through the twentieth via V21, the third conductive connection portion 43 is coupled to the eighth transition pattern 38 through the twentieth via V22, the eighth transition pattern 38 is coupled to the ninth transition pattern 39 through the twentieth via V23, and the ninth transition pattern 39 is coupled to the first level signal line through the twentieth via V24.

[0210] The first electrode of the sixth transistor T6 is coupled to the second conductive connection part 42 through the twenty-fifth via V25, and the second conductive connection part 42 serves as the first node Q1. The second electrode of the sixth transistor T6 is coupled to the fourth conductive connection part 44 through the twenty-sixth via V26, and the fourth conductive connection part 44 serves as the second node Q2.

[0211] For example, the active layer 26 of the sixth transistor T6 includes a strip extending along a second direction. The active layer 26 of the sixth transistor T6 is aligned with the active layer 21 of the first transistor T1 along the second direction. The active layer 26 of the sixth transistor T6 and the active layer 21 of the first transistor T1 are at least partially offset along a first direction.

[0212] For example, the first direction includes the lateral direction, and the second direction includes the longitudinal direction, but is not limited thereto.

[0213] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0214] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a fourth conductive connection portion 44; the first terminal of the eighth transistor T8 is coupled to the second clock signal input terminal CKB, and the second terminal of the eighth transistor T8 is coupled to the cascaded signal output terminal CR; the bottom gate layer b8 of the eighth transistor T8 is coupled to the top gate layer g8 of the eighth transistor T8 through the fourth conductive connection portion 44.

[0215] For example, the first terminal of the eighth transistor T8 is coupled to the fifth conductive connection portion 45 through the twenty-eighth via V28, the fifth conductive connection portion 45 is coupled to the second clock signal input terminal CKB, and the second terminal of the eighth transistor T8 is coupled to the third transition pattern 33 through the seventh via V7, the third transition pattern 33 serving as the cascaded signal output terminal CR.

[0216] The fourth conductive connection portion 44 is coupled to the top gate layer g8 of the eighth transistor T8 through the twenty-ninth via V29, and to the bottom gate layer b8 of the eighth transistor T8 through the thirtieth via V30.

[0217] For example, the active layer 28 of the eighth transistor T8 includes a strip extending along a second direction.

[0218] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0219] As shown in Figures 1, 6 to 21, in some embodiments, in the shift register, the first terminal of the nineteenth transistor T19 is coupled to the first level signal line, and the second terminal of the nineteenth transistor T19 is coupled to the first output node Q3; the bottom gate layer b19 of the nineteenth transistor T19 is coupled to the bottom gate layer b8 of the eighth transistor T8, and the top gate layer g19 of the nineteenth transistor T19 is coupled to the top gate layer g8 of the eighth transistor T8.

[0220] For example, the first terminal of the nineteenth transistor T19 is coupled to the ninth conductive connection 49 through the twenty-seventh via V27, the ninth conductive connection 49 is coupled to the first level signal line, and the second terminal of the nineteenth transistor T19 is coupled to the tenth transition pattern through the thirty-first via V31, the tenth transition pattern 310 serving as the first output node Q3.

[0221] The bottom gate layer b19 of the nineteenth transistor T19 and the bottom gate layer b8 of the eighth transistor T8 are formed into an integral structure, and the top gate layer g19 of the nineteenth transistor T19 and the top gate layer g8 of the eighth transistor T8 are formed into an integral structure.

[0222] For example, the active layer 219 of the nineteenth transistor T19 includes a strip extending along a second direction.

[0223] For example, the active layer 219 of the nineteenth transistor T19 and the active layer 28 of the eighth transistor T8 are arranged along a first direction.

[0224] The above configuration allows the nineteenth transistor T19 and the eighth transistor T8 to share a single conductive connection, which helps reduce the number of conductive connections and the number of vias required. This, in turn, helps to reduce the overall layout space occupied by the shift register and better adapt to the narrow bezel requirements of the display panel.

[0225] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a fifth conductive connection portion 45. The first terminal of the fourth transistor T4 is coupled to the third level signal line VGH, the second terminal of the fourth transistor T4 is coupled to the first terminal of the fifth transistor T5, and the second terminal of the fifth transistor T5 is coupled to the first node Q1. The bottom gate layer b5 of the fifth transistor T5 is coupled to the top gate layer g5 of the fifth transistor T5 through the fifth conductive connection portion 45. The top gate layer g5 of the fifth transistor T5 is coupled to the second clock signal input terminal CKB.

[0226] For example, the second terminal of the fifth transistor T5 is coupled to the second conductive connection portion 42 through the thirty-second via V32, and the second conductive connection portion 42 serves as the first node Q1; the fifth conductive connection portion 45 is coupled to the top gate layer g5 of the fifth transistor T5 through the thirty-third via V33, and to the bottom gate layer b5 of the fifth transistor T5 through the thirty-fourth via V34; the top gate layer g5 of the fifth transistor T5 and the twelfth transition pattern 312 are formed as an integral structure, the twelfth transition pattern 312 is coupled to the eleventh transition pattern 311 through the thirty-fifth via V35, and the eleventh transition pattern 311 is coupled to the second clock signal input terminal CKB through the thirty-sixth via V36.

[0227] For example, the active layer 25 of the fifth transistor T5 includes a strip extending along the second direction, and the active layer 24 of the fourth transistor T4 includes a strip extending along the second direction. The active layer 25 of the fifth transistor T5 and the active layer 24 of the fourth transistor T4 are arranged along the second direction, and the active layer 25 of the fifth transistor T5 and the active layer 24 of the fourth transistor T4 are formed into an integral structure.

[0228] For example, the active layer 25 of the fifth transistor T5, the active layer 28 of the eighth transistor T8, and the active layer 219 of the nineteenth transistor T19 are arranged sequentially along the first direction.

[0229] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0230] As shown in Figures 1, 6 to 21, in some embodiments, the shift register further includes a sixth conductive connection portion 46. The first terminal of the seventh transistor T7 is coupled to the third level signal line VGH, and the second terminal of the seventh transistor T7 is coupled to the cascaded signal output terminal CR. The bottom gate layer b7 of the seventh transistor T7 and the bottom gate layer b4 of the fourth transistor T4 form a third bottom gate portion of an integral structure. The top gate layer g7 of the seventh transistor T7 and the top gate layer g4 of the fourth transistor T4 form a third top gate portion of an integral structure. The third bottom gate portion is coupled to the third top gate portion through the sixth conductive connection portion 46, and the sixth conductive connection portion 46 is coupled to the sixth node QB1.

[0231] For example, the active layer 27 of the seventh transistor T7 includes a strip extending along a second direction.

[0232] For example, the active layer 27 of the seventh transistor T7 and the active layer 28 of the eighth transistor T8 are arranged along a second direction. The active layer 27 of the seventh transistor T7 and the active layer 28 of the eighth transistor T8 are formed as a single structure.

[0233] For example, the active layer 24 of the fourth transistor T4 and the active layer 27 of the seventh transistor T7 are arranged along a first direction.

[0234] The above configuration allows the fourth transistor T4 and the seventh transistor T7 to share a single conductive connection, which helps reduce the number of conductive connections and the number of vias required. This, in turn, helps to reduce the overall layout space occupied by the shift register and better adapt to the narrow bezel requirements of the display panel.

[0235] As shown in Figures 1, 6 to 21, in some embodiments, the third bottom gate portion includes at least a portion extending along the first direction, and the third bottom gate portion includes a first bottom gate portion, a second bottom gate portion, and a third bottom gate portion coupled in sequence; the third top gate portion includes a second top gate portion, a third top gate portion, and a fourth top gate portion coupled in sequence; the orthographic projection of the first bottom gate portion on the substrate at least partially overlaps with the orthographic projection of the second top gate portion on the substrate, the orthographic projection of the second bottom gate portion on the substrate and the orthographic projection of the third top gate portion on the substrate are arranged along a second direction, and the orthographic projection of the third bottom gate portion on the substrate at least partially overlaps with the orthographic projection of the fourth top gate portion on the substrate; the second bottom gate portion is coupled to the second top gate portion through the sixth conductive connection portion 46.

[0236] For example, the first terminal of the fourth transistor T4 is coupled to the thirteenth transition pattern 313 through the thirty-seventh via V37, and the thirteenth transition pattern 313 is coupled to the third level signal line VGH through the forty-first via V41; the sixth conductive connection portion 46 is coupled to the second top gate portion through the thirty-eighth via V38, and the sixth conductive connection portion 46 is coupled to the second bottom gate portion through the thirty-ninth via V39. For example, the thirty-ninth via V39, the thirty-fourth via V34, and the thirtieth via V30 are arranged sequentially along the second direction. The sixth conductive connection portion 46 is coupled to the twenty-fifth transition pattern 325 through the seventy-eighth via V78, and the twenty-fifth transition pattern 325 is coupled to the sixth transition pattern 36 through the seventy-ninth via V79, and the sixth transition pattern 36 serves as the sixth node QB1.

[0237] For example, the second terminal of the seventh transistor T7 and the second terminal of the eighth transistor T8 are formed as an integral structure, and the first terminal of the seventh transistor T7 is coupled to the thirteenth transition pattern 313 through the fortieth via V40.

[0238] The above configuration can minimize the layout space occupied by the fourth transistor T4, the seventh transistor T7 and the sixth conductive connection part 46, while ensuring the connection performance between the sixth conductive connection part 46 and the third bottom gate part and the third top gate part.

[0239] As shown in Figures 1, 6 to 21, in some embodiments, the plurality of transistors further includes a thirteenth transistor T13, the shift register further includes a seventh conductive connection 47 and a fourth node GD, the first terminal of the thirteenth transistor T13 is coupled to the third level signal line VGH, the second terminal of the thirteenth transistor T13 is coupled to the fourth node GD, and the bottom gate layer b13 of the thirteenth transistor T13 is coupled to the top gate layer g13 of the thirteenth transistor T13 through the seventh conductive connection 47.

[0240] For example, the first terminal of the thirteenth transistor T13 is coupled to the thirteenth transition pattern 313 through the forty-third via V43, and the second terminal of the thirteenth transistor T13 is coupled to the fourteenth transition pattern 314 through the forty-second via V42, with the fourteenth transition pattern 314 serving as the fourth node GD; the seventh conductive connection portion 47 is coupled to the top gate layer g13 of the thirteenth transistor T13 through the forty-fourth via V44, and the seventh conductive connection portion 47 is coupled to the bottom gate layer b13 of the thirteenth transistor T13 through the forty-fifth via V45. The first extension Y1 of the top gate layer g13 of the thirteenth transistor T13 is coupled to the twenty-first transition pattern 321 through the sixty-fourth via V64. The twenty-first transition pattern 321 is coupled to the twenty-second transition pattern 322 through the sixty-fifth via V65. The twenty-second transition pattern 322 is coupled to the second conductive connection 42 through the sixty-sixth via V66. The second conductive connection 42 serves as the first node Q1.

[0241] For example, the active layer 213 of the thirteenth transistor T13 includes a strip extending along a second direction. The active layer 213 of the thirteenth transistor T13 and the active layer 219 of the nineteenth transistor T19 are arranged along a first direction.

[0242] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0243] As shown in Figures 1, 6 to 21, in some embodiments, the plurality of transistors further includes a twelfth transistor T12 and a fourteenth transistor T14, and the shift register further includes an eighth conductive connection 48, a fourth node GD, a fifth node QB3, and a second output node QB2. The first terminal of the twelfth transistor T12 is coupled to the fourth clock signal input terminal CKA2, the second terminal of the twelfth transistor T12 is coupled to the fourth node GD, the first terminal of the fourteenth transistor T14 is coupled to the fifth node QB3, and the second terminal of the fourteenth transistor T14 is coupled to the second output node QB2.

[0244] The bottom gate layer b12 of the twelfth transistor T12 and the bottom gate layer b14 of the fourteenth transistor T14 are formed into a fourth bottom gate portion, and the top gate layer g12 of the twelfth transistor T12 and the top gate layer g14 of the fourteenth transistor T14 are formed into a fourth top gate portion, and the fourth bottom gate portion is coupled to the fourth top gate portion through an eighth conductive connection portion 48.

[0245] For example, the first terminal of the twelfth transistor T12 is coupled to the fifteenth transition pattern 315 through the forty-sixth via V46, and the fifteenth transition pattern 315 is coupled to the twelfth transition pattern 312 in the adjacent upper-level shift register through the fifty-first via V51. The twelfth transition pattern 312 in the adjacent upper-level shift register serves as the fourth clock signal input terminal CKA2. The second terminal of the twelfth transistor T12 and the second terminal of the thirteenth transistor T13 are formed as an integral structure.

[0246] For example, the first terminal of the fourteenth transistor T14 is coupled to the eighth conductive connection 48 through the forty-eighth via V48, which serves as the fifth node QB3. The second terminal of the fourteenth transistor T14 is coupled to the fifteenth transition pattern 315 through the forty-seventh via V47, which serves as the second output node QB2.

[0247] The eighth conductive connection portion 48 is coupled to the fourth top gate portion through the forty-ninth via V48, and the eighth conductive connection portion 48 is coupled to the fourth bottom gate portion through the first unseen via V50.

[0248] For example, the active layer 212 of the twelfth transistor T12 includes a strip extending along a second direction, and the active layer 212 of the twelfth transistor T12 and the active layer 213 of the thirteenth transistor T13 are formed as an integral structure, and the active layer 212 of the twelfth transistor T12 and the active layer 213 of the thirteenth transistor T13 are arranged along the second direction.

[0249] For example, the active layer 212 of the twelfth transistor T12 and the active layer 214 of the fourteenth transistor T14 are arranged along a first direction.

[0250] The above configuration integrates the twelfth transistor T12 and the fourteenth transistor T14, allowing them to share a single conductive connection. This reduces the number of conductive connections and the number of vias required, thereby minimizing the overall layout space occupied by the shift register and better adapting to the narrow bezel requirements of display panels.

[0251] As shown in Figures 1, 6 to 21, in some embodiments, the plurality of transistors further includes a fifteenth transistor T15, and the shift register further includes a ninth conductive connection portion 49 and a seventh node QB4. The first terminal of the fifteenth transistor T15 is coupled to the seventh node QB4, the second terminal of the fifteenth transistor T15 is coupled to the fifth node QB3, and the bottom gate layer b15 of the fifteenth transistor T15 is coupled to the top gate layer g15 of the fifteenth transistor T15 through the ninth conductive connection portion 49.

[0252] For example, the first terminal of the fifteenth transistor T15 is coupled to the sixteenth transition pattern 316 through the fifty-third via V53, the sixteenth transition pattern 316 is coupled to the seventeenth transition pattern 317 through the fifty-sixth via V56, and the seventeenth transition pattern 317 is coupled to the seventh transition pattern 37 through the fifty-seventh via V57, wherein the seventh transition pattern 37 serves as the seventh node QB4; the second terminal of the fifteenth transistor T15 is coupled to the eighth conductive connection portion 48 through the fifty-second via V52.

[0253] The ninth conductive connection portion 49 is coupled to the top gate layer g15 of the fifteenth transistor T15 through the fifty-fourth via V54, and is coupled to the bottom gate layer b15 of the fifteenth transistor T15 through the fifty-fifth via V55. The ninth conductive connection portion 49 is coupled to the first level signal line through the eighty-third via V83.

[0254] For example, the active layer 215 of the fifteenth transistor T15 includes a strip extending along a second direction.

[0255] For example, the active layer 215 of the fifteenth transistor T15 and the active layer 213 of the thirteenth transistor T13 are arranged along a first direction.

[0256] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0257] As shown in Figures 1, 6 to 21, in some embodiments, the plurality of transistors further includes a ninth transistor T9 and a sixteenth transistor T16, and the shift register further includes a first node Q1, a sixth node QB1 and a first output node Q3;

[0258] The first terminal of the ninth transistor T9 is coupled to the sixth node QB1, the second terminal of the ninth transistor T9 is coupled to the second output node QB2, the first terminal of the sixteenth transistor T16 is coupled to the first node Q1, and the second terminal of the sixteenth transistor T16 is coupled to the first output node Q3.

[0259] The top gate layer g9 of the ninth transistor T9 and the top gate layer g15 of the fifteenth transistor T15 are formed into a single structure, and the bottom gate layer b9 of the ninth transistor T9 and the bottom gate layer b15 of the fifteenth transistor T15 are formed into a single structure; and / or, the top gate layer g16 of the sixteenth transistor T16 and the top gate layer g15 of the fifteenth transistor T15 are formed into a single structure, and the bottom gate layer b16 of the sixteenth transistor T16 and the bottom gate layer b15 of the fifteenth transistor T15 are formed into a single structure.

[0260] For example, the first terminal of the ninth transistor T9 is coupled to the eighteenth transition pattern 318 through the fifty-eighth via V58, the eighteenth transition pattern 318 is coupled to the top gate layer g7 of the seventh transistor T7 through the sixty-second via V62, the top gate layer g7 of the seventh transistor T7 is coupled to the sixth conductive connection portion 46, and the sixth conductive connection portion 46 serves as the sixth node QB1; the second terminal of the ninth transistor T9 is coupled to the tenth conductive connection portion 410 through the fifty-ninth via V59, and the tenth conductive connection portion 410 serves as the second output node QB2.

[0261] The first terminal of the sixteenth transistor T16 is coupled to the twentieth transition pattern 320 through the sixty-first via V61. The twentieth transition pattern 320 is coupled to the second extension Y2 of the top gate layer g13 of the thirteenth transistor T13 through the sixty-third via V63. The second extension Y2 of the top gate layer g13 of the thirteenth transistor T13 is connected to the potential of the first node Q1. The second terminal of the sixteenth transistor T16 is coupled to the tenth transition pattern 310 through the sixtieth via V60. The tenth transition pattern 310 serves as the first output node Q3.

[0262] For example, the active layer 29 of the ninth transistor T9 includes a strip extending along the second direction. The active layer 216 of the sixteenth transistor T16 includes a strip extending along the second direction.

[0263] For example, the active layer 29 of the ninth transistor T9 and the active layer 216 of the sixteenth transistor T16 are arranged along a second direction. The active layers 29 of the ninth transistor T9 and the active layers 216 of the sixteenth transistor T16 are partially offset or not offset along the second direction. For example, in a partial shift register, the orthographic projection of the nineteenth transition pattern 319 on the substrate is positioned between the orthographic projections of the active layers 29 of the ninth transistor T9 and the active layers 216 of the sixteenth transistor T16 on the substrate. This arrangement facilitates the connection of the eleventh transistor T11 to the corresponding clock signal line in the second group of clock signal lines.

[0264] For example, the active layer 215 of the fifteenth transistor T15 and the active layer 216 of the sixteenth transistor T16 are arranged along a first direction and partially offset along a second direction. The active layer 215 of the fifteenth transistor T15 and the active layer 29 of the ninth transistor T9 are arranged along the first direction and completely offset along the second direction.

[0265] The above arrangement allows the ninth transistor T9, the fifteenth transistor T15, and the sixteenth transistor T16 to share a single conductive connection, which simplifies the manufacturing process and reduces the number of conductive connections and vias required. This, in turn, helps to reduce the overall layout space occupied by the shift register, better adapting to the narrow bezel requirements of display panels. Furthermore, this arrangement minimizes the layout space occupied by the ninth transistor T9, the fifteenth transistor T15, the sixteenth transistor T16, and the ninth conductive connection 49. Moreover, this arrangement facilitates the coupling of the ninth transistor T9, the fifteenth transistor T15, and the sixteenth transistor T16 with the first first-level signal line VGL11.

[0266] As shown in Figures 1 and 6 to 21, in some embodiments, the plurality of transistors further includes a tenth transistor T10, and the shift register further includes a tenth conductive connection portion 410 and a second output node QB2. The first terminal of the tenth transistor T10 is coupled to the second level signal line VGL2, the second terminal of the tenth transistor T10 is coupled to the gate drive signal output terminal OUT of the shift register, the bottom gate layer b10 of the tenth transistor T10 is coupled to the top gate layer g10 of the tenth transistor T10 through the tenth conductive connection portion 410, and the tenth conductive connection portion 410 is coupled to the second output node QB2.

[0267] For example, the first terminal of the tenth transistor T10 is coupled to the twenty-third transition pattern 323 through the sixty-seventh via V67, and the twenty-third transition pattern 323 is coupled to the second level signal line VGL2 through the seventy-first via V71; the second terminal of the tenth transistor T10 is coupled to the twenty-fourth transition pattern 324 through the sixty-eighth via V68, and the twenty-fourth transition pattern 324 is coupled to the gate drive signal output terminal OUT of the shift register.

[0268] For example, the tenth conductive connection 410 is coupled to the top gate layer g10 of the tenth transistor T10 through the sixty-ninth via V69, and the tenth conductive connection 410 is coupled to the bottom gate layer b10 of the tenth transistor T10 through the seventieth via V70. The tenth conductive connection 410 serves as the second output node QB2.

[0269] For example, the active layer 210 of the tenth transistor T10 includes a strip extending along a first direction.

[0270] For example, since the second level signal line VGL2 is connected to the transistor used to control the output, the line width of the second level signal line VGL2 can be set to be greater than the line width of the first level signal line VGL11, and / or greater than the line width of the second first level signal line VGL12. Setting the display panel to include multiple level signal lines is beneficial for realizing independent input level signals for different transistors and for improving the stability of the shift register output.

[0271] For example, the potentials of the level signals transmitted by the first first level signal line VGL11, the second first level signal line VGL12, and the second level signal line VGL2 may be all the same, partially the same, or completely different.

[0272] For example, the voltage of the voltage signals transmitted by the first first level signal line VGL11 and the second first level signal line VGL12 is the same.

[0273] For example, the absolute value of the potential of the level signal transmitted by the first first level signal line VGL11 and / or the second first level signal line VGL12 is greater than the absolute value of the potential of the level signal transmitted by the second level signal line VGL2.

[0274] The display panel is equipped with two first-level signal lines. On the one hand, this reduces the layout difficulty of the first-level signal lines and the transistors they are coupled with. On the other hand, it allows for independent and flexible control of the potential of the first-level signal received by each transistor according to the actual needs of different transistors, thus better meeting the characteristic requirements of each transistor.

[0275] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0276] As shown in Figures 1, 6 to 21, in some embodiments, the plurality of transistors further includes an eleventh transistor T11, the shift register further includes an eleventh conductive connection portion 411 and a first output node Q3, the first terminal of the eleventh transistor T11 is coupled to the first clock signal input terminal GCK, the second terminal of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT of the shift register, and the bottom gate layer b11 of the eleventh transistor T11 is coupled to the top gate layer g11 of the eleventh transistor T11 through the eleventh conductive connection portion 411.

[0277] For example, the first terminal of the eleventh transistor T11 is coupled to the nineteenth transition pattern 319 through the seventy-third via V73, the nineteenth transition pattern 319 is coupled to the first clock signal input terminal GCK through the seventy-seventh via V77, the second terminal of the eleventh transistor T11 is coupled to the twenty-fourth transition pattern 324 through the seventy-second via V72 and the sixty-eighth via V68, and the twenty-fourth transition pattern 324 is coupled to the gate drive signal output terminal OUT of the shift register.

[0278] For example, the eleventh conductive connection portion 411 is coupled to the top gate layer g11 of the eleventh transistor T11 through the seventy-fourth via V74, and to the bottom gate layer b11 of the eleventh transistor T11 through the seventy-fifth via V75. The top gate layer g11 of the eleventh transistor T11 is coupled to the tenth transition pattern 310 through the seventy-sixth via, and the tenth transition pattern 310 serves as the first output node Q3.

[0279] For example, the active layer 211 of the eleventh transistor T11 includes a strip extending along a first direction.

[0280] For example, the active layer 211 of the eleventh transistor T11 and the active layer 210 of the tenth transistor T10 are arranged along a second direction. The active layer 211 of the eleventh transistor T11 and the active layer 210 of the tenth transistor T10 are formed as an integral structure.

[0281] For example, the eleventh conductive connection portion 411 and the twenty-third transition pattern 323 are arranged along a first direction.

[0282] For example, along the first direction, the width of the active layer 211 of the eleventh transistor T11 is greater than the width of the active layer 210 of the tenth transistor T10. The tenth transistor T10 is connected to the third level signal line VGH, and the eleventh transistor T11 is connected to the first level signal line VGL11 through the nineteenth transistor T19. When the PMOS-type tenth transistor T10 outputs a high voltage, its gate-source voltage Vgs is a fixed value, and its output capability is stronger than that of the eleventh transistor T11. When the eleventh transistor T11 outputs the first level signal, its gate-source voltage Vgs decreases, requiring a larger channel width-to-length ratio W / L to ensure its output capability. At the same time, this arrangement can leave enough space for the seventy-fifth via V75.

[0283] The above configuration not only enables the bottom gate layer to shield the influence of induced charges on the substrate on the transistor channel, but also improves the transistor's performance after reliability testing, making the transistor's characteristics more stable.

[0284] As shown in Figures 24 to 31, in some embodiments, the shift register includes transistors in each of its sub-circuits; at least some of the transistors include a top gate layer, a bottom gate layer, and an active layer, the bottom gate layer, the active layer, and the top gate layer being stacked sequentially in a direction away from the substrate, the top gate layer and the bottom gate layer being independent of each other; the bottom gate layers (e.g., b1 to b19) of at least two transistors are coupled together, and the at least two transistors are coupled to a fixed potential signal terminal.

[0285] For example, the bottom gate layers (such as b1 to b19) of all the transistors included in the shift register are formed as a single structure and coupled to a fixed potential signal terminal.

[0286] For example, the fixed signal input terminal can receive a fixed signal with a stable potential.

[0287] For example, the signal input to the fixed signal input terminal can have the same potential as a level signal or an initialization signal.

[0288] The above configuration reduces the number of vias required in the shift register while ensuring transistor stability after reliability testing. Furthermore, reducing the number of vias in the shift register allows for a further reduction in its lateral width.

[0289] As shown in Figures 24 to 31, in the same transistor, the top gate layer and the bottom gate layer are independent of each other; the bottom gate layers of at least two transistors are coupled together, and the at least two transistors are coupled to a fixed potential signal terminal.

[0290] As shown in Figures 24 to 31, exemplarily, the display panel further includes a fixed potential signal line DC, which serves as the fixed potential signal terminal. Exemplarily, the orthographic projection of the fixed potential signal line DC onto the substrate is located between the orthographic projection of the second level signal line VGL2 onto the substrate and the display area.

[0291] For example, the conductive connection 59 is coupled to the bottom gate layer and is coupled to the fixed potential signal line DC through the 90th via V90.

[0292] For example, the fixed potential signal line can be connected to an independent voltage source, or an existing DC voltage source can be used, such as a power signal voltage source (e.g., the same as the VDD signal potential), a level signal voltage source (e.g., the same as the level signal line potential), or an initialization signal voltage source.

[0293] It should be noted that in the embodiments shown in Figures 24 to 31, the transistor layout is the same as that shown in Figures 6 to 21. The difference is that in the embodiments shown in Figures 24 to 31, the conductive connection portions (marked as 51 to 59 in Figure 27) are not coupled to the bottom gate layer through vias. Therefore, the parts that are the same in the two embodiments can be referred to each other, and will not be described again.

[0294] As shown in Figures 5 and 32, in some embodiments, the display panel includes a display area 80 and a non-display area 81 located around the display area 80. The display area 80 includes a light-shielding layer. In the same transistor, the top gate layer and the bottom gate layer are independent of each other. The bottom gate layers of at least two transistors are coupled together, and the bottom gate layers of the at least two transistors are coupled to the light-shielding layer.

[0295] It should be noted that Figure 32 also includes sub-pixels 801 arranged in an array. The shift register is located in the non-display area 81, for example, in the left border area and / or the right border area.

[0296] For example, the bottom gate layers of all the transistors included in the shift register are formed as a single structure and coupled to the light-shielding layer. Specifically, see Figure 5; on the right side of Figure 5, the bottom gate layer of the single structure is coupled to the light-shielding layer.

[0297] For example, the bottom gate layers of all the transistors included in the shift register are formed as a single structure, and are also formed as a single structure with the light-shielding layer.

[0298] For example, the light-shielding layer is connected to a power signal, and the bottom gate layer is also connected to a power signal (such as a VDD signal).

[0299] For example, as shown in Figure 5, in each shift register, on the side of the tenth transistor T10 and the eleventh transistor T11 near the display area, the bottom gate layer of the integral structure extends two connected portions (as marked 90) for coupling with the light-shielding layer. This arrangement helps to reduce the resistance of the connection.

[0300] The above configuration completely eliminates the vias connected to the bottom gate layer, further reducing the number of vias in the layout, further compressing the overall area of ​​the shift register, and narrowing the overall layout space occupied by the shift register. Additionally, it can improve the reliability of the shift register output.

[0301] As shown in Figure 21, in some embodiments, in the display panel, the second first-level signal line VGL12, the third-level signal line VGH, the first first-level signal line VGL11, and the second-level signal line VGL2 are arranged sequentially along the direction close to the display area of ​​the display panel.

[0302] The above layout allows each signal line to better match the transistor layout, shortens the distance between the signal line and its coupled transistor, reduces the connection difficulty between the signal line and its coupled transistor, and also helps to reduce the layout space occupied by the shift register as a whole and its coupled signal lines.

[0303] It is worth noting that the vias penetrating the interlayer insulating layer include vias of different depths. These vias can be used to connect the first source / drain metal layer and the bottom gate layer, or to connect the first source / drain metal layer and the active layer, or to connect the first source / drain metal layer and the top gate layer, or to connect the first source / drain metal layer and the second gate metal layer, or to connect the first source / drain metal layer and the third gate metal layer.

[0304] As shown in Figures 1, 6 to 31, in some embodiments, the shift register further includes a fifth transistor T5, and the fourth node control sub-circuit 15 includes a twelfth transistor T12. The top gate layer g5 of the fifth transistor T5 is coupled to the second clock signal input terminal CKB, the second terminal of the fifth transistor T5 is coupled to the first node Q1, the first terminal of the twelfth transistor T12 is coupled to the fourth clock signal input terminal CKA2, and the second terminal of the twelfth transistor T12 is coupled to the fourth node GD. The second clock signal input terminal CKB coupled to the fifth transistor T5 in the Nth stage shift register is multiplexed to the fourth clock signal input terminal CKA2 coupled to the twelfth transistor T12 in the (N+1)th stage shift register, where N is an integer greater than or equal to 1.

[0305] For example, the shift register further includes an eleventh transition pattern 311, a twelfth transition pattern 312, and a fifteenth transition pattern 315. The second clock signal input terminal CKB, which is coupled to the fifth transistor T5 in the Nth stage shift register, is sequentially coupled to the first terminal of the twelfth transistor T12 in the N+1th stage shift register through the eleventh transition pattern 311, the twelfth transition pattern 312, and the fifteenth transition pattern 315. The display panel further includes a first gate metal layer, and the twelfth transition pattern 312 is disposed in the same layer and with the same material as the first gate metal layer.

[0306] Setting the twelfth transition pattern 312 and the first gate metal layer in the same layer and with the same material not only helps to simplify the manufacturing process of the display panel, but also helps to reduce the layout difficulty of the shift register in a limited layout space.

[0307] As shown in Figures 20 and 21, in some embodiments, at least a portion of the signal lines included in the display panel have their orthogonal projections on the substrate at least partially overlapping with the orthogonal projections of a plurality of shift registers on the substrate; the display panel also includes a second source / drain metal layer, and the signal lines are disposed in the same layer and with the same material as the second source / drain metal layer.

[0308] For example, the signal lines include at least one of the following: a frame start signal line STV', a first clock signal line GCK1, a second clock signal line GCK2, a third clock signal line GCK3, a fourth clock signal line GCK4, a fifth clock signal line CKA', a sixth clock signal line CKA2', a seventh clock signal line CKB', an eighth clock signal line CKB2', a first first level signal line VGL11, a second first level signal line VGL12, a second level signal line VGL2, and a third level signal line VGH.

[0309] The above arrangement allows the signal transmission line to overlap with each shift register in the direction perpendicular to the substrate, which not only helps to narrow the bezel of the display panel, but also helps to reduce the coupling difficulty between the signal transmission line and the shift register.

[0310] As shown in Figures 6 to 21, in some embodiments, the shift register further includes a seventh transition pattern 37, a sixteenth transition pattern 316, and a seventeenth transition pattern 317; the third isolation control sub-circuit 18 includes a fifteenth transistor T15, and the second input sub-circuit 19 includes a seventeenth transistor T17; the first terminal of the fifteenth transistor T15 is coupled to the seventh transition pattern 37 in sequence through the sixteenth transition pattern 316 and the seventeenth transition pattern 317, the seventh transition pattern 37 serves as the seventh node QB4, and the second terminal of the fifteenth transistor T15 is coupled to the fifth node QB3; the first terminal of the seventeenth transistor T17 is coupled to the input node QB5, and the second terminal of the seventeenth transistor T17 is coupled to the seventh node QB4.

[0311] For example, the display panel further includes a second gate metal layer and a third gate metal layer. As shown in Figures 22 and 23, the seventeenth transition pattern 317 is disposed in the same layer and with the same material as the second gate metal layer, or, as shown in Figure 13, the seventeenth transition pattern 317 is disposed in the same layer and with the same material as the third gate metal layer.

[0312] The above configuration can prevent short circuits between the seventeenth transition pattern 317 and other transition patterns, which helps to reduce the layout difficulty of the shift register.

[0313] In addition, by setting the seventeenth transition pattern 317 and the third gate metal layer in the same layer and with the same material, the seventeenth transition pattern 317 is further away from the first gate metal layer in the direction perpendicular to the substrate, resulting in a smaller parasitic capacitance.

[0314] As shown in Figure 1, all transistors in the shift register are LTPS PMOS transistors. When the shift register adopts the structure shown in Figure 1, the driving timing of the shift register is shown in Figure 3, and the specific working process is as follows:

[0315] During the P1 period, when the start signal input at the start signal input terminal STV is high voltage and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1, the second node Q2, and the first output node Q3 maintain high voltage, the fourth node GD is high voltage, the fifth node QB3 maintains low voltage, the sixth node QB1 maintains low voltage, the second output node QB2 maintains an even lower voltage, the cascade signal output at the cascade signal output terminal CR maintains high voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0316] During the P2 period, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the first node Q1, the second node Q2, and the first output node Q3 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low from low voltage to an even lower voltage. The second output node QB2 maintains a very low voltage. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0317] During the P3 period, when the start signal input at the start signal input terminal STV changes from high voltage to low voltage, and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1 and the second node Q2 change from high voltage to low voltage, the eighth transistor T8 remains on, the first output node Q3 changes from high voltage to low voltage, and the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 maintain the low voltage of the previous state. Since the second clock signal input at the second clock signal input terminal CKB is high voltage at this time, the cascade signal output at the cascade signal output terminal CR is high voltage, the first clock signal input at the first clock signal input terminal GCK is low voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains a low voltage.

[0318] During period P4, when the start signal input at the start signal input terminal STV goes low, and the third clock signal input at the third clock signal input terminal CKA goes high, due to the voltage stabilization effect of the first capacitor C1 and the second capacitor C2, the first node Q1, the second node Q2, and the first output node Q3 maintain low voltage. At this time, the third transistor T3 and the eighteenth transistor T18 remain in the open state, and the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 go high. Since the second clock signal input at the second clock signal input terminal CKB is high, the cascade signal output at the cascade signal output terminal CR is high, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0319] During period P5, when the third clock signal input at the third clock signal input terminal CKA is high, and the second clock signal input at the second clock signal input terminal CKB changes from high to low, since the eighth transistor T8 remains on, the voltage change of the cascaded signal output at the cascaded signal output terminal CR from high to low is coupled to the second node Q2 through the second capacitor C2. The second node Q2 is pulled down to an even lower voltage. Due to the voltage limiting effect of the sixth transistor T6, the first node Q1 is slightly pulled down to near the first level signal input at the first level signal line VGL1. At this time, the nineteenth transistor T19 turns on, and the first output node Q3 is pulled down to around the voltage value of the first level signal. At this time, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT remains low. At this time, the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 remain high.

[0320] During period P6, when the third clock signal input at the third clock signal input terminal CKA is high, and the first clock signal input at the first clock signal input terminal GCK changes from low to high (the change from low to high voltage of the first clock signal input at the first clock signal input terminal GCK occurs when the second clock signal input at the second clock signal input terminal CKB is low), the nineteenth transistor T19 remains on. The first output node Q3 maintains a potential around the current first level signal voltage value, and the gate drive signal output at the gate drive signal output terminal OUT changes from low to high voltage. The voltages of other nodes remain unchanged.

[0321] During period P7, when the third clock signal input at the third clock signal input terminal CKA is high, and the second clock signal input at the second clock signal input terminal CKB changes from low to high, due to the coupling effect of the second capacitor C2, the second node Q2 and the first node Q1 are affected by the process of the cascaded signal output from the cascaded signal output terminal CR changing from low to high voltage. This causes the voltage to return to the potential at the end of the change in the third clock signal input at the third clock signal input terminal CKA. At this time, the voltage of the first output node Q3 remains essentially unchanged due to the isolation effect of the sixteenth transistor T16. The cascaded signal output from the cascaded signal output terminal CR changes from low to high voltage, while the voltages of other nodes remain unchanged. It should be noted that at this time, the sixteenth transistor T16 is in the off state due to the influence of the gate voltage and the source voltage.

[0322] During the P8 period, when the third clock signal input at the third clock signal input terminal CKA is a high voltage, since the eleventh transistor T11 is a buffer transistor with a relatively large parasitic capacitance, the voltage of the first output node Q3 is pulled down to a very low level, ensuring that the eleventh transistor T11 outputs a complete falling edge, and the voltages of other nodes do not change.

[0323] During the P9 period, when the start signal input at the start signal input terminal STV is high voltage and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1, the second node Q2, and the first output node Q3 change from low voltage to high voltage. The fourth node GD maintains a high voltage at this time, while the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 change from high voltage to low voltage. The cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains a low voltage.

[0324] During period P10, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the first node Q1, the second node Q2, and the first output node Q3 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low to an even lower voltage, and the second output node QB2 is pulled low to an even lower voltage. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0325] During the P11 period, when the third clock signal input at the third clock signal input terminal CKA is at a high voltage and the second clock signal input at the second clock signal input terminal CKB changes from a high voltage to a low voltage, the fourth transistor T4 and the fifth transistor T5 turn on. The first node Q1, the second node Q2, and the first output node Q3 are connected to the third level signal input by the third level signal line VGH, making them less susceptible to interference from other clock signals.

[0326] As shown in Figure 4, in the case of multiple cascaded shift registers, the third clock signal input terminal CKA of the (4N+1)th shift register is coupled to the fifth clock signal line CKA'; the fourth clock signal input terminal CKA2 of the (4N+1)th shift register is coupled to the sixth clock signal line CKA2'; the second clock signal input terminal CKB of the (4N+1)th shift register is coupled to the seventh clock signal line CKB'; and the first clock signal input terminal GCK of the (4N+1)th shift register is coupled to the first clock signal line GCK1. N is an integer greater than or equal to 0.

[0327] As shown in Figure 4, the third clock signal input terminal CKA in the 4N+2nd shift register is coupled to the sixth clock signal line CKA2'; the fourth clock signal input terminal CKA2 in the 4N+2nd shift register is coupled to the seventh clock signal line CKB'; the second clock signal input terminal CKB in the 4N+2nd shift register is coupled to the eighth clock signal line CKB2'; and the first clock signal input terminal GCK in the 4N+2nd shift register is coupled to the second clock signal line GCK2.

[0328] As shown in Figure 4, the third clock signal input terminal CKA in the 4N+3 shift register is coupled to the seventh clock signal line CKB'; the fourth clock signal input terminal CKA2 in the 4N+3 shift register is coupled to the eighth clock signal line CKB2'; the second clock signal input terminal CKB in the 4N+3 shift register is coupled to the fifth clock signal line CKA'; and the first clock signal input terminal GCK in the 4N+3 shift register is coupled to the third clock signal line GCK3.

[0329] As shown in Figure 4, the third clock signal input terminal CKA in the 4N+4th shift register is coupled to the eighth clock signal line CKB2'; the fourth clock signal input terminal CKA2 in the 4N+4th shift register is coupled to the fifth clock signal line CKA'; the second clock signal input terminal CKB in the 4N+4th shift register is coupled to the sixth clock signal line CKA2'; and the first clock signal input terminal GCK in the 4N+4th shift register is coupled to the fourth clock signal line GCK4.

[0330] Figure 3 also illustrates the cascaded signal output terminal CR of the Nth shift register unit. <n>The cascaded signal output terminal CR of the (N+1)th shift register unit<N+1> The timing of the cascaded output signals; and the gate drive signal output terminal OUT of the Nth shift register unit. <n>and the gate drive signal output terminal OUT of the (N+1)th shift register unit<N+1> Timing of the output gate drive signal.

[0331] For example, starting from the third-stage shift register, the cascaded signals output by the odd-stage shift registers are provided to the start signal input STV of the adjacent next-stage odd-stage shift register, and the cascaded signals output by the even-stage shift registers are provided to the start signal input STV of the adjacent next-stage even-stage shift register. The start signal input STV of the first-stage and second-stage shift registers are coupled to the start signal line STV'.

[0332] The shift register provided in the above embodiments can use a P-type transistor to output a gate drive signal with a high voltage pulse that has shifted, and the waveform of the signal can maintain low potential stability.

[0333] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0334] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0335] In the display panel provided in the above embodiment, by setting the orthographic projection of the first first-level signal line VGL11 on the substrate between the orthographic projection of the transistors included in the first output node control sub-circuit 11 on the substrate and the orthographic projection of the clock signal line on the substrate, not only does this make the first output node control sub-circuit 11 closer to the first first-level signal line VGL11, which helps reduce the connection difficulty between the first output node control sub-circuit 11 and the first first-level signal line VGL11, and also helps to narrow the overall layout space occupied by the shift register; moreover, since the first first-level signal line VGL11 is used to transmit stable signals, this setting helps to shield the influence of clock signal changes transmitted by the clock signal line on the transistors included in the first output node control sub-circuit 11, ensuring the stability of the characteristics of the transistors included in the first output node control sub-circuit 11. At the same time, at least a portion of the orthographic projection of the first output sub-circuit 10 on the substrate is located on the side where the orthographic projection of the clock signal line on the substrate is far from the orthographic projection of the third level signal line VGH on the substrate, so that the first output sub-circuit 10 can be arranged adjacent to the clock signal line coupled to it, which is beneficial to further narrow the layout space occupied by the shift register as a whole.

[0336] The display device provided in this disclosure has the same beneficial effects as the display panel provided in the above embodiments, and will not be repeated here.

[0337] This disclosure also provides a method for manufacturing a display panel, used to manufacture the display panel provided in the above embodiments, the method comprising:

[0338] A gate drive circuit, a clock signal line, and a first first-level signal line VGL11 are fabricated on a substrate. The gate drive circuit includes cascaded multi-stage shift registers. The shift registers include a first output node Q3, a second node Q2, a first output sub-circuit 10, and a first output node control sub-circuit 11. The first output sub-circuit 10 is coupled to the gate drive signal output terminal OUT of the shift register, the first output node Q3, and the clock signal input terminal, respectively. The clock signal input terminal is coupled to the corresponding clock signal line. The first output node control sub-circuit 11 is coupled to the second node Q2, the first output node Q3, and the first first-level signal line VGL11, respectively. The orthographic projection of the first first-level signal line VGL11 on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit 11 on the substrate and the orthographic projection of the clock signal line on the substrate.

[0339] In the display panel manufactured using the method provided in this embodiment of the invention, by setting the orthographic projection of the first first-level signal line VGL11 on the substrate between the orthographic projection of the transistors included in the first output node control sub-circuit 11 on the substrate and the orthographic projection of the clock signal line on the substrate, not only does this make the first output node control sub-circuit 11 closer to the first first-level signal line VGL11, which helps reduce the connection difficulty between the first output node control sub-circuit 11 and the first first-level signal line VGL11, and also helps to narrow the overall layout space occupied by the shift register; moreover, since the first first-level signal line VGL11 is used to transmit stable signals, this setting helps to shield the influence of clock signal changes transmitted by the clock signal line on the transistors included in the first output node control sub-circuit 11, ensuring the stability of the characteristics of the transistors included in the first output node control sub-circuit 11. At the same time, at least a portion of the orthographic projection of the first output sub-circuit 10 on the substrate is located on the side where the orthographic projection of the clock signal line on the substrate is far from the orthographic projection of the third level signal line VGH on the substrate, so that the first output sub-circuit 10 can be arranged adjacent to the clock signal line coupled to it, which is beneficial to further narrow the layout space occupied by the shift register as a whole.

[0340] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0341] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0342] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0343] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0344] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connection," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0345] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be an intermediate component.

[0346] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0347] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n>

Claims

A display panel, comprising: The substrate, the gate driving circuit disposed on the substrate, the clock signal line and the first first level signal line; The gate drive circuit includes cascaded multi-stage shift registers; the shift registers include: a first output node, a second node, a first output sub-circuit, and a first output node control sub-circuit; The first output sub-circuit is coupled to the gate drive signal output terminal of the shift register, the first output node, and the first clock signal input terminal, respectively. The first clock signal input terminal is coupled to the corresponding clock signal line. The first output node control sub-circuit is coupled to the second node, the first output node, and the first first level signal line, respectively. The orthographic projection of the first first level signal line on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit on the substrate and the orthographic projection of the clock signal line on the substrate. The display panel according to claim 1, wherein, The shift register further includes: a first node, a fourth node, a fifth node, and a fourth node control sub-circuit; the display panel further includes a third level signal line; the fourth node control sub-circuit is coupled to the first node, the fourth node, the fifth node, the fourth clock signal input terminal, and the third level signal line respectively; the orthographic projection of the transistor included in the fourth node control sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line on the substrate. The display panel according to claim 2, wherein, The shift register further includes a second output node and a second output node control sub-circuit; the second output node control sub-circuit is coupled to the second output node and the fifth node respectively; at least a portion of the orthographic projection of the transistor included in the second output node control sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line on the substrate. The display panel according to claim 3, wherein, The shift register further includes a second output sub-circuit; the display panel further includes a second level signal line; the second output sub-circuit is coupled to the second output node, the second level signal line and the gate drive signal output terminal respectively; the orthographic projection of the transistor included in the second output sub-circuit on the substrate overlaps at least partially with the orthographic projection of the second level signal line on the substrate; The second level signal line is located on the side of the third level signal line that is closer to the display area of ​​the display panel. The display panel according to claim 4, wherein, The shift register further includes a seventh node and a third isolation control sub-circuit; the third isolation control sub-circuit is coupled to the first first level signal line, the fifth node and the seventh node respectively; at least a portion of the orthographic projection of the transistor included in the third isolation control sub-circuit on the substrate is located between the orthographic projection of the first first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate. The display panel according to claim 5, wherein, The shift register further includes a sixth node and a second input sub-circuit; the display panel further includes a second first-level signal line; the second input sub-circuit is coupled to a third clock signal input terminal, the second first-level signal line, the sixth node, and the seventh node respectively; at least a portion of the orthographic projection of the transistor included in the second input sub-circuit onto the substrate is located between the orthographic projection of the second first-level signal line onto the substrate and the orthographic projection of the third-level signal line onto the substrate, and the second first-level signal line is located on the side of the third-level signal line away from the display area. The display panel according to claim 5, wherein, The shift register further includes a seventh node control sub-circuit, which is coupled to the first node, the third clock signal input terminal and the seventh node respectively; the display panel includes a first group of clock signal lines and a second group of clock signal lines, the first group of clock signal lines includes at least one clock signal line, the second group of clock signal lines includes at least one clock signal line, and the third level signal line is located between the first group of clock signal lines and the second group of clock signal lines. The clock signal line coupled to the first clock signal input terminal belongs to the second group of clock signal lines; The clock signal line coupled to the third clock signal input terminal belongs to the first group of clock signal lines; The orthographic projection of the transistors included in the seventh node control sub-circuit onto the substrate overlaps at least partially with the orthographic projection of the clock signal lines in the first group of clock signal lines onto the substrate. The display panel according to any one of claims 1 to 7, wherein, The shift register further includes a cascaded output sub-circuit, which is coupled to the sixth node and the second node in the shift register, the third level signal line and the second clock signal input terminal in the display panel, respectively. The orthographic projection of the transistor included in the cascaded output sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line coupled to the first clock signal input terminal on the substrate. The display panel according to claim 8, wherein, The cascaded output sub-circuit includes a first capacitor and a second capacitor; the first plate of the first capacitor is coupled to a sixth node, and the second plate of the first capacitor is coupled to a third level signal line; the first plate of the second capacitor is coupled to a second node, and the second plate of the second capacitor is coupled to the cascaded signal output terminal; the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the third level signal line on the substrate at least partially overlap. And / or, the orthographic projection of the second plate of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the third level signal line onto the substrate. The display panel according to claim 9, wherein, The cascaded output sub-circuit further includes a seventh transistor and an eighth transistor. The first terminal of the seventh transistor is coupled to the third level signal line, and the second terminal of the seventh transistor is coupled to the cascaded signal output terminal. The first terminal of the eighth transistor is coupled to the second clock signal input terminal, and the second terminal of the eighth transistor is coupled to the cascaded signal output terminal. The gate of the seventh transistor is multiplexed to at least a portion of the first plate of the first capacitor. And / or, the gate of the eighth transistor is multiplexed to at least a portion of the first plate of the second capacitor. The display panel according to any one of claims 2 to 7, wherein, The fourth node control sub-circuit includes a third capacitor, the first plate of which is coupled to the fifth node, and the second plate of which is coupled to the fourth node; the orthographic projection of the second plate of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the first first level signal line on the substrate. The display panel according to claim 11, wherein, The fourth node control sub-circuit also includes a twelfth transistor, the gate of which is coupled to the fifth node, and the first terminal of which is coupled to the fourth clock signal input terminal. And / or, the second output node control sub-circuit includes a fourteenth transistor, the gate of which is coupled to the fifth node, the first terminal of which is coupled to the fifth node, and the second terminal of which is coupled to the second output node; the gate of the twelfth transistor is multiplexed to at least a portion of the first plate of the third capacitor; And / or, the gate of the fourteenth transistor is multiplexed to at least a portion of the first plate of the third capacitor. The display panel according to any one of claims 1 to 7, wherein, The shift register further includes a first input sub-circuit; the display panel further includes a start signal line; the first input sub-circuit is coupled to a third clock signal input terminal, a start signal input terminal, and a first node respectively; the start signal input terminal coupled to the first-stage shift register is coupled to the start signal line; the orthographic projection of the transistor included in the first input sub-circuit on the substrate is located between the orthographic projection of the start signal line on the substrate and the orthographic projection of the second first level signal line on the substrate. The display panel according to claim 13, wherein, The shift register further includes a first isolation control sub-circuit, which is coupled to the second first level signal line in the display panel, the first node and the second node of the shift register, respectively; the orthographic projection of the transistor included in the first isolation control sub-circuit on the substrate is located between the orthographic projection of the start signal line on the substrate and the orthographic projection of the second first level signal line on the substrate. The display panel according to claim 13, wherein, The shift register further includes a sixth node control sub-circuit, which is coupled to the third clock signal input terminal, the first node and the sixth node in the shift register respectively; the orthographic projection of the transistor included in the sixth node control sub-circuit on the substrate is located between the orthographic projection of the start signal line on the substrate and the orthographic projection of the second first level signal line on the substrate. The display panel according to claim 13, wherein, The cascaded signal output of the Nth stage shift register serves as the start signal input of the first input sub-circuit in the (N+2)th stage shift register; N is an integer greater than or equal to 1. The display panel according to any one of claims 1 to 7, wherein, The shift register further includes a first node control sub-circuit, which is coupled to the first node, the sixth node, the second clock signal input terminal, and the third level signal line in the display panel, respectively. The orthographic projection of the transistor in the first node control sub-circuit on the substrate is located between the orthographic projection of the third level signal line on the substrate and the orthographic projection of the clock signal line coupled to the second clock signal input terminal on the substrate. The display panel according to any one of claims 1 to 7, wherein, The shift register further includes a second isolation control sub-circuit and a fourth isolation control sub-circuit. The second isolation control sub-circuit is coupled to the first first-level signal line, the sixth node and the second output node in the shift register, respectively. The fourth isolation control sub-circuit is coupled to the first first-level signal line, the first node and the first output node in the shift register, respectively. The orthographic projection of the transistors included in the second isolation control sub-circuit on the substrate overlaps with the orthographic projection of the clock signal line coupled to a portion of the first clock signal input terminal on the substrate. And / or, the orthographic projection of the transistors included in the fourth isolation control sub-circuit on the substrate overlaps with the orthographic projection of the clock signal line coupled to a portion of the first clock signal input terminal on the substrate. The display panel according to any one of claims 1 to 7, wherein, In the shift register, each sub-circuit includes a transistor, at least a portion of which includes a top gate layer, a bottom gate layer, and an active layer; the bottom gate layer, the active layer, and the top gate layer are stacked sequentially along a direction away from the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the bottom gate layer on the substrate, and the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the top gate layer on the substrate. The display panel according to claim 19, wherein, In the same transistor, the bottom gate layer is coupled to the top gate layer. The display panel according to claim 19, wherein, In the same transistor, the top gate layer and the bottom gate layer are independent of each other; the bottom gate layers of at least two transistors are coupled together, and the at least two transistors are coupled to a fixed potential signal terminal. The display panel according to claim 19, wherein, The display panel includes a display area and a non-display area surrounding the display area. The display area includes a light-shielding layer. In the same transistor, the top gate layer and the bottom gate layer are independent of each other. The bottom gate layers of at least two transistors are coupled together, and the bottom gate layers of the at least two transistors are coupled together with the light-shielding layer. The display panel according to any one of claims 1 to 7, wherein, In the display panel, the second first-level signal line, the third level signal line, the first first-level signal line, and the second level signal line are arranged sequentially along the direction close to the display area of ​​the display panel. A display device comprising a display panel as claimed in any one of claims 1 to 23. A method for manufacturing a display panel, used to manufacture a display panel as described in any one of claims 1 to 23, the method comprising: A gate drive circuit, a clock signal line, and a first first-level signal line are fabricated on a substrate. The gate drive circuit includes cascaded multi-stage shift registers; The shift register includes: a first output node, a second node, a first output sub-circuit, and a first output node control sub-circuit; The first output sub-circuit is coupled to the gate drive signal output terminal of the shift register, the first output node, and the clock signal input terminal, respectively. The clock signal input terminal is coupled to the corresponding clock signal line. The first output node control sub-circuit is coupled to the second node, the first output node, and the first first level signal line, respectively. The orthographic projection of the first first level signal line on the substrate is located between the orthographic projection of the transistor included in the first output node control sub-circuit on the substrate and the orthographic projection of the clock signal line on the substrate.

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