Shifting register, driving method thereof and display device

Abstract

The invention discloses a shift register, a driving method thereof and a display device. The shift register comprises an input sub-circuit, an output sub-circuit and a scanning control sub-circuit, the scanning control sub-circuit is configured to provide a signal of a first scanning input end (IN1) or a second scanning input end (IN2) for a first node (N1) and provide a signal of a first scanning reset end (RST1) or a second scanning reset end (RST1) for a second node (N2) under the control of signals of a first control signal end (CN) and a second control signal end (CNB).

Description

Shift registers and their driving methods, display devices

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a shift register and its driving method, and a display device.

[0002] In recent years, flat panel displays, such as thin film transistor liquid crystal displays (TFT-LCD) and active matrix organic light emitting diode displays (AMOLED), have been widely used in electronic products such as televisions and mobile phones due to their advantages of light weight, thinness and low power consumption.

[0003] With the advancement of technology, high-resolution, narrow-bezel display panels have become a development trend, leading to the emergence of Gate Driver on Array (GOA) technology. GOA technology refers to the technique of placing the GOA circuits used to drive the gate lines on both sides of the effective display area of ​​the array substrate in the display panel.

[0004]

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a shift register and its driving method, as well as a display device.

[0007] In a first aspect, this disclosure provides a shift register, including: an input sub-circuit, an output sub-circuit, and a scan control sub-circuit;

[0008] The input sub-circuit is electrically connected to the first node, the second node, the first control signal terminal, the second control signal terminal, and the main pull-up node, respectively. It is configured to provide the signal of the first control signal terminal to the main pull-up node under the control of the signal of the first node, and to provide the signal of the second control signal terminal to the main pull-up node under the control of the signal of the second node.

[0009] The output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, at least one clock signal terminal and at least one output terminal respectively, and is configured to provide a signal of one of the clock signal terminals to one of the at least one output terminal under the control of the signals of the main pull-up node and the first power supply terminal.

[0010] The scan control sub-circuit is electrically connected to the first scan input terminal, the second scan input terminal, the first scan reset terminal, the second scan reset terminal, the first control signal terminal, the second control signal terminal, the first node, and the second node, respectively. It is configured to provide the first scan input terminal or the second scan input terminal signal to the first node and the first scan reset terminal or the second scan reset terminal signal to the second node under the control of the signals of the first control signal terminal and the second control signal terminal.

[0011] In a second aspect, this disclosure also provides a display device having a display area and a non-display area, wherein the display area is provided with an array of pixel driving circuits and the non-display area is provided with a gate driving circuit, the gate driving circuit comprising: a plurality of cascaded shift registers as described above;

[0012] At least one shift register is electrically connected to at least one row of pixel driving circuitry and is configured to provide drive signals to the connected pixel driving circuitry.

[0013] Thirdly, this disclosure also provides a display device having a display area and a non-display area, wherein the display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit, the gate driving circuit including: a plurality of cascaded shift registers, the shift registers including: an input sub-circuit, an output sub-circuit, and a first node control sub-circuit;

[0014] The input sub-circuit is electrically connected to the scan input terminal, the scan reset terminal, the second node, the first control signal terminal, the second control signal terminal, and the main pull-up node, respectively. It is configured to provide the signal of the first control signal terminal to the main pull-up node under the control of the signal of the scan input terminal, and to provide the signal of the second control signal terminal to the main pull-up node under the control of the signal of the scan reset terminal.

[0015] The output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the third clock signal terminal, the fourth clock signal terminal and at least one output terminal respectively, and is configured to provide a signal of at least one clock signal terminal to one of the at least one output terminal under the control of the signals of the main pull-up node and the first power supply terminal.

[0016] The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, the main pull-up node, the first power supply terminal, the second power supply terminal, and the pull-down node, respectively, and is configured to provide the first power supply terminal or the second power supply terminal signal to the pull-down node under the control of the signals of the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, and the main pull-up node.

[0017] Fourthly, this disclosure also provides a method for driving a shift register, configured to drive the shift register, the method comprising: an input sub-circuit, an output sub-circuit, and a scan control sub-circuit;

[0018] The input sub-circuit, under the control of the signal of the first node, provides the signal of the first control signal terminal to the main pull-up node, and under the control of the signal of the second node, provides the signal of the second control signal terminal to the main pull-up node;

[0019] Under the control of the signals from the main pull-up node and the first power supply terminal, the output sub-circuit provides a signal from one of the clock signal terminals to one of the at least one output terminal.

[0020] Under the control of the signals at the first control signal terminal and the second control signal terminal, the scan control sub-circuit provides the first scan input terminal or the second scan input terminal signal to the first node, and provides the first scan reset terminal or the second scan reset terminal signal to the second node.

[0021] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0022] Overview of the attached figures

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a schematic diagram of the structure of the shift register provided in an embodiment of this disclosure;

[0025] Figure 2 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0026] Figure 3 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment;

[0027] Figure 4 is a schematic diagram of the shift register connection;

[0028] Figure 5 is a schematic diagram of multiple shift registers cascaded together;

[0029] Figure 6 is a schematic diagram of multiple shift registers cascaded (II).

[0030] Figure 7 is a schematic diagram of the cascading of multiple shift registers (Part 3).

[0031] Figure 8 is a schematic diagram of the cascading of multiple shift registers (IV).

[0032] Figure 9 is a schematic diagram of multiple clock signal lines in the non-eye-focusing area;

[0033] Figure 10 is a schematic diagram of multiple clock signal lines in the eye's fixation area.

[0034] Figure 11 is the timing diagram of the shift register provided in Figure 2 in the first scan state;

[0035] Figure 12 is the timing diagram of the shift register provided in Figure 2 in the second scan state;

[0036] Figure 13 is an equivalent circuit diagram of a shift register provided in another exemplary embodiment;

[0037] Figure 14 is an equivalent circuit diagram of a shift register provided in another exemplary embodiment;

[0038] Figure 15 is a schematic diagram of the connection of another gate drive circuit;

[0039] Figure 16 is a schematic diagram of multiple clock signal lines in the non-eye-fixation area;

[0040] Figure 17 is a schematic diagram of multiple clock signal lines in the eye's fixation area (II).

[0041] Figure 18 is a schematic diagram of multiple shift registers cascaded together;

[0042] Figure 19 is a schematic diagram of multiple shift registers cascaded together;

[0043] Figure 20 is a schematic diagram of the cascading of multiple shift registers;

[0044] Figure 21 is a schematic diagram of multiple shift registers cascaded together.

[0045] Figure 22 is the timing diagram of the shift register provided in Figure 13 in the first scan state;

[0046] Figure 23 is the timing diagram of the shift register provided in Figure 13 in the second scan state.

[0047] Detailed Explanation

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0049] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0050] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0051] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0052] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. "Joining" can include "electrical connection," which includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components. Those skilled in the art will understand the meaning of the above terms in this disclosure as appropriate.

[0053] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0054] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0055] In this specification, "approximately parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "approximately perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0056] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0057] In this specification, "approximately" and "roughly" mean without strictly defined limits, allowing for conditions within the permissible range of processes and measurements. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0058] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0059] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0060] As a new type of high-tech product, Virtual Reality (VR) devices can simulate environments, perceive natural skills, and utilize sensing devices. To enhance the user experience, VR devices employ foveated rendering technology, which involves scanning a single line in the area the eye is focused on, while scanning at least two lines simultaneously in the non-focused area. The display device comprises multiple rows of sub-pixels, with the number of rows of sub-pixels in the focused area being less than the number of rows in the non-focused area. This foveated rendering technology reduces the scanning time per display frame. Foveated rendering technology is essential for achieving high PPI and high-frequency displays in VR devices.

[0061] In some specialized applications, display devices need to support both forward and reverse scanning. For example, a mobile phone screen can be displayed either upright or upside down. This requires the gate drive circuit to perform both top-down and bottom-up scanning. Current VR devices only support forward scanning and cannot support both forward and reverse scanning, resulting in lower reliability.

[0062] Figure 1 is a schematic diagram of the structure of a shift register provided in an embodiment of this disclosure. As shown in Figure 1, the shift register provided in an embodiment of this disclosure includes: an input sub-circuit, an output sub-circuit, and a scan control sub-circuit.

[0063] As shown in Figure 1, the input sub-circuit is electrically connected to the first node N1, the second node N2, the first control signal terminal CN, the second control signal terminal CNB, and the main pull-up node PUCN, respectively. It is configured to provide the signal of the first control signal terminal CN to the main pull-up node PUCN under the control of the signal of the first node N1, and to provide the signal of the second control signal terminal CNB to the main pull-up node PUCN under the control of the signal of the second node N2.

[0064] As shown in Figure 1, the output sub-circuit is electrically connected to the main pull-up node PUCN, the first power supply terminal VGH, at least one clock signal terminal, and at least one output terminal OUT, respectively. It is configured to provide a clock signal of at least one of the at least one clock signal terminals to one of the at least one output terminal OUT under the control of the signals of the main pull-up node PUCN and the first power supply terminal VGH.

[0065] As shown in Figure 1, the scan control sub-circuit is electrically connected to the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, the second scan reset terminal RST2, the first control signal terminal CN, the second control signal terminal CNB, the first node N1, and the second node N2, respectively. It is configured to provide the first scan input terminal IN1 or the second scan input terminal IN2 to the first node N1 and the first scan reset terminal RST1 or the second scan reset terminal RST2 to the second node N2 under the control of the signals of the first control signal terminal CN and the second control signal terminal CNB.

[0066] In an exemplary embodiment, at least one clock signal terminal includes: a third clock signal terminal CK3 and a fourth clock signal terminal CK4.

[0067] This disclosure, by setting up a scan control sub-circuit, utilizes the cascading relationship between four signal terminals (first scan input terminal IN1, second scan input terminal IN2, first scan reset terminal RST1, and second scan reset terminal RST2) connected to a first-level shift register and at least one output terminal of the remaining shift registers, to ensure that the gate drive circuit where the shift register is located can realize the functions of forward scanning and reverse scanning, thereby meeting the display requirements of the display device and improving the reliability of the display device.

[0068] In an exemplary embodiment, at least one output terminal may include: a first output terminal and a second output terminal, or may include: a first drive output terminal, a first cascaded output terminal, a second drive output terminal and a second cascaded output terminal.

[0069] As shown in Figure 1, in an exemplary embodiment, the shift register may further include: a first node control subcircuit and a second node control subcircuit. The first node control subcircuit is electrically connected to a first clock signal terminal CK1, a second clock signal terminal CK2, a first control signal terminal CN, a second control signal terminal CNB, a first power supply terminal VGH, a second power supply terminal VGL, a total pull-up node PUCN, and a pull-down node PD, respectively. It is configured to provide a signal from the first power supply terminal VGH or the second power supply terminal VGL to the pull-down node PD under the control of the signals from the first clock signal terminal CK1, the second clock signal terminal CK2, the first control signal terminal CN, the second control signal terminal CNB, and the total pull-up node PUCN. The second node control subcircuit is electrically connected to at least one output terminal OUT, a second power supply terminal VGL, a reset signal terminal TRST, the pull-down node PD, and the total pull-up node PUCN, respectively. It is configured to provide a signal from the second power supply terminal VGL to the total pull-up node PUCN and at least one output terminal OUT under the control of the signal from the pull-down node PD, and to provide a signal from the second power supply terminal VGL to the total pull-up node PUCN under the control of the signal from the reset signal terminal TRST.

[0070] In an exemplary embodiment, Figure 2 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment, and Figure 3 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment. Figure 2 illustrates the shift register connected to two output terminals, such as a first output terminal OUT1 and a second output terminal OUT2, and Figure 3 illustrates the shift register connected to four output terminals (such as a first drive output terminal OUT11, a first cascaded output terminal OUT12, a second drive output terminal OUT21, and a second cascaded output terminal OUT22).

[0071] In an exemplary embodiment, the input sub-circuit includes: a first input sub-circuit and a second input sub-circuit, wherein the first input sub-circuit is electrically connected to a first node, a first control signal terminal, and a total pull-up node, and is configured to provide a signal from the first control signal terminal to the total pull-up node under the control of the signal from the first node; the second input sub-circuit is electrically connected to a second node, a second control signal terminal, and the total pull-up node, and is configured to provide a signal from the second control signal terminal to the total pull-up node under the control of the signal from the second node.

[0072] As shown in Figures 2 and 3, the first input sub-circuit includes a first transistor T1, and the second input sub-circuit includes a second transistor T2. The control electrode of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the first control signal terminal CN, and the second terminal of the first transistor T1 is electrically connected to the total pull-up node PUCN. Similarly, the control electrode of the second transistor T2 is electrically connected to the second node N2, the first terminal of the second transistor T2 is electrically connected to the second control signal terminal CNB, and the second terminal of the second transistor T2 is electrically connected to the total pull-up node PUCN.

[0073] Figures 2 and 3 illustrate an exemplary structure of the input sub-circuit. The implementation of the input sub-circuit is not limited to this; any implementation that achieves its function is acceptable.

[0074] In an exemplary embodiment, when at least one output terminal includes a first output terminal and a second output terminal, the output sub-circuit includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the third clock signal terminal, and the first output terminal, and is configured to provide the signal of the third clock signal terminal to the first output terminal under the control of the signals from the main pull-up node and the first power supply terminal. The second output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the fourth clock signal terminal, and the second output terminal, and is configured to provide the signal of the fourth clock signal terminal to the second output terminal under the control of the signals from the main pull-up node and the first power supply terminal.

[0075] As shown in Figure 2, the first output sub-circuit includes a third transistor T3, a fourth transistor T4, and a first capacitor C1. The second output sub-circuit includes a fifth transistor T5, a sixth transistor T6, and a second capacitor C2. Specifically, the control electrode of the third transistor T3 is electrically connected to the first pull-up node PU1, the first electrode of the third transistor T3 is electrically connected to the third clock signal terminal CK3, and the second electrode of the third transistor T3 is electrically connected to the first output terminal OUT1. The control electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, the first electrode of the fourth transistor T4 is electrically connected to the general pull-up node PUCN, and the second electrode of the fourth transistor T4 is electrically connected to the first pull-up node PU1. The control electrode of the fifth transistor T5 is electrically connected to the second pull-up node PU2, and the first electrode of the fifth transistor T5 is electrically connected to the fourth clock signal terminal. CK4 is electrically connected; the second terminal of the fifth transistor T5 is electrically connected to the second output terminal OUT2; the control terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VGH; the first terminal of the sixth transistor T6 is electrically connected to the total pull-up node PUCN; and the second terminal of the sixth transistor T6 is electrically connected to the second pull-up node PU2; the first terminal of the first capacitor C1 is electrically connected to the first pull-up node PU1; and the second terminal of the first capacitor C1 is electrically connected to the first output terminal OU1; the first terminal of the second capacitor C2 is electrically connected to the second pull-up node; and the second terminal of the second capacitor C2 is electrically connected to the second output terminal OUT2.

[0076] In an exemplary embodiment, when at least one output terminal includes a first drive output terminal, a first cascaded output terminal, a second drive output terminal, and a second cascaded output terminal, the output sub-circuit includes a first output sub-circuit and a second output sub-circuit. The first output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the third clock signal terminal, the first drive output terminal, and the first cascaded output terminal, respectively, and is configured to provide the third clock signal terminal to the first drive output terminal and the first cascaded output terminal, respectively, under the control of the signals from the main pull-up node and the first power supply terminal. The second output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the fourth clock signal terminal, the second drive output terminal, and the second cascaded output terminal, respectively, and is configured to provide the fourth clock signal terminal to the second drive output terminal and the second cascaded output terminal, respectively, under the control of the signals from the main pull-up node and the first power supply terminal.

[0077] As shown in Figure 3, the first output sub-circuit includes: a third transistor T3, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. The second output sub-circuit includes: a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. Specifically, the control electrode of the third transistor T3 is electrically connected to the first pull-up node PU1, the first electrode of the third transistor T3 is electrically connected to the third clock signal terminal CK3, and the second electrode of the third transistor T3 is electrically connected to the first drive output terminal OUT11. The control electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, the first electrode of the fourth transistor T4 is electrically connected to the total pull-up node PUCN, and the second electrode of the fourth transistor T4 is electrically connected to the first pull-up node PU1. The control electrode of the fifth transistor T5 is electrically connected to the second pull-up node PU2, the first electrode of the fifth transistor T5 is electrically connected to the fourth clock signal terminal CK4, and the second electrode of the fifth transistor T5 is electrically connected to the second drive output terminal OUT21. The control electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH. The first terminal of the sixth transistor T6 is electrically connected to the main pull-up node PUCN, and the second terminal of the sixth transistor T6 is electrically connected to the second pull-up node PU2; the control terminal of the seventh transistor T7 is electrically connected to the first pull-up node PU1, the first terminal of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, and the second terminal of the seventh transistor T7 is electrically connected to the first cascade output terminal OUT12; the control terminal of the eighth transistor T8 is electrically connected to the second pull-up node PU2, the first terminal of the eighth transistor T8 is electrically connected to the fourth clock signal terminal CK4, and the second terminal of the eighth transistor T8 is electrically connected to the second cascade output terminal OUT22; the first terminal of the first capacitor C1 is electrically connected to the first pull-up node PU1, and the second terminal of the first capacitor C1 is electrically connected to the first drive output terminal OUT11; the first terminal of the second capacitor C2 is electrically connected to the second pull-up node PU2, and the second terminal of the second capacitor C2 is electrically connected to the second drive output terminal OUT21.

[0078] Figures 2 and 3 illustrate an exemplary structure of the output sub-circuit. The implementation of the output sub-circuit is not limited to this; any implementation that achieves its function is acceptable.

[0079] In an exemplary embodiment, the first node control sub-circuit includes a pull-up sub-circuit and a pull-down sub-circuit. The pull-up sub-circuit is electrically connected to a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a first node, a second node, and a pull-down node, and is configured to provide a first power supply signal to the pull-down node under the control of the signals from the first clock signal terminal, the second clock signal terminal, the first node, and the second node. The pull-down sub-circuit is electrically connected to the pull-down node, the main pull-up node, and the second power supply terminal, and is configured to provide a second power supply signal to the pull-down node under the control of the signal from the main pull-up node.

[0080] As shown in Figures 2 and 3, the pull-up circuit includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and the pull-down circuit includes a twelfth transistor T12. Specifically, the control electrode of the ninth transistor T9 is electrically connected to the first control signal terminal CN, its first electrode is electrically connected to the first clock signal terminal CK1, and its second electrode is electrically connected to the third node N3; the control electrode of the tenth transistor T10 is electrically connected to the second control signal terminal CNB, its first electrode is electrically connected to the second clock signal terminal CK2, and its second electrode is electrically connected to the third node N3; the control electrode of the eleventh transistor T11 is electrically connected to the third node N3, its first electrode is electrically connected to the first power supply terminal VGH, and its second electrode is electrically connected to the pull-down node PD; the control electrode of the twelfth transistor T12 is electrically connected to the overall pull-up node PUCN, its first electrode is electrically connected to the second power supply terminal VGL, and its second electrode is electrically connected to the pull-down node PD.

[0081] Figures 2 and 3 illustrate an exemplary structure of the first node control sub-circuit. The implementation of the first node control sub-circuit is not limited to this; any implementation that achieves its function is acceptable.

[0082] In an exemplary embodiment, the second node control sub-circuit includes a node pull-down sub-circuit and an output pull-down sub-circuit. The node pull-down sub-circuit is electrically connected to a reset signal terminal, a second power supply terminal, a pull-down node, and a total pull-up node, and is configured to provide a signal from the second power supply terminal to the total pull-up node under the control of a signal from the pull-down node or the reset signal terminal. The output pull-down sub-circuit is electrically connected to a pull-down node, at least one output terminal, and a second power supply terminal, and is configured to provide a signal from the second power supply terminal to at least one output terminal under the control of a signal from the pull-down node.

[0083] As shown in Figures 2 and 3, the node pull-down sub-circuit includes: a thirteenth transistor T13 and a fourteenth transistor T14; the control terminal of the thirteenth transistor T13 is electrically connected to the pull-down node PD, the first terminal of the thirteenth transistor T13 is electrically connected to the second power supply terminal VGL, and the second terminal of the thirteenth transistor T13 is electrically connected to the total pull-up node PUCN; the control terminal of the fourteenth transistor T14 is electrically connected to the reset signal terminal TRST, the first terminal of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second terminal of the fourteenth transistor T14 is electrically connected to the total pull-up node PUCN.

[0084] As shown in Figure 2, when at least one output terminal includes a first output terminal OUT1 and a second output terminal OUT2, the output pull-down sub-circuit includes a fifteenth transistor T15, a sixteenth transistor T16, and a third capacitor C3. Specifically, the control electrode of the fifteenth transistor T15 is electrically connected to the pull-down node PD, the first electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected to the first output terminal OUT1; the control electrode of the sixteenth transistor T16 is electrically connected to the pull-down node PD, the first electrode of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixteenth transistor T16 is electrically connected to the second output terminal OUT2; the first terminal of the third capacitor C3 is electrically connected to the pull-down node PD, and the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0085] As shown in Figure 3, when at least one output terminal includes: a first drive output terminal OUT11, a first cascaded output terminal OUT12, a second drive output terminal OUT21, and a second cascaded output terminal OUT22, the output pull-down circuit includes: a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a third capacitor C3. Specifically, the control electrode of the fifteenth transistor T15 is electrically connected to the pull-down node PD, the first electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected to the first drive output terminal OUT11; the control electrode of the sixteenth transistor T16 is electrically connected to the pull-down node PD, the first electrode of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixteenth transistor T16 is electrically connected to the second drive output terminal OUT21; the control electrode of the seventeenth transistor T17 is electrically connected to the pull-down node PD, the first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal VGL, and the second electrode of the seventeenth transistor T17 is electrically connected to the first cascade output terminal OUT12; the control electrode of the eighteenth transistor T18 is electrically connected to the pull-down node PD, the first electrode of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL, and the second electrode of the eighteenth transistor T18 is electrically connected to the second cascade output terminal OUT22; the first terminal of the third capacitor C3 is electrically connected to the pull-down node PD, and the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0086] The setting of the third capacitor C3 in the second node control sub-circuit of this disclosure can ensure the stability of the signal of the pull-down node PD and improve the noise reduction effect of the shift register.

[0087] Figures 2 and 3 illustrate an exemplary structure of the second node control sub-circuit. The implementation of the second node control sub-circuit is not limited to this; any implementation that achieves its function is acceptable.

[0088] The configuration of the second node control sub-circuit in this disclosure can reduce the noise of the shift register and also ensure the normal operation of the shift register.

[0089] In an exemplary embodiment, when at least one output terminal includes a first output terminal OUT1 and a second output terminal OUT2, both the first output terminal OUT1 and the second output terminal OUT2 can provide driving signals to the pixel driving circuit located in the display area, and can also provide cascaded signals to one of the signal terminals of the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 connected to the shift registers of the remaining stages.

[0090] In an exemplary embodiment, when at least one output terminal includes: a first drive output terminal OUT11, a first cascaded output terminal OUT12, a second drive output terminal OUT21, and a second cascaded output terminal OUT22, the first drive output terminal OUT11 and the second drive output terminal OUT21 can provide drive signals to the pixel drive circuit disposed in the display area, and the first cascaded output terminal OUT12 and the second cascaded output terminal OUT22 can provide cascaded signals to one of the signal terminals of the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 connected to the shift registers of the remaining stages.

[0091] In an exemplary embodiment, the scan control subcircuit may include a first scan control subcircuit and a second scan control subcircuit. The first scan control subcircuit is electrically connected to a first control signal terminal, a second control signal terminal, a first scan input terminal, a second scan input terminal, and a first node, and is configured to provide a signal from the first scan input terminal to the first node under the control of the signal from the first control signal terminal, and to provide a signal from the second scan input terminal to the first node under the control of the signal from the second control signal terminal. The second scan control subcircuit is electrically connected to the first control signal terminal, the second control signal terminal, a first scan reset terminal, a second scan reset terminal, and a second node, and is configured to provide a signal from the first scan reset terminal to the second node under the control of the signal from the first control signal terminal, and to provide a signal from the second scan reset terminal to the second node under the control of the signal from the second control signal terminal.

[0092] As shown in Figures 2 and 3, the first scan control sub-circuit may include: the nineteenth transistor T19 and the twentieth transistor T20. The second scan control sub-circuit may include: the twenty-first transistor T21 and the twenty-second transistor T22. Specifically, the control electrode of the nineteenth transistor T19 is electrically connected to the first control signal terminal CN, the first electrode of the nineteenth transistor T19 is electrically connected to the first scan input terminal IN1, and the second electrode of the nineteenth transistor T19 is electrically connected to the first node N1; the control electrode of the twentieth transistor T20 is electrically connected to the second control signal terminal CNB, the first electrode of the twentieth transistor T20 is electrically connected to the second scan input terminal IN2, and the second electrode of the twentieth transistor T20 is electrically connected to the first node N1; the control electrode of the twenty-first transistor T21 is electrically connected to the second control signal terminal CNB, the first electrode of the twenty-first transistor T21 is electrically connected to the second scan reset terminal RST2, and the second electrode of the twenty-first transistor T21 is electrically connected to the second node N2; the control electrode of the twenty-second transistor T22 is electrically connected to the first control signal terminal CN, the first electrode of the twenty-second transistor T22 is electrically connected to the first scan reset terminal RST1, and the second electrode of the twenty-second transistor T22 is electrically connected to the second node N2.

[0093] A shift register is disposed in a display device, which may include an eye-focused area and a non-eye-focused area. In an exemplary embodiment, when the display device displays in the eye-focused area, it includes a first scanning state and a second scanning state. The first scanning state refers to a forward scanning state where the start time of the driving signal provided by the gate driving circuit to the i-th row pixel driving circuit is earlier than the start time of the driving signal provided by the gate driving circuit to the (i+1)-th row pixel driving circuit. The second scanning state refers to a reverse scanning state where the start time of the driving signal provided by the gate driving circuit to the (i+1)-th row pixel driving circuit is earlier than the start time of the driving signal provided by the gate driving circuit to the i-th row pixel driving circuit.

[0094] In an exemplary embodiment, when the display device scans forward, the signal at the first control signal terminal CN is an active level signal, and the signal at the second control signal terminal CNB is an inactive level signal. At this time, the nineteenth transistor T19 and the twenty-second transistor T22 are turned on, while the twentieth transistor T20 and the twenty-first transistor T21 are turned off. That is, during forward scanning, the signal written to the first node N1 is the signal at the first scan input terminal IN1, and the signal written to the second node N2 is the signal at the first scan reset terminal RST1. When the display device scans backward, the signal at the first control signal terminal CN is an inactive level signal, and the signal at the second control signal terminal CNB is an active level signal. At this time, the nineteenth transistor T19 and the twenty-second transistor T22 are turned on, while the twentieth transistor T20 and the twenty-first transistor T21 are turned off. That is, during reverse scanning, the signal written to the first node N1 is the signal at the second scan input terminal IN2, and the signal written to the second node N2 is the signal at the second scan reset terminal RST2. In this context, "signal at the signal terminal is an effective level signal" implies that the signal terminal is electrically connected to the control electrode of the transistor. An effective level signal at the signal terminal is a signal that turns on the transistor connected to the signal terminal, while an ineffective level signal at the signal terminal is a signal that turns off the transistor connected to the signal terminal. For example, when the transistor connected to the signal terminal is an N-type transistor, the effective level signal at the signal terminal is a high level signal, and the ineffective level signal at the signal terminal is a low level signal. When the transistor connected to the signal terminal is a P-type transistor, the effective level signal at the signal terminal is a low level signal, and the ineffective level signal at the signal terminal is a high level signal.

[0095] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0096] In an exemplary embodiment, all transistors in the shift register are N-type transistors. Exemplarily, all transistors in the shift register can be metal-oxide-semiconductor (MOS) transistors. Because MOS transistors have higher mobility and lower leakage current, using MOS transistors in the shift register can improve the refresh rate of the display product, enabling high-frequency displays, and also enabling low-frequency displays, thereby reducing power consumption.

[0097] In an exemplary embodiment, any of the transistors in FIG2 is an N-type transistor.

[0098] In an exemplary embodiment, any one of the first transistor T1 to the twenty-second transistor T22 in FIG3 is an N-type transistor.

[0099] This disclosure also provides a display device having a display area and a non-display area. The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit. The gate driving circuit includes: a plurality of cascaded shift registers provided in any of the foregoing embodiments; at least one shift register GOA is electrically connected to at least one row of pixel driving circuits and is configured to provide driving signals to the connected pixel driving circuits.

[0100] In an exemplary embodiment, Figure 4 is a schematic diagram of the shift register connections. As shown in Figure 4, the nth-stage shift register is electrically connected to the (2n-1)th row pixel driving circuit and the 2nth row pixel driving circuit, respectively, where 1 ≤ n ≤ N, and N is the total number of shift register stages included in the gate driving circuit. Exemplarily, the first-stage shift register GOA(1) is electrically connected to the first row pixel driving circuit R1 and the second row pixel driving circuit R2, respectively, and the second-stage shift register GOA(2) is electrically connected to the third row pixel driving circuit R3 and the fourth row pixel driving circuit R4, respectively, and so on.

[0101] In an exemplary embodiment, the first control signal terminal CN connected to at least one level shift register can be connected to the same signal line, and the second control signal terminal CNB connected to at least one level shift register can be connected to the same signal line.

[0102] In an exemplary embodiment, as shown in FIG4, at least one shift register is electrically connected to the first clock signal terminal CK1 to the fourth clock signal terminal CK4, and the display device further includes: the first clock signal line CLK1 to the twelfth clock signal line CLK12 disposed in the non-display area.

[0103] In an exemplary embodiment, the signal of at least one clock signal line includes: multiple pulse signals, wherein the start time of the j-th pulse of the k-th clock signal line is earlier than or equal to the start time of the j-th pulse of the (k+1)-th clock signal line, 1≤k≤K, 1≤l≤L, K is the total number of clock signal lines, and L is the number of pulse signals included in the signal of at least one clock signal line.

[0104] In an exemplary embodiment, as shown in FIG4, the first clock signal terminal CK1 of the 6r-5 stage shift register is electrically connected to the eighth clock signal line; the second clock signal terminal CK2 of the 6r-5 stage shift register is electrically connected to the seventh clock signal line; the third clock signal terminal CK3 of the 6r-5 stage shift register is electrically connected to the first clock signal line; and the fourth clock signal terminal CK4 of the 6r-5 stage shift register is electrically connected to the second clock signal line. The first clock signal terminal CK1 of the 6r-4 stage shift register is connected to... The tenth clock signal line is electrically connected; the second clock signal terminal CK2 of the 6r-4 stage shift register is electrically connected to the ninth clock signal line; the third clock signal terminal CK3 of the 6r-4 stage shift register is electrically connected to the third clock signal line; and the fourth clock signal terminal CK4 of the 6r-4 stage shift register is electrically connected to the fourth clock signal line. The first clock signal terminal CK1 of the 6r-3 stage shift register is electrically connected to the twelfth clock signal line; and the second clock signal terminal CK2 of the 6r-3 stage shift register is electrically connected to the eleventh clock signal line. The clock signal lines are electrically connected as follows: the third clock signal terminal CK3 of the 6r-3 stage shift register is electrically connected to the fifth clock signal line; the fourth clock signal terminal CK4 of the 6r-3 stage shift register is electrically connected to the sixth clock signal line; the first clock signal terminal CK1 of the 6r-2 stage shift register is electrically connected to the second clock signal line; the second clock signal terminal CK2 of the 6r-2 stage shift register is electrically connected to the first clock signal line; and the third clock signal terminal CK3 of the 6r-2 stage shift register is electrically connected to the seventh clock signal line. The fourth clock signal terminal CK4 of the 6r-2 stage shift register is electrically connected to the eighth clock signal line; the first clock signal terminal CK1 of the 6r-1 stage shift register is electrically connected to the fourth clock signal line; the second clock signal terminal CK2 of the 6r-1 stage shift register is electrically connected to the third clock signal line; the third clock signal terminal CK3 of the 6r-1 stage shift register is electrically connected to the ninth clock signal line; and the fourth clock signal terminal CK4 of the 6r-1 stage shift register is electrically connected to the tenth clock signal line.The first clock signal terminal CK1 of the 6r-stage shift register is electrically connected to the sixth clock signal line. The second clock signal terminal CK2 of the 6r-stage shift register is electrically connected to the fifth clock signal line. The third clock signal terminal CK3 of the 6r-stage shift register is electrically connected to the eleventh clock signal line. The fourth clock signal terminal CK4 of the 6r-stage shift register is electrically connected to the twelfth clock signal line. 1≤r≤N / 6, where N is the total number of shift register stages in the gate drive circuit. For example, the first clock signal terminal CK1 of the first-stage shift register GOA(1) is electrically connected to the eighth clock signal line CLK8; the second clock signal terminal CK2 of the first-stage shift register GOA(1) is electrically connected to the seventh clock signal line CLK7; the third clock signal terminal CK3 of the first-stage shift register GOA(1) is electrically connected to the first clock signal line CLK1; and the fourth clock signal terminal CK4 of the first-stage shift register GOA(1) is electrically connected to the second clock signal line CLK2. The first clock signal terminal CK1 of the second-stage shift register GOA(2) is electrically connected to the tenth clock signal line CLK10; the second clock signal terminal CK2 of the second-stage shift register GOA(2) is electrically connected to the ninth clock signal line CLK9; the third clock signal terminal CK3 of the second-stage shift register GOA(2) is electrically connected to the third clock signal line CLK3; and the fourth clock signal terminal CK4 of the second-stage shift register GOA(2) is electrically connected to the fourth clock signal line CLK4. Electrical connections; the first clock signal terminal CK1 of the third-level shift register GOA(3) is electrically connected to the twelfth clock signal line CLK12, the second clock signal terminal CK2 of the third-level shift register GOA(3) is electrically connected to the eleventh clock signal line CLK11, the third clock signal terminal CK3 of the third-level shift register GOA(3) is electrically connected to the fifth clock signal line CLK5, and the fourth clock signal terminal CK4 of the third-level shift register GOA(3) is electrically connected to the sixth clock signal line CLK6; the first clock signal terminal CK1 of the fourth-level shift register GOA(4) is electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the fourth-level shift register GOA(4) is electrically connected to the first clock signal line CLK1, the third clock signal terminal CK3 of the fourth-level shift register GOA(4) is electrically connected to the seventh clock signal line CLK7, and the fourth clock signal terminal CK4 of the fourth-level shift register GOA(4) is electrically connected to the eighth clock signal line CLK8;The first clock signal terminal CK1 of the fifth-level shift register GOA(5) is electrically connected to the fourth clock signal line CLK4. The second clock signal terminal CK2 of the fifth-level shift register GOA(5) is electrically connected to the third clock signal line CLK3. The third clock signal terminal CK3 of the fifth-level shift register GOA(5) is electrically connected to the ninth clock signal line CLK9. The fourth clock signal terminal CK4 of the fifth-level shift register GOA(5) is electrically connected to the tenth clock signal line CLK10. The first clock signal terminal CK1 of the sixth-level shift register GOA(6) is electrically connected to the sixth clock signal line CLK6. The second clock signal terminal CK2 of the sixth-level shift register GOA(6) is electrically connected to the fifth clock signal line CLK5. The third clock signal terminal CK3 of the sixth-level shift register GOA(6) is electrically connected to the eleventh clock signal line CLK11. The fourth clock signal terminal CK4 of the sixth-level shift register GOA(6) is electrically connected to the twelfth clock signal line CLK12. In the gate drive circuit, every six shift registers form a loop unit, and each loop unit has the same connection relationship with multiple clock signal lines.

[0105] In an exemplary embodiment, Figure 5 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 5, when at least one shift register is electrically connected to the first output terminal OUT1 and the second output terminal OUT2 respectively, the first output terminal OUT1 of the nth shift register is electrically connected to at least one of the signal terminals of the (2n-1)th row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register. The second output terminal OUT2 of the nth shift register is electrically connected to at least one of the signal terminals of the 2nth row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register. In Figure 5, OUT1(i) refers to the first output terminal connected to the i-th shift register, and OUT2(i) refers to the second output terminal connected to the i-th shift register.

[0106] As shown in Figure 5, the display device also includes a first initial signal line STV1 and a second initial signal line STV2 disposed in the non-display area.

[0107] In an exemplary embodiment, as shown in FIG5, the first scan input terminal IN1 of the first-stage shift register GOA(1) is electrically connected to the first initial signal line STV1; the first scan input terminal IN1 of the second-stage shift register GOA(2) is electrically connected to the second initial signal line STV2; the first scan input terminal IN1 of the N1-stage shift register is electrically connected to the second output terminal OUT2 of the N1-2-stage shift register, where 3≤N1≤N. Exemplarily, the first scan input terminal IN1 of the third-stage shift register GOA(3) is electrically connected to the second output terminal OUT2(1) of the first-stage shift register; the first scan input terminal IN1 of the fourth-stage shift register GOA(4) is electrically connected to the second output terminal OUT2(2) of the second-stage shift register, and so on.

[0108] In an exemplary embodiment, as shown in FIG5, the second scan input terminal IN2 connected to the N2-th stage shift register is electrically connected to the first output terminal OUT1 connected to the N2-3-th stage shift register, where 4≤N2≤N. Exemplarily, the second scan input terminal IN2 connected to the fourth stage shift register is electrically connected to the first output terminal OUT1(1) connected to the first stage shift register, the second scan input terminal IN2 connected to the fifth stage shift register is electrically connected to the first output terminal OUT1(2) connected to the second stage shift register, and so on.

[0109] In an exemplary embodiment, as shown in FIG5, the first scan reset terminal RST1 connected to the N3rd stage shift register is electrically connected to the second output terminal OUT2 connected to the N3+3rd stage shift register, where 1≤N3≤N-3. Exemplarily, the first scan reset terminal RST1 connected to the first stage shift register is electrically connected to the second output terminal OUT2(4) connected to the fourth stage shift register, the first scan reset terminal RST1 connected to the second stage shift register is electrically connected to the second output terminal OUT2(5) connected to the fifth stage shift register, and so on.

[0110] In an exemplary embodiment, as shown in FIG5, the second scan reset terminal RST2 connected to the N4th stage shift register is electrically connected to the first output terminal OUT1 connected to the N4+2th stage shift register, where 3≤N4≤N-2. Exemplarily, the second scan reset terminal RST2 connected to the third stage shift register is electrically connected to the first output terminal OUT1(5) connected to the fifth stage shift register, the second scan reset terminal RST2 connected to the fourth stage shift register is electrically connected to the first output terminal OUT1(6) connected to the sixth stage shift register, and so on.

[0111] In an exemplary embodiment, Figure 6 is a second schematic diagram of the cascading of multiple shift registers. As shown in Figure 6, at least one level of shift register is electrically connected to the first cascaded output terminal OUT12, the first drive output terminal OUT11, the second cascaded output terminal OUT22, and the second drive output terminal OUT21, respectively. The first drive output terminal OUT11 connected to the nth level shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal OUT12 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register. The second drive output terminal OUT21 connected to the nth level shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal OUT22 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register. In Figure 6, OUT11(i) refers to the first drive output terminal connected to the i-th stage shift register, OUT12(i) refers to the first cascaded output terminal connected to the i-th stage shift register, OUT21(i) refers to the second drive output terminal connected to the i-th stage shift register, and OUT22(i) refers to the second cascaded output terminal connected to the i-th stage shift register.

[0112] In an exemplary embodiment, as shown in FIG6, the display device further includes: a first initial signal line STV1 and a second initial signal line STV2 disposed in the non-display area.

[0113] In an exemplary embodiment, as shown in FIG6, the first scan input terminal IN1 of the first-stage shift register GOA(1) is electrically connected to the first initial signal line STV1, the first scan input terminal IN1 of the second-stage shift register is electrically connected to the second initial signal line STV2, the first scan input terminal IN1 of the N1-stage shift register is electrically connected to the second cascaded output terminal of the N1-2-stage shift register, and 3≤N1≤N. Exemplarily, the first scan input terminal IN1 of the third-stage shift register GOA(3) is electrically connected to the second cascaded output terminal OUT22(1) of the first-stage shift register, the first scan input terminal IN1 of the fourth-stage shift register GOA(4) is electrically connected to the second cascaded output terminal OUT22(2) of the second-stage shift register, and so on.

[0114] In an exemplary embodiment, as shown in FIG6, the second scan input terminal IN2 connected to the N2-th stage shift register is electrically connected to the first cascade output terminal OUT12 connected to the N2-3-th stage shift register, where 4 ≤ N2 ≤ N. Exemplarily, the second scan input terminal IN2 connected to the fourth stage shift register GOA(4) is electrically connected to the first cascade output terminal OUT12(1) connected to the first stage shift register GOA(1), the second scan input terminal IN2 connected to the fifth stage shift register is electrically connected to the first cascade output terminal OUT12(2) connected to the second stage shift register, and so on.

[0115] In an exemplary embodiment, as shown in FIG6, the first scan reset terminal RST1 connected to the N3rd stage shift register is electrically connected to the second cascaded output terminal OUT22 connected to the N3+3rd stage shift register, where 1≤N3≤N-3. Exemplarily, the first scan reset terminal RST1 connected to the first stage shift register is electrically connected to the second cascaded output terminal OUT22(4) connected to the fourth stage shift register, the first scan reset terminal RST1 connected to the second stage shift register is electrically connected to the second cascaded output terminal OUT22(5) connected to the fifth stage shift register, and so on.

[0116] In an exemplary embodiment, as shown in FIG6, the second scan reset terminal RST2 connected to the N4th stage shift register is electrically connected to the first cascaded output terminal OUT12 connected to the N4+2th stage shift register, where 3≤N4≤N-2. Exemplarily, the second scan reset terminal RST2 connected to the third stage shift register is electrically connected to the first cascaded output terminal OUT12(5) connected to the fifth stage shift register, the second scan reset terminal RST2 connected to the fourth stage shift register is electrically connected to the first output terminal OUT12(6) connected to the sixth stage shift register, and so on.

[0117] The shift registers shown in Figures 5 and 6 have the same cascading relationship, the only difference being the output terminals of the cascaded connections.

[0118] In an exemplary embodiment, Figure 7 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 7, when at least one shift register is electrically connected to the first output terminal OUT1 and the second output terminal OUT2 respectively, the first output terminal OUT1 of the nth shift register is electrically connected to at least one of the signal terminals of the (2n-1)th row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register. The second output terminal OUT2 of the nth shift register is electrically connected to at least one of the signal terminals of the 2nth row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register.

[0119] In an exemplary embodiment, as shown in FIG7, the display device further includes: a first initial signal line STV1 and a second initial signal line STV2 located in the non-display area.

[0120] In an exemplary embodiment, as shown in FIG7, the first scan input terminal IN1 of the first-stage shift register is electrically connected to the first initial signal line, the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line, the first scan input terminal IN1 of the N1-stage shift register is electrically connected to the second output terminal OUT2 of the N1-2-stage shift register, and 3≤N1≤N. Exemplarily, the first scan input terminal IN1 of the third-stage shift register is electrically connected to the second output terminal OUT2(1) of the first-stage shift register, the first scan input terminal IN1 of the fourth-stage shift register is electrically connected to the second output terminal OUT2(2) of the second-stage shift register, and so on.

[0121] In an exemplary embodiment, as shown in FIG7, the second scan input terminal IN2 connected to the N2-th stage shift register is electrically connected to the first output terminal OUT1 connected to the N2-4-th stage shift register, where 5≤N2≤N. Exemplarily, the second scan input terminal IN2 connected to the fifth stage shift register GOA(5) is electrically connected to the first output terminal OUT1(1) connected to the first stage shift register GOA(1), the second scan input terminal IN2 connected to the sixth stage shift register GOA(6) is electrically connected to the first output terminal OUT1(2) connected to the second stage shift register GOA(2), and so on.

[0122] In an exemplary embodiment, as shown in FIG7, the first scan reset terminal RST1 connected to the N3rd stage shift register is electrically connected to the second output terminal OUT2 connected to the N3+4th stage shift register, where 1≤N3≤N-4. Exemplarily, the first scan reset terminal RST1 connected to the first stage shift register GOA(1) is electrically connected to the second output terminal OUT2(5) connected to the fifth stage shift register, the first scan reset terminal RST1 connected to the second stage shift register GOA(2) is electrically connected to the second output terminal OUT2(6) connected to the sixth stage shift register GOA(6), and so on.

[0123] In an exemplary embodiment, as shown in FIG7, the second scan reset terminal RST2 connected to the N4th stage shift register is electrically connected to the first output terminal OUT1 connected to the N4+2th stage shift register, where 3≤N4≤N-2. Exemplarily, the second scan reset terminal RST2 connected to the third stage shift register GOA(3) is electrically connected to the first output terminal OUT1(5) connected to the fifth stage shift register GOA(5), the second scan reset terminal RST2 connected to the fourth stage shift register GOA(4) is electrically connected to the first output terminal OUT1(6) connected to the sixth stage shift register GOA(6), and so on.

[0124] In an exemplary embodiment, Figure 8 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 8, at least one level of shift register is electrically connected to the first cascaded output terminal OUT12, the first drive output terminal OUT11, the second cascaded output terminal OUT22, and the second drive output terminal OUT21, respectively. The first drive output terminal OUT11(n) connected to the nth level shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal OUT12(n) connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register. The second drive output terminal OUT21(n) connected to the nth level shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal OUT22(n) connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register.

[0125] In an exemplary embodiment, as shown in FIG8, the display device further includes: a first initial signal line STV1 and a second initial signal line STV2 disposed in the non-display area.

[0126] In an exemplary embodiment, as shown in FIG8, the first scan input terminal IN1 of the first-stage shift register is electrically connected to the first initial signal line STV1, the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line STV2, the first scan input terminal IN1 of the N1-stage shift register is electrically connected to the second cascaded output terminal OUT22 of the N1-2-stage shift register, and 3≤N1≤N. Exemplarily, the first scan input terminal IN1 of the third-stage shift register is electrically connected to the second cascaded output terminal OUT22(1) of the first-stage shift register, the first scan input terminal IN1 of the fourth-stage shift register is electrically connected to the second cascaded output terminal OUT22(2) of the second-stage shift register, and so on.

[0127] In an exemplary embodiment, as shown in FIG8, the second scan input terminal IN2 connected to the N2-th stage shift register is electrically connected to the first cascade output terminal OUT12 connected to the N2-4-th stage shift register, where 5 ≤ N2 ≤ N. Exemplarily, the second scan input terminal IN2 connected to the fifth stage shift register GOA(5) is electrically connected to the first cascade output terminal OUT12(1) connected to the first stage shift register GOA(1), the second scan input terminal IN2 connected to the sixth stage shift register GOA(6) is electrically connected to the first cascade output terminal OUT12(2) connected to the second stage shift register GOA(2), and so on.

[0128] In an exemplary embodiment, as shown in FIG8, the first scan reset terminal RST1 connected to the N3rd stage shift register is electrically connected to the second cascaded output terminal OUT22 connected to the N3+4th stage shift register, where 1≤N3≤N-4. Exemplarily, the first scan reset terminal RST1 connected to the first stage shift register GOA(1) is electrically connected to the second cascaded output terminal OUT22(5) connected to the fifth stage shift register, the first scan reset terminal RST1 connected to the second stage shift register GOA(2) is electrically connected to the second cascaded output terminal OUT22(6) connected to the sixth stage shift register GOA(6), and so on.

[0129] In an exemplary embodiment, as shown in FIG8, the second scan reset terminal RST2 connected to the N4th stage shift register is electrically connected to the first cascade output terminal OUT12 connected to the N4+2th stage shift register, where 3≤N4≤N-2. Exemplarily, the second scan reset terminal RST2 connected to the third stage shift register GOA(3) is electrically connected to the first cascade output terminal OUT12(5) connected to the fifth stage shift register GOA(5), the second scan reset terminal RST2 connected to the fourth stage shift register GOA(4) is electrically connected to the first cascade output terminal OUT12(6) connected to the sixth stage shift register GOA(6), and so on.

[0130] The cascading relationships of the shift registers shown in Figures 7 and 8 are the same, differing only in the output terminals of the cascaded connections. The cascading relationships of the shift registers shown in Figures 5 and 6 differ from those shown in Figures 7 and 8.

[0131] Figure 9 is a schematic diagram of multiple clock signal lines in the non-eye-focused area. Figure 9 uses twelve clock signal lines, specifically clock signal lines CLK1 through CLK12, as an example. When the content displayed on the display device is in the eye-focused area, at least two of the multiple clock signal lines have the same clock signal. Figure 9 illustrates this using the following examples: clock signal lines CLK1 and CLK2 have the same signal; clock signal lines CLK3 and CLK4 have the same signal; clock signal lines CLK5 and CLK6 have the same signal; clock signal lines CLK7 and CLK8 have the same signal; clock signal lines CLK9 and CLK10 have the same signal; and clock signal lines CLK11 and CLK12 have the same signal.

[0132] Figure 10 is a schematic diagram of multiple clock signal lines in the eye's gaze area. Figure 10 uses twelve clock signal lines, specifically clock signal lines CLK1 to CLK12, as an example. When the displayed content is shown in the non-eye-gazing area, at least two of the multiple clock signal lines will have different clock signals.

[0133] Figure 11 is a timing diagram of the shift register provided in Figure 2 in the first scan state. The operation process of the shift register in the first scan state provided in this embodiment includes the following steps:

[0134] In the first stage S1, the input stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 to the fourth clock signal terminal CK4 are low, the signal at the first scan input terminal IN1 is high, and the signals at the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 are low. The ninth transistor T9, the nineteenth transistor T19, and the twenty-second transistor T22 are turned on, while the tenth transistor T10, the twentieth transistor T20, and the twenty-first transistor T21 are turned off.

[0135] When transistor T19 is turned on, the high-level signal of the first scan input terminal IN1 is written to the first node N1. When transistor T1 is turned on, the high-level signal of the first control signal terminal CN is written to the total pull-up node PUCN. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turned-on fourth transistor T4. When transistor T3 is turned on, the low-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turned-on sixth transistor T6. When transistor T5 is turned on, the low-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. When transistor T22 is turned on, the low-level signal of the first scan reset terminal RST1 is written to the second node N2. When transistor T2 is turned off, the total pull-up node PUCN will not be pulled low by the signal of the second control signal terminal CNB. When transistor T9 is turned on, the low-level signal of the first clock signal terminal CK1 is written to the third node N3. When transistor T11 is turned off, the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0136] In the second stage S2, the output stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are low, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, and the signals at the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 are low. The ninth transistor T9, the nineteenth transistor T19, and the twenty-second transistor T22 are turned on, while the tenth transistor T10, the twentieth transistor T20, and the twenty-first transistor T21 are turned off.

[0137] When transistor T19 is turned on, the low-level signal of the first scan input terminal IN1 is written to the first node N1. When transistor T1 is turned off, under the bootstrap effect of the first capacitor C1 and the third capacitor C3, the total pull-up node PUCN maintains the high-level signal of the previous stage. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turn-on fourth transistor T4. The third transistor T3 remains on, and the high-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turn-on sixth transistor T6. When transistor T5 is turned on, the high-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. When transistor T22 is turned on, the low-level signal of the first scan reset terminal RST1 is written to the second node N2. When transistor T2 is turned off, the total pull-up node PUCN will not be pulled low by the signal of the second control signal terminal CNB. When the ninth transistor T9 is turned on, the low-level signal of the first clock signal terminal CK1 is written to the third node N3. When the eleventh transistor T11 is turned off, the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0138] In the third stage (S3), the noise reduction stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high for a portion of the time, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, the signals at the first scan input terminal IN1 and the second scan input terminal IN2 are low, and the signals at the first scan reset terminal RST1 and the second scan reset terminal RST2 are high for a portion of the time. Transistors T9, T19, and T22 are turned on, while transistors T10, T20, and T21 are turned off.

[0139] When the ninth transistor T9 is turned on, the high-level signal of the first clock signal terminal CK1 is written to the third node N3. When the eleventh transistor T11 is turned on, the high-level signal of the first power supply terminal VGH is written to the pull-down node PD. When the thirteenth transistor T13 is turned on, the low-level signal of the second power supply terminal VGL is written to the total pull-up node PUCN. When the third transistor T3 and the fifth transistor T5 are turned off, the fifteenth transistor T1 is turned on, and the low-level signal of the second power supply terminal VGL is written to the first output terminal OUT1. When the sixteenth transistor T16 is turned on, the low-level signal of the second power supply terminal VGL is written to the second output terminal OUT2.

[0140] Figure 12 is a timing diagram of the shift register provided in Figure 2 operating in the second scan state. The operation process of the shift register provided in this embodiment of the present disclosure in the second scan state includes the following steps:

[0141] In the first stage S1, the input stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 to the fourth clock signal terminal CK4 are low, the signal at the second scan reset terminal RST2 is high, and the signals at the first scan input terminal IN1, the second scan input terminal IN2, and the first scan reset terminal RST1 are low. The ninth transistor T9, the nineteenth transistor T19, and the twenty-second transistor T22 are off, while the tenth transistor T10, the twentieth transistor T20, and the twenty-first transistor T21 are on.

[0142] When transistor T21 is turned on, the high-level signal of the second scan reset terminal RST2 is written to the second node N2. When transistor T2 is turned on, the high-level signal of the second control signal terminal CNB is written to the total pull-up node PUCN. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turned-on fourth transistor T4. When transistor T3 is turned on, the low-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turned-on sixth transistor T6. When transistor T5 is turned on, the low-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. When transistor T20 is turned on, the low-level signal of the second scan input terminal IN2 is written to the first node N1. When transistor T1 is turned off, the total pull-up node PUCN will not be pulled low by the signal of the first control signal terminal CN. When transistor T10 is turned on, the low-level signal of the second clock signal terminal CK2 is written to the third node N3. When transistor T11 is turned off, the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0143] In the second stage S2, the output stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are low, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, and the signals at the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 are low. The ninth transistor T9, the nineteenth transistor T19, and the twenty-second transistor T22 are off, while the tenth transistor T10, the twentieth transistor T20, and the twenty-first transistor T21 are on.

[0144] When transistor T21 is turned on, the low-level signal of the second scan reset terminal RST2 is written to the second node N2. When transistor T2 is turned off, under the bootstrap effect of the first capacitor C1 and the third capacitor C3, the total pull-up node PUCN maintains the high-level signal of the previous stage. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turned-on fourth transistor T4. The third transistor T3 remains on, and the high-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turned-on sixth transistor T6. When transistor T5 is turned on, the high-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. When transistor T22 is turned on, the low-level signal of the first scan reset terminal RST1 is written to the second node N2. When transistor T2 is turned off, the total pull-up node PUCN will not be pulled low by the signal of the second control signal terminal CNB. When the tenth transistor T10 is turned on, the low-level signal of the second clock signal terminal CK2 is written to the third node N3. When the eleventh transistor T11 is turned off, the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0145] In the third stage (S3), the noise reduction stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high for a portion of the time, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, the signals at the first scan input terminal IN1 and the second scan input terminal IN2 are high for a portion of the time, and the signals at the first scan reset terminal RST1 and the second scan reset terminal RST2 are low. Transistors T9, T19, and T22 are off, while transistors T10, T20, and T21 are on.

[0146] The tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CK2 is written to the third node N3. The eleventh transistor T11 is turned on, and the high-level signal of the first power supply terminal VGH is written to the pull-down node PD. The thirteenth transistor T13 is turned on, and the low-level signal of the second power supply terminal VGL is written to the total pull-up node PUCN. The third transistor T3 and the fifth transistor T5 are turned off. The fifteenth transistor T15 is turned on, and the low-level signal of the second power supply terminal VGL is written to the first output terminal OUT1. The sixteenth transistor T16 is turned on, and the low-level signal of the second power supply terminal VGL is written to the second output terminal OUT2.

[0147] The shift register shown in Figure 3 has the same operating timing as the shift register shown in Figure 2, and will not be described again here.

[0148] Figures 11 and 12 illustrate the operation of a shift register in the eye-fixing area using an example. The only difference between the operation of a shift register in the non-eye-fixing area and the shift register in the eye-fixing area is whether the first and second output terminals are output simultaneously during the output phase. In the eye-fixing area, the signals of the first and second output terminals are output simultaneously during the output phase, which will not be elaborated further in this disclosure.

[0149] In summary, the gate drive circuit in the display device provided in this disclosure can achieve both forward scanning and reverse scanning, thereby improving the reliability of the display device.

[0150] This disclosure also provides a method for driving a shift register, configured to drive the shift register provided in any of the foregoing embodiments. The driving method includes:

[0151] The input sub-circuit, under the control of the signal of the first node, provides the signal of the first control signal terminal to the main pull-up node, and under the control of the signal of the second node, provides the signal of the second control signal terminal to the main pull-up node;

[0152] Under the control of the signals from the main pull-up node and the first power supply terminal, the output sub-circuit provides a signal from one of the clock signal terminals to one of the at least one output terminal.

[0153] Under the control of the signals at the first control signal terminal and the second control signal terminal, the scan control sub-circuit provides the first scan input terminal or the second scan input terminal signal to the first node, and provides the first scan reset terminal or the second scan reset terminal signal to the second node.

[0154] This disclosure also provides a display device having a display area and a non-display area. The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers, and the shift registers include an input sub-circuit, an output sub-circuit, and a first node control sub-circuit.

[0155] An input sub-circuit, electrically connected to the scan input terminal, scan reset terminal, second node, first control signal terminal, second control signal terminal, and main pull-up node, is configured to provide a signal from the first control signal terminal to the main pull-up node under the control of the signal from the scan input terminal, and to provide a signal from the second control signal terminal to the main pull-up node under the control of the signal from the scan reset terminal. An output sub-circuit, electrically connected to the main pull-up node, first power supply terminal, third clock signal terminal, fourth clock signal terminal, and at least one output terminal, is configured to provide a signal from at least one of the at least one clock signal terminals to one of the at least one output terminal under the control of the signals from the main pull-up node and the first power supply terminal. A first node control sub-circuit, electrically connected to the first clock signal terminal, second clock signal terminal, first control signal terminal, second control signal terminal, main pull-up node, first power supply terminal, second power supply terminal, and pull-down node, is configured to provide a signal from the first power supply terminal or the second power supply terminal to the pull-down node under the control of the signals from the first clock signal terminal, second clock signal terminal, first control signal terminal, second control signal terminal, and main pull-up node.

[0156] In an exemplary embodiment, FIG13 is an equivalent circuit diagram of a shift register provided in another exemplary embodiment. As shown in FIG13, the shift register includes: first transistors T1 to sixth transistors T6, ninth transistors T9 to sixteenth transistors T16, and first capacitors C1 to third capacitors C3. The control electrode of the first transistor T1 is electrically connected to the scan input terminal IN, the first electrode of the first transistor T1 is electrically connected to the first control signal terminal CN, and the second electrode of the first transistor T1 is electrically connected to the total pull-up node PUCN; the control electrode of the second transistor T2 is electrically connected to the scan reset terminal RST, the first electrode of the second transistor T2 is electrically connected to the second control signal terminal CNB, and the second electrode of the second transistor T2 is electrically connected to the total pull-up node PUCN; the control electrode of the third transistor T3 is electrically connected to the first pull-up node PU1, the first electrode of the third transistor T3 is electrically connected to the third clock signal terminal CK3, and the third transistor... The second terminal of transistor T3 is electrically connected to the first output terminal OUT1; the control terminal of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, the first terminal of the fourth transistor T4 is electrically connected to the total pull-up node PUCN, and the second terminal of the fourth transistor T4 is electrically connected to the first pull-up node PU1; the control terminal of the fifth transistor T5 is electrically connected to the second pull-up node PU2, the first terminal of the fifth transistor T5 is electrically connected to the fourth clock signal terminal CK4, and the second terminal of the fifth transistor T5 is electrically connected to the second output terminal OUT2; the control terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the first terminal of the sixth transistor T6 is electrically connected to the total pull-up node PU1; the control terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the first terminal of the sixth transistor T6 is electrically connected to the first pull-up node PU1; the control terminal of the fifth transistor T5 is electrically connected to the second pull-up node PU2, the first terminal of the sixth transistor T6 is electrically connected to the fourth clock signal terminal CK4, and the second terminal of the fifth transistor T5 is electrically connected to the second output terminal OUT2; the control terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and the first terminal of the sixth transistor T6 is electrically connected to the first clock signal terminal CK4. Pull-up node PUCN is electrically connected; the second terminal of the sixth transistor T6 is electrically connected to the second pull-up node PU2; the control terminal of the ninth transistor T9 is electrically connected to the first control signal terminal CN; the first terminal of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1; the second terminal of the ninth transistor T9 is electrically connected to the third node N3; the control terminal of the tenth transistor T10 is electrically connected to the second control signal terminal CNB; the first terminal of the tenth transistor T10 is electrically connected to the second clock signal terminal CK2; the second terminal of the tenth transistor T10 is electrically connected to the third node N3; the control terminal of the eleventh transistor T11 is electrically connected to the third node N3. Electrical connections: The first terminal of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second terminal of the eleventh transistor T11 is electrically connected to the pull-down node PD; the control terminal of the twelfth transistor T12 is electrically connected to the total pull-up node PUCN, the first terminal of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, and the second terminal of the twelfth transistor T12 is electrically connected to the pull-down node PD; the control terminal of the thirteenth transistor T13 is electrically connected to the pull-down node PD, the first terminal of the thirteenth transistor T13 is electrically connected to the second power supply terminal VGL, and the second terminal of the thirteenth transistor T13 is electrically connected to the total pull-up node PUCN.The control electrode of the fourteenth transistor T14 is electrically connected to the reset signal terminal TRST. The first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourteenth transistor T14 is electrically connected to the total pull-up node PUCN. The control electrode of the fifteenth transistor T15 is electrically connected to the pull-down node PD. The first electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected to the first output terminal OUT1. The control electrode of the sixteenth transistor T16 is electrically connected to the pull-down node PD. The first electrode of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixteenth transistor T16 is electrically connected to the second output terminal OUT2. The first terminal of the first capacitor C1 is electrically connected to the first pull-up node PU1, and the second terminal of the first capacitor C1 is electrically connected to the first output terminal OUT1. The first terminal of the second capacitor C2 is electrically connected to the second pull-up node PU2, and the second terminal of the second capacitor C2 is electrically connected to the second output terminal OUT2. The first terminal of the third capacitor C3 is electrically connected to the pull-down node PD, and the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0157] In an exemplary embodiment, FIG14 is an equivalent circuit diagram of a shift register provided in another exemplary embodiment. As shown in FIG14, the shift register includes: a first transistor T1 to an eighteenth transistor T18 and a first capacitor C1 to a third capacitor C3. Specifically, the control electrode of the first transistor T1 is electrically connected to the scan input terminal IN, the first electrode of the first transistor T1 is electrically connected to the first control signal terminal CN, and the second electrode of the first transistor T1 is electrically connected to the total pull-up node PUCN; the control electrode of the second transistor T2 is electrically connected to the scan reset terminal RST, the first electrode of the second transistor T2 is electrically connected to the second control signal terminal CNB, and the second electrode of the second transistor T2 is electrically connected to the total pull-up node PUCN; the control electrode of the third transistor T3 is electrically connected to the first pull-up node PU1, the first electrode of the third transistor T3 is electrically connected to the third clock signal terminal CK3, and the second electrode of the third transistor T3 is electrically connected to the first drive output terminal OUT11; the control electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, the first electrode of the fourth transistor T4 is electrically connected to the total pull-up node PUCN, and the second electrode of the fourth transistor T4 is electrically connected to the first pull-up node PU1; the control electrode of the fifth transistor T5 is electrically connected to the second pull-up node PU2, and the first electrode of the fifth transistor T5 is electrically connected to the fourth clock signal terminal CK4. The second terminal of the fifth transistor T5 is electrically connected to the second drive output terminal OUT21; the control terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, the first terminal of the sixth transistor T6 is electrically connected to the total pull-up node PUCN, and the second terminal of the sixth transistor T6 is electrically connected to the second pull-up node PU2; the control terminal of the seventh transistor T7 is electrically connected to the first pull-up node PU1, the first terminal of the seventh transistor T7 is electrically connected to the third clock signal terminal CK3, and the second terminal of the seventh transistor T7 is electrically connected to the first cascade output terminal OUT12; the control terminal of the eighth transistor T8 is electrically connected to the second pull-up node PU2, the first terminal of the eighth transistor T8 is electrically connected to the fourth clock signal terminal CK4, and the second terminal of the eighth transistor T8 is electrically connected to the second drive output terminal OUT21. The control electrode of the ninth transistor T9 is electrically connected to the first control signal terminal CN, the first electrode of the ninth transistor T9 is electrically connected to the first clock signal terminal CK1, and the second electrode of the ninth transistor T9 is electrically connected to the third node N3; the control electrode of the tenth transistor T10 is electrically connected to the second control signal terminal CNB, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CK2, and the second electrode of the tenth transistor T10 is electrically connected to the third node N3; the control electrode of the eleventh transistor T11 is electrically connected to the third node N3, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the pull-down node PD;The control electrode of the twelfth transistor T12 is electrically connected to the main pull-up node PUCN, the first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, and the second electrode of the twelfth transistor T12 is electrically connected to the pull-down node PD; the control electrode of the thirteenth transistor T13 is electrically connected to the pull-down node PD, the first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VGL, and the second electrode of the thirteenth transistor T13 is electrically connected to the main pull-up node PUCN; the control electrode of the fourteenth transistor T14 is electrically connected to the reset signal terminal TRST, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourteenth transistor T14 is electrically connected to the main pull-up node PUCN; the control electrode of the fifteenth transistor T15 is electrically connected to the pull-down node PD, the first electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifteenth transistor T15 is electrically connected to the first drive output terminal OUT11; the control electrode of the sixteenth transistor T16 is electrically connected to the pull-down node PD, and the second electrode of the sixteenth transistor T16 is electrically connected to the first drive output terminal OUT11; The first terminal of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL; the second terminal of the sixteenth transistor T16 is electrically connected to the second drive output terminal OUT21; the control terminal of the seventeenth transistor T17 is electrically connected to the pull-down node PD; the first terminal of the seventeenth transistor T17 is electrically connected to the second power supply terminal VGL; the second terminal of the seventeenth transistor T17 is electrically connected to the first cascade output terminal OUT12; the control terminal of the eighteenth transistor T18 is electrically connected to the pull-down node PD; the first terminal of the eighteenth transistor T18 is electrically connected to the second power supply terminal VGL; the second terminal of the eighteenth transistor T18 is electrically connected to the second cascade output terminal OUT22; the first terminal of the first capacitor C1 is electrically connected to the first pull-up node PU1; the second terminal of the first capacitor C1 is electrically connected to the first output terminal OUT1; the first terminal of the second capacitor C2 is electrically connected to the second pull-up node PU2; the second terminal of the second capacitor C2 is electrically connected to the second output terminal OUT2; the first terminal of the third capacitor C3 is electrically connected to the pull-down node PD; the second terminal of the third capacitor C3 is electrically connected to the second power supply terminal VGL.

[0158] In an exemplary embodiment, FIG15 is a connection diagram of another gate drive circuit. As shown in FIG15, at least one shift register is electrically connected to the first clock signal terminal CK1 to the fourth clock signal terminal CK4, and the display device includes: the first clock signal line CLK1 to the sixteenth clock signal line CLK16 disposed in the non-display area.

[0159] The signal of at least one clock signal line includes: multiple pulse signals, the start time of the j-th pulse of the k-th clock signal line is earlier than or equal to the start time of the j-th pulse of the (k+1)-th clock signal line, 1≤k≤K, 1≤l≤L, K is the total number of clock signal lines, and L is the number of pulse signals included in the signal of at least one clock signal line.

[0160] As shown in Figure 15, the first clock signal terminal CK1 of the 8s-7 stage shift register is electrically connected to the eighth clock signal line CLK8; the second clock signal terminal CK2 of the 8s-7 stage shift register is electrically connected to the seventh clock signal line CLK7; the third clock signal terminal CK3 of the 8s-7 stage shift register is electrically connected to the first clock signal line CLK8; and the fourth clock signal terminal CK4 of the 8s-7 stage shift register is electrically connected to the second clock signal line CLK2. The first clock signal terminal of the 8s-6 stage shift register is... The first clock signal terminal CK1 is electrically connected to the tenth clock signal line CLK10; the second clock signal terminal CK2, connected to the 8s-6 stage shift register, is electrically connected to the ninth clock signal line CLK9; the third clock signal terminal CK3, connected to the 8s-6 stage shift register, is electrically connected to the third clock signal line CLK3; the fourth clock signal terminal CK4, connected to the 8s-6 stage shift register, is electrically connected to the fourth clock signal line CLK4; the first clock signal terminal CK1, connected to the 8s-5 stage shift register, is electrically connected to the twelfth clock signal line CLK12. The second clock signal terminal CK2 of the 8s-5 stage shift register is electrically connected to the eleventh clock signal line CLK11; the third clock signal terminal CK3 of the 8s-5 stage shift register is electrically connected to the fifth clock signal line CLK5; and the fourth clock signal terminal CK4 of the 8s-5 stage shift register is electrically connected to the sixth clock signal line CLK6. The first clock signal terminal CK1 of the 8s-4 stage shift register is electrically connected to the fourteenth clock signal line CLK14; the second clock signal terminal CK2 of the 8s-4 stage shift register is electrically connected to the thirteenth clock signal line CLK13; and the third clock signal terminal of the 8s-4 stage shift register is electrically connected to the... Terminal CK3 is electrically connected to the seventh clock signal line CLK7; terminal CK4, the fourth clock signal line of the 8s-4 stage shift register, is electrically connected to the eighth clock signal line CLK8; terminal CK1, the first clock signal line of the 8s-3 stage shift register, is electrically connected to the sixteenth clock signal line CLK16; terminal CK2, the second clock signal line of the 8s-3 stage shift register, is electrically connected to the fifteenth clock signal line CLK15; terminal CK3, the third clock signal line of the 8s-3 stage shift register, is electrically connected to the ninth clock signal line CLK9; and terminal CK4, the fourth clock signal line of the 8s-3 stage shift register, is electrically connected to the tenth clock signal line CLK10.The first clock signal terminal CK1 of the 8s-2 stage shift register is electrically connected to the second clock signal line CLK2; the second clock signal terminal CK2 of the 8s-2 stage shift register is electrically connected to the first clock signal line CLK1; the third clock signal terminal CK3 of the 8s-2 stage shift register is electrically connected to the eleventh clock signal line CLK11; and the fourth clock signal terminal CK4 of the 8s-2 stage shift register is electrically connected to the twelfth clock signal line CLK12. Similarly, the first clock signal terminal CK1 of the 8s-1 stage shift register is electrically connected to the fourth clock signal line CLK4; the second clock signal terminal CK2 of the 8s-1 stage shift register is electrically connected to the third clock signal line CLK3; and the 8s-1 stage shift register... The third clock signal terminal CK3 is electrically connected to the thirteenth clock signal line CLK13; the fourth clock signal terminal CK4 of the 8s-1 stage shift register is electrically connected to the fourteenth clock signal line CLK14; the first clock signal terminal CK1 of the 8s stage shift register is electrically connected to the sixth clock signal line CLK6; the second clock signal terminal CK2 of the 8s stage shift register is electrically connected to the fifth clock signal line CLK5; the third clock signal terminal CK3 of the 8s stage shift register is electrically connected to the fifteenth clock signal line CLK15; and the fourth clock signal terminal CK4 of the 8s stage shift register is electrically connected to the sixteenth clock signal line CLK16. 1 ≤ s ≤ N / 8, where N is the total number of shift register stages in the gate drive circuit. Because the number of clock signal lines in this embodiment differs from the number of clock signal lines provided in the previous embodiment, the parameters used to describe the connection relationship between the clock signal terminals and clock signal lines are different.

[0161] Figure 16 is a schematic diagram of multiple clock signal lines in the non-eye-focused area. Figure 16 uses sixteen clock signal lines, specifically clock signal lines CLK1 through CLK16, as an example. When the content displayed on the display device is in the eye-focused area, at least two of the multiple clock signal lines have the same clock signal. Figure 16 illustrates this using the following examples: clock signal lines CLK2 and CLK3 have the same signal; clock signal lines CLK4 and CLK5 have the same signal; clock signal lines CLK6 and CLK7 have the same signal; clock signal lines CLK8 and CLK9 have the same signal; clock signal lines CLK10 and CLK11 have the same signal; and clock signal lines CLK12 and CLK13 have the same signal.

[0162] Figure 17 is a schematic diagram of multiple clock signal lines in the eye's gaze area (Figure 2). Figure 17 uses sixteen clock signal lines, specifically clock signal lines CLK1 to CLK16, as an example. When the displayed content is shown in the non-eye-gazing area, at least two of the multiple clock signal lines will have different clock signals.

[0163] In an exemplary embodiment, the display device further includes a first initial signal line and a second initial signal line located in a non-display area.

[0164] In an exemplary embodiment, Figure 18 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 18, when at least one shift register is electrically connected to the first output terminal OUT1 and the second output terminal OUT2 respectively, the first output terminal OUT1 of the nth shift register is electrically connected to at least one of the signal terminals of the (2n-1)th row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register. The second output terminal OUT2 of the nth shift register is electrically connected to at least one of the signal terminals of the 2nth row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register.

[0165] As shown in Figure 18, the scan input terminal IN connected to the first-stage shift register GOA(1) and the second-stage shift register GOA(2) is electrically connected to the first initial signal line STV1, and the scan input terminal IN connected to the third-stage shift register GOA(3) and the fourth-stage shift register GOA(4) is electrically connected to the second initial signal line STV2.

[0166] As shown in Figure 18, the scan reset terminal connected to the M1-th stage shift register is electrically connected to the second output terminal OUT2 connected to the M1+4-th stage shift register, where 1≤M1≤N-4. For example, the scan reset terminal RST connected to the first-stage shift register GOA(1) is electrically connected to the second output terminal OUT2(5) connected to the fifth-stage shift register, the scan reset terminal RST connected to the second-stage shift register GOA(2) is electrically connected to the second output terminal OUT2(6) connected to the sixth-stage shift register, and so on.

[0167] As shown in Figure 18, the scan input terminal connected to the M2-level shift register is electrically connected to the second output terminal OUT2 connected to the M2-4-level shift register, where 5 ≤ M2 ≤ N. For example, the scan input terminal IN connected to the fifth-level shift register GOA(5) is electrically connected to the second output terminal OUT2(1) connected to the first-level shift register, the scan input terminal IN connected to the sixth-level shift register GOA(6) is electrically connected to the second output terminal OUT2(2) connected to the second-level shift register, and so on.

[0168] In an exemplary embodiment, Figure 19 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 19, at least one level of shift register is electrically connected to the first cascaded output terminal OUT12, the first drive output terminal OUT11, the second cascaded output terminal OUT22, and the second drive output terminal OUT21, respectively. The first drive output terminal OUT11 connected to the nth level shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal OUT12 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register. The second drive output terminal OUT21 connected to the nth level shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal OUT22 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register.

[0169] As shown in Figure 19, the scan input terminal IN connected to the first-stage shift register GOA(1) and the second-stage shift register GOA(2) is electrically connected to the first initial signal line STV1, and the scan input terminal IN connected to the third-stage shift register GOA(3) and the fourth-stage shift register GOA(4) is electrically connected to the second initial signal line STV2.

[0170] As shown in Figure 19, the scan reset terminal connected to the M1-th stage shift register is electrically connected to the second cascaded output terminal OUT22 connected to the M1+4-th stage shift register, where 1≤M1≤N-4. For example, the scan reset terminal RST connected to the first-stage shift register GOA(1) is electrically connected to the second cascaded output terminal OUT22(5) connected to the fifth-stage shift register, the scan reset terminal RST connected to the second-stage shift register GOA(2) is electrically connected to the second cascaded output terminal OUT22(6) connected to the sixth-stage shift register, and so on.

[0171] As shown in Figure 19, the scan input terminal connected to the M2-level shift register is electrically connected to the second cascaded output terminal OUT22 connected to the M2-4-level shift register, where 5 ≤ M2 ≤ N. For example, the scan input terminal IN connected to the fifth-level shift register GOA(5) is electrically connected to the second cascaded output terminal OUT22(1) connected to the first-level shift register, the scan input terminal IN connected to the sixth-level shift register GOA(6) is electrically connected to the second cascaded output terminal OUT22(2) connected to the second-level shift register, and so on.

[0172] In an exemplary embodiment, Figure 20 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 20, when at least one shift register is electrically connected to the first output terminal OUT1 and the second output terminal OUT2 respectively, the first output terminal OUT1 of the nth shift register is electrically connected to at least one of the signal terminals of the (2n-1)th row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register. The second output terminal OUT2 of the nth shift register is electrically connected to at least one of the signal terminals of the 2nth row pixel driving circuit and the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one shift register.

[0173] As shown in Figure 20, the scan input terminal IN connected to the first-stage shift register GOA(1) and the second-stage shift register GOA(2) is electrically connected to the first initial signal line STV1, and the scan input terminal IN connected to the third-stage shift register GOA(3) and the fourth-stage shift register GOA(4) is electrically connected to the second initial signal line STV2.

[0174] As shown in Figure 20, the scan reset terminal connected to the M1-th stage shift register is electrically connected to the second output terminal OUT2 connected to the M1+4-th stage shift register, where 1≤M1≤N-4. For example, the scan reset terminal RST connected to the first-stage shift register GOA(1) is electrically connected to the second output terminal OUT2(5) connected to the fifth-stage shift register, the scan reset terminal RST connected to the second-stage shift register GOA(2) is electrically connected to the second output terminal OUT2(6) connected to the sixth-stage shift register, and so on.

[0175] As shown in Figure 20, the scan input terminal connected to the M2-level shift register is electrically connected to the first output terminal OUT1 connected to the M2-4-level shift registers, where 5 ≤ M2 ≤ N. For example, the scan input terminal IN connected to the fifth-level shift register GOA(5) is electrically connected to the first output terminal OUT1(1) connected to the first-level shift register, the scan input terminal IN connected to the sixth-level shift register GOA(6) is electrically connected to the second output terminal OUT1(2) connected to the second-level shift register, and so on.

[0176] In an exemplary embodiment, Figure 21 is a schematic diagram of the cascading of multiple shift registers. As shown in Figure 21, when at least one level of shift register is electrically connected to the first cascaded output terminal OUT12, the first drive output terminal OUT11, the second cascaded output terminal OUT22, and the second drive output terminal OUT21, the first drive output terminal OUT11 connected to the nth level shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal OUT12 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register. The second drive output terminal OUT21 connected to the nth level shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal OUT22 connected to the nth level shift register is electrically connected to at least one signal terminal among the first scan input terminal IN1, the second scan input terminal IN2, the first scan reset terminal RST1, and the second scan reset terminal RST2 in the at least one level shift register.

[0177] As shown in Figure 21, the scan input terminals connected to the first-stage shift register and the second-stage shift register are electrically connected to the first initial signal line, and the scan input terminals connected to the third-stage shift register and the fourth-stage shift register are electrically connected to the second initial signal line.

[0178] As shown in Figure 21, the scan reset terminal connected to the M1-th stage shift register is electrically connected to the second cascaded output terminal OUT22 connected to the M1+4-th stage shift register, where 1≤M1≤N-4. For example, the scan reset terminal RST connected to the first-stage shift register GOA(1) is electrically connected to the second cascaded output terminal OUT22(5) connected to the fifth-stage shift register, the scan reset terminal RST connected to the second-stage shift register GOA(2) is electrically connected to the second cascaded output terminal OUT22(6) connected to the sixth-stage shift register, and so on.

[0179] As shown in Figure 21, the scan input terminal connected to the M2-level shift register is electrically connected to the first cascaded output terminal OUT12 connected to the M2-4-level shift registers, where 5 ≤ M2 ≤ N. For example, the scan input terminal IN connected to the fifth-level shift register GOA(5) is electrically connected to the first cascaded output terminal OUT12(1) connected to the first-level shift register, the scan input terminal IN connected to the sixth-level shift register GOA(6) is electrically connected to the first cascaded output terminal OUT12(2) connected to the second-level shift register, and so on.

[0180] Figure 22 is a timing diagram of the shift register shown in Figure 13 in the first scan state. The operation process of the shift register in the first scan state provided in this embodiment includes the following steps:

[0181] In the first stage S1, the input stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 to the fourth clock signal terminal CK4 are low, the signal at the scan input terminal IN is high, and the signal at the scan reset terminal RST is low. The first transistor T1 and the ninth transistor T9 are turned on, while the second transistor T2 and the tenth transistor T10 are turned off.

[0182] The first transistor T1 is turned on, and the high-level signal of the first control signal terminal CN is written to the total pull-up node PUCN. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turned-on fourth transistor T4. The third transistor T3 is turned on, and the low-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turned-on sixth transistor T16. The fifth transistor T5 is turned on, and the low-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. The ninth transistor T9 is turned on, and the low-level signal of the first clock signal terminal CK1 is written to the third node N3. The eleventh transistor T11 is turned off, and the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0183] In the second stage S2, the output stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are low, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, and the signals at the scan input terminal IN and the scan reset terminal RST are low. The ninth transistor T9 is turned on, while the first transistor T1, the second transistor T2, and the tenth transistor T10 are turned off.

[0184] Under the bootstrap effect of the first capacitor C1 and the third capacitor C3, the total pull-up node PUCN maintains the high-level signal of the previous stage. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the conduction of the fourth transistor T4. The third transistor T3 remains on, and the high-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the conduction of the sixth transistor T6. The fifth transistor T5 is on, and the high-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. The ninth transistor T9 is on, and the low-level signal of the first clock signal terminal CK1 is written to the third node N3. The eleventh transistor T11 is off, and the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0185] In the third stage (S3), the noise reduction stage, the signal at the first control signal terminal CN is high, the signal at the second control signal terminal CNB is low, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high for a portion of the time, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, the signal at the scan input terminal IN is low, and the signal at the scan reset terminal RST is low for a portion of the time. The ninth transistor T9 is turned on, while the first transistor T1, the second transistor T2, and the tenth transistor T10 are turned off.

[0186] When the ninth transistor T9 is turned on, the high-level signal of the first clock signal terminal CK1 is written to the third node N3. When the eleventh transistor T11 is turned on, the high-level signal of the first power supply terminal VGH is written to the pull-down node PD. When the thirteenth transistor T13 is turned on, the low-level signal of the second power supply terminal VGL is written to the total pull-up node PUCN. When the third transistor T3 and the fifth transistor T5 are turned off, the fifteenth transistor T15 is turned on, and the low-level signal of the second power supply terminal VGL is written to the first output terminal OUT1. When the sixteenth transistor T16 is turned on, the low-level signal of the second power supply terminal VGL is written to the second output terminal OUT2.

[0187] Figure 23 is a timing diagram of the shift register provided in Figure 13 operating in the second scan state. The operation process of the shift register in the second scan state provided in this embodiment includes the following steps:

[0188] In the first stage S1, the input stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 to the fourth clock signal terminal CK4 are low, the signal at the scan reset terminal RST is high, and the signal at the scan input terminal IN is low. The second transistor T2 and the tenth transistor T10 are turned on, while the first transistor T1 and the ninth transistor T9 are turned off.

[0189] The second transistor T2 is turned on, and the high-level signal of the second control signal terminal CNB is written to the total pull-up node PUCN. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the turned-on fourth transistor T4. The third transistor T3 is turned on, and the low-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the turned-on sixth transistor T6. The fifth transistor T5 is turned on, and the low-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. The tenth transistor T10 is turned on, and the low-level signal of the second clock signal terminal CK2 is written to the third node N3. The eleventh transistor T11 is turned off, and the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0190] In the second stage S2, the output stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are low, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, and the signals at the scan input terminal IN and the scan reset terminal RST are low. The ninth transistor T9 is turned on, while the first transistor T1, the second transistor T2, and the tenth transistor T10 are turned off.

[0191] With the second transistor T2 off, and under the bootstrap effect of the first capacitor C1 and the third capacitor C3, the total pull-up node PUCN maintains the high-level signal of the previous stage. The high-level signal of the total pull-up node PUCN is written to the first pull-up node PU1 through the conducting fourth transistor T4. The third transistor T3 remains on, and the high-level signal of the third clock signal terminal CK3 is written to the first output terminal OUT1. The high-level signal of the total pull-up node PUCN is written to the second pull-up node PU2 through the conducting sixth transistor T6. The fifth transistor T5 is on, and the high-level signal of the fourth clock signal terminal CK4 is written to the second output terminal OUT2. The tenth transistor T10 is on, and the low-level signal of the second clock signal terminal CK2 is written to the third node N3. The eleventh transistor T11 is off, and the signal of the pull-down node PD will not be pulled high by the signal of the first power supply terminal VGH.

[0192] In the third stage (S3), the noise reduction stage, the signal at the first control signal terminal CN is low, the signal at the second control signal terminal CNB is high, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are high for a portion of the time, the signals at the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are low, the signal at the scan input terminal IN is high for a portion of the time, and the signal at the scan reset terminal RST is low. The first transistor T1, the second transistor T2, and the ninth transistor T9 are off, while the tenth transistor T10 is on.

[0193] The tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CK2 is written to the third node N3. The eleventh transistor T11 is turned on, and the high-level signal of the first power supply terminal VGH is written to the pull-down node PD. The thirteenth transistor T13 is turned on, and the low-level signal of the second power supply terminal VGL is written to the total pull-up node PUCN. The third transistor T3 and the fifth transistor T5 are turned off. The fifteenth transistor T15 is turned on, and the low-level signal of the second power supply terminal VGL is written to the first output terminal OUT1. The sixteenth transistor T16 is turned on, and the low-level signal of the second power supply terminal VGL is written to the second output terminal OUT2.

[0194] The shift register shown in Figure 14 has the same operating timing as the shift register shown in Figure 13, and will not be described again here.

[0195] Figures 22 and 23 illustrate the operation of the shift register in the eye-gazing area using the example of the shift register's operation. The only difference between the shift register in the non-eye-gazing area and the shift register in the eye-gazing area is whether the first and second output terminals are output simultaneously during the output phase. The shift register in the eye-gazing area outputs the signals of the first and second output terminals simultaneously during the output phase, which will not be elaborated further in this disclosure.

[0196] In summary, the gate drive circuit in the display device provided in this disclosure can achieve both forward scanning and reverse scanning, thereby improving the reliability of the display device.

[0197] In exemplary embodiments, the display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or it can be a product or component with touch and display functionality. In exemplary embodiments, the display device can be a wearable display device, for example, one that can be worn on the human body in some way. For example, the display device can be a smartwatch, smart bracelet, etc. However, this embodiment is not limited to this.

[0198] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0199] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

A shift register, comprising: Input sub-circuit, output sub-circuit, and scan control sub-circuit; The input sub-circuit is electrically connected to the first node, the second node, the first control signal terminal, the second control signal terminal, and the main pull-up node, respectively. It is configured to provide the first control signal terminal to the main pull-up node under the control of the signal from the first node, and to provide the second control signal terminal to the main pull-up node under the control of the signal from the second node. The output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, at least one clock signal terminal, and at least one output terminal, respectively. It is configured to provide the clock signal terminal of at least one of the at least one output terminal to one of the at least one output terminal under the control of the signals from the main pull-up node and the first power supply terminal. The scan control sub-circuit is electrically connected to the first scan input terminal, the second scan input terminal, the first scan reset terminal, the second scan reset terminal, the first control signal terminal, the second control signal terminal, the first node, and the second node, respectively. It is configured to provide the first scan input terminal or the second scan input terminal to the first node, and the first scan reset terminal or the second scan reset terminal to the second node, respectively, under the control of the signals from the first control signal terminal and the second control signal terminal. The shift register according to claim 1 further includes: First node control sub-circuit and second node control sub-circuit; The first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, the first power supply terminal, the second power supply terminal, the main pull-up node, and the pull-down node, respectively, and is configured to provide the first power supply terminal or the second power supply terminal signal to the pull-down node under the control of the signals of the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, and the main pull-up node; The second node control sub-circuit is electrically connected to at least one output terminal, a second power supply terminal, a reset signal terminal, a pull-down node, and a total pull-up node, respectively. It is configured to provide the second power supply terminal signal to the total pull-up node and at least one output terminal under the control of the pull-down node signal, and to provide the second power supply terminal signal to the total pull-up node under the control of the reset signal terminal signal. According to claim 2, the shift register, wherein, The input sub-circuit includes: a first input sub-circuit and a second input sub-circuit; the first input sub-circuit is electrically connected to a first node, a first control signal terminal, and a total pull-up node, and is configured to provide a signal from the first control signal terminal to the total pull-up node under the control of the signal from the first node; the second input sub-circuit is electrically connected to a second node, a second control signal terminal, and the total pull-up node, and is configured to provide a signal from the second control signal terminal to the total pull-up node under the control of the signal from the second node. According to claim 3, the shift register, wherein, The first input sub-circuit includes a first transistor, and the second input sub-circuit includes a second transistor. The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the first control signal terminal, and the second electrode of the first transistor is electrically connected to the total pull-up node. The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the second control signal terminal, and the second electrode of the second transistor is electrically connected to the total pull-up node. According to claim 2, the shift register, wherein, At least one clock signal terminal includes a third clock signal terminal and a fourth clock signal terminal; at least one output terminal includes a first output terminal and a second output terminal; the output sub-circuit includes a first output sub-circuit and a second output sub-circuit; the first output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the third clock signal terminal, and the first output terminal, respectively, and is configured to provide the signal of the third clock signal terminal to the first output terminal under the control of the signals of the main pull-up node and the first power supply terminal; the second output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the fourth clock signal terminal, and the second output terminal, respectively, and is configured to provide the signal of the fourth clock signal terminal to the second output terminal under the control of the signals of the main pull-up node and the first power supply terminal. The shift register according to claim 5, wherein, The first output sub-circuit includes a third transistor, a fourth transistor, and a first capacitor; the second output sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor. The control electrode of the third transistor is electrically connected to the first pull-up node, the first electrode of the third transistor is electrically connected to the third clock signal terminal, and the second electrode of the third transistor is electrically connected to the first output terminal. The control electrode of the fourth transistor is electrically connected to the first power supply terminal, the first electrode of the fourth transistor is electrically connected to the general pull-up node, and the second electrode of the fourth transistor is electrically connected to the first pull-up node. The control electrode of the fifth transistor is electrically connected to the second pull-up node, the first electrode of the fifth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the second output terminal. The control electrode of the sixth transistor is electrically connected to the first power supply terminal, the first electrode of the sixth transistor is electrically connected to the general pull-up node, and the second electrode of the sixth transistor is electrically connected to the second pull-up node. The first terminal of the first capacitor is electrically connected to the first pull-up node, and the second terminal of the first capacitor is electrically connected to the first output terminal. The first terminal of the second capacitor is electrically connected to the second pull-up node, and the second terminal of the second capacitor is electrically connected to the second output terminal. According to claim 2, the shift register, wherein, At least one clock signal terminal includes a third clock signal terminal and a fourth clock signal terminal; at least one output terminal includes a first drive output terminal, a first cascaded output terminal, a second drive output terminal, and a second cascaded output terminal; the first output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the third clock signal terminal, the first drive output terminal, and the first cascaded output terminal, respectively, and is configured to provide the signal of the third clock signal terminal to the first drive output terminal and the first cascaded output terminal under the control of the signals of the main pull-up node and the first power supply terminal, respectively; the second output sub-circuit is electrically connected to the main pull-up node, the first power supply terminal, the fourth clock signal terminal, the second drive output terminal, and the second cascaded output terminal, respectively, and is configured to provide the signal of the fourth clock signal terminal to the second drive output terminal and the second cascaded output terminal under the control of the signals of the main pull-up node and the first power supply terminal, respectively. The shift register according to claim 7, wherein, The first output sub-circuit includes: a third transistor, a fourth transistor, a seventh transistor, and a first capacitor; the second output sub-circuit includes: a fifth transistor, a sixth transistor, an eighth transistor, and a second capacitor; the control electrode of the third transistor is electrically connected to the first pull-up node, the first electrode of the third transistor is electrically connected to the third clock signal terminal, and the second electrode of the third transistor is electrically connected to the first drive output terminal; the control electrode of the fourth transistor is electrically connected to the first power supply terminal, the first electrode of the fourth transistor is electrically connected to the main pull-up node, and the second electrode of the fourth transistor is electrically connected to the first pull-up node; the control electrode of the fifth transistor is electrically connected to the second pull-up node, the first electrode of the fifth transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the second drive output terminal; the sixth transistor... The control electrode of the sixth transistor is electrically connected to the first power supply terminal; the first electrode of the sixth transistor is electrically connected to the main pull-up node; the second electrode of the sixth transistor is electrically connected to the second pull-up node; the control electrode of the seventh transistor is electrically connected to the first pull-up node; the first electrode of the seventh transistor is electrically connected to the third clock signal terminal; the second electrode of the seventh transistor is electrically connected to the first cascaded output terminal; the control electrode of the eighth transistor is electrically connected to the second pull-up node; the first electrode of the eighth transistor is electrically connected to the fourth clock signal terminal; the second electrode of the eighth transistor is electrically connected to the second cascaded output terminal; the first terminal of the first capacitor is electrically connected to the first pull-up node; the second terminal of the first capacitor is electrically connected to the first drive output terminal; the first terminal of the second capacitor is electrically connected to the second pull-up node; the second terminal of the second capacitor is electrically connected to the second drive output terminal. The shift register according to any one of claims 5 to 8, wherein, The first node control sub-circuit includes: a pull-up sub-circuit and a pull-down sub-circuit; the pull-up sub-circuit is electrically connected to a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a first node, a second node, and a pull-down node, and is configured to provide a first power supply signal to the pull-down node under the control of the signals of the first clock signal terminal, the second clock signal terminal, the first node, and the second node; the pull-down sub-circuit is electrically connected to the pull-down node, the main pull-up node, and the second power supply terminal, and is configured to provide a second power supply signal to the pull-down node under the control of the signal of the main pull-up node. The shift register according to claim 9, wherein, The pull-up sub-circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor; the pull-down sub-circuit includes a twelfth transistor. The control electrode of the ninth transistor is electrically connected to a first control signal terminal, the first electrode of the ninth transistor is electrically connected to a first clock signal terminal, and the second electrode of the ninth transistor is electrically connected to a third node. The control electrode of the tenth transistor is electrically connected to a second control signal terminal, the first electrode of the tenth transistor is electrically connected to a second clock signal terminal, and the second electrode of the tenth transistor is electrically connected to a third node. The control electrode of the eleventh transistor is electrically connected to a third node, the first electrode of the eleventh transistor is electrically connected to a first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to a pull-down node. The control electrode of the twelfth transistor is electrically connected to the overall pull-up node, the first electrode of the twelfth transistor is electrically connected to a second power supply terminal, and the second electrode of the twelfth transistor is electrically connected to a pull-down node. The shift register according to claim 10, wherein, The second node control sub-circuit includes: a node pull-down sub-circuit and an output pull-down sub-circuit; the node pull-down sub-circuit is electrically connected to a reset signal terminal, a second power supply terminal, a pull-down node, and a total pull-up node, and is configured to provide a signal from the second power supply terminal to the total pull-up node under the control of a signal from the pull-down node or the reset signal terminal; the output pull-down sub-circuit is electrically connected to a pull-down node, at least one output terminal, and a second power supply terminal, and is configured to provide a signal from the second power supply terminal to at least one output terminal under the control of a signal from the pull-down node. The shift register according to claim 11, wherein, The node pull-down sub-circuit includes: a thirteenth transistor and a fourteenth transistor; the control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the overall pull-up node; the control electrode of the fourteenth transistor is electrically connected to the reset signal terminal, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the overall pull-up node; when at least one output terminal includes: a first output terminal and a second output terminal, the output pull-down sub-circuit includes: a fifteenth transistor, a sixteenth transistor, and a third capacitor; the control electrode of the fifteenth transistor is electrically connected to the pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first output terminal; the control electrode of the sixteenth transistor is electrically connected to the pull-down node, the first electrode of the sixteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the second output terminal; the first terminal of the third capacitor is electrically connected to the pull-down node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal; at least one output terminal When the circuit includes a first drive output terminal, a first cascaded output terminal, a second drive output terminal, and a second cascaded output terminal, the output pull-down sub-circuit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a third capacitor: the control electrode of the fifteenth transistor is electrically connected to the pull-down node, the first electrode of the fifteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifteenth transistor is electrically connected to the first drive output terminal; the control electrode of the sixteenth transistor is electrically connected to the pull-down node, the first electrode of the sixteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixteenth transistor is electrically connected to the second drive output terminal; the control electrode of the seventeenth transistor is electrically connected to the pull-down node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the first cascaded output terminal; the control electrode of the eighteenth transistor is electrically connected to the pull-down node, the first electrode of the eighteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the second cascaded output terminal; the first terminal of the third capacitor is electrically connected to the pull-down node, and the second terminal of the third capacitor is electrically connected to the second power supply terminal. The shift register according to claim 12, wherein, The scan control subcircuit includes: a first scan control subcircuit and a second scan control subcircuit; the first scan control subcircuit is electrically connected to a first control signal terminal, a second control signal terminal, a first scan input terminal, a second scan input terminal, and a first node, and is configured to provide a signal from the first scan input terminal to the first node under the control of the signal from the first control signal terminal, and to provide a signal from the second scan input terminal to the first node under the control of the signal from the second control signal terminal; the second scan control subcircuit is electrically connected to the first control signal terminal, the second control signal terminal, a first scan reset terminal, a second scan reset terminal, and a second node, and is configured to provide a signal from the first scan reset terminal to the second node under the control of the signal from the first control signal terminal, and to provide a signal from the second scan reset terminal to the second node under the control of the signal from the second control signal terminal. The shift register according to claim 13, wherein, The first scan control sub-circuit includes a nineteenth transistor and a twentieth transistor; the second scan control sub-circuit includes a twenty-first transistor and a twenty-second transistor. The control electrode of the nineteenth transistor is electrically connected to a first control signal terminal, its first electrode is electrically connected to a first scan input terminal, and its second electrode is electrically connected to a first node. The control electrode of the twentieth transistor is electrically connected to a second control signal terminal, its first electrode is electrically connected to a second scan input terminal, and its second electrode is electrically connected to a first node. The control electrode of the twenty-first transistor is electrically connected to a second control signal terminal, its first electrode is electrically connected to a second scan reset terminal, and its second electrode is electrically connected to a second node. The control electrode of the twenty-second transistor is electrically connected to the first control signal terminal, its first electrode is electrically connected to a first scan reset terminal, and its second electrode is electrically connected to a second node. A display device includes a display area and a non-display area. The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit. The gate driving circuit includes: Multiple cascaded shift registers as described in any one of claims 1 to 14; at least one shift register is electrically connected to at least one row of pixel driving circuitry and is configured to provide drive signals to the connected pixel driving circuitry. The display device according to claim 15, wherein, The nth-stage shift register is electrically connected to the (2n-1)th row pixel driving circuit and the 2nth row pixel driving circuit, respectively, where 1 ≤ n ≤ N, and N is the total number of shift register stages included in the gate driving circuit. The display device according to claim 16, wherein, The display area includes: an eye-focusing area and a non-eye-focusing area; when the display device displays in the eye-focusing area, at least two of the multiple clock signal lines have different clock signals; when the display content is displayed in the non-eye-focusing area, at least two of the multiple clock signal lines have the same clock signal; the display device displays in the eye-focusing area including: a first scanning state and a second scanning state, wherein the first scanning state refers to the start time of the driving signal provided by the gate driving circuit to the i-th row pixel driving circuit being earlier than the start time of the driving signal provided by the gate driving circuit to the (i+1)-th row pixel driving circuit, and the second scanning state refers to the start time of the driving signal provided by the gate driving circuit to the (i+1)-th row pixel driving circuit being earlier than the start time of the driving signal provided by the gate driving circuit to the (i+1)-th row pixel driving circuit. The start time of the driving signal provided by the driving circuit is earlier than the start time of the driving signal provided by the gate driving circuit to the i-th row pixel driving circuit; the first control signal terminals connected to at least one level shift register are connected to the same signal line, and the second control signal terminals connected to at least one level shift register are connected to the same signal line; in the first scan state, the signal of the first control signal terminal connected to at least one level shift register is a valid level signal, and the signal of the second control signal terminal connected to at least one level shift register is an invalid level signal; in the second scan state, the signal of the first control signal terminal connected to at least one level shift register is an invalid level signal, and the signal of the second control signal terminal connected to at least one level shift register is a valid level signal. The display device according to claim 16, wherein, At least one shift register is electrically connected to the first to fourth clock signal terminals. The display device further includes: a first to twelfth clock signal line disposed in the non-display area; the signal of at least one clock signal line includes: multiple pulse signals, the start time of the j-th pulse of the k-th clock signal line is earlier than or equal to the start time of the j-th pulse of the (k+1)-th clock signal line, 1≤k≤K, 1≤l≤L, K is the total number of clock signal lines, and L is the number of pulse signals included in the signal of at least one clock signal line; the first clock signal terminal connected to the 6r-5th shift register is connected to the eighth clock signal line. The 6r-5 stage shift register is electrically connected to the 7th clock signal line; the 6r-5 stage shift register is electrically connected to the 1st clock signal line; the 6r-5 stage shift register is electrically connected to the 2nd clock signal line; the 6r-4 stage shift register is electrically connected to the 10th clock signal line; the 6r-4 stage shift register is electrically connected to the 9th clock signal line; the 6r-4 stage shift register is electrically connected to the 3rd clock signal line; the 6r-4 stage shift register... The fourth clock signal terminal of the register is electrically connected to the fourth clock signal line; the first clock signal terminal of the 6r-3 stage shift register is electrically connected to the twelfth clock signal line, the second clock signal terminal of the 6r-3 stage shift register is electrically connected to the eleventh clock signal line, the third clock signal terminal of the 6r-3 stage shift register is electrically connected to the fifth clock signal line, and the fourth clock signal terminal of the 6r-3 stage shift register is electrically connected to the sixth clock signal line; the first clock signal terminal of the 6r-2 stage shift register is electrically connected to the second clock signal line, and the second clock signal terminal of the 6r-2 stage shift register is electrically connected to the second clock signal line. The first clock signal terminal of the 6r-2 stage shift register is electrically connected to the first clock signal line; the third clock signal terminal of the 6r-2 stage shift register is electrically connected to the seventh clock signal line; the fourth clock signal terminal of the 6r-2 stage shift register is electrically connected to the eighth clock signal line; the first clock signal terminal of the 6r-1 stage shift register is electrically connected to the fourth clock signal line; the second clock signal terminal of the 6r-1 stage shift register is electrically connected to the third clock signal line; the third clock signal terminal of the 6r-1 stage shift register is electrically connected to the ninth clock signal line; and the fourth clock signal terminal of the 6r-1 stage shift register is electrically connected to the tenth clock signal line.The first clock signal terminal of the 6r-stage shift register is electrically connected to the sixth clock signal line; the second clock signal terminal is electrically connected to the fifth clock signal line; the third clock signal terminal is electrically connected to the eleventh clock signal line; and the fourth clock signal terminal is electrically connected to the twelfth clock signal line. 1 ≤ r ≤ N / 6, where N is the total number of shift register stages in the gate drive circuit. The display device according to claim 18, wherein, At least one level of shift register is electrically connected to a first output terminal and a second output terminal, respectively. The first output terminal connected to the nth level shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one level of shift register. The second output terminal connected to the nth level shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one level of shift register. The display device further includes: a first initial signal line and a second initial signal line disposed in the non-display area; the first level shift register is connected to the first... The scan input terminal is electrically connected to the first initial signal line; the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line; the first scan input terminal connected to the N1-stage shift register is electrically connected to the second output terminal connected to the N1-2-stage shift register, where 3 ≤ N1 ≤ N; the second scan input terminal connected to the N2-stage shift register is electrically connected to the first output terminal connected to the N2-3-stage shift register, where 4 ≤ N2 ≤ N; the first scan reset terminal connected to the N3-stage shift register is electrically connected to the second output terminal connected to the N3+3-stage shift register, where 1 ≤ N3 ≤ N-3; and the second scan reset terminal connected to the N4-stage shift register is electrically connected to the first output terminal connected to the N4+2-stage shift register, where 3 ≤ N4 ≤ N-2. The display device according to claim 18, wherein, At least one shift register is electrically connected to a first cascaded output terminal, a first drive output terminal, a second cascaded output terminal, and a second drive output terminal, respectively. The first drive output terminal connected to the nth shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal connected to the nth shift register is electrically connected to at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The second drive output terminal connected to the nth shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal connected to the nth shift register is electrically connected to at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The display device further includes: a device disposed in the non-display area. The first initial signal line and the second initial signal line; the first scan input terminal of the first-stage shift register is electrically connected to the first initial signal line, the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line, the first scan input terminal of the N1-stage shift register is electrically connected to the second cascaded output terminal of the N1-2-stage shift register, 3≤N1≤N; the second scan input terminal of the N2-stage shift register is electrically connected to the first cascaded output terminal of the N2-3-stage shift register, 4≤N2≤N; the first scan reset terminal of the N3-stage shift register is electrically connected to the second cascaded output terminal of the N3+3-stage shift register, 1≤N3≤N-3; the second scan reset terminal of the N4-stage shift register is electrically connected to the first cascaded output terminal of the N4+2-stage shift register, 3≤N4≤N-2. The display device according to claim 18, wherein, At least one shift register is electrically connected to a first output terminal and a second output terminal, respectively. The first output terminal of the nth shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The second output terminal of the nth shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The display device further includes: a first initial signal line and a second initial signal line located in the non-display area; the first scan input terminal connected to the first shift register... The scanning input terminal is electrically connected to the first initial signal line; the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line; the first scan input terminal connected to the N1-stage shift register is electrically connected to the second output terminal connected to the N1-2-stage shift register, where 3 ≤ N1 ≤ N; the second scan input terminal connected to the N2-stage shift register is electrically connected to the first output terminal connected to the N2-4-stage shift register, where 5 ≤ N2 ≤ N; the first scan reset terminal connected to the N3-stage shift register is electrically connected to the second output terminal connected to the N3+4-stage shift register, where 1 ≤ N3 ≤ N-4; and the second scan reset terminal connected to the N4-stage shift register is electrically connected to the first output terminal connected to the N4+2-stage shift register, where 3 ≤ N4 ≤ N-2. The display device according to claim 18, wherein, At least one shift register is electrically connected to a first cascaded output terminal, a first drive output terminal, a second cascaded output terminal, and a second drive output terminal, respectively. The first drive output terminal connected to the nth shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output terminal connected to the nth shift register is electrically connected to at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The second drive output terminal connected to the nth shift register is electrically connected to the 2nth row pixel drive circuit. The second cascaded output terminal connected to the nth shift register is electrically connected to at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The display device further includes: a device disposed in the non-display area. The first initial signal line and the second initial signal line; the first scan input terminal of the first-stage shift register is electrically connected to the first initial signal line, the first scan input terminal of the second-stage shift register is electrically connected to the second initial signal line, the first scan input terminal of the N1-stage shift register is electrically connected to the second cascaded output terminal of the N1-2-stage shift register, 3≤N1≤N; the second scan input terminal of the N2-stage shift register is electrically connected to the first cascaded output terminal of the N2-4-stage shift register, 5≤N2≤N; the first scan reset terminal of the N3-stage shift register is electrically connected to the second cascaded output terminal of the N3+4-stage shift register, 1≤N3≤N-4; the second scan reset terminal of the N4-stage shift register is electrically connected to the first cascaded output terminal of the N4+2-stage shift register, 3≤N4≤N-2. A display device includes a display area and a non-display area. The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a gate driving circuit. The gate driving circuit includes: Multiple cascaded shift registers, each comprising an input sub-circuit, an output sub-circuit, and a first node control sub-circuit; the input sub-circuit is electrically connected to a scan input terminal, a scan reset terminal, a second node, a first control signal terminal, a second control signal terminal, and a total pull-up node, and is configured to provide a signal from the first control signal terminal to the total pull-up node under the control of the signal from the scan input terminal, and to provide a signal from the second control signal terminal to the total pull-up node under the control of the signal from the scan reset terminal; the output sub-circuit is electrically connected to the total pull-up node, a first power supply terminal, a third clock signal terminal, a fourth clock signal terminal, and at least one output terminal. The circuit is configured to provide a signal from one of at least one clock signal terminals to one of at least one of at least one output terminals under the control of the signals from the main pull-up node and the first power supply terminal; the first node control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, the main pull-up node, the first power supply terminal, the second power supply terminal, and the pull-down node, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the pull-down node under the control of the signals from the first clock signal terminal, the second clock signal terminal, the first control signal terminal, the second control signal terminal, and the main pull-up node. The display device according to claim 23, wherein, At least one shift register is electrically connected to the first to fourth clock signal terminals. The display device includes: a first to sixteenth clock signal lines disposed in the non-display area; the signal of at least one clock signal line includes: multiple pulse signals, the start time of the j-th pulse of the k-th clock signal line is earlier than or equal to the start time of the j-th pulse of the (k+1)-th clock signal line, 1≤k≤K, 1≤l≤L, where K is the total number of clock signal lines, and L is the number of pulse signals included in the signal of at least one clock signal line; the first clock signal terminal connected to the 8s-7th shift register is connected to the eighth clock signal line. Electrical connections: The second clock signal terminal of the 8s-7 stage shift register is electrically connected to the seventh clock signal line; the third clock signal terminal of the 8s-7 stage shift register is electrically connected to the first clock signal line; the fourth clock signal terminal of the 8s-7 stage shift register is electrically connected to the second clock signal line; the first clock signal terminal of the 8s-6 stage shift register is electrically connected to the tenth clock signal line; the second clock signal terminal of the 8s-6 stage shift register is electrically connected to the ninth clock signal line; the third clock signal terminal of the 8s-6 stage shift register is electrically connected to the third clock signal line; the 8s-6 stage shift register... The fourth clock signal terminal of the shift register is electrically connected to the fourth clock signal line; the first clock signal terminal of the 8s-5 stage shift register is electrically connected to the twelfth clock signal line; the second clock signal terminal of the 8s-5 stage shift register is electrically connected to the eleventh clock signal line; the third clock signal terminal of the 8s-5 stage shift register is electrically connected to the fifth clock signal line; the fourth clock signal terminal of the 8s-5 stage shift register is electrically connected to the sixth clock signal line; the first clock signal terminal of the 8s-4 stage shift register is electrically connected to the fourteenth clock signal line; the second clock signal terminal of the 8s-4 stage shift register is electrically connected to... The thirteenth clock signal line is electrically connected; the third clock signal terminal of the 8s-4 stage shift register is electrically connected to the seventh clock signal line; the fourth clock signal terminal of the 8s-4 stage shift register is electrically connected to the eighth clock signal line; the first clock signal terminal of the 8s-3 stage shift register is electrically connected to the sixteenth clock signal line; the second clock signal terminal of the 8s-3 stage shift register is electrically connected to the fifteenth clock signal line; the third clock signal terminal of the 8s-3 stage shift register is electrically connected to the ninth clock signal line; and the fourth clock signal terminal of the 8s-3 stage shift register is electrically connected to the tenth clock signal line.The first clock signal terminal of the 8s-2 stage shift register is electrically connected to the second clock signal line; the second clock signal terminal of the 8s-2 stage shift register is electrically connected to the first clock signal line; the third clock signal terminal of the 8s-2 stage shift register is electrically connected to the eleventh clock signal line; and the fourth clock signal terminal of the 8s-2 stage shift register is electrically connected to the twelfth clock signal line. The first clock signal terminal of the 8s-1 stage shift register is electrically connected to the fourth clock signal line; the second clock signal terminal of the 8s-1 stage shift register is electrically connected to the third clock signal line. The 8s-1 stage shift register... The third clock signal terminal of the shift register is electrically connected to the thirteenth clock signal line; the fourth clock signal terminal of the 8s-1 stage shift register is electrically connected to the fourteenth clock signal line; the first clock signal terminal of the 8s stage shift register is electrically connected to the sixth clock signal line; the second clock signal terminal of the 8s stage shift register is electrically connected to the fifth clock signal line; the third clock signal terminal of the 8s stage shift register is electrically connected to the fifteenth clock signal line; and the fourth clock signal terminal of the 8s stage shift register is electrically connected to the sixteenth clock signal line. 1 ≤ s ≤ N / 8, where N is the total number of shift register stages in the gate drive circuit. The display device according to claim 23, wherein, At least one shift register is electrically connected to a first output terminal and a second output terminal, respectively. The first output terminal of the nth shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The second output terminal of the nth shift register is electrically connected to the (2n)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. It also includes: a first initial signal line and a second initial signal line located in the non-display area; the scan input terminals connected to the first-stage shift register and the second-stage shift register are electrically connected to the first initial signal line; the scan input terminals connected to the third-stage shift register and the fourth-stage shift register are electrically connected to the second initial signal line; the scan reset terminal connected to the M1-stage shift register is electrically connected to the second output terminal connected to the M1+4-stage shift register, 1≤M1≤N-4; the scan input terminal connected to the M2-stage shift register is electrically connected to the second output terminal connected to the M2-4-stage shift register, 5≤M2≤N. The display device according to claim 23, wherein, At least one shift register is electrically connected to the first cascaded output, the first drive output, the second cascaded output, and the second drive output, respectively. The first drive output connected to the nth shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output connected to the nth shift register is electrically connected to at least one signal terminal among the first scan input, the second scan input, the first scan reset, and the second scan reset of the at least one shift register. The second drive output connected to the nth shift register is electrically connected to the (2n-1)th row pixel drive circuit. The second cascaded output connected to the nth shift register is electrically connected to the first scan input, the second scan input, the first scan reset, and the second scan reset of the at least one shift register. At least one of the scan reset terminal and the second scan reset terminal is electrically connected; the display device further includes: a first initial signal line and a second initial signal line disposed in the non-display area; the scan input terminal connected to the first-stage shift register and the second-stage shift register is electrically connected to the first initial signal line, the scan input terminal connected to the third-stage shift register and the fourth-stage shift register is electrically connected to the second initial signal line; the scan reset terminal connected to the M1-stage shift register is electrically connected to the second cascaded output terminal connected to the M1+4-stage shift register, 1≤M1≤N-4; the scan input terminal connected to the M2-stage shift register is electrically connected to the second cascaded output terminal connected to the M2-4-stage shift register, 5≤M2≤N. The display device according to claim 23, wherein, At least one shift register is electrically connected to a first output terminal and a second output terminal, respectively. The first output terminal of the nth shift register is electrically connected to the (2n-1)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The second output terminal of the nth shift register is electrically connected to the (2n)th row pixel driving circuit and at least one signal terminal among the first scan input terminal, second scan input terminal, first scan reset terminal, and second scan reset terminal of the at least one shift register. The display device... The device also includes: a first initial signal line and a second initial signal line located in the non-display area; the scan input terminals connected to the first-stage shift register and the second-stage shift register are electrically connected to the first initial signal line; the scan input terminals connected to the third-stage shift register and the fourth-stage shift register are electrically connected to the second initial signal line; the scan reset terminal connected to the M1-stage shift register is electrically connected to the second output terminal of the M1+4-stage shift register, 1≤M1≤N-4; the scan input terminal connected to the M2-stage shift register is electrically connected to the first output terminal connected to the M2-4-stage shift register, 5≤M2≤N. The display device according to claim 23, wherein, At least one shift register is electrically connected to the first cascaded output, the first drive output, the second cascaded output, and the second drive output, respectively. The first drive output connected to the nth-th shift register is electrically connected to the (2n-1)th row pixel drive circuit. The first cascaded output connected to the nth-th shift register is electrically connected to at least one signal terminal among the first scan input, the second scan input, the first scan reset, and the second scan reset of the at least one shift register. The second drive output connected to the nth-th shift register is electrically connected to the (2n-1)th row pixel drive circuit. The second cascaded output connected to the nth-th shift register is electrically connected to the first scan input, the second scan input, the first scan reset, and the second scan reset of the at least one shift register. At least one of the first and second scan reset terminals is electrically connected; the display device further includes: a first initial signal line and a second initial signal line disposed in the non-display area; the scan input terminals connected to the first and second stage shift registers are electrically connected to the first initial signal line, and the scan input terminals connected to the third and fourth stage shift registers are electrically connected to the second initial signal line; the scan reset terminal connected to the M1 stage shift register is electrically connected to the second cascaded output terminal of the M1+4 stage shift register, 1≤M1≤N-4; the scan input terminal connected to the M2 stage shift register is electrically connected to the first cascaded output terminal connected to the M2-4 stage shift register, 5≤M2≤N. A method for driving a shift register, configured to drive a shift register as described in any one of claims 1 to 14, the method comprising: Input sub-circuit, output sub-circuit, and scan control sub-circuit; The input sub-circuit, under the control of the signal of the first node, provides the signal of the first control signal terminal to the main pull-up node, and under the control of the signal of the second node, provides the signal of the second control signal terminal to the main pull-up node; Under the control of the signals from the main pull-up node and the first power supply terminal, the output sub-circuit provides a signal from one of the clock signal terminals to one of the at least one output terminal. Under the control of the signals at the first control signal terminal and the second control signal terminal, the scan control sub-circuit provides the first scan input terminal or the second scan input terminal signal to the first node, and provides the first scan reset terminal or the second scan reset terminal signal to the second node.

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