Inverted buck-boost hybrid converter topology

Abstract

Embodiments of a voltage converter are disclosed. In some embodiments, the voltage converter includes a voltage conversion circuit and a charging circuit. The voltage conversion circuit includes an output capacitor coupled to an output node at which an output voltage is generated, and an output inductor having a first inductor node and a second inductor node, the first inductor node being operably associated with the output node. The charging circuit is coupled to the second inductor node. The charging circuit includes a flying capacitor, a supply node configured to receive an input voltage, and a set of switches, wherein the set of switches is arranged in at least one switch configuration to charge the flying capacitor and at least one switch configuration to present a flying voltage across the flying capacitor as a negative voltage at the second inductor node.

Description

Inverting buck-boost hybrid converter topology

[0001] Related applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 638,061, filed on April 24, 2024, and provisional patent application serial number 63 / 594,385, filed on October 30, 2023, the disclosures of which are hereby incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to voltage converters and methods of operating said voltage converters. Background Technology

[0004] Voltage converters used in radio frequency (RF) circuits or light-emitting diode (LED) displays play a crucial role in ensuring optimal performance and efficiency. They convert direct current (DC) voltage to another DC voltage at a different level. RF circuits and LED displays require precise and stable voltage levels to function properly, as deviations can lead to signal distortion and performance degradation. By effectively managing voltage levels within RF circuits and LED displays, these converters help maintain signal integrity, minimize interference, and optimize overall system reliability.

[0005] One type of design used for voltage converters is the inverting buck-boost converter, which converts positive voltage to negative voltage. In some existing applications, inverting buck-boost converters use two transistors and one inductor. In some applications, the size of the inductor is constrained (e.g., mobile applications with a height <1 mm), and / or there are performance efficiency issues with the transistors. For example, in active-matrix organic light-emitting diode (AMOLED) display power applications for cellular phones, a typical implementation of an inverting buck-boost converter converts power at nominal conditions with an efficiency of 87%, and at maximum output power with an efficiency of less than 80%. For portable applications, this level of efficiency limits battery life and thermal performance. Summary of the Invention

[0006] In some embodiments, the voltage converter includes a voltage conversion circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operatively associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: a flying capacitor; a power node configured to receive an input voltage; and a set of switches, wherein the set of switches can be configured in at least one switching configuration for charging the flying capacitor and in at least one switching configuration for presenting the flying voltage across the flying capacitor as a negative voltage at the second inductor node. In some embodiments, the charging circuit is a first charging circuit, the flying capacitor is a first flying capacitor, and the set of switches is a first set of switches. The voltage converter further includes a second charging circuit coupled to the second inductor node, wherein the second charging circuit includes: a second flying capacitor; the power node configured to receive the input voltage; and a second set of switches, wherein in a second switching configuration, the second set of switches is configured to charge the second flying capacitor, and in a first switching configuration, the second set of switches is configured to present a second flying voltage across the second flying capacitor as a negative voltage at the second inductor node. In some embodiments, the first flying capacitor includes a first capacitor node and a second capacitor node; the first set of switches includes: a first switch coupled between the power node and the first capacitor node; and a second switch coupled between the first capacitor node and a ground node; the second flying capacitor includes a third capacitor node and a fourth capacitor node; and the second set of switches includes: a third switch coupled between the power node and the third capacitor node; and a fourth switch coupled between the third capacitor node and the ground node. In some embodiments, the first set of switches further includes a fifth switch coupled between the second capacitor node and the ground node; and the second set of switches further includes a sixth switch coupled between the fourth capacitor node and the ground node. In some embodiments, the first set of switches further includes a seventh switch coupled between the second capacitor node and the second inductor node; and the second set of switches further includes an eighth switch coupled between the fourth capacitor node and the second inductor node. In some embodiments, the voltage conversion circuit further includes a first switch connected between the first inductor node and the output node. In some embodiments, the output capacitor is connected between the output node and the ground node. In some embodiments, the voltage conversion circuit further includes a second switch coupled between the power supply node and the first inductor node.In some embodiments, the voltage conversion circuit further includes a second switch coupled between a ground node and the first inductor node. In some embodiments, the set of switches further includes a first switch coupled between the second inductor node and the ground node. In some embodiments, the set of switches further includes a first switch coupled between the second inductor node and the power supply node. In some embodiments, the flying capacitor includes a first capacitor node and a second capacitor node; and the set of switches includes: a first switch coupled between the power supply node and the first capacitor node; and a second switch coupled between the first capacitor node and the ground node. In some embodiments, the set of switches further includes a third switch coupled between the second capacitor node and the ground node. In some embodiments, the set of switches further includes a fourth switch coupled between the second capacitor node and the second inductor node. In some embodiments, the flying capacitor is a first flying capacitor having a first capacitor node and a second capacitor node; the set of switches includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; the charging circuit further includes a second flying capacitor having a third capacitor node and a fourth capacitor node; the first switch is coupled between the second inductor node and the first capacitor node; the second capacitor node is coupled to a ground node; the second switch is coupled between the second capacitor node and the third capacitor node; the third switch is coupled between the third capacitor node and the power supply node; the fourth switch is coupled between the first capacitor node and the fourth capacitor node; and the fourth capacitor node is coupled to ground. In some embodiments, the set of switches further includes a sixth switch, wherein the sixth switch is coupled between the second inductor node and the ground. In some embodiments, the voltage conversion circuit further includes the fifth switch connected between the first inductor node and the output node. In some embodiments, the output capacitor is connected between the output node and the ground node. In some embodiments, the voltage conversion circuit further includes a sixth switch coupled between the power supply node and the first inductor node. In some embodiments, the voltage conversion circuit is configured as an inverting voltage conversion circuit.

[0007] In some embodiments, a method of converting an input voltage into an output voltage at an output node includes: receiving the input voltage at a power node, wherein the output node is operatively associated with a first inductor node of an output inductor; configuring a set of switches in a switch configuration to charge a flying capacitor; and configuring the set of switches in the same switch configuration or in a different switch configuration to present the flying voltage across the flying capacitor as a negative voltage at a second inductor node of the output inductor.

[0008] In some embodiments, the user element includes a voltage converter, wherein the voltage converter includes a voltage conversion circuit comprising: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operatively associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit comprising: a flying capacitor; a power node configured to receive an input voltage; and a set of switches, wherein the set of switches is configured to at least one switch configuration for charging the flying capacitor and to at least one switch configuration for presenting the flying voltage across the flying capacitor as a negative voltage at the second inductor node.

[0009] In another respect, any of the foregoing aspects and / or the various individual aspects and features as described herein may be combined, individually or together, to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0010] Those skilled in the art will understand the scope of this disclosure and recognize its other aspects after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0012] Figure 1 illustrates one embodiment of a voltage converter according to some embodiments;

[0013] Figures 1A and 1B illustrate the voltage converter shown in Figure 1 according to some embodiments, with closed circuit paths exhibiting different switching configurations;

[0014] Figure 2 illustrates one embodiment of a voltage converter according to some embodiments;

[0015] Figures 2A to 2D illustrate voltage converters as shown in Figure 2 according to some embodiments, exhibiting closed circuit paths with different switch configurations;

[0016] Figure 2E illustrates states 1-4 of a buck circuit implemented during a switching cycle for the voltage converter shown in Figure 2, according to some embodiments.

[0017] Figure 2F illustrates boost circuit states 1-4 implemented during the switching cycle of the voltage converter shown in Figure 2, according to some embodiments.

[0018] Figure 2G illustrates states 1-3 of a buck-boost circuit implemented during the switching cycle of the voltage converter shown in Figure 2, according to some embodiments.

[0019] Figure 3 illustrates an embodiment of a voltage converter according to some embodiments;

[0020] Figure 3A is a voltage and current graph illustrating the operation of the voltage converter shown in Figure 3 according to some embodiments, wherein the error amplifier and buck comparator are activated in continuous conduction mode (CCM).

[0021] Figure 3B is a voltage and current graph illustrating the operation of the voltage converter shown in Figure 3 according to some embodiments, wherein the error amplifier and boost comparator are activated in discrete conduction mode (DCM).

[0022] Figure 3C is a voltage and current graph illustrating the operation of the voltage converter shown in Figure 3 according to some embodiments, wherein the error amplifier, boost comparator and buck comparator are activated in CCM (i.e., second operating mode);

[0023] Figure 4 illustrates another embodiment of the voltage converter according to some embodiments;

[0024] Figure 5 illustrates a voltage converter according to some embodiments, and another embodiment of five different switch configurations for the voltage converter; and

[0025] Figure 6 shows user elements according to some embodiments. Detailed Implementation

[0026] The embodiments described below represent the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the accompanying embodiments.

[0027] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly located on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on top of another element" or "extending directly over another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0029] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a”, “an”, and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0032] The embodiments of this disclosure are illustrated herein with reference to schematic diagrams. Therefore, the actual dimensions of layers and elements may differ, and variations in shape are expected due to (for example) manufacturing techniques and / or tolerances. For instance, areas shown or described as square or rectangular may have rounded or curved features, and areas shown as straight lines may have some irregularities. Therefore, the areas shown in the figures are schematic, and their shapes are not intended to represent the precise shapes of areas of the device, nor are they intended to limit the scope of this disclosure. Additionally, the size of structures or areas may be particularly exaggerated relative to other structures or areas for illustrative purposes, and is therefore provided to illustrate the general structure of the subject matter of this disclosure, and may or may not be drawn to scale. Common elements in the figures may be presented herein using common element designations and will not be described further thereafter.

[0033] The switch is described throughout this disclosure as either "open" or "closed". When the switch is "open", it is in a non-conducting state and / or a high-impedance state. For example, if the switch is a field-effect transistor (FET), the gate-to-source voltage applied to the gate of the FET is below the threshold voltage, so no current or very little current (i.e., leakage current) flows between the drain and source of the FET. When the switch is "open", it is also referred to as being in a "turn-off state". When the switch is "closed", it is in a conducting state and / or a low-impedance state. For example, if the switch is a FET, the gate-to-source voltage applied to the gate of the FET is above the threshold voltage, so current flows between the drain and source of the FET. When the switch is "closed", it is also referred to as being in a "turn-on state".

[0034] A buck-boost converter is a voltage converter in which the amplitude difference between the input voltage and the output voltage is less than 5% (where the percentage is calculated relative to the input voltage, i.e., the amplitude difference is less than 5% of the input voltage).

[0035] A buck converter is a voltage converter in which the amplitude of the input voltage is greater than the amplitude of the output voltage, wherein the voltage difference between the amplitude of the input voltage and the amplitude of the output voltage is greater than 5% (where the percentage is calculated relative to the input voltage, i.e., the amplitude difference is greater than 5% of the input voltage).

[0036] A boost converter is a voltage converter in which the amplitude of the output voltage is greater than the amplitude of the input voltage, wherein the voltage difference between the amplitude of the input voltage and the amplitude of the output voltage is greater than 5% (where the percentage is calculated relative to the input voltage, i.e., the amplitude difference is greater than 5% of the input voltage).

[0037] Embodiments of a voltage converter are disclosed. The voltage converter includes a voltage conversion circuit and at least one charging circuit. In some embodiments, the voltage conversion circuit is an inverting voltage conversion circuit. One or more charging circuits may be designed to operate as charge pumps. The voltage conversion circuit includes an output inductor and an output capacitor, wherein the output capacitor is coupled to an output node. An output voltage is generated at the output node, and in some embodiments, the output voltage is a voltage having a non-zero amplitude and a negative voltage polarity. The output inductor has a first inductor node operatively associated with the output node (e.g., in some embodiments, a switch is connected between the first inductor node and the output inductor) and a second inductor node connected to one or more of the charging circuits.

[0038] Each charging circuit includes a different set of switches. These switches can operate in at least one switch configuration for charging the flying capacitor and can also operate in at least one switch configuration to present the flying voltage across the flying capacitor as a negative voltage at the second inductor node. The presentation of a negative flying voltage at the second inductor node reduces the peak current value and reduces the root mean square (RMS) current through the output inductor. In some embodiments, the voltage converter improves efficiency across all load ranges, reduces inductor current ripple and output voltage ripple, reduces saturation current requirements (which results in physically smaller inductors, and in some cases, a reduced number of inductors), and results in better transient performance compared to other previously known designs. In some embodiments, the voltage converter has a power efficiency of 96%.

[0039] Figure 1 illustrates one embodiment of a voltage converter 100 according to some embodiments.

[0040] Voltage converter 100 includes charging circuit 102 and voltage conversion circuit 104. Charging circuit 102 includes switches S0, S1, S2, S3, S4, S7 and a flying capacitor CFLY. In some embodiments, switches S1, S2, S3, and S4 are FETs, microelectromechanical switches (MEMS), etc. In some embodiments, the flying capacitor CFLY is a metal-insulator-metal (MIM) capacitor, a metal-oxide-semiconductor (MOS) capacitor, a polycrystalline capacitor, a film capacitor, a varactor diode, a trench capacitor, a parallel plate capacitor, an interdigitated capacitor, a varactor diode, a high-k dielectric capacitor, a capacitor array, or a combination of one or more of the listed capacitors.

[0041] Charging circuit 102 includes power node 106, ground node 108, capacitor node 110, and capacitor node 112. Charging circuit 102 is connected to inductor node 114 (also referred to as output inductor node 114). In an alternative embodiment, switch S4 is not provided, and capacitor node 112 is identical to output inductor node 114. Regarding the charging circuit 102 shown in FIG. 1, power node 106 is configured to receive a power supply voltage VIN (also referred to as input voltage VIN), which is a reference voltage having a non-zero voltage amplitude and positive voltage polarity. Power supply voltage VIN is the input voltage and is typically a direct current (DC) voltage. Ground node 108 is configured to receive a ground voltage, which is a reference voltage defining a zero voltage amplitude and therefore having no polarity. Capacitor node 110 is connected to a capacitor terminal on a first side of the flying capacitor CFLY, while capacitor node 112 is connected to the opposite capacitor terminal on a second side of the flying capacitor CFLY. Output inductor node 114 is connected to the inductor terminal at the first side of output inductor 116 in voltage conversion circuit 104.

[0042] Switch S0 is optional. In an embodiment of the charging circuit 102 including switch S0, switch S0 is connected between output inductor node 114 and ground node 108. Switch S7 is optional. In an embodiment of the charging circuit 102 including switch S7, switch S7 is connected between output inductor node 114 and power supply node 106.

[0043] Voltage conversion circuit 104 includes switches S5 and S6, an output inductor 116, and an output capacitor 118. In some embodiments, switches S5 and S6 are FETs, MEMs, etc. In some embodiments, output capacitor 118 is a MIM capacitor, a MOS capacitor, a polycrystalline capacitor, a film capacitor, a varactor diode, a trench capacitor, a parallel plate capacitor, an interdigital capacitor, a varactor diode, a high-k dielectric capacitor, a capacitor array, a combination of one or more of the listed capacitors, etc. In some embodiments, output inductor 116 is a wire-wound inductor, a ferrite bead inductor, a transformer or part of a transformer, a multilayer chip inductor, a molded power inductor, an integrated inductor, a shielded inductor, etc. Although load 120 is shown as part of voltage conversion circuit 104, load 120 is generally not part of voltage conversion circuit 104 and is shown herein for ease of explanation. Voltage conversion circuit 104 includes an output node 122, where the output voltage VOUT is presented by voltage conversion circuit 104 at output node 122. Load 120 refers only to a circuit or device that consumes power from output node 122. For example, one application of voltage converter 100 is to provide power to a radio frequency (RF) circuit system in a user component. Another exemplary application of voltage converter 100 is for providing power to a light-emitting diode (LED) display. Note that these applications are considered exemplary and are not limiting. Therefore, in some embodiments, load 120 refers to an RF circuit or an LED circuit system.

[0044] The voltage conversion circuit 104 includes an output inductor node 114, an inductor node 124 (also referred to as output inductor node 124), a voltage node 126, an output node 122, and a ground node 108. An output inductor 116 is connected between output inductor node 114 and output inductor node 124. A switch S5 is connected between output inductor node 124 and voltage node 126. In some embodiments, voltage node 126 receives a ground voltage and is therefore the same as ground node 108. In other embodiments, voltage node 126 receives a supply voltage VIN and is therefore the same as supply node 106.

[0045] Switch S6 is connected between output inductor node 124 and output node 122. Output capacitor 118 is connected between output node 122 and ground node 108. In other words, output capacitor 118 is connected in parallel with load 120 and in parallel with respect to output node 122.

[0046] Voltage conversion circuit 104 is configured to convert input voltage VIN into output voltage VOUT. In this embodiment, output voltage VOUT has a non-zero amplitude and a negative voltage polarity. Therefore, this embodiment of voltage conversion circuit 104 is an inverting voltage conversion circuit because input voltage VIN has a positive voltage polarity and output voltage VOUT has a negative voltage polarity. To this end, output inductor 116 is magnetized by generating a current using input voltage VIN, which increases the strong magnetic field generated by output inductor 116. Output inductor 116 is then disconnected from input voltage VIN and demagnetized. During the demagnetization of output inductor 116, magnetic energy in output inductor 116 is released, thereby reducing the strength of the magnetic field generated by output inductor 116.

[0047] Output capacitor 118 acts as an energy collector, absorbing and supplying charge to reduce periodic amplitude voltage fluctuations (i.e., ripple current) in the output voltage VOUT. Output capacitor 118 and output inductor 116 are configured as a low-pass filter to reduce voltage ripple and provide a more stable output voltage VOUT. Despite the presence of ripple voltage in the voltage amplitude, the output voltage VOUT is treated as a DC voltage.

[0048] Charging circuit 102 is configured to charge flying capacitor CFLY with input voltage VIN. Once flying capacitor CFLY is charged, it is coupled to output inductor node 114. In this way, flying capacitor CFLY is configured to present voltage -VFLY at output inductor node 114. By presenting voltage -VFLY at output inductor node 114, the peak amplitude of the current through output inductor 116 is reduced. Furthermore, the RMS current through output inductor 116 is further reduced.

[0049] Switches S1-S6 (and optionally, switches S0 and S7) are closed and opened to magnetize, demagnetize, charge, and discharge the flying capacitor CFLY, respectively. As explained in further detail below, different operating techniques used to open and close switches S1-S6 (and optionally, switches S0 and S7) will produce different operations. For example, depending on how switches S1-S6 are configured, the voltage converter 100 operates as a buck converter, a boost converter, or a buck-boost converter.

[0050] Voltage converter 100 has control circuitry 130. Control circuitry 130 is configured to generate control output 132, which is configured to operate switches S0-S7. More specifically, control circuitry 130 is configured to generate control output 132, which opens and closes switches S0-S7 according to the switch configuration. As explained below, by switching between different switch configurations, voltage converter 100 operates as a specific type of voltage converter (i.e., a buck converter, a boost converter, or a buck-boost converter). In some embodiments, control circuitry 130 is a voltage-mode controller, current-mode controller, average current-mode controller, hysteresis controller, relay controller, predictive current controller, digital controller, analog controller, adaptive controller, voltage feedforward controller, proportional-integral (PI) controller, proportional-integral-derivative (PID) controller, etc.

[0051] Figures 1A and 1B illustrate the voltage converter 100 shown in Figure 1 according to some embodiments, having closed circuit paths exhibiting different switch configurations.

[0052] More specifically, Figures 1A and 1B illustrate the voltage converter 100 in five different switch configurations referred to as switch configurations 1-5. The lines corresponding to each of switch configurations 1-5 are closed circuit paths, thereby indicating which switches S1-S6 are closed. For a particular switch configuration in switch configurations 1-5, all other switches S1-S6 not shown along a specific line in Figures 1A and 1B are considered open. Table I below indicates the specific switch state of each of switches S1-S6 in each configuration.

[0053] The integer X is an integer corresponding to a specific switch configuration of switches S1-S6. Therefore, the integer X has a value of 1-5 to indicate a specific switch configuration.

[0054]

[0055] Regarding the voltage converter 100 in Figures 1A and 1B, complete the following sentences according to each of the switch configurations 1-5 in Table I.

[0056] In switch configuration X, control circuit 130 is configured to generate control output 132, such that:

[0057] ● Switch S1 is (from row X, column S1 switch state in table I);

[0058] ● Switch S2 is (from row X, column S2 switch state in table I);

[0059] ● Switch S3 is (from row X, column S3 switch state in table I);

[0060] ● Switch S4 is (from row X, column S4 switch state in table I);

[0061] ● Switch S5 is (from row X, column S5 switch state in Table I); and

[0062] ● Switch S6 is (from row X, column S6 switch state of table I).

[0063] In Figures 1A and 1B, voltage node 126 is configured to receive input voltage VIN and is therefore equivalent to power node 106.

[0064] In switch configuration 1, the flying capacitor CFLY is charged by the input voltage VIN from power node 106, and output node 122 is connected to ground through output inductor 116. If |VFLY|>|VOUT|, ​​output inductor 116 is demagnetized, the flying capacitor CFLY is recharged, output capacitor 118 is recharged, and energy is transferred to output node 122. However, if |VFLY|<|VOUT|, ​​output inductor 116 is magnetized, the flying capacitor CFLY is recharged, output capacitor 118 is recharged, and energy is transferred to output node 122. In the alternative switch configuration, switch S0 is closed and switch S4 is open.

[0065] In switch configuration 2, the flying capacitor CFLY is recharged by the input voltage VIN. In one embodiment, if voltage node 126 is grounded, the output inductor 116 can also be connected to ground via switches S5 and S2 (or, in an alternative embodiment, via a closed switch S0) to generate a voltage close to 0 V across the output inductor 116. In an alternative embodiment, if voltage node 126 is set to the input voltage VIN, the output inductor 116 is presented on both sides of the input voltage VIN via switches S5 and S7.

[0066] In switch configuration 3, it is assumed that voltage node 126 is configured to receive input voltage VIN. In this case, the flying capacitor CFLY is recharged, output inductor 116 is magnetized, and switch S2 grounds inductor node 114. Unlike in switch configuration 2, in switch configuration 3, switches S0 and S7 are not closed.

[0067] In switch configuration 4, the flying capacitor CFLY discharges. If |VFLY|>|VOUT|, ​​the output inductor 116 is magnetized. If |VFLY|<|VOUT|, ​​the output inductor 116 is demagnetized. Furthermore, energy is transferred to output node 122.

[0068] In switch configuration 5, the flying capacitor CFLY discharges. If voltage node 126 is configured to receive input voltage VIN, output inductor 116 is magnetized. If voltage node 126 is configured to receive ground voltage, output inductor 116 is demagnetized.

[0069] Figure 2 illustrates one embodiment of a voltage converter 200 according to some embodiments.

[0070] The voltage converter 200 includes a charging circuit 102(1), a charging circuit 102(2), and a voltage conversion circuit 104. The voltage conversion circuit 104 has been described above with respect to FIG1. ​​In this embodiment, voltage node 126 is configured to receive the input voltage VIN.

[0071] The charging circuit 102(1) is the same as the charging circuit 102 described above with respect to FIG1. ​​In this embodiment, the elements of the charging circuit 102(1) have the same elements as those described in FIG1, and the element numbers in the charging circuit 102(1) are the same as those in the charging circuit 102, except that the corresponding element numbers include the symbol (1) to indicate that the charging circuit 102(1) is the first instance of the charging circuit, just like the charging circuit 102 in FIG1. ​​The charging circuit 102(1) shown in FIG2 includes switch S7, but does not include an instance of switch S0 described above.

[0072] Charging circuit 102(2) is the same as the charging circuit 102 described above with respect to FIG. 1. In this embodiment, the elements of charging circuit 102(2) have the same elements as those described in FIG. 1, and the element numbers in charging circuit 102(2) are the same as those in charging circuit 102, except that the corresponding element numbers include the symbol (2) to indicate that charging circuit 102(2) is a second instance of the charging circuit, just like charging circuit 102 in FIG. 1. The charging circuit 102(2) shown in FIG. 2 includes switch S0, but does not include an instance of switch S7 described above.

[0073] Charging circuit 102(1) and charging circuit 102(2) are connected to inductor node 114 and are parallel to each other.

[0074] Figures 2A to 2D illustrate the voltage converter 200 shown in Figure 2 according to some embodiments, having closed circuit paths exhibiting different switch configurations.

[0075] More specifically, Figures 2A to 2D show the voltage converter 200 in five different switch configurations referred to as switch configurations 1-15. The lines corresponding to each of switch configurations 1-15 are closed circuit paths, thereby indicating which switches S1-S6 are closed. For a particular switch configuration in switch configurations 1-15, all other switches S1-S6 not shown along the specific lines in Figures 2A to 2D are considered open. Table II below indicates the specific switch state of each of switches S1(1)-S4(1), S5, and S6 in each configuration.

[0076] The integer Y is an integer corresponding to a specific switch configuration, where Y has a value of 1-15 to indicate a specific switch configuration among switch configurations 1-15. Table II indicates whether a specific switch among switches S1(1)-S4(1), S5, S6 is open or closed in charging circuit 102(1) in switch configurations 1-15. Table III indicates whether a specific switch among switches S1(2)-S4(2), S5, S6 is open or closed in charging circuit 102(2) in switch configurations 1-15.

[0077]

[0078] Regarding the voltage converter 200 in Figures 2A to 2D, complete the following sentences according to each of the switch configurations 1-15 in Table II.

[0079] In switch configuration Y, control circuit 130 is configured to generate control output 132, such that:

[0080] ● Switch S1(1) is (from row Y, column S1(1) switch state of Table II);

[0081] ● Switch S2(1) is (from row Y, column S2(1) switch state from Table II);

[0082] ● Switch S3(1) is (from row Y, column S3(1) switch state of Table II);

[0083] ● Switch S4(1) is (from row Y, column S4(1) switch state of Table II);

[0084] ● Switch S5 is (from row Y, column S5 switch state in Table II); and

[0085] ● Switch S6 is (from row Y, column S6 switch state in Table II).

[0086]

[0087] In switch configuration Y, control circuit 130 is configured to generate control output 132, such that:

[0088] ● Switch S1(2) is (from row Y, column S1(2) switch state in Table III);

[0089] ● Switch S2(2) is (the switch state of row Y and column S2(2) from Table III);

[0090] ● Switch S3(2) is (from row Y, column S3(2) switch state in Table III);

[0091] ● Switch S4(2) is (from row Y, column S4(2) switch state of Table III);

[0092] ● Switch S5 is (from row Y, column S5 switch state in Table III); and

[0093] ● Switch S6 is (from the switch state of row Y and column S6 in Table III).

[0094] A reversible switch configuration is a configuration in which the corresponding switch in charging circuit 102(1) and the corresponding switch in charging circuit 102(2) are in the same switching state, and vice versa. In other words, in a reversible switch configuration, switch state S1(1) = switch state S1(2), switch state S2(1) = switch state S2(2), switch state S3(1) = switch state S3(2), switch state S4(1) = switch state S4(2), switch state S5 = switch state S5, and switch state S6 = switch state S6. As shown in Tables II and III, switch configuration 1 and switch configuration 8 are reversible switch configurations. Switch configuration 2 and switch configuration 9 are reversible switch configurations. Switch configuration 3 and switch configuration 10 are reversible switch configurations. Switch configuration 4 and switch configuration 11 are reversible switch configurations. Switch configuration 5 and switch configuration 12 are reversible switch configurations. Switch configuration 6 and switch configuration 13 are reversible switch configurations. Switch configuration 7 and switch configuration 14 are mutually inverted switch configurations.

[0095] Voltage converter 200 includes 10 main switches S1(1), S1(2), S2(1), S2(2), S3(1), S3(2), S4(1), S4(2), S5, S6, an output inductor 116, and two flying capacitors CFLY(1) and CFLY(2). The topology of voltage conversion circuit 104 is an inverting voltage conversion circuit. This means that the input voltage VIN has a non-zero amplitude and a positive voltage polarity, and the output voltage VOUT has a non-zero and a negative voltage polarity. As explained above, voltage converter 200 shown in Figure 2 can be used as a buck converter, a boost converter, or a buck-boost converter. However, in some embodiments, the flying capacitor CFLY may deplete its charge, thus reducing some of the advantages of the topology. In other words, the flying capacitor CFLY must be charged at some point during the duty cycle, or in some cycles. As explained below, voltage converter 200 shown in Figure 2 can be used as a buck converter, a boost converter, or a buck-boost converter. The topology has two charging circuits 102(1), 102(2). This allows one of the two charging circuits 102(1), 102(2) to operate in order to provide charge for voltage conversion while the other of the two charging circuits 102(2), 102(1) is charging. In an alternative embodiment, the voltage converter 200 has more than two charging circuits, such as charging circuits 102(1), 102(2).

[0096] The voltage converter 200 achieves higher efficiency, better transient performance, and in some cases, smaller area consumption and corresponding components for the same power output. Charging circuits 102(1), 102(2) allow inductor node 114 to be biased to the input voltage -VIN. In some instances, the voltage converter 200 operates as a buck converter, where inductor node 114 switches between the input voltage -VIN and ground to generate a filtered output voltage -VOUT. Different cycles can be switched back and forth between charging circuits 102(1), 102(2) in a ping-pong manner to allow longer recharge times for flying capacitors CFLY(1), CFLY(2). In this case, when operating in Discrete Conductive Mode (DCM), one of charging circuits 102(1), 102(2) can be deactivated and the other enabled. Providing both charging circuits 102(1), 102(2) reduces the RMS current through switches S1(1), S2(1), S1(2), S2(2). In addition, by using charging circuits 102(1) and 102(2), the average voltage level of voltages VFLY(1) and VFLY(2) is increased by flying capacitors CFLY(1) and CFLY(2), thereby reducing energy loss.

[0097] In this embodiment, voltage node 126 is configured to receive input voltage VIN. This allows inductor node 124 to be biased at the input voltage VIN level, while inductor node 114 of output inductor 116 is biased at a voltage level close to the input voltage -VIN or ground. Biasing inductor node 124 at the input voltage +VIN level allows the magnetization speed of output inductor 116 to be almost twice as fast, thereby reducing inductor current ripple, DC current, and saturation current requirements. Biasing inductor node 124 to ground via switch S5 reduces voltage stress through switch S5 (and optionally through switch S7). Multiple operating regions exist, implemented using different sequences of circuit states. Each of the circuit states corresponds to a different switch configuration from switch configurations 1-15 in Tables II and III, as explained below. In the buck region, when |VOUT| < |VIN|, the topology can operate in continuous conduction mode (CCM) or direct conduction mode (DCM). In the buck-boost region, when |VOUT|~|VIN|, the voltage converter 200 operates in pass mode or uses the buck-boost region sequence operation in CCM or DCM. In the boost region, when |VOUT|>|VIN|, the voltage converter 200 can operate in CCM or DCM.

[0098] As shown in Tables II and III, control circuit 130 can achieve energy transfer in different operating regions using at least 15 configurations. In switch configuration 1 and switch configuration 8, inductor current IL flows from output node 122 to ground node 108 through output inductor 116 and flying capacitor CFLY(1) (for switch configuration 1) or flying capacitor CFLY(2) (for switch configuration 8). If |VOUT| < |VCFLY(1)| (for switch configuration 1) or |VCFLY(2)| (for switch configuration 8), the energy of flying capacitor CFLY(1) (for switch configuration 1) or flying capacitor CFLY(2) (for switch configuration 8) decreases, while the energy stored in output inductor 116 increases. In this case, energy transfer to output node 122 occurs. Additionally, output inductor 116 is magnetized, flying capacitor CFLY(1) (for switch configuration 1) or flying capacitor CFLY(2) (for switch configuration 8) loses charge, and output capacitor 118 is recharged. If |VOUT| > |VCFLY(1)| (for switch configuration 1) or |VCFLY(2)| (for switch configuration 8), the energy stored by the flying capacitor CFLY(1) (for switch configuration 1) or flying capacitor CFLY(2) (for switch configuration 8) decreases, the energy of the output inductor 116 decreases, and there is energy transfer to the output node 122. Moreover, the output inductor 116 is demagnetized, the flying capacitor CFLY(1) (for switch configuration 1) or flying capacitor CFLY(2) (for switch configuration 8) loses charge, and the output capacitor 118 is recharged.

[0099] In switch configurations 2 and 9, the output inductor 116 is demagnetized, the flying capacitor CFLY(1) (for switch configuration 2) or the flying capacitor CFLY(2) (for switch configuration 9) is recharged, and the output capacitor 118 is recharged. In some cases, the flying capacitor CFLY(1) (for switch configuration 2) or the flying capacitor CFLY(2) (for switch configuration 9) is not recharged.

[0100] In switch configurations 3 and 10, switches S1, S2, S4, and S5 are enabled (where switches S1, S2, and S4 refer to switches S1(1), S2(1), and S4(1) for switch configuration 3, and where switches S1, S2, and S4 refer to switches S1(2), S2(2), and S4(2) for switch configuration 10). Switch S0 may also be enabled if available. If switch S0 is available and enabled, switch S4 may be disabled. In some cases, when the first terminal of switch S5 is connected to the input voltage VIN via voltage node 126, the flying capacitors CFLY(1) and CFLY(2) are recharged (gain energy) and the output inductor 116 is magnetized (gain energy). In other embodiments, voltage node 126 is connected to ground (see Figure 4). In this alternative embodiment, the first terminal of switch S5 is connected to the ground voltage GND. Therefore, the flying capacitors CFLY(1) and CFLY(2) are recharged (gain energy) and the output inductor 116 is slowly demagnetized (leakage energy). In some cases, switch S1 can be deactivated, and flying capacitors CFLY(1) and CFLY(2) are not recharged. In switch configurations 1-3, switches S1(2) and S2(2) are enabled, and flying capacitor CFLY(2) is recharged. In switch configurations 8-11, switches S1(1) and S2(1) are enabled, and flying capacitor CFLY(1) is recharged.

[0101] In switch configurations 4-7 and reversible switch configurations 11-14, output inductor 116 is demagnetized, flying capacitor CFLY(1) (in switch configuration 4-7) or flying capacitor CFLY(2) (in switch configuration 11-14) is recharged and output capacitor 118 is recharged.

[0102] In switch configurations 5 and 12, the flying capacitor CFLY(1) (in switch configurations 4-6) or the flying capacitor CFLY(2) (in switch configurations 11-13) discharges and thus loses energy, the output inductor 116 is magnetized (gains energy) at a rate approximately proportional to VIN+(|VCFLY(1)| (in switch configuration 5) or VIN+(|VCFLY(2)| (in switch configuration 12), and the voltage node 126 is supplied with energy by the input voltage VIN.

[0103] In switch configurations 6 and 13, flying capacitors CFLY(1) (in switch configuration 6) and CFLY(2) (in switch configuration 13) are recharged. In some embodiments, switch S0 is closed. Switch S4(1) (in switch configuration 6) or switch S4(2) (in switch configuration 13) maintains one side of output inductor 116 at a low impedance. In switch configuration 6, switches S4(1) and S2(1) connect inductor node 114 to ground, while switch S5 is open, and therefore inductor node 124 floats. In switch configuration 13, switches S4(2) and S2(2) connect inductor node 114 to ground, while switch S5 is open, and therefore inductor node 124 floats.

[0104] In switch configurations 7 and 14, flying capacitors CFLY(1) (in switch configuration 7) and CFLY(2) (in switch configuration 14) are recharged. In some embodiments, switch S0 is closed. Switch S5 (in switch configurations 6 and 14) maintains one side of output inductor 116 at a low impedance. In switch configurations 7 and 14, switches S4(1), S2(1), S1(2), and S2(2) are open, causing inductor node 114 to float, while switch S5 is closed, and thus inductor node 124 is connected to voltage node 126 to receive input voltage VIN.

[0105] In switch configuration 15, both flying capacitors CFLY(1) and CFLY(2) are recharged via power node 106 using the input voltage VIN. In switch configurations 1-7, charging circuit 102(1) supplies charge to output inductor 116, and flying capacitor CFLY(2) is recharged. Additionally, in switch configurations 8-14, charging circuit 102(2) supplies charge to output inductor 116, and flying capacitor CFLY(1) is recharged. Therefore, by using two charging circuits 102(1) and 102(2) with reversible switch configurations, the power stage efficiency of voltage converter 200 is increased because less current ripple exists at output capacitor 118. Switch configuration 15 recharges both flying capacitors CFLY(1) and CFLY(2). Switch configuration 15 can be used for DCM operation, where the inductor current IL is zero or near zero. In switch configuration 15, the inductor current IL of output inductor 116 can be recirculated by including and closing switch S7. Not all switch configurations 1-15 are necessary for proper operation. Some switch configurations 1-15 may or may not be used depending on whether the voltage converter 200 is operating in a buck, boost, or buck-boost operation region. Switch configurations 1-15 do not need to follow a specific order, and some switch configurations 1-15 may not be used during switching cycles, depending on the operating mode.

[0106] Figure 2E illustrates states 1-4 of a buck circuit implemented during a switching cycle for the voltage converter 200 shown in Figure 2, according to some embodiments.

[0107] In states 1-4, the voltage converter 200 operates in the inverting buck region, where |VOUT| is lower than |VIN|. Charging circuits 102(1) and 102(2) operate in a ping-pong manner. While one of the charging circuits 102(1) and 102(2) is actively transferring energy between output node 122, power node 106, and inductor node 126, the other of the charging circuits 102(2) and 102(1) is recharging flying capacitors CFLY(1) and CFLY(2). This allows for at least a full capacitor recharge cycle. When the load impedance of load 120 is low, only one of the two charging circuits 102(1) and 102(2) can be used during each switching cycle, and one of the other charging circuits 102(2) can be used when the other charging circuit is idle during each switching cycle.

[0108] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck circuit state 1 during the first part of the switching cycle. In buck circuit state 1, voltage converter 200 is in switching configuration 1 from Table II and Table III. Therefore, charging circuit 102 (1) magnetizes output inductor 116 by presenting a flying voltage VFLY (1) across flying capacitor CFLY (1) at inductor node 114. At the start of buck circuit state 1, flying voltage VFLY (1) is presented at inductor node 114 to have negative polarity and a voltage amplitude at or near |VIN|. Charging circuit 102 (2) charges flying capacitor CFLY (2) with input voltage VIN at power supply node 106.

[0109] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck circuit state 2 during the second part of the switching cycle. In buck circuit state 2, voltage converter 200 is in switch configuration 2 from Table II and Table III. In some embodiments of buck circuit state 2, switch S0 is closed. In buck circuit state 2, charging circuit 102(1) demagnetizes output inductor 116 while transferring energy between output node 122 and power node 106. Charging circuit 102(2) charges flying capacitor CFLY(2) with input voltage VIN from power node 106.

[0110] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck circuit state 3 during the third part of the switching cycle. In buck circuit state 3, voltage converter 200 is in switching configuration 8 from Table II and Table III. Switching configuration 8 is an inverse switching configuration of switching configuration 1. Therefore, charging circuit 102 (2) magnetizes output inductor 116 by presenting a flying voltage VFLY (2) across flying capacitor CFLY (2) at inductor node 114. At the start of buck circuit state 3, flying voltage VFLY (2) is presented at inductor node 114 to have negative voltage polarity and a voltage amplitude at or near |VIN|. Charging circuit 102 (1) charges flying capacitor CFLY (1) with input voltage VIN at power supply node 106.

[0111] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck circuit state 4 during the fourth part of the switching cycle. In buck circuit state 4, voltage converter 200 is in switching configuration 9 from Table II and Table III. In some embodiments of buck circuit state 4, switch S0 is closed. In buck circuit state 4, charging circuit 102 (2) demagnetizes output inductor 116 while transferring energy between output node 122 and node 106 (4). Charging circuit 102 (1) charges flying capacitor CFLY (1) with input voltage VIN from node 106.

[0112] For the next switching cycle, control circuit 130 is then configured to generate control output 132 to return to buck circuit state 1, then to buck circuit state 2, then to buck circuit state 3, and then through buck circuit state 4. Control circuit 130 is configured to operate voltage converter 200 to cycle through buck circuit states 1-4, as long as voltage converter 200 is configured to operate in the buck region.

[0113] Figure 2F illustrates boost circuit states 1-4 implemented during the switching cycle of the voltage converter 200 shown in Figure 2, according to some embodiments.

[0114] In boost circuit states 1-4, voltage converter 200 operates in the inverting boost region, where |VOUT| is greater than |VIN|. Charging circuits 102(1) and 102(2) operate in a ping-pong manner. While one of the charging circuits 102(1) and 102(2) is actively transferring energy between output node 122 and nodes 106 and 126, the other charging circuits 102(2) and 102(1) are recharging the corresponding flying capacitors CFLY(1) and CFLY(2). When the load impedance is low, only one of the charging circuits 102(1) and 102(2) may be used.

[0115] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in boost circuit state 1 during the first part of the switching cycle. In boost circuit state 1, voltage converter 200 is in switching configuration 5 from Tables II and III. In boost circuit state 1, charging circuit 102(1) magnetizes output inductor 116 without transferring energy between output node 122 and power node 106. Alternatively, charging circuit 102(1) magnetizes output inductor 116 with charge from input voltage VIN from voltage node 126. Charging circuit 102(2) is configured to charge flying capacitor CFLY(2) with input voltage VIN from power node 106.

[0116] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in boost circuit state 2 during the second part of the switching cycle. In boost circuit state 2, voltage converter 200 is in switching configuration 1 from Table II and Table III. In boost circuit state 2, charging circuit 102(1) demagnetizes output inductor 116 while transferring energy between output node 122 and power node 106. Charging circuit 102(2) is configured to charge flying capacitor CFLY(2) with input voltage VIN from power node 106.

[0117] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in boost circuit state 3 during the third part of the switching cycle. In boost circuit state 3, voltage converter 200 is in switching configuration 12 from Table II and Table III. Switching configuration 12 and switching configuration 5 are inverse switching configurations. In boost circuit state 3, charging circuit 102(2) magnetizes output inductor 116 without transferring energy between output node 122 and power node 106. Alternatively, charging circuit 102(2) magnetizes output inductor 116 with charge from input voltage VIN from voltage node 126. Charging circuit 102(1) is configured to charge flying capacitor CFLY(1) with input voltage VIN from power node 106.

[0118] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in boost circuit state 4 during the fourth part of the switching cycle. In boost circuit state 4, voltage converter 200 is in switching configuration 8 from Table II and Table III. In boost circuit state 4, charging circuit 102(2) demagnetizes output inductor 116 while transferring energy between output node 122 and power node 106. Charging circuit 102(1) is configured to charge flying capacitor CFLY(1) with input voltage VIN from power node 106.

[0119] For the next switching cycle, control circuit 130 is then configured to generate control output 132 to return to boost circuit state 1, then to boost circuit state 2, then to boost circuit state 3, and then through boost circuit state 4. Control circuit 130 is configured to operate voltage converter 200 to cycle through boost circuit states 1-4, as long as voltage converter 200 is configured to operate in the boost region. Arrows indicate current flow. States do not need to be executed in any particular order within the switching cycle; however, the presented digital sequence provides efficient energy-saving operation. States with no current flow are possible and provide a method for DCM operation. States with recirculating current in output inductor 116 can also provide a method for DCM operation. Under light load conditions and low buck duty cycles (e.g., magnetization time relatively similar to or less than demagnetization time), a single charging circuit can be used (see Figure 1). To minimize switching losses, in some embodiments, switches S1(1)-S4(1) and S1(2)-S4(2) are switched at a frequency of fsw / 2 (where fsw refers to the switching frequency), and switch S6 is switched at a frequency of fsw. In some embodiments, switch S0 is an optional switch that can be used to further optimize efficiency.

[0120] Figure 2G illustrates states 1-3 of a buck-boost circuit implemented during a switching cycle for the voltage converter 200 shown in Figure 2, according to some embodiments.

[0121] Buck-boost circuit states 1-3 operate the voltage converter 200 in the inverting buck-boost region, where |VOUT| is approximately equal to |VIN|. Charging circuits 102(1) and 102(2) operate in a ping-pong manner. However, buck-boost circuit states 1-3 are shown only when charging circuit 102(1) is transferring energy to output node 122 and charging circuit 102(2) is charging flying capacitor CFLY(2). For clarity, buck-boost circuit states 4-6 are not shown in Figure 2G. However, buck-boost circuit states 1-3 and buck-boost circuit states 4-6 are inverse circuit states, as will be explained in further detail below. While one of the charging circuits 102(1) and 102(2) is actively transferring energy between output node 122 and power node 106, the other charging circuit 102(2) is recharging the corresponding one of the flying capacitors CFLY(1) and CFLY(2). When the load impedance is low, only one of the charging circuits 102(1) and 102(2) can be used (see Figure 2).

[0122] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 1 during the first portion of the switching cycle. In buck-boost circuit state 1, voltage converter 200 is in switching configuration 4 from Tables II and III. In some embodiments, switch S0 is closed in buck-boost circuit state 1. In buck-boost circuit state 1, charging circuit 102 (1) demagnetizes output inductor 116 while transferring energy from output node 122 to ground. Charging circuit 102 (2) is configured to charge flying capacitor CFLY (2) with input voltage VIN from power node 106.

[0123] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 2 during the second part of the switching cycle. In buck-boost circuit state 2, voltage converter 200 is in switching configuration 5 from Table II and Table III. In buck-boost circuit state 2, charging circuit 102(1) magnetizes output inductor 116 by transferring energy from voltage node 126 to output inductor 116. Charging circuit 102(2) is configured to charge flying capacitor CFLY(2) with input voltage VIN from power node 106.

[0124] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 3 during the third part of the switching cycle. In buck-boost circuit state 3, voltage converter 200 is in switching configuration 1 from Table II and Table III. In buck-boost circuit state 3, charging circuit 102 (1) demagnetizes output inductor 116 in response to |VOUT|>|VIN| and magnetizes output inductor 116 in response to |VOUT|<|VIN| by transferring energy between output capacitor 118 and flying capacitor CFLY (1). Charging circuit 102 (2) is configured to charge flying capacitor CFLY (2) with input voltage VIN from power node 106.

[0125] The buck-boost states 4-6 are not shown, but are only the reverse states of buck-boost states 1-3.

[0126] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 4 during the fourth portion of the switching cycle. In buck-boost circuit state 4, voltage converter 200 is in switching configuration 11 from Tables II and III. In some embodiments, switch S0 is closed in buck-boost circuit state 4. In buck-boost circuit state 4, charging circuit 102 (2) demagnetizes output inductor 116 while transferring energy from output node 122 to ground. Charging circuit 102 (1) is configured to charge flying capacitor CFLY (1) with input voltage VIN from power node 106.

[0127] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 5 during the fifth part of the switching cycle. In buck-boost circuit state 5, voltage converter 200 is in switching configuration 5 from Table II and Table III. In buck-boost circuit state 5, charging circuit 102(2) magnetizes output inductor 116 by transferring energy from voltage node 126 to output inductor 116. Charging circuit 102(1) is configured to charge flying capacitor CFLY(1) with input voltage VIN from power node 106.

[0128] Control circuit 130 is configured to generate control output 132 to provide voltage converter 200 in buck-boost circuit state 6 during the sixth part of the switching cycle. In buck-boost circuit state 6, voltage converter 200 is in switching configuration 8 from Table II and Table III. In buck-boost circuit state 6, charging circuit 102(2) demagnetizes output inductor 116 in response to |VOUT|>|VIN| and magnetizes output inductor 116 in response to |VOUT|<|VIN| by transferring energy between output capacitor 118 and flying capacitor CFLY(2). Charging circuit 102(1) is configured to charge flying capacitor CFLY(1) with input voltage VIN from power node 106.

[0129] Switch S0 is optional and can be used to further optimize efficiency. The states do not need to be executed in any particular order during the switching cycle. However, the proposed digital sequence provides an energy-efficient switching method. A state with no current flow is possible and provides a method for DCM operation. A state with recirculating current in output inductor 116 also provides a method for DCM operation. To minimize switching losses, switches S1(1)-S4(1) and S1(2)-S4(2) are switched at a frequency fsw / 2, and switches S6 and S7 are switched at a frequency fsw.

[0130] Figure 3 illustrates an embodiment of a voltage converter 300 according to some embodiments.

[0131] The voltage converter 300 includes the voltage conversion circuit 104, charging circuit 102(1), and charging circuit 102(2) described above with respect to FIG2. The voltage converter 300 includes a control circuit 302. The control circuit 302 is an embodiment of the control circuit 130 shown in FIG1 and FIG2. The control circuit 302 is configured to operate the voltage conversion circuit 104, charging circuit 102(1), and charging circuit 102(2) in the same manner as described above with respect to FIG2A to 2G.

[0132] Control circuit 302 includes an inverting voltage amplifier 304, resistors 306 and 308, a constant peak current pulse frequency modulation (PFM) controller 310, a feedback node 312, resistor 318, capacitor 320, an error amplifier 321, capacitor 322, a resistor ladder digital-to-analog converter (DAC) 324, a boost comparator 325 and a buck comparator 326, resistor 328, capacitor 330, and control logic and latch 332. The latch in control logic and latch 332 is simply a latch used to hold the value of the control logic for timing purposes. Therefore, this component will be simply referred to as control logic 332.

[0133] Inverting voltage amplifier 304 is configured to receive output voltage VOUT and to generate an inverted output voltage VOUT'. Therefore, the inverted output voltage VOUT' has the same voltage amplitude |VOUT| as the output voltage VOUT, but with a positive voltage polarity. Resistor 306 is connected between the output of inverting voltage amplifier 304 and feedback node 312. Resistor 308 is connected between feedback node 312 and ground. Resistor 306 has resistance R1 and resistor 308 has resistance R2. Therefore, resistors 306 and 308 form a voltage divider that generates a feedback voltage VFB based on the inverted output voltage VOUT' and therefore also based on the output voltage VOUT.

[0134] The constant peak current PFM controller 310 is configured to receive a feedback voltage VFB to generate a control output C-PFM in a first operating mode. In the first operating mode (explained in further detail below), the boost comparator 325 and the buck comparator 326 are deactivated. In the second operating mode (also explained in further detail below), the constant peak current PFM controller 310 is deactivated, and the boost comparator 325 and the buck comparator 326 are activated.

[0135] Resistor 318 and capacitor 320 are connected in parallel between feedback node 312 and the inverting input of error amplifier 321. The non-inverting input of error amplifier 321 is configured to receive a reference voltage VREF_P. A resistive ladder DAC 324 (also known as a boost ramp generator 324) is configured to receive the reference voltage VREF and generate a reference voltage VREF_P based on VREF. The voltage level of the reference voltage VREF_P is based on the eight-bit input VSET, which selects the voltage level of the reference voltage VREF_P. The voltage level of the reference voltage VREF_P varies between 0.5 V and 5.7 V, depending on the value of the eight-bit input VSET.

[0136] Resistor 328 is connected in series with capacitor 330. The series-connected resistor 328 and capacitor 330 are connected in parallel with capacitor 322 between the inverting input and output of error amplifier 321. Error amplifier 321 is configured to generate an error voltage VERR at its output. The error voltage VERR is based on the difference between the feedback voltage VFB and the reference voltage VREF_P.

[0137] The boost comparator 325 is configured to receive the error voltage VERR at the inverting terminal and the boost ramp voltage VBOOST at the non-inverting terminal. In response to receiving the error voltage VERR and the boost ramp voltage VBOOST, the boost comparator 325 is configured to generate an output voltage C-PWM-BOOST based on the difference between the boost ramp voltage VBOOST and the error voltage VERR.

[0138] Buck comparator 326 is configured to receive the error voltage VERR at the inverting terminal and the buck ramp voltage VBUCK (shown as "BUCK RAMP" in Figure 3) at the non-inverting terminal. In response to receiving the error voltage VERR and the buck ramp voltage VBUCK, buck comparator 326 is configured to generate an output voltage C-PWM-BUCK based on the difference between the buck ramp voltage VBUCK and the error voltage VERR.

[0139] Output voltages C-PWM-BOOST and C-PWM-BUCK are received by control logic 332. Based on output voltages C-PWM-BOOST and C-PWM-BUCK, control logic 332 is configured to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo. Combined, control voltages Φbu, Φ'bu, Φbo, and Φ'bo are examples of control output 132 shown in Figure 2. Switches S1(1), S2(1), and S3(2) are configured to receive control voltage Φbu. Therefore, switches S1(1), S2(1), and S3(2) open and close in response to control voltage Φbu (as described in Tables II and III). Switches S1(2), S2(2), and S3(1) are configured to receive control voltage Φ'bu. Therefore, switches S1(2), S2(2), and S3(1) open and close in response to the control voltage Φ'bu (as described in Tables II and III). Switch S6 is configured to receive the control voltage Φbo. Therefore, switch S6 opens and closes in response to the control voltage Φbo (as described in Tables II and III). Switch S5 is configured to receive the control voltage Φ'bo. Therefore, switch S5 opens and closes in response to the control voltage Φ'bo (as described in Tables II and III).

[0140] In the first operating mode, the constant peak current PFM controller 310 is activated, and the boost converter DAC 324 and the buck comparator 326 are deactivated. The constant peak current PFM controller 310 is configured to receive the feedback voltage VFB and generate a control output C-PFM. The control logic 332 is configured to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo based on the control output C-PFM. In buck mode, the constant peak current PFM controller 310 generates the control output C-PFM such that the control voltages Φbu, Φ'bu, Φbo, and Φ'bo cycle through buck circuit states 1-4, as described above with respect to Figure 2E. In boost mode, the constant peak current PFM controller 310 generates the control output C-PFM such that the control voltages Φbu, Φ'bu, Φbo, and Φ'bo cycle through boost circuit states 1-4, as described above with respect to Figure 2F. In buck-boost mode, the constant peak current PFM controller 310 generates a control output C-PFM such that control voltages Φbu, Φ'bu, Φbo, and Φ'bo cycle through buck-boost circuit states 1-6, where buck-boost circuit states 1-3 are shown in Figure 2G and buck-boost circuit states 4-6 are reversible buck-boost states. The constant peak current PFM controller 310 is configured to detect peak current. The constant peak current PFM controller 310 is advantageous in situations with light loads where the inductor current IL cycles to its peak and then remains at a minimum current level for most of the switching cycles with minimal losses. The constant peak current PFM controller 310 is activated in DCM. The constant peak current PFM controller 310 detects the peak current level of the inductor current IL based on the feedback voltage VFB, such that the control output C-PFM contains a pulse once the peak current level is detected. The pulse directs control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo based on the subsequent circuit state, which depends on whether a buck operation, a boost operation, or a buck-boost operation is being performed.

[0141] Figure 3A is a voltage and current graph illustrating the operation of the voltage converter 300 shown in Figure 3 according to some embodiments, wherein the error amplifier 321 and the buck comparator 326 are activated in CCM (i.e., second operating mode).

[0142] The top graph is a voltage graph showing the output voltage C-PWM-BOOST and output voltage C-PWM-BUCK versus time (for all graphs in Figure 3A, the bottom axis is the time axis). As shown, the output voltage C-PWM-BOOST remains at the same voltage level because the boost comparator 325 is inactive.

[0143] The next graph, starting from the top, is a voltage graph showing the boost ramp voltage VBOOST, buck ramp voltage VBUCK, and error voltage VERR. In this embodiment, the error voltage VERR only intersects with the buck ramp voltage VBUCK because the voltage converter 300 operates in the buck region.

[0144] The second graph, starting from the bottom, is a current curve showing the inductor current IL versus time.

[0145] The graph at the bottom shows the output voltage VOUT at output node 122 versus time.

[0146] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -2 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0147] As shown in Figure 3A, at 4.00345 ms, the buck ramp exceeds the error voltage VERR. In response, the output voltage C-PWM-BUCK is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck circuit state 1 described above with respect to Figure 2E. Therefore, output inductor 116 is magnetized, and inductor current IL becomes increasingly positive. In response, the magnitude of output voltage VOUT decreases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck circuit state 1 from 4.00345 ms until 4.00375 ms.

[0148] As shown in Figure 3A, at 4.00375 ms, the buck ramp reaches the error voltage VERR and then drops below it. In response, the output voltage C-PWM-BUCK is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck circuit state 2 described above with respect to Figure 2E. As a result, output inductor 116 is demagnetized, and inductor current IL becomes increasingly negative. In response, the amplitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck circuit state 2 from 4.00375 ms to 4.00413 ms.

[0149] As shown in Figure 3A, at 4.00413 ms, the buck ramp exceeds the error voltage VERR. In response, the output voltage C-PWM-BUCK is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck circuit state 3 described above with respect to Figure 2E. As a result, output inductor 116 is magnetized, and inductor current IL becomes increasingly positive. In response, the magnitude of output voltage VOUT decreases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck circuit state 3 from 4.00413 ms until 4.00445 ms.

[0150] As shown in Figure 3A, at 4.00445 ms, the buck ramp reaches the error voltage VERR and then drops below it. In response, the output voltage C-PWM-BUCK is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck circuit state 4 described above with respect to Figure 2E. Therefore, output inductor 116 is demagnetized, and inductor current IL becomes increasingly negative. In response, the magnitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck circuit state 4 from 4.00445 ms until 4.00483 ms. Then, the loop returns to buck circuit state 1 and repeats.

[0151] Figure 3B is a voltage and current graph illustrating the operation of the voltage converter 300 shown in Figure 3 according to some embodiments, wherein the error amplifier 321 and the boost comparator 325 are activated in DCM (i.e., first operating mode).

[0152] The top graph is a voltage graph showing the boost ramp voltage VBOOST, buck ramp voltage VBUCK, and error voltage VERR against time (for all graphs in Figure 3B, the bottom axis is the time axis). In this embodiment, the error voltage VERR intersects only with the boost ramp voltage VBOOST because the voltage converter 300 operates in the boost region.

[0153] The next graph starting from the top is a voltage graph showing the output voltage C-PWM-BOOST versus time.

[0154] The second graph, starting from the bottom, is a current curve showing the inductor current IL versus time.

[0155] The graph at the bottom shows the output voltage VOUT at output node 122 versus time.

[0156] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -6 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0157] As shown in Figure 3B, at 3.6335 ms, the boost ramp is below the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in boost circuit state 1 described above with respect to Figure 2F. Therefore, output inductor 116 is magnetized, and the inductor current IL becomes increasingly negative. In response, the magnitude of output voltage VOUT decreases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck circuit state 1 from 3.6335 ms until 3.6333 ms.

[0158] As shown in Figure 3B, at 3.6333 ms, the boost ramp reaches and exceeds the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in boost circuit state 2 described above with respect to Figure 2F. Therefore, output inductor 116 is demagnetized, and inductor current IL becomes increasingly positive. In response, the magnitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in boost circuit state 2 from 3.6333 ms until 3.63375 ms.

[0159] As shown in Figure 3B, at 3.63375 ms, the boost ramp drops below the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in boost circuit state 3 described above with respect to Figure 2F. Therefore, output inductor 116 is magnetized, and the inductor current IL becomes increasingly negative. In response, the magnitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in boost circuit state 3 from 3.63375 ms until 3.63340 ms.

[0160] As shown in Figure 3B, at 3.63340 ms, the boost ramp reaches and then exceeds the error voltage VERR. In response, the output voltage C-PWM-BOOST is received by control logic 332, which causes control logic 332 to generate control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in boost circuit state 4 described above with respect to Figure 2F. Therefore, output inductor 116 is demagnetized, and inductor current IL becomes increasingly positive. In response, the magnitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in boost circuit state 4 from 3.63340 ms until 3.6345 ms. Then, the loop returns to boost circuit state 1 and repeats.

[0161] Figure 3C is a voltage and current graph illustrating the operation of the voltage converter 300 shown in Figure 3 according to some embodiments, wherein the error amplifier 321, the boost comparator 325 and the buck comparator 326 are activated in CCM (i.e., second operating mode).

[0162] The top plot is a current curve showing the inductor current IL versus time (for all plots in Figure 3C, the bottom axis is the time axis).

[0163] The next graph, starting from the top, shows the output voltage VOUT at output node 122 versus time.

[0164] The intermediate curve shows the input voltage VIN versus time.

[0165] The second curve, starting from the bottom, shows the output voltage C-PWM-BUCK versus time.

[0166] The bottom graph shows the output voltage C-PWM-BOOST versus time.

[0167] In this embodiment, the input voltage VIN is 4 V and the output voltage VOUT is approximately -4 V. The output inductor 116 is 2.2 microhenries and the output capacitor 118 is approximately 10 microfarads.

[0168] As shown in Figure 3C, at 3.7324 ms, the output voltage C-PWM-BUCK is triggered to a high voltage state (approximately ground), while the output voltage C-PWM-BOOST remains in a low voltage state (approximately -4 V). In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 1 described above with respect to Figure 2G. Therefore, output inductor 116 is demagnetized, and inductor current IL becomes increasingly positive. In response, the magnitude of output voltage VOUT decreases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 1 from 3.7324 ms to 3.73245 ms.

[0169] As shown in Figure 3C, at 3.73245 milliseconds, the output voltage C-PWM-BUCK is triggered to a low voltage state, while the output voltage C-PWM-BOOST is triggered to a high voltage state. In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 2 described above with respect to Figure 2G. Therefore, output inductor 116 is magnetized, and inductor current IL becomes increasingly negative. Moreover, in response, the amplitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 2 from 3.73245 milliseconds to 3.73255 milliseconds.

[0170] As shown in Figure 3C, at 3.73255 ms, the output voltage C-PWM-BUCK remains in a low voltage state, while the output voltage C-PWM-BOOST is triggered to a low voltage state. In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 3 described above with respect to Figure 2G. Therefore, the output inductor 116 is slowly demagnetized, and the inductor current IL slowly becomes more and more positive. Moreover, in response, the amplitude of the output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 3 from 3.73255 ms to 3.73331 ms.

[0171] As shown in Figure 3C, at 3.73331 ms, the output voltage C-PWM-BUCK is triggered to a high voltage state (approximately ground), while the output voltage C-PWM-BOOST remains in a low voltage state (approximately -4 V). In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 4 described above with respect to Figure 2G. Therefore, the output inductor 116 is demagnetized, and the inductor current IL becomes increasingly positive. In response, the amplitude of the output voltage VOUT decreases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 4 from 3.73331 ms to 3.733315 ms.

[0172] As shown in Figure 3C, at 3.733315 milliseconds, the output voltage C-PWM-BUCK is triggered to a low voltage state, while the output voltage C-PWM-BOOST is triggered to a high voltage state. In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 5 described above with respect to Figure 2G. Therefore, output inductor 116 is magnetized, and inductor current IL becomes increasingly negative. Moreover, in response, the amplitude of output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 5 from 3.733315 milliseconds to 3.73332 milliseconds.

[0173] As shown in Figure 3C, at 3.73332 milliseconds, the output voltage C-PWM-BUCK remains in a low voltage state, while the output voltage C-PWM-BOOST is triggered to a low voltage state. In response, control logic 332 generates control voltages Φbu, Φ'bu, Φbo, and Φ'bo to provide charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 in buck-boost circuit state 6 described above with respect to Figure 2G. Therefore, the output inductor 116 is slowly demagnetized, and the inductor current IL slowly becomes more and more positive. Moreover, in response, the amplitude of the output voltage VOUT increases. Charging circuit 102(1), charging circuit 102(2), and voltage conversion circuit 104 remain in buck-boost circuit state 6 from 3.73332 milliseconds to 3.73339 milliseconds. Then the voltage converter 300 is placed back into buck-boost circuit state 1, and the cycle repeats.

[0174] Figure 4 illustrates another embodiment of the voltage converter 400 according to some embodiments.

[0175] The voltage converter 400 includes a charging circuit 102(1), a charging circuit 102(2), and a voltage conversion circuit 104, except that in this embodiment, the voltage node 126 is configured to receive the ground voltage instead of the input voltage VIN.

[0176] The voltage converter 200 shown in Figure 2 has higher withstand voltage requirements for switches S5 and S6, but compared to the voltage converter 400 in Figure 4, the inductor saturation current requirement, DC current, and inductor ripple are reduced. The choice between voltage converter 200 and switch converter 400 depends on the process technology quality factor, the available process technology components, and the selection of passive components. The buck, boost, and buck-boost circuit states of the voltage converter 400 in Figure 4 are similar to the buck, boost, and buck-boost circuit states of the voltage converter 200 shown in Figure 2.

[0177] Figure 5 illustrates a voltage converter 500 according to some embodiments, and another embodiment of five different switch configurations for the voltage converter 500.

[0178] The voltage converter 500 includes the voltage conversion circuit 104 and control circuit 130 discussed above with respect to FIG1. ​​However, the voltage converter 500 includes a charging circuit 502 instead of the charging circuit 102 or the charging circuits 102(1) and 102(2) shown in FIG2.

[0179] The charging circuit 502 includes a flying capacitor CFLY (3), a flying capacitor CFLY (4), a switch S10, a switch S11, a switch S12, a switch S13, a switch S14, and a switch S15.

[0180] One side of the flying capacitor CFLY(3) is capacitor node 507, and the opposite side of the flying capacitor CFLY(3) is capacitor node 506. One side of the flying capacitor CFLY(4) is capacitor node 505, and the opposite side of the flying capacitor CFLY(4) is capacitor node 504. Switch S10 is connected between power node 106 and capacitor node 507. Switch S11 is connected between ground node 108 and capacitor node 506. Switch S12 is connected between capacitor node 507 and capacitor node 505. Switch S13 is connected between capacitor node 506 and capacitor node 504. Capacitor node 505 is connected to ground node 108. Switch S14 is connected between capacitor node 504 and inductor node 114. Switch S15 is connected between inductor node 114 and ground node 108. The flying capacitor CFLY(3) is configured to present a flying voltage VFLY(3) at capacitor node 506. The flying capacitor CFLY(4) is configured to present a flying voltage VFLY(4) at capacitor node 504.

[0181] Figure 5 shows the voltage converter 500 in five different switch configurations referred to as switch configurations 1-5.

[0182] The lines corresponding to each of switch configurations 1-5 are closed circuit paths, thereby indicating which switches S5, S6, and S10-S15 are closed. For a particular switch configuration in switch configurations 1-5, all other switches S5, S6, and S10-S15 not provided along the specific lines in Figure 5 are considered open. Table IV below indicates the specific switch states of each switch S5, S6, and S10-S15 in each of switch configurations 1-5.

[0183] The integer Z is an integer corresponding to a specific switch configuration, where Z has values ​​from 1 to 5 to indicate the specific switch configuration in the switch configuration. Table IV indicates whether a specific switch among switches S5, S6, and S10-S15 is open or closed in the charging circuit 502 and voltage conversion circuit 104 in switch configurations 1-5.

[0184]

[0185] For the voltage converter 500 in Figure 5, complete the following sentences according to each of the switch configurations 1-5 in Table IV.

[0186] In switch configuration Z, control circuit 130 is configured to generate control output 132, such that:

[0187] ● Switch S10 is (from the switch state of row Z and column S10 in table IV);

[0188] ● Switch S11 is (from row Z, column S11 switch state of table IV);

[0189] ● Switch S12 is (from row Z, column S12 switch state of table IV);

[0190] ● Switch S13 is (from the switch state of row Z and column S13 in table IV);

[0191] ● Switch S14 is (from the switch state of row Z and column S14 in table IV).

[0192] ● Switch S15 is (from the switch state of row Z and column S15 in table IV);

[0193] ● Switch S5 is (from row Z, column S5 switch state in table IV); and

[0194] ● Switch S6 is (from table IV, row Z, column S6 switch state).

[0195] Charging circuit 502 provides a cascaded connection for flying capacitors CFLY(3) and CFLY(4) to provide a charge pump in the 4-switch configuration. Charging circuit 502 generates a flying voltage VFLY(4) such that the flying voltage VFLY(4) is close to or equal to -VIN. Charging of flying capacitors CFLY(3) and CFLY(4) is performed in switch configurations 1 and 5. Switches S14, S15, S5, and S6 convert the flying voltage VFLY(4) at capacitor node 504 into an output voltage VOUT at output node 122, which is a voltage with negative voltage polarity. Switches S14, S15, S5, and S6 are operated by switch configurations 3-5.

[0196] In switch configuration 3, the output inductor 116 is magnetized in response to |VOUT|<|VIN| and demagnetized in response to |VOUT|>|VFLY(4)|. Energy is transferred between the flyby voltage VFLY(4) and the output voltage VOUT.

[0197] In switch configuration 4, the output inductor 116 is magnetized.

[0198] In switch configuration 5, the output inductor 116 is demagnetized.

[0199] Not all switch configurations 1-5 require balancing the inductor current IL of output inductor 116 within a single switching cycle. In some embodiments, switch configurations 3 and 5 are used to balance the inductor current IL of output inductor 116 when |VOUT| < |VIN|, and switch configurations 4 and 3 are used to balance the inductor current IL of output inductor 116 when |VOUT| > |VIN|. In some embodiments, the switch configurations do not provide inductor current and can be used during DCM operation. It should be noted that the operation of switch configurations 1 and 5 can be independent of switch configurations 3, 4, and 5. An advantage of the voltage converter 500 is that the charge pump can provide extremely high efficiency under high loads. At first glance, switch configuration 4 appears to be a typical 4-switch buck-boost circuit operating in a negative voltage environment. However, by connecting one terminal of switch S5 to the input voltage VIN, the duty cycle of the boost operation is reduced. This reduces the ripple of output inductor 116, the average current, and improves efficiency compared to a typical 4-switch buck-boost configuration.

[0200] Referring to Figure 6, the concepts described above can be implemented in various types of user elements 600, such as mobile terminals, smartwatches, tablets, computers, navigation devices, access points, and similar wireless communication devices supporting wireless communications such as cellular, wireless local area networks (WLAN), Bluetooth, and near-field communication. User element 600 typically includes a control system 602, a baseband processor 604, a transmission circuitry system 606, a receiving circuitry system 608, an antenna switching circuitry system 610, multiple antennas 612, and a user interface circuitry system 614. In a non-limiting example, the control system 602 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this respect, the control system 602 may include at least one or more microprocessors, one or more embedded memory circuits, and one or more communication bus interfaces. The receiving circuitry system 608 receives radio frequency signals from one or more base stations via antennas 612 and through the antenna switching circuitry system 610. Low-noise amplifiers and filters cooperate to amplify and neutralize broadband interference from the received signals for processing. Then, a down-conversion and digitization circuitry system (not shown) down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0201] The baseband processor 604 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 604 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0202] For transmission, baseband processor 604 receives digitized data representing voice, data, or control information from control system 602, and encodes the digitized data for transmission. The encoded data is output to transmission circuitry 606, where one or more digital-to-analog converters (DACs) convert the digitally encoded data into analog signals, and a modulator modulates the analog signals onto a carrier signal at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and then delivers the modulated carrier signal to antenna 612 via antenna switching circuitry 610. Multiple antennas 612 and replicated transmission circuitry 606 and receiver circuitry 608 provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0203] Upon consideration, any of the foregoing aspects, and / or the various individual aspects and features as described herein, may be combined to obtain additional advantages. Unless otherwise indicated herein, any embodiment of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0204] Those skilled in the art will understand that improvements and modifications can be made to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the embodiments described below.

Claims

1. A voltage converter, comprising: A voltage conversion circuit includes: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operatively associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit including: a flying capacitor; a power node configured to receive an input voltage; and a set of switches, wherein the set of switches can be configured in at least one switching configuration for charging the flying capacitor and in at least one switching configuration for presenting a flying voltage across the flying capacitor as a negative voltage at the second inductor node.

2. The voltage converter according to claim 1, wherein the charging circuit is a first charging circuit, the flying capacitor is a first flying capacitor, and the set of switches is a first set of switches, the voltage converter further comprising: A second charging circuit coupled to the second inductor node, wherein the second charging circuit includes: a second flying capacitor; the power node configured to receive the input voltage; and a second set of switches, wherein in a second switch configuration, the second set of switches is configured to charge the second flying capacitor, and in a first switch configuration, the second set of switches is configured to present a second flying voltage across the second flying capacitor as a negative voltage at the second inductor node.

3. The voltage converter according to claim 2, wherein: The first flying capacitor includes a first capacitor node and a second capacitor node; The first set of switches includes: a first switch coupled between the power node and the first capacitor node; and a second switch coupled between the first capacitor node and the ground node; the second flying capacitor includes a third capacitor node and a fourth capacitor node; and the second set of switches includes: a third switch coupled between the power node and the third capacitor node; and a fourth switch coupled between the third capacitor node and the ground node.

4. The voltage converter according to claim 3, wherein: The first set of switches further includes a fifth switch coupled between the second capacitor node and the ground node; and the second set of switches further includes a sixth switch coupled between the fourth capacitor node and the ground node.

5. The voltage converter according to claim 4, wherein: The first set of switches further includes a seventh switch coupled between the second capacitor node and the second inductor node; and the second set of switches further includes an eighth switch coupled between the fourth capacitor node and the second inductor node.

6. The voltage converter of claim 1, wherein the voltage conversion circuit further comprises a first switch connected between the first inductor node and the output node.

7. The voltage converter of claim 6, wherein the output capacitor is connected between the output node and the ground node.

8. The voltage converter of claim 6, wherein the voltage conversion circuit further includes a second switch coupled between the power supply node and the first inductor node.

9. The voltage converter of claim 6, wherein the voltage conversion circuit further comprises a second switch coupled between the ground node and the first inductor node.

10. The voltage converter of claim 1, wherein the set of switches further comprises a first switch coupled between the second inductor node and the ground node.

11. The voltage converter of claim 1, wherein the set of switches further comprises a first switch coupled between the second inductor node and the power supply node.

12. The voltage converter according to claim 1, wherein: The flying capacitor includes a first capacitor node and a second capacitor node; Furthermore, the set of switches includes: a first switch coupled between the power supply node and the first capacitor node; And a second switch, which is coupled between the first capacitor node and the ground node.

13. The voltage converter of claim 12, wherein the set of switches further comprises a third switch coupled between the second capacitor node and the ground node.

14. The voltage converter of claim 1, wherein the set of switches further comprises a fourth switch coupled between the second capacitor node and the second inductor node.

15. The voltage converter according to claim 1, wherein: The flying capacitor is a first flying capacitor having a first capacitor node and a second capacitor node; the set of switches includes a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; The charging circuit further includes a second flying capacitor having a third capacitor node and a fourth capacitor node; The first switch is coupled between the second inductor node and the first capacitor node; The second capacitor node is coupled to the ground node; The second switch is coupled between the second capacitor node and the third capacitor node; The third switch is coupled between the third capacitor node and the power supply node; The fourth switch is coupled between the first capacitor node and the fourth capacitor node; and the fourth capacitor node is coupled to ground.

16. The voltage converter of claim 15, wherein the set of switches further comprises a sixth switch, wherein the sixth switch is coupled between the second inductor node and the ground.

17. The voltage converter of claim 15, wherein the voltage conversion circuit further comprises the fifth switch connected between the first inductor node and the output node.

18. The voltage converter of claim 17, wherein the output capacitor is connected between the output node and the ground node.

19. The voltage converter of claim 17, wherein the voltage conversion circuit further comprises a sixth switch coupled between the power supply node and the first inductor node.

20. The voltage converter of claim 1, wherein the voltage conversion circuit is configured as an inverting voltage conversion circuit.

21. A method for converting an input voltage into an output voltage at an output node, the method comprising: The input voltage is received at the power node, wherein the output node is operatively associated with the first inductor node of the output inductor. Configure a set of switches to charge the flying capacitor; The set of switches can be configured with the same or different switch configurations to present the flying voltage across the flying capacitor as a negative voltage at the second inductor node of the output inductor.

22. A user element, the user element comprising a voltage converter, wherein the voltage converter comprises: A voltage conversion circuit includes: an output capacitor coupled to an output node, wherein an output voltage is generated at the output node; an output inductor having a first inductor node and a second inductor node, the first inductor node being operatively associated with the output node; and a charging circuit coupled to the second inductor node, the charging circuit including: a flying capacitor; a power node configured to receive an input voltage; and a set of switches, wherein the set of switches is configurable for at least one switching configuration to charge the flying capacitor and at least one switching configuration to present the flying voltage across the flying capacitor as a negative voltage at the second inductor node.

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