Word line contact scheme in integrated three-dimensional charge-coupled device memory

Abstract

The invention relates to a charge-coupled device (CCD) memory. Specifically, the present disclosure provides a design and contact scheme for a three-dimensional (3D) integrated CCD memory, which may be a multi-phase CCD memory. The 3D CCD memory includes a stack including a plurality of gate layers and spacer layers alternately arranged one above the other along a first direction; a plurality of semiconductor-based channels extending in the stack. The channel is combined with the gate layer and one or more gate dielectric layers to form a plurality of charge storage capacitor strings operable as a plurality of CCD registers. A plurality of contact vias extend in the stack. Each contact via is associated with one of a plurality of groups of non-intersecting gate layers, and is electrically connected to all of the gate layers of the group associated therewith, where at least one group includes two or more gate layers.

Description

Technical Field

[0001] This disclosure relates to charge-coupled device (CCD) memories. Specifically, this disclosure provides designs and word line contact schemes for three-dimensional (3D) integrated CCD memories, which may be multiphase CCD memories. Background Technology

[0002] Today, driven by data-driven technologies, data creation is advancing rapidly. This necessitates a radical overhaul of the memory pyramid. In particular, the gap between low-cost storage and high-speed operating memory must be bridged. This gap arises from the mismatch between the ever-increasing demand for computing on ever-growing volumes of data and the evolving trends in underlying memory technologies. The growing demand for traditional Dynamic Random Access Memory (DRAM) and the ever-approaching expansion "brick wall" are prompting the search for new types of memory.

[0003] For example, various types of so-called storage-class memory (SCM) have been proposed, but a completely satisfactory solution has yet to emerge. Available alternatives to DRAM either lack the scalability of phase-change memory (PCM), the energy efficiency of magnetic random access memory (MRAM), or the cycle life of low-latency NAND memory.

[0004] CCD-based SCMs have emerged as a novel memory category and are considered ideal for bridging the memory gap, while offering significant cost advantages over DRAM. CCDs lack byte addressing capability, a standard requirement for RAM. One approach adopted in this disclosure is to trade this byte addressing capability for lower costs.

[0005] However, a 3D CCD-based memory array architecture will be needed to achieve the desired high memory cell density. Summary of the Invention

[0006] Therefore, this disclosure aims to provide a 3D CCD memory with high storage cell density.

[0007] An exemplary 3D CCD memory forming the basis of the solution of this disclosure includes a plurality of CCD registers, wherein each CCD register is formed according to a semiconductor-based channel extending in a stack of alternately stacked gate and dielectric layers. Each channel is combined with a gate layer and at least one dielectric layer to form a string of charge storage capacitors that can function as CCD registers.

[0008] To reduce bit costs and increase the density of this exemplary 3D CCD memory, a straightforward approach is to add more layers to the stack, i.e., increase the number of memory cells per CCD register. Alternatively, accessing the gate layers of the stack could be achieved by implementing a stepped structure, where each step of the stepped structure can be connected to the top metal via contacts on that step. However, adding more layers to the stack would increase the vertical height of the stepped structure, and ultimately the area overhead due to the steps would increase too much.

[0009] In particular, designing 3D multiphase CCD memories requires numerous gate layers. Multiphase CCD memories may combine multiple independent gate electrodes within a single memory cell, each potentially requiring a separate input clock signal to properly transfer the accumulated charge through the CCD register. Furthermore, the same phase across all memory cells needs to be connected together. Therefore, balancing memory density, manufacturing yield, and process complexity / cost is challenging when constructing such memories.

[0010] In view of the above, a particular object of this disclosure is to provide a contact scheme for contacting the gate layer of a high-density 3D multiphase CCD memory without excessively increasing area overhead and manufacturing complexity.

[0011] These and other objectives are achieved by the solutions provided in the independent claims of this disclosure. Advantageous embodiments are defined in the dependent claims.

[0012] A first aspect of this disclosure provides an integrated 3D CCD memory comprising: a stack including a plurality of gate layers and spacer layers arranged alternately along a first direction in a manner one on top of the other; a plurality of semiconductor-based channels extending in the stack; wherein the channels are combined with the gate layers and one or more gate dielectric layers to form a plurality of charge storage capacitor strings operable as a plurality of CCD registers; and a plurality of contact vias extending in the stack; wherein each contact via is associated with one of a plurality of sets of non-intersecting gate layers and is electrically connected to all gate layers of the associated set, wherein at least one set comprises two or more gate layers.

[0013] A series of charge storage capacitors can be connected in series to form a CCD register. The charge storage capacitors can be MOS capacitors, and one or more storage capacitors in the CCD register can be considered as storage cells of the CCD memory.

[0014] By integrating CCD registers in a 3D arrangement—that is, by constructing a stack of gate and spacer layers along a first direction and forming channels in this stack, preferably perpendicularly aligned along the first direction—high density similar to that in 3D NAND flash memory can be achieved. Therefore, the cost (per bit stored) can be reduced. The CCD memory of the first aspect can be used as a single-mode memory (SCM) where byte addressing capability can be omitted. CCD memory can provide high speed, good reliability, virtually unlimited cycle time, and low power consumption.

[0015] Each non-overlapping group of the plurality of groups may be in contact with one or more contact vias. All layers in each group are connected together. There may be multiple groups comprising two or more gate layers. For example, each non-overlapping group may comprise two or more gate layers. Multiple CCD registers formed in the stack share the gate layers of the same group. If the 3D CCD memory is a multi-phase memory, each group may be associated with one of multiple timing phases. The timing phases of all CCD registers may be connected together.

[0016] The contact scheme described above allows for contacting the gate layer with a smaller area overhead than that of an exemplary 3D CCD memory. Therefore, this contact scheme allows for a better balance between memory density, manufacturing yield, and manufacturing process complexity.

[0017] In a 3D CCD memory implementation, each contact via is associated with a different set of gate layers.

[0018] In an implementation of a 3D CCD memory, at least one contact via extends through the gate layer of its associated group.

[0019] In an implementation of a 3D CCD memory, at least one contact via extends through one or more gate layers of at least one group that are not associated with it, wherein the contact via and the one or more gate layers of the at least one group that are not associated with it are electrically isolated.

[0020] In an implementation of a 3D CCD memory, at least one contact via extends through the gate layer of an associated group and also extends through one or more gate layers of at least one unassociated group, wherein the contact via and the one or more gate layers of the unassociated group are electrically isolated.

[0021] In an implementation of a 3D CCD memory, one or more gate layers in at least one group not associated with the contact via have a larger opening than the gate layers in the group associated with the contact via, through which the contact via extends.

[0022] The above implementations can provide multiple contact vias with a small area overhead for contacting multiple different groups of non-intersecting gate layers.

[0023] In an implementation of a 3D CCD memory, the stack has a stepped shape, including multiple steps extending in a second direction perpendicular to the first direction. Each step includes multiple gate layers, and the topmost gate layer of each step belongs to the same group. The topmost gate layer of each step is electrically connected to the same contact via located on the top surface of each topmost gate layer.

[0024] In an implementation of a 3D CCD memory, contact vias pass through multiple steps of other gate layers and are electrically isolated from each of these other gate layers by spacers.

[0025] In an implementation of a 3D CCD memory, each step has a stepped structure comprising multiple sub-steps extending in a third direction perpendicular to the first and second directions. Each sub-step includes a gate layer, and the gate layers of different sub-steps belong to different groups. Furthermore, each sub-step of the step is electrically connected through different contact vias located on the top surface of the gate layer of the sub-step.

[0026] The aforementioned step-based implementation can provide multiple contact vias with a small area overhead for contacting multiple different groups of non-intersecting gate layers.

[0027] In an implementation of a 3D CCD memory, a set of stacked gate layers can be operated as multiple timing phases of multiple CCD registers to transfer charge along the CCD registers; and each set of gate layers is associated with a different timing phase among the multiple timing phases.

[0028] Therefore, an efficient way to connect and provide signals to different CCD timing phases is provided. 3D CCD memories can be multiphase CCD memories, which have a small footprint while still achieving high storage density. It is worth noting that each CCD register may also need to be connected to additional signals on gate layers other than the set of gate layers, which are related to the timing phase. For example, input and output transmission gates at the input and output of the CCD register, respectively. Or, for example, a back barrier or output summing well at the output of the CCD register. Typically, each such signal is connected to only a single gate layer, so no special contact scheme is required in these cases.

[0029] In an implementation of a 3D CCD memory, the multiple gate layers of each step include one gate layer for each of the multiple timing phases.

[0030] In an implementation of a 3D CCD memory, a plurality of contact vias include a first contact via connected to a first set of gate layers, the first set of gate layers including gate layers associated with a first timing phase; and a second contact via connected to a second set of gate layers, the second set of gate layers including gate layers associated with a second timing phase.

[0031] In an implementation of a 3D CCD memory, the plurality of contact vias further include: a third contact via connected to a third set of gate layers, the third set of gate layers including gate layers associated with a third timing phase; and / or one or more additional contact vias respectively connected to one or more additional sets of gate layers, the additional sets of gate layers each including gate layers associated with one or more additional timing phases.

[0032] Based on the above implementation, an efficient contact scheme for multiphase 3D CCD memory is provided.

[0033] In an implementation of a 3D CCD memory, the stack has a first region and a second region adjacent to the first region, wherein the CCD register is located in the first region and the contact via is located in the second region.

[0034] A second aspect of this disclosure provides a method for manufacturing an integrated 3D CCD memory, the method comprising: forming a stack comprising a plurality of gate layers and spacer layers, the gate layers and spacer layers being alternately arranged along a first direction in a manner one on top of the other; forming a plurality of semiconductor-based channels in the stack, wherein the channels are combined with gate layers and one or more gate dielectric layers formed in the stack to form a plurality of charge storage capacitor strings operable as a plurality of CCD registers; and forming a plurality of contact vias in the stack; wherein each contact via is associated with one of a plurality of sets of non-intersecting gate layers and is electrically connected to the gate layer of the set associated with it.

[0035] The second approach achieves the same advantages as the device of the first approach and can be extended by the corresponding implementations described above for the 3D CCD memory of the first approach.

[0036] In one implementation, the method further includes: for each contact via, forming a corresponding opening through the stack; constructing the corresponding opening such that the corresponding opening of one set of gate layers is smaller than the corresponding opening of another set of gate layers; forming contact vias in each opening, wherein the contact vias are electrically connected to the gate layers of that set due to the smaller opening in the gate layer of that set associated with the contact via, and are electrically isolated from the gate layers of the other sets due to the larger opening in the gate layers of the other sets; wherein the corresponding openings of the different contact vias have smaller openings in the gate layers of the different sets.

[0037] This implementation achieves a contact scheme with low area overhead.

[0038] In summary, this disclosure presents a design and contact scheme for 3D CCD memories, particularly multiphase 3D CCD memories. The contact scheme may include a stepped structure and / or a structure with contact vias through the gate stack. The contact vias may be formed prior to the replacement metal gate (RMG) step in the 3D CCD memory manufacturing process. Attached Figure Description

[0039] The above aspects and implementations are explained in the following specific embodiments with reference to the accompanying drawings: Figure 1 A 3D CCD memory according to this disclosure is shown.

[0040] Figure 2 A first exemplary contact scheme for a 3D CCD memory according to the present disclosure is shown.

[0041] Figure 3 A second exemplary contact scheme for a 3D CCD memory according to the present disclosure is shown.

[0042] Figure 4 More details of the second exemplary contact scheme are shown.

[0043] Figure 5 More details of the second exemplary contact scheme are shown.

[0044] Figure 6 More details of the second exemplary contact scheme are shown.

[0045] Figure 7 A method for processing a 3D CCD memory according to the present disclosure is shown.

[0046] Figure 8 The process steps for implementing the first exemplary contact scheme are shown.

[0047] Figure 9 The process steps for implementing the first exemplary contact scheme are shown. Detailed Implementation

[0048] Figure 1An integrated 3D CCD memory 10 according to this disclosure is shown. The 3D CCD memory 10 can be an SCM, such as a block-addressable SCM. The CCD memory 10 can be used as a replacement for DRAM in some use cases, or as an improved replacement for various other types of SCM. For example, the CCD memory 10 of this disclosure can provide better scalability than PCM, and / or can have better power efficiency than MRAM, and / or can have better cycle life than low-latency NAND memory.

[0049] The CCD memory 10 includes a layer stack 11 comprising a plurality of gate layers 12 and spacer layers 13, which are arranged alternately along a first direction, one on top of the other. The gate layers 12 may be metal layers or other conductive layers. The spacer layers 13 may be dielectric layers, oxide layers, or other insulating layers. The first direction corresponds to... Figure 1 The vertical direction in the coordinate system can specifically correspond to the first axis of the coordinate system, such as the z-axis shown. Stack 11 can begin with either gate layer 12 or spacer layer 13 (as the bottom layer of the stack), for example, by being set or grown on the substrate. Stack 11 can also end with either gate layer 12 or spacer layer 13 (as the top layer of the stack 11, for example, furthest from the substrate), and Figure 1 The stack shown in Figure 11 is just one example.

[0050] The CCD memory 10 also includes a plurality of semiconductor-based channels 14 extending in the stack 11. These channels 14, together with gate layers 12 and one or more gate dielectric layers 15 (which may extend through the stack adjacent to the semiconductor-based channels 14), form a plurality of charge storage capacitor strings. These charge storage capacitors can function as a plurality of CCD registers 16. Notably, each gate layer 12 may surround one or more semiconductor-based channels 14. One end (bottom) of each CCD register 16 may include an output transmission gate and may ultimately be connected to readout circuitry. The other end (top) may include an input transmission gate and may be connected to a bit line.

[0051] The semiconductor-based channel 14 can be made of a semiconductor oxide material. For example, the semiconductor oxide material may include at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO), or another wide-bandgap oxide semiconductor. Such a wide-bandgap oxide semiconductor allows for increased retention time of the CCD memory 10. The semiconductor-based channel 14 may also be made of silicon-based semiconductor materials or III-V group semiconductor materials.

[0052] To fabricate multiple channels 14, multiple vias can be formed throughout the entire layer stack 11 after the stack 11 has been grown, e.g., on a substrate, and subsequently filled or blocked with a semiconductor-based material (e.g., a semiconductor oxide material such as IGZO) and a material for forming one or more gate dielectric layers 15. Gate dielectric layers 15 can each be disposed between one of the semiconductor-based channels 14 and at least one gate layer 12. This forms a string of charge storage capacitors connected together as a CCD register 16.

[0053] The semiconductor-based channel 14 may extend along a first direction, i.e., along the z-axis, and / or may extend perpendicular to the parallel surfaces of the gate layer 12 and the spacer layer 13. The semiconductor-based channel 14 may be straight or curved in the stack 11, and in particular, they may each have a U-shape. The semiconductor-based channel 14 may be a full-channel or a macaroni-type channel (a hollow channel, e.g., filled with a dielectric material).

[0054] The CCD memory 10 also includes a plurality of contact vias 17 extending in the stack 11. The contact vias 17 may be metallic vias and may extend along a first direction and / or parallel to the channel 14. Each contact via 17 is associated with one of a plurality of sets of non-intersecting gate layers 12—note that in Figure 1 The two groups labeled I and II shown are merely examples. At least one group includes two or more gate layers 12. In one example, all non-intersecting groups include at least two gate layers 12. These groups are non-intersecting because no gate layer 12 in one group is included in any other group. That is, the gate layer 12 of each group is not an element of other groups. Each contact via 17 is electrically connected to all gate layers 12 of its associated group. Each contact via 17 may be associated with different groups. However, more than one contact via 17 may be associated with the same group. Each contact via 17 may be isolated from or at least not connected to the gate layers of one or more groups that are not associated with it.

[0055] Figure 2 A first exemplary contact scheme for a 3D CCD memory 10 according to the present disclosure is shown, which can be established, for example, on... Figure 1 The 3D CCD memory 10 shown. Figure 1 and 2 The same elements are labeled with the same reference numerals, and can be implemented similarly.

[0056] A first exemplary contact scheme includes one or more contact vias 17, each extending through a gate layer 12 of an associated group, again illustrated by groups I and II. Each contact via 17 may extend through its associated gate layer 12. Furthermore, each contact via 17 also extends through one or more gate layers 12 of at least one unassociated group, and the contact vias 17 and the one or more gate layers 12 of the unassociated group are electrically isolated. For example, Figure 2 Two contact vias 17 are shown. One of these contact vias 17 extends through and connects to the gate layer 12 associated with group I, and extends through but is isolated from the gate layer 12 of group II. That is, the contact via 17 is electrically contacted with the gate layer 12 of group I, but not with the gate layer of group II. The other contact via 17 extends through and connects to the gate layer 12 associated with group II, and extends through but is isolated from the gate layer 12 of group I.

[0057] This can be achieved by openings of different sizes in the gate layers 12 of the stack 11, through which contact vias 17 extend. For example, gate layers 12 in groups not associated with the contact vias 17 have larger openings than those in groups of gate layers 12 associated with the contact vias 17. Figure 2 The contact via 17 associated with Group I extends through the gate layer 12 of Group I and the gate layer of Group II. However, since the gate layer 12 of Group II has a larger opening around the contact via 17, the contact via 17 can be isolated from the gate layer 12 of Group II, for example, through a dielectric material.

[0058] It is worth noting that, in Figure 2 The diagram shows that the gate layer 12 of group I can be a first timing phase (phase 1), while the gate layer of group II can be a second timing phase (phase 2). Typically, at least some of the multiple gate layers 12 of the stack 11 can operate as multiple timing phases of multiple CCD registers 16 to transfer charge along the CCD registers 16. Each group of gate layers 12 can be associated with a different timing phase among the multiple timing phases—in Figure 2 In the example, it is phase 1 and phase 2.

[0059] from Figure 2 It can also be seen that the stack 11 may have a first region 20 and a second region 21 adjacent to the first region 20. The CCD register 16 is located in the first region 20, which can therefore also be referred to as the memory core. The contact via 17 is located in the second region 21, which can be referred to as the contact region.

[0060] Figure 3A second exemplary contact scheme for the 3D CCD memory 10 according to this disclosure is shown, which can be established, for example, on... Figure 1 The 3D CCD memory 10 shown. Figure 1 and 3 The same elements are labeled with the same reference numerals, and can be implemented similarly.

[0061] Figure 3 The stack 11 is shown to have a stepped shape. That is, the stack 11 may include multiple steps 31 extending in a second direction perpendicular to the first direction. The second direction may be along a second axis, such as the x-axis shown. Therefore, each step 31 extends further along / into the x-axis than the steps 31 above it. Each step 31 includes multiple gate layers 12. The topmost gate layers 12 of each step 31 belong to the same group. For example, as... Figure 3 As shown, the top gate layer 12 of both illustrated steps 31 belongs to group I. The top gate layer 12 of each step 31 is electrically connected to the same contact via 17, which is located on the exposed top surface of the top gate layer 12. For example, Figure 3 The contact via 17 is located on the top gate layer 12 of the upper step 31 and the lower step 31, both of which belong to group I.

[0062] Each contact via 17 can further pass through other gate layers 12 via multiple steps 31, and can be electrically isolated from each of these other gate layers 12 by spacers 32. For example, Figure 3 The contact via 17 passes through the gate layers 12 of the two steps 31 belonging to group II, and is separated from these gate layers 12 by two separators 32 respectively. That is, the contact via 17 is only in electrical contact with the gate layers 12 of group I, but not in electrical contact with the gate layers of group II.

[0063] Figure 3 The diagram also shows that each contact via 17 can be connected to a metal contact 22. Each CCD register 16 can also be connected to a metal contact and / or via.

[0064] Gate layer ladder architecture is very useful for multiphase 3D CCD memories, such as— Figure 3 The groups I and II shown are associated with different timing phases (phase 1, phase 2). Each gate layer 12 is connected to or can be connected to a word line.

[0065] Figure 4 More details of the second exemplary contact scheme are shown. Figure 3 and Figure 4 The same elements of the 3D CCD memory 10 are labeled with the same reference numerals. Figure 4The image depicts a 3D view of a 3D CCD memory 10 with a stepped shape.

[0066] In particular, Figure 4 In this example, the 3D CCD memory 10 is a 3-phase CCD memory. That is, each step 31 includes three gate layers 12 for three different timing phases, which in this example are phase 1, phase 2, and phase 3. The step 31 extends in the x-direction.

[0067] In the y-direction, each step 31 is split from a single stack in the y-direction. That is, each step 31 itself also has a stepped structure. Therefore, each step 31 includes multiple sub-steps 41, as shown, which unfold along the y-axis. Each sub-step 41 includes a gate layer 12, and the gate layers 12 of different sub-steps 41 belong to different groups of multiple non-overlapping groups. For example, in Figure 4 In this design, each sub-step 41 includes a gate layer 12 for phase 1, another gate layer 12 for phase 2, and another gate layer for phase 3. By making the steps two-dimensional instead of one-dimensional, area can be saved in the x-direction. Meanwhile, the sub-steps in the y-direction provide a pathway to connect the same timing phase to the common back-end process (BEOL) metal via contact vias 17.

[0068] Figure 5 and Figure 6 Further details of the second exemplary contact scheme are shown. Figure 4 , 5 The same elements as the 3D CCD memory 10 in Figure 6 are labeled with the same reference numerals.

[0069] like Figure 5 and Figure 6 As shown in (b), each sub-step 41 of each step 31 is electrically connected via different contact vias 17 located on the top surface of the gate layer 12 of the sub-step 41. Specifically, a first contact via 17a is connected to a first group of gate layers 12 associated with timing phase 1, a second contact via 17b is connected to a second group of gate layers 12 associated with timing phase 2, and a third contact via 17c is connected to a third group of gate layers 12 associated with timing phase 3. The 3D CCD memory 10 may include one or more additional contact vias 17, which are respectively connected to one or more groups of gate layers 12, each group including gate layers 12 associated with one or more additional timing phases.

[0070] Using steps 31 and sub-steps 41 to make the steps two-dimensional instead of one-dimensional can save area, but the size of the steps is still limited by the spacing of the contact vias 17. To improve this, a trench-based contact metal filling is proposed, in which dedicated and controlled trenches are formed in the x-direction, which exposes the same phase for each unit memory bit cell (a unit bit cell can have multiple phase / gate layers; for example, for a 3-phase 3D CCD memory 10, each memory cell may include 3 phases and therefore three gate layers 12). The trenches are filled with metal for the contact vias 17, which electrically connects the same timing phase of each memory cell. Figure 6 As shown in (a), sidewall spacers 32 are formed on each step 31 of the step in the x-direction to isolate the other stacked gate layers 12 (other phases) from the contact metal vias 17. This contact scheme can be applied to all three sub-steps 41 (corresponding to different phases), which extend in the bit line direction (y-direction), as... Figure 6 As shown.

[0071] Figure 6 The x- and y-direction side views of the stepped structure of the 3D CCD memory 10 are shown in particular. Using this stepped structure, all the same timing phases of the 3D-CCD memory 10 can be electrically connected, which alleviates the limitation of the WL stepped size imposed by the conventional stepped contact spacing.

[0072] Figure 7 A flowchart of a general method 70 for manufacturing the present disclosure, for example, a 3D CCD memory 10 as shown in the preceding figures, is illustrated. Method 70 includes a step 71 of forming a stack 11 comprising a plurality of gate layers 12 and spacer layers 13 arranged alternately along a first direction, one on top of the other. Method 70 further includes a step 72 of forming a plurality of semiconductor-based channels 14 in the stack 11. The channels 14, combined with gate layers 12 also formed in the stack 11 and one or more gate dielectric layers 15, form a plurality of charge storage capacitor strings operable as a plurality of CCD registers 16. Method 70 further includes a step 73 of forming a plurality of contact vias 17 in the stack 11. Each contact via 17 is associated with and electrically connected to one of a plurality of sets I, II of non-intersecting gate layers 12, and is connected to the associated gate layer 12 of said set I, II.

[0073] In addition to the solutions described above, this disclosure also proposes a specific process architecture for implementing the second exemplary contact scheme, wherein the contact via 17 can be formed prior to RMG. Figure 8 and 9 The detailed process architecture is shown.

[0074] The process architecture includes forming a corresponding opening through the stack 11 for each contact via 17, and constructing the corresponding opening such that the corresponding opening of one group of gate layers 12 is smaller than the corresponding opening of other groups of gate layers 12. The process also includes forming the contact via 17 in each opening, wherein the contact via 17 is electrically connected to these gate layers due to the smaller opening in the group of gate layers 12 associated with it, and is electrically isolated from these other groups of gate layers 12 due to the larger opening in the other groups of gate layers 12. Therefore, the corresponding openings of different contact vias 17 have smaller openings in different groups of gate layers 12.

[0075] One approach is to first position the mating contact holes 17, and then perform RMG. For example... Figure 8 As shown in (d), the contact via 17 can be fully in place, including metallization prior to the RMG. However, this may present problems with placing the RMG on the metal plug connected to the contact via 17. Alternatively, a plug made of sacrificial material can be used on which the RMG can be placed. This material can then be removed after the RMG and replaced with metal, as shown in (d). Figure 8 As shown in (f).

[0076] Figure 8 The processing of a second exemplary contact scheme is illustrated. One possible option is to etch and fill the storage via before contact etching. However, contact etching can also be performed beforehand. In the latter case, it may initially be impossible to fill with metal, and sacrificial plugs may have to be used, such as... Figure 8 As described in (d), a challenging aspect is how to achieve contact etching (e.g., for multiphase 3D-CCD memories) Figure 8 (b) shown). Figure 9 This illustrates one possible approach to handling contact etching.

[0077] Here, prior to RMG, a stack 11 comprising multiple gate layers 12 and spacer layers 13 is formed, these layers 13 being alternately arranged along a first direction, one on top of the other. The multiple gate layers 12 are formed by multicolor die deposition, wherein one set of multiple sets of non-intersecting gate layers 12 is formed of the same material, while different non-intersecting sets are formed of different materials for the gate layers 12. Figure 9 As shown, after the contact via etch, a recess is performed on the gate layer in one of a group of multiple non-intersecting gate layers. For each contact via 17, the gate layer recess can be performed alternately to form a corresponding opening through the stack 11 and to construct a corresponding opening such that the corresponding opening of one group of gate layers 12 is smaller than the corresponding opening of other groups of gate layers 12.

[0078] In the claims and in the description herein, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plural. A single element may perform the function of several entities or items recited in the claims. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be used in an advantageous implementation.

Claims

1. An integrated three-dimensional charge-coupled device (CCD) memory (10), comprising: The stack (11) includes a plurality of gate layers (12) and spacer layers (13) arranged alternately along a first direction (z) in a manner that one is on top of the other. Multiple semiconductor-based channels (14) extending in the stack; The channel (14) is combined with the gate layer (12) and one or more gate dielectric layers (15) to form a plurality of charge storage capacitor strings operable as a plurality of CCD registers (16); and Multiple contact vias (17) extending in the stack (11); Each contact via (17) is associated with one of a plurality of non-intersecting gate layers (12) (I, II) and is electrically connected to all gate layers (12) of the associated group (I, II), wherein at least one of the groups (I, II) comprises two or more gate layers (12).

2. The 3D CCD memory (10) according to claim 1, characterized in that, Each contact via (17) is associated with a gate layer (12) of a different group (I, II).

3. The 3D CCD memory (10) according to claim 1 or 2, characterized in that, At least one contact via (17) extends through the gate layer (12) of the group (I, II) associated therewith.

4. The 3D CCD memory (10) according to any one of claims 1 to 3, characterized in that, At least one contact via (17) extends through one or more gate layers (12) of at least one group (I, II) which are not associated with it, wherein the contact via (17) and the one or more gate layers (12) of the at least one group (I, II) which are not associated with it are electrically isolated.

5. The 3D CCD memory (10) according to claims 3 and 4, characterized in that, Compared to the gate layer (12) of the group (I, II) not associated with the contact via (17), the gate layer (12) of at least one group (I, II) not associated with the contact via (17) has a larger opening through which the contact via (17) extends.

6. The 3D CCD memory (10) according to any one of claims 1 to 5, characterized in that: The stack (11) has a stepped shape, comprising multiple steps (31) extending in a second direction (x) perpendicular to the first direction (z), each step (31) comprising multiple gate layers (12), and the topmost gate layer (12) of each step (31) belonging to the same group (I, II); and The topmost gate layer (12) of each step (31) is electrically connected to the same contact via (17) located on the top surface of each topmost gate layer (12).

7. The 3D CCD memory (10) according to claim 6, characterized in that, The contact via (17) passes through the other gate layers (12) of the plurality of steps (31) and is electrically isolated from each of these other gate layers (12) by spacers (32).

8. The 3D CCD memory (10) according to claim 6 or 7, characterized in that: Each step (31) has a stair-like structure, including multiple sub-steps (41) extending to a third direction (y) perpendicular to the first direction (z) and the second direction (x). Each sub-step (41) includes a gate layer (12), and the gate layers (12) of different sub-steps (41) belong to different groups (I, II). Each sub-step (41) of the step (31) is electrically connected by different contact vias (17) placed on the top surface of the gate layer (12) of the sub-step (41).

9. The 3D CCD memory (10) according to any one of claims 1 to 8, characterized in that: The collection of the plurality of gate layers (12) of the stack (11) is operable as a plurality of timing phases of the plurality of CCD registers (16) to transfer charge along the CCD registers (16); and Each group (I, II) gate layer (12) is associated with a different timing phase among the plurality of timing phases.

10. The 3D CCD memory (10) according to claim 9 and claim 6 or 7, characterized in that, Each of the plurality of gate layers (12) of each step (31) includes one gate layer (12) for each of the plurality of timing phases.

11. The 3D CCD memory (10) according to claim 9 or 10, characterized in that, The plurality of contact vias (17) include: A first contact via (17a) is connected to a first group (I) gate layer (12), the first group (I) gate layer (12) including a gate layer (12) associated with a first timing phase; and A second contact via (17b) is connected to a second group (II) gate layer (12), the second group (II) gate layer (12) including a gate layer (12) associated with a second timing phase.

12. The 3D CCD memory (10) according to claim 11, characterized in that, The plurality of contact vias (17) also include: A third contact via (17c) is connected to a third set of gate layers (12), the third set of gate layers including a gate layer (12) associated with a third timing phase; and / or One or more additional contact vias (17) are respectively connected to one or more additional groups (I, II) gate layers (12), each of which includes a gate layer (12) associated with one or more additional timing phases.

13. The 3D CCD memory (10) according to any one of claims 1 to 12, characterized in that, The stack (11) has a first region (20) and a second region (21) adjacent to the first region (20), wherein the CCD register (16) is located in the first region (20) and the contact via (17) is located in the second region (21).

14. A method (70) for manufacturing an integrated three-dimensional charge-coupled device (CCD) memory (10), the method (70) comprising: Forming (71) a stack (11) comprising a plurality of gate layers (12) and spacer layers (13), the gate layers and spacer layers being arranged alternately along a first direction (z) in such a manner that one is on top of the other; A plurality of semiconductor-based channels (14) are formed (72) in the stack (11), wherein the channels (14) are combined with the gate layer (12) and the one or more gate dielectric layers (15) formed in the stack (11) to form a plurality of charge storage capacitor strings operable as a plurality of CCD registers (16); and Multiple contact vias (17) are formed (73) in the stack (11); Each contact via (17) is associated with one of a plurality of non-intersecting gate layers (12) (I, II) and is electrically connected to the gate layer (12) of the associated group (I, II).

15. The method (70) according to claim 14, characterized in that, include: A corresponding opening is formed through the stack (11) for each contact via (17); The corresponding openings are constructed such that the corresponding openings of one group (I) gate layer (12) are smaller than the corresponding openings of the other group (II) gate layers (12); The contact via (17) is formed in the respective opening, wherein the contact via (17) is electrically connected to the gate layers (12) of the group (I, II) associated with the contact via (17) due to the smaller opening in the gate layer (12) of the other group, and is electrically isolated from the gate layers (12) due to the larger opening in the gate layer (12) of the other group; The corresponding openings of different contact vias (17) have smaller openings in the gate layers (12) of different groups (I, II).

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