Columnar groove type power MOSFET and forming method thereof

Abstract

A MOSFET (100) includes: an active region (101) formed on a drift region (102); a gate trench (105), the gate trench (105) being formed in the active region (101) and extending into the drift region (102), the gate trench (105) being filled with a gate electrode material (106); the semiconductor device comprises a drift region (102), an active region (101), a gate trench (105) and a columnar trench (107), the columnar trench (107) is adjacent to the active region (101) and extends into the drift region (102), the extension depth of the columnar trench (107) is larger than that of the gate trench (105), the columnar trench (107) is filled with a source electrode material (108) and a gate electrode material (106), and the source electrode material (108) is surrounded by the gate electrode material (106).

Description

Technical Field

[0001] This invention relates to metal-oxide-semiconductor field-effect transistors (MOSFETs), such as silicon trench power MOSFETs. Background Technology

[0002] Typically, in traditional silicon trench power MOSFETs, trenches of a certain depth are formed, filled with a dielectric and a gate metal electrode. The trench depth, dielectric thickness, and doping distribution in the channel and drift region can be optimized to achieve performance superior to the equivalent planar concept, especially at high cell densities. Furthermore, deeper trenches and thicker field oxides can be used to improve on-resistance. However, these optimizations may introduce additional mechanical stress on the wafer and potentially lead to manufacturing problems such as wafer bending, which could increase the risk of mechanical yield loss. Summary of the Invention

[0003] In view of this, the present invention aims to provide an improved MOSFET and a method for forming the same. The objective is to avoid manufacturing problems associated with wafer bending caused by inherent mechanical stresses from, for example, deeper trenches and thicker field oxides. Another objective is to reduce on-resistance.

[0004] These and other objectives are achieved through embodiments of the invention, as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0005] According to a first aspect of the present invention, a MOSFET is provided. The MOSFET includes: an active region formed on a drift region; a gate trench formed in the active region and extending into the drift region, the gate trench being filled with a gate electrode material; and a columnar trench adjacent to the active region and extending into the drift region, the columnar trench having an extension depth greater than the extension depth of the gate trench, the columnar trench being filled with an active electrode material and the gate electrode material, the source electrode material being surrounded by the gate electrode material.

[0006] Therefore, the present invention provides an alternative for achieving the superior performance of trench power MOSFETs by providing pillar-side gate trench power MOSFETs. In particular, the trench cells can be designed as individual pillars, rather than conventional elongated trenches that apply mechanical stress in a single direction, thereby causing wafer bending.

[0007] Advantageously, the inherent mechanical stress from the thick field oxide can be self-balancing. Furthermore, columnar trenches can provide greater conduction lengths, for example, compared to conventional strip arrangements, thereby reducing on-resistance. Additionally, gate trenches can provide additional reverse channels to increase channel density, which can allow for further reductions in on-resistance.

[0008] In the implementation of the first aspect, the gate electrode material in the gate trench is interconnected with the gate electrode material in the columnar trench.

[0009] In other words, the gate electrode material in the gate trench and the gate electrode material in the pillar trench can be electrically coupled to each other to realize a three-terminal device. This may help to achieve a simple gate drive scheme.

[0010] In the implementation of the first aspect, the gate electrode material in the columnar trench is laterally spaced from the source electrode material in the columnar trench.

[0011] In the implementation of the first aspect, the gate electrode material in the columnar trench is electrically isolated from the source electrode material in the columnar trench.

[0012] Advantageously, for example, an electrical short circuit between the gate electrode and the source electrode of the MOSFET can be avoided.

[0013] In the implementation of the first aspect, the depth of the source electrode material in the columnar trench is greater than the depth of the gate electrode material in the columnar trench and / or the depth of the gate electrode material in the gate trench.

[0014] Advantageously, for example, a deeper source electrode in the drift region can result in a more efficient field plate, thereby increasing voltage blocking capability, i.e., a higher breakdown voltage of the MOSFET.

[0015] In the first aspect of the implementation, the MOSFET further includes a source contact connected to the active region and the source electrode material in the columnar trench.

[0016] This allows current to flow vertically from the active region through the drift region.

[0017] In the implementation of the first aspect, the gate electrode material in the gate trench and the gate electrode material in the columnar trench are interconnected via a gate pickup structure.

[0018] For example, the gate pickup structure can be made of the same material as the gate electrode, such as polysilicon.

[0019] According to a second aspect of the invention, a chip system is provided. According to a first aspect of the invention, the chip system includes a plurality of MOSFETs. In this respect, the gate trench of each of the plurality of MOSFETs is formed between two pillar trenches of two adjacent MOSFETs.

[0020] In a second implementation, each of the columnar trenches has a square shape along the top surface of the chip system. Additionally or alternatively, each of the gate trenches has a rectangular shape along the top surface of the chip system. Additionally or alternatively, the length of each gate trench is less than or equal to the length of each of the columnar trenches along the top surface of the chip system.

[0021] Advantageously, for example, the inherent mechanical stress can be self-balancing.

[0022] In the second implementation, the gate electrode materials of two adjacent columnar trenches are diagonally connected on the top surface of the chip system. Alternatively or additionally, the gate electrode materials of two adjacent gate trenches are orthogonally connected on the top surface of the chip system.

[0023] Advantageously, for example, interconnecting the gate terminals on the silicon surface via the gate pickup structure can allow for a simpler layout and a simpler manufacturing process.

[0024] In the second implementation, each of the columnar trenches has a hexagonal shape along the top surface of the chip system.

[0025] According to a third aspect of the present invention, a method for forming a MOSFET is provided. The method includes the steps of: forming an active region on a drift region; forming a gate trench extending into the drift region in the active region and filling the gate trench with a gate electrode material; forming a columnar trench adjacent to the active region and extending into the drift region, the columnar trench having an extension depth greater than the extension depth of the gate trench; and filling the columnar trench with a source electrode material and a gate electrode material such that the source electrode material is surrounded by the gate electrode material.

[0026] In a third implementation, the method further includes the following steps: interconnecting the gate electrode material in the gate trench with the gate electrode material in the columnar trench; and connecting the active region with the source electrode material in the columnar trench via a source contact.

[0027] In a third aspect of implementation, forming the gate trench includes the following steps: etching the active region from the top side opposite the drift region to form the gate trench extending into the drift region; filling the gate trench with a gate oxide material; etching the gate oxide material from the top side to form a recess in the gate oxide material; and filling the recess with the gate electrode material.

[0028] In a third aspect implementation, forming the columnar trench includes the following steps: etching the active region from the top side opposite the drift region to form the columnar trench extending into the drift region; filling the columnar trench with a field oxide material; etching the field oxide material from the top side to form a first recess in the field oxide material, and filling the first recess with the source electrode material; etching the field oxide from the top side to form a second recess in the field oxide material, such that the second recess surrounds the first recess and is laterally spaced from the first recess, and filling the second recess with the gate electrode material.

[0029] It should be noted that the chip system according to the second aspect and the method according to the third aspect correspond to the MOSFET according to the first aspect and its implementation. Furthermore, the chip system of the second aspect and the method of the third aspect achieve the same advantages and effects as the MOSFET of the first aspect and its corresponding implementation. Attached Figure Description

[0030] The following description of specific embodiments, in conjunction with the accompanying drawings, will illustrate the above aspects and their implementation methods, as shown in the drawings: Figure 1 An exemplary diagram of a MOSFET according to the present invention is shown; Figure 2 A first exemplary diagram of a chip system according to the present invention is shown; Figure 3 It shows Figure 2 A first cross-sectional view of the chip system; Figure 4 It shows Figure 2 A second cross-sectional view of the chip system; Figure 5 It shows Figure 2 A third cross-sectional view of the chip system; Figure 6A It shows Figure 2 An example of the off state of a chip system; Figure 6B It shows Figure 2 An exemplary on-state of a chip system; Figure 7 A second exemplary diagram of a chip system according to the present invention is shown; Figure 8An exemplary flowchart of the method according to the present invention is shown. Detailed Implementation

[0031] The exemplary embodiments of the invention shown in the accompanying drawings are described in detail below. However, various modifications can be made to the following embodiments of the invention, and the scope of the invention is not limited to the following embodiments. Reference numerals for similar entities in different embodiments have been omitted in some instances.

[0032] Figure 1 An exemplary diagram of a MOSFET 100 according to a first aspect of the present invention is shown. The MOSFET 100 may include an active region 101 formed on a drift region 102. For example, the active region 101 may include one or more semiconductor regions of a first conductivity type (e.g., an N+ region) and one or more semiconductor regions of a second conductivity type (e.g., a P-body region). The drift region 102 may include a semiconductor epitaxial region of a first conductivity type, such as an N- epitaxial region.

[0033] The drift region 102 may be formed on a substrate 103 of a first conductivity type (e.g., an N+ substrate). The MOSFET 100 may also include a drain electrode material or drain metal 104 that is electrically coupled to the substrate 103 on a surface of the substrate 103 opposite to the drift region 102.

[0034] The MOSFET 100 may further include a gate trench or shallow trench 105 formed in the active region 101 and extending into the drift region 102. The gate trench 105 may be filled with a gate electrode material or a gate electrode 106. The MOSFET 100 may further include a pillared trench 107 adjacent to the active region 101 and extending into the drift region 102, the depth of the pillared trench 107 being greater than the depth of the gate trench 105.

[0035] The columnar trench 107 can be filled with active electrode material or source electrode 108 and gate electrode 106, such that the source electrode 108 can be surrounded by the gate electrode 106 in the columnar trench 107 and can be electrically isolated from the gate electrode 106.

[0036] For example, gate trench 105 can be formed by etching active region 101 from the top side opposite to drift region 102 and extending into drift region 102. The etched gate trench can be filled with a gate oxide material, such as silicon dioxide. Then, the gate oxide material can be etched from the top side to form a recess in the gate oxide material. Subsequently, the recess in the gate oxide material can be filled with a gate electrode material, such as polysilicon, silicide, or metal composite material.

[0037] For example, the columnar trench 107 can be formed by etching the active region 101 from the top side and extending it into the drift region 102 (especially extending into the drift region 102, where the extension depth of the columnar trench 107 is greater than the extension depth of the gate trench 105). The etched columnar trench can be filled with a field oxide material, such as thick silicon dioxide. Subsequently, the field oxide material can be etched from the top side to form deep recesses in the field oxide material, and further shallow recesses surrounding the deep recesses can be formed in the field oxide material, wherein the recesses are laterally spaced.

[0038] Subsequently, the deep recesses can be filled with active electrode materials, such as polysilicon, silicides, or metal composites, while the shallow recesses can be filled with gate electrode materials. A thick field oxide layer between the source and gate electrode materials provides electrical isolation.

[0039] The MOSFET 100 may also include a source contact 109 formed between the gate trench 105 and the pillar trench 107, for example, connected to the source electrode 108 in the active region 101 and the pillar trench 107. For example, the gate electrode 106 in the gate trench 105 and the gate electrode 106 in the pillar trench 107 may be connected together via a gate pickup structure 110. The material used for the gate pickup structure 110 may be the same material as the gate electrode 106, such as polysilicon, silicide, or a metal composite material.

[0040] In this way, current can flow vertically from the active region 101, for example, from the N+ region through the P-body region and through the drift region 102, and this current can be collected by the bottom drain metal 104 via the substrate 103.

[0041] Figure 2 A first exemplary diagram of a chip system 200 according to a second aspect of the present invention is shown. The chip system 200 may include a plurality of MOSFETs 100 such that each gate trench in the gate trench 105 may be formed between two adjacent columnar trenches 107, i.e., a mesa region between two adjacent columnar trenches 107.

[0042] Furthermore, source contacts 109 may be formed between each gate trench 105 and columnar trench 107, and on the columnar trench 107, thereby connecting the source electrode 108 in the columnar trench 107. In this example, the columnar trench 107 may have a square shape, and the gate trench 105 may have a rectangular shape, particularly along the top silicon surface of the chip system 200.

[0043] For example, the length of the gate trench 105 (especially the longer side of the rectangular gate trench 105) can be less than or equal to the length of the columnar trench 107, that is, one side of the square columnar trench 107.

[0044] For example, the gate electrode 106 in the gate trench 105 and the gate electrode 106 in the pillar trench 107 can be connected together via a star gate pickup structure 110. In this respect, the gate electrodes 106 of two adjacent pillar trenches 107 can be diagonally connected on the silicon surface via the gate pickup structure 110. Additionally, the gate electrodes 106 of two adjacent gate trenches 105 can be orthogonally connected on the silicon surface via the gate pickup structure 110.

[0045] Figure 3 A first cross-sectional view of the chip system 200 is shown. Specifically, Figure 3 It shows along Figure 2 The cross-sectional view of the chip system 200 with the A1 dicing line shown specifically illustrates both the columnar trench 107 and the gate trench 105. From the top side, source metal 301 can be provided to interconnect source contacts 109. Source contacts 109 can be formed on the columnar trench 107 to connect the source electrode S, and further formed between the columnar trench 107 and the gate trench 105 to connect the active region 101.

[0046] The columnar groove 107 can extend to a depth d in the drift region 102. PT Furthermore, the gate trench 105 can be formed between two adjacent columnar trenches 107, that is, a mesa region between two adjacent columnar trenches 107, which can extend to a depth d in the drift region 102. GT The gate electrode G in the columnar trench 107 and the gate electrode G in the gate trench 105 can be interconnected via a gate pickup structure, for example, as shown in the figure. Figure 2 As shown.

[0047] For example, for a drift region with a depth of 10 micrometers, the columnar trench 107 can have a depth d of approximately 7 micrometers in the drift region 102. PT The gate trench 105 can have a depth of approximately 1.5 micrometers in the drift region 102. GT .

[0048] For example, in the active region 101, implantation can be performed accordingly to create a P-type reverse channel and an N+ top source contact. On the bottom side, a substrate 103 and subsequently a drain metal 104 can be provided to collect current flowing from the top side to the bottom side.

[0049] Figure 4 A second cross-sectional view of the chip system 200 is shown. Specifically, Figure 4 It shows along Figure 2 The cross-sectional view of the chip system 200 with the A2 dicing line shown specifically shows only the columnar trench 107. As shown here, the gate electrode G in the columnar trench 107 can be diagonally connected on the silicon surface via the gate pickup structure 110.

[0050] For example, in the active region 101 between the columnar trenches 107, i.e., below the gate pickup structure 110 and in the mesa region between two adjacent columnar trenches 107, selective injection, i.e., N+ type or P type, can be performed, for example, based on application requirements, to customize the gate-source capacitance C. GS and gate-drain capacitance C GD .

[0051] Figure 5 A third cross-sectional view of the chip system 200 is shown. Specifically, Figure 5 It shows along Figure 2 The cross-sectional view of the chip system 200 with the A3 cut line shown specifically shows only the gate trench 105. As shown here, the gate electrode G in the gate trench 105 can be orthogonally connected on the silicon surface via the gate pickup structure 110.

[0052] For example, in the active region 101 between the gate trenches 105, i.e., below the gate pickup structure 110 and in the mesa region between two adjacent gate trenches 105, selective implantation, i.e., N+ type or P type, can be performed, for example, based on application requirements, to customize the gate-source capacitance C. GS and gate-drain capacitance C GD .

[0053] Figure 6A An exemplary off-state of the chip system 200 is shown. For example, in the off-state, the chip system 200 can use the source electrode 108 in the columnar trench 107 as an insulating deep field plate to achieve lateral charge compensation or depletion of the drift region 102. It can be seen that lateral depletion can occur simultaneously in the horizontal and vertical planes (i.e., all four sides of the columnar trench 107), thereby producing three-dimensional charge compensation.

[0054] Figure 6B An exemplary on-state of the chip system 200 is shown. For example, in the on-state, the pillar trenches 107 can facilitate an increased conduction length, i.e., a higher channel density, thereby allowing inversion along the conduction length to allow current conduction, thus achieving a reduction in on-resistance. Furthermore, the gate trenches 105 between the pillar trenches 107 can further increase the total conduction length, thereby achieving a further reduction in on-resistance.

[0055] Figure 7 A second exemplary diagram of a chip system 700 according to a second aspect of the present invention is shown. The chip system 700 may include a plurality of MOSFETs 100 such that each gate trench in the gate trench 105 may be formed between two adjacent columnar trenches 107A, i.e., a mesa region between two adjacent columnar trenches 107A.

[0056] Furthermore, source contacts 109 may be formed between each gate trench 105 and the columnar trench 107A, and on the columnar trench 107A, thereby connecting the source electrode 108 in the columnar trench 107A. In this example, the columnar trench 107A may have a hexagonal shape, and the gate trench 105 may have a rectangular shape, particularly along the top silicon surface of the chip system 700.

[0057] For example, the length of the gate trench 105 (especially the longer side of the rectangular gate trench 105) can be less than or equal to the length of the columnar trench 107A, that is, one side of the hexagonal columnar trench 107A. For example, the gate electrode 106 in the gate trench 105 and the gate electrode 106 in the columnar trench 107A can be connected together via the gate pickup structure 110.

[0058] In other words, gate trenches 105 can be formed between columnar trenches 107A to form a network that interconnects the gate trenches 105. Depletion may occur at all six planes of the hexagonal columnar trenches 107A.

[0059] Figure 8 An exemplary embodiment of a method 800 according to a third aspect of the present invention is shown. In a first step 801, an active region is formed on a drift region. In a second step 802, a gate trench extending into the drift region is formed in the active region, and the gate trench is filled with a gate electrode material. In a third step 803, a columnar trench is formed adjacent to the active region and extending into the drift region, the columnar trench having a greater depth than the gate trench, and the columnar trench is filled with both active electrode material and gate electrode material such that the source electrode material is surrounded by the gate electrode material.

[0060] It is important to note that in the specification and claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "an" or "a" does not exclude multiple. A single element or other unit can fulfill the function of several entities or items described in the claims. Furthermore, the words "connected" or "linked" mean that elements can be directly connected together or can be linked through one or more intermediate elements. Moreover, any aspect of the invention relates to other aspects of the invention.

[0061] Although the invention has been illustrated and described in conjunction with one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, while specific features of the invention may have been disclosed only in conjunction with one of several implementations, such features may be combined with one or more other features of other implementations, provided that they are necessary or advantageous for any given or particular application.

Claims

1. A metal-oxide-semiconductor field-effect transistor (MOSFET), characterized in that, include: An active region (101) is formed on a drift region (102). A gate trench (105) is formed in the active region (101) and extends into the drift region (102), and the gate trench (105) is filled with gate electrode material (106). A columnar trench (107) is adjacent to the active region (101) and extends into the drift region (102). The extension depth of the columnar trench (107) is greater than the extension depth (105) of the gate trench. The columnar trench (107) is filled with active electrode material (108) and gate electrode material (106). The source electrode material (108) is surrounded by the gate electrode material (106).

2. The MOSFET according to claim 1, characterized in that, The gate electrode material (106) in the gate trench (105) and the gate electrode material (106) in the columnar trench (107) are interconnected.

3. The MOSFET according to claim 1 or 2, characterized in that, The gate electrode material (106) in the columnar trench (107) is laterally spaced from the source electrode material (108) in the columnar trench (107).

4. The MOSFET according to any one of claims 1 to 3, characterized in that, The gate electrode material (106) in the columnar trench (107) is electrically isolated from the source electrode material (108) in the columnar trench (107).

5. The MOSFET according to any one of claims 1 to 4, characterized in that, The depth of the source electrode material (108) in the columnar trench (107) is greater than the depth of the gate electrode material (106) in the columnar trench (107) and / or the depth of the gate electrode material (106) in the gate trench (105).

6. The MOSFET according to any one of claims 1 to 5, characterized in that, It also includes a source contact (109) that is connected to the source electrode material (108) in the active region (101) and the columnar trench (107).

7. The MOSFET according to any one of claims 1 to 6, characterized in that, The gate electrode material (106) in the gate trench (105) and the gate electrode material (106) in the columnar trench (107) are interconnected via a gate pickup structure (110).

8. A chip system (200, 700), characterized in that, include: A plurality of MOSFETs according to any one of claims 1 to 7, In this plurality of MOSFETs, the gate trench (105) of each MOSFET is formed between two columnar trenches (107) of two adjacent MOSFETs.

9. The chip system according to claim 8, characterized in that, Each of the columnar trenches (107) has a square shape along the top surface of the chip system (200), and / or Each of the gate trenches (105) has a rectangular shape along the top surface of the chip system (200), and / or The length of each gate trench (105) is less than or equal to the length of each columnar trench (107) along the top surface of the chip system (200).

10. The chip system according to claim 9, characterized in that, The gate electrode material (106) of two adjacent columnar trenches (107) is diagonally connected on the top surface of the chip system (200), and / or The gate electrode materials (106) of two adjacent gate trenches (105) are orthogonally connected on the top surface of the chip system (200).

11. The chip system according to claim 8, characterized in that, Each columnar trench (107A) has a hexagonal shape along the top surface of the chip system (700).

12. A method (800) for forming a metal-oxide-semiconductor field-effect transistor (MOSFET), characterized in that, include: An active region (801) is formed in the drift region. A gate trench (802) is formed in the active region and extends into the drift region, and the gate trench is filled with gate electrode material. A columnar trench (803) is formed, the columnar trench being adjacent to the active region and extending into the drift region, the extension depth of the columnar trench being greater than the extension depth of the gate trench, and the columnar trench being filled with source electrode material and the gate electrode material, such that the source electrode material is surrounded by the gate electrode material.

13. The method according to claim 12, characterized in that, Also includes: The gate electrode material in the gate trench is interconnected with the gate electrode material in the columnar trench. The active region is connected to the source electrode material in the columnar trench via the source electrode contact.

14. The method according to claim 12 or 13, characterized in that, Forming the gate trench includes: The active region is etched from the top side opposite the drift region to form the gate trench extending into the drift region. The gate trench is filled with a gate oxide material. The gate oxide material is etched from the top side to form a recess in the gate oxide material. The recess is filled with the gate electrode material.

15. The method according to any one of claims 12 to 14, characterized in that, Forming the columnar groove includes: The active region is etched from the top side opposite the drift region to form the columnar trench extending into the drift region. The columnar trenches are filled with a field oxide material. The field oxide material is etched from the top side to form a first recess in the field oxide material, and the first recess is filled with the source electrode material. The field oxide is etched from the top side to form a second recess in the field oxide material, such that the second recess surrounds the first recess and is laterally spaced from the first recess, and the second recess is filled with the gate electrode material.

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