Structure of shielded gate power mosfet and method of manufacturing the same

Abstract

The application relates to the field of semiconductor technology and provides a shielded gate power MOSFET structure and a manufacturing method thereof. When an avalanche occurs after the device is turned off, a reverse peak voltage generated by a load inductance is applied to the drain of the device, the withstand voltage is borne by a terminal trench ring, an electric field generated by the trench ring has a repelling effect on avalanche holes, and there are no avalanche holes around the field oxide layer of the terminal trench ring. The direction of an electric field generated by additional N-type polysilicon in the terminal additional trench is from the periphery to the additional N-type polysilicon. Under the condition of the same chip area, the current density of the on-current is increased, the on-resistance is reduced, and the performance of the product is improved due to the fact that there is no region without N+ source area; the avalanche hole current flowing into the source area is reduced, the anti-avalanche breakdown characteristic of the device is improved, the avalanche tolerance EAS is increased, and the reliability of the device is improved by adopting the structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to the structure of a shielded gate power MOSFET and its manufacturing method. Background Technology

[0002] The primary research focus for power VDMOS is continuously reducing power consumption (including conduction and switching losses) and improving the robustness of device dynamic performance. Currently, power trench MOSFET devices are suitable for most power applications, and their characteristics are approaching the one-dimensional limits of silicon. The introduction of RESURF (Reduced Surface Field) technology allows power trench MOSFET devices with a withstand voltage of 600V to exceed the one-dimensional limits of silicon. Based on the same RESURF principle, the industry has also proposed a split-gate trench MOSFET device structure, which can break the one-dimensional limits of silicon in the low-to-medium voltage range (20V-300V), exhibiting lower conduction losses and superior device performance.

[0003] A common method to increase the avalanche tolerance of conventional shielded gate power MOSFETs is to create regions in the source region that contain only P-well regions and no N+ source regions (i.e., dummy structures) to provide a path for avalanche hole current, thereby reducing the magnitude and density of the cell avalanche hole current. Conventional shielded gate power MOSFETs do not have a trench structure between the termination trench ring and the termination trench stop ring.

[0004] The problem with conventional methods for increasing avalanche tolerance in shielded gate power MOSFETs is that regions with only P-wells and no N+ source regions (i.e., dummy structures) cannot generate forward current due to the lack of N+ source regions. Therefore, the presence of these structures increases chip area and cost. Furthermore, N+ lithography is required to fabricate the dummy structures. Summary of the Invention

[0005] To address the technical problems existing in the prior art, the main objective of this invention is to provide a structure and manufacturing method of a shielded gate power MOSFET that does not require N+ lithography, reducing the number of lithography steps compared to conventional shielded gate power MOSFET manufacturing methods. Under the same chip area conditions, this invention increases the current density of the conduction current and reduces the on-resistance due to the absence of an N+ source region, thereby improving product performance.

[0006] In a first aspect, the present invention provides a structure for a shielded gate power MOSFET, comprising an N+ substrate, an N- epitaxial layer, a trench field oxide layer, an isolation oxide layer between the shielded gate and the control gate, a gate oxide layer, an N-type shielded gate, a P-well, an N+ source region, a dielectric layer, a back metal, an N-type control gate, a trench, a front metal, a terminal trench polysilicon, and a contact hole; wherein the contact hole contains source metal.

[0007] As a further aspect of the present invention, when the device in the inductive circuit is turned off, the load inductor generates a reverse spike voltage applied to the drain of the device, the terminal trench ring withstands the withstand voltage, the trench ring generates an electric field that repels avalanche holes, and no avalanche holes are generated around the field oxide layer of the terminal trench ring.

[0008] As a further aspect of the present invention, the electric field generated by the additional N-type polysilicon in the terminal avalanche enhancement structure, i.e., the terminal additional trench, is directed from all sides toward the additional N-type polysilicon.

[0009] As a further aspect of the present invention, avalanche holes are attracted around the field oxide layer of the additional trench under the action of the electric field generated by the additional N-type polysilicon in the terminal additional trench.

[0010] As a further aspect of the present invention, the hole current flows to the terminal additional trench in addition to being discharged through the source region.

[0011] As a further aspect of the present invention, the direction of the transverse electric field around the avalanche tolerance enhancement structure, i.e., the additional trench structure, is horizontal and points towards the polycrystalline silicon in the additional trench structure.

[0012] As a further aspect of the present invention, when the devices in the inductive circuit are turned off, part of the avalanche hole current flows to the source region, enters the P-well and is discharged to the source region metal, while the other part of the avalanche hole current is adsorbed on the sidewall of the additional trench field oxygen and the bottom of the additional trench field oxygen under the action of the transverse electric field.

[0013] As a further aspect of the present invention, when the devices in the inductive circuit are turned on, the electron current flowing down from the N+ source region enters the region between the last trench ring and the trench stop ring of the terminal, and then disappears after recombination with the avalanche hole current around the avalanche enhancement structure in that region.

[0014] As a further aspect of the present invention, the avalanche enhancement structure, i.e., the terminal additional groove, is formed by arranging grooves at equal intervals.

[0015] Secondly, the present invention provides a method for manufacturing a shielded gate power MOSFET structure, the method comprising the following steps:

[0016] A. Form an N- epitaxial layer on an N+ substrate;

[0017] B. Perform trench photolithography and etching on the N-epitaxial layer to form trenches and terminal additional trenches of the avalanche resistance enhancement structure. During this process, the terminal additional trenches are formed simultaneously.

[0018] C. An oxide layer and an additional trench field oxide layer grow on the sidewall of the trench, with the additional trench field oxide layer forming simultaneously during the process.

[0019] D. Polycrystalline silicon is deposited and polycrystalline phosphorus diffusion is carried out to form N-type polycrystalline silicon. During this process, additional polycrystalline silicon is formed simultaneously in the terminal trench.

[0020] E. Polycrystalline lithography and etching form an N-type shielding gate;

[0021] F. Forming an isolation oxide layer: An oxide film is deposited using chemical vapor deposition, and then the oxide film is etched back to the specified depth of the isolation oxide film thickness. At this time, there is no oxide layer on the trench sidewalls above the isolation oxide layer.

[0022] G. A gate oxide layer is formed above the trench using a thermal oxidation method;

[0023] H. Deposit N-type polysilicon and etch it back to form a control gate;

[0024] I. Boron implantation and diffusion are performed to form a P-well, while arsenic implantation and diffusion are performed directly to form an N+ source region without N+ photolithography;

[0025] J. Form a dielectric layer, which is made of USG layer and PSG layer;

[0026] K. Contact holes are formed by photolithography and etching, and P-type high-doping implantation is performed on the contact holes;

[0027] L. Front metal sputtering, photolithography and etching to form front metal;

[0028] M, passivation layer deposition, photolithography and etching, to form passivation layer lead windows;

[0029] N. The back metal evaporates, forming the back metal.

[0030] As a further aspect of the present invention, in step B, when forming the trench, the trench includes a source region trench and a terminal trench.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] This invention improves the device's reliability by adding an avalanche withstand capability enhancement structure, namely a terminal additional trench structure, between the last trench ring and the trench stop ring of a conventional shielded gate power MOSFET. This reduces the current intensity and current density of the total avalanche hole current in the source region, improves the device's resistance to avalanche breakdown, and increases the avalanche withstand capability (EAS).

[0033] This reduces reverse recovery time and increases the device's operating frequency, thereby reducing power consumption and temperature rise during operation.

[0034] This invention reduces one N+ lithography step compared to conventional shielded gate power MOSFET fabrication methods, thereby reducing chip throughput and chip manufacturing costs.

[0035] Under the same chip area conditions, the present invention reduces the on-resistance and improves the performance of the product.

[0036] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. In the drawings:

[0038] Figure 1 This is a schematic diagram of the structure of a shielded gate power MOSFET according to an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram illustrating the avalanche hole current flow direction of a shielded gate power MOSFET according to an embodiment of the present invention.

[0040] In the figure, the following labels are used: 1-N+ substrate, 2-N-epitaxial layer, 3-trench field oxide layer, 4-isolation oxide layer, 5-gate oxide layer, 6-N-type shielding gate, 7-P-well, 8-N+ source region, 9-dielectric layer, 10-backside metal, 11-N-type control gate, 12-trench, 13-front side metal, 14-terminal trench polysilicon, 15-contact hole, 3A-additional trench field oxide layer, 12A-terminal additional trench, 14A-terminal additional trench polysilicon.

[0041] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0043] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than", "less than", "exceeding" are understood to exclude the number itself, and "above", "below", "within" are understood to include the number itself.

[0044] In the description of this invention, the consecutive numbers of the method steps are for ease of review and understanding. Considering the overall technical solution of this invention and the logical relationship between each step, adjusting the implementation order of the steps will not affect the technical effect achieved by the technical solution of this invention.

[0045] In the description of this invention, unless otherwise explicitly defined, terms such as "setup" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0046] Since conventional shielded gate power MOSFETs only have the P-well region and no N+ source region (i.e., dummy structure) to increase avalanche tolerance, the absence of the N+ source region means that forward current cannot be generated. Therefore, the presence of these structures increases the chip area and chip cost; N+ lithography is required to fabricate the dummy structure.

[0047] Therefore, compared with the prior art, the present invention provides a structure and manufacturing method of a shielded gate power MOSFET that does not require N+ lithography, reducing one lithography step compared with the conventional shielded gate power MOSFET manufacturing method. Under the same chip area conditions, the present invention increases the current density of the conduction current and reduces the on-resistance due to the absence of the N+ source region, thereby improving the performance of the product.

[0048] See Figure 1 and Figure 2 As shown, one embodiment of the present invention provides a structure for a shielded gate power MOSFET, including an N+ substrate 1, an N- epitaxial layer 2, a trench field oxide layer 3, an isolation oxide layer 4 between the shielded gate and the control gate, a gate oxide layer 5, an N-type shielded gate 6, a P-well 7, an N+ source region 8, a dielectric layer 9, a back metal 10, an N-type control gate 11, a trench 12, a front metal 13, a terminal trench polysilicon 14, and a contact hole 15; the contact hole 15 contains the source metal.

[0049] See Figure 1 and Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the avalanche hole current flow direction of the shielded gate power MOSFET of the present invention. In this embodiment, when the device in the inductive circuit is turned off, the load inductor generates a reverse spike voltage applied to the drain of the device, the terminal trench ring withstands the withstand voltage, and the trench ring generates an electric field that repels avalanche holes. No avalanche holes are generated around the field oxide layer of the terminal trench ring.

[0050] In this embodiment, the electric field generated by the additional N-type polysilicon in the terminal avalanche enhancement structure, i.e., the terminal additional trench 12A, points from all sides towards the additional N-type polysilicon. Under the action of the electric field generated by the additional N-type polysilicon in the terminal additional trench 12A, avalanche holes are attracted around the field oxide layer 3A of the additional trench. In addition to being discharged through the source region, the hole current also flows to the terminal additional trench 12A. Therefore, the hole current basically flows to the terminal, mainly to the terminal additional trench 12A, in addition to being discharged through the source region.

[0051] See Figure 2 As shown in the figure, arrow A represents the total avalanche hole current flowing into the device, A1 represents the avalanche hole current discharged into the source region, and A2 represents the avalanche hole current discharged into the terminal region. Therefore, by adopting this structure, the avalanche hole current flowing into the source region is reduced, improving the device's avalanche breakdown resistance and increasing the avalanche withstand rating (EAS), thereby improving the device's reliability.

[0052] In this embodiment, the direction of the lateral electric field around the avalanche tolerance enhancement structure, i.e., the additional trench structure, is horizontal and points towards the polysilicon in the additional trench structure.

[0053] The working principle of this invention is as follows: Since the trench ring of the avalanche reinforcement structure located between the last trench ring and the trench stop ring is N-type polycrystalline silicon, its electric field direction is: around the avalanche resistance reinforcement structure, i.e. the additional trench structure, the direction of the transverse electric field is along the horizontal direction pointing towards the polycrystalline silicon in the additional trench structure.

[0054] In this embodiment, when the devices in the inductive circuit are turned off, part of the avalanche hole current flows to the source region, enters the P-well 7 and is discharged to the source region metal, while the other part of the avalanche hole current is adsorbed on the sidewall of the additional trench field oxygen and the bottom of the additional trench field oxygen under the action of the transverse electric field. This reduces the current intensity and current density of the total avalanche hole current in the source region.

[0055] In this embodiment, the avalanche enhancement structure proposed in this invention, namely the terminal additional groove 12A structure, is formed by arranging grooves 12 at equal intervals.

[0056] The avalanche enhancement structure of this invention serves the same purpose as traditional avalanche enhancement structures: reducing the current density of avalanche hole current flowing through the effective cell structure. Essentially, it moves the avalanche enhancement structure from the source region to the terminal in a traditional structure. Since it does not increase the overall length of the terminal, this invention saves the chip area occupied by traditional avalanche enhancement structures. In other words, with the same chip area, this invention can increase the forward conduction current density, reduce the on-resistance, and improve product performance.

[0057] In one embodiment of the present invention, a method for manufacturing a shielded gate power MOSFET structure is also provided, the method comprising the following steps:

[0058] A. An N- epitaxial layer 2 is formed on an N+ substrate 1;

[0059] B. Perform photolithography and etching on the N-epitaxial layer 2 to form the trench 12 (including the source trench and the terminal trench) and the terminal additional trench 12A of the avalanche tolerance enhancement structure. During this process, the terminal additional trench 12A is formed simultaneously.

[0060] C. A field oxide layer and an additional trench field oxide layer 3A are grown on the sidewall of trench 12, and the additional trench field oxide layer 3A is formed simultaneously during this process.

[0061] D. Deposit polysilicon and perform polysilicon phosphorus diffusion to form N-type polysilicon. During this process, additional polysilicon 14A is formed simultaneously in the terminal trench.

[0062] E. Polycrystalline lithography and etching form an N-type shielding gate;

[0063] F. Forming the isolation oxide layer 4: Deposit the oxide film using chemical vapor deposition, and then etch the oxide film back to the specified depth of the isolation oxide film thickness. At this time, there is no oxide layer on the sidewall of the trench 12 above the isolation oxide layer 4.

[0064] G. A gate oxide layer 5 is formed above the trench 12 by thermal oxidation;

[0065] H. Deposit N-type polysilicon and etch it back to form a control gate;

[0066] I. Boron implantation and diffusion form the P-well 7, while arsenic implantation and diffusion form the N+ source region 8 directly without N+ lithography; traditional shielded gate power MOSFETs require N+ lithography. Compared with traditional shielded gate power MOSFETs, this invention saves N+ lithography.

[0067] J. Forming a dielectric layer 9, which is made of a USG layer and a PSG layer;

[0068] K. Contact hole 15 is formed by photolithography and etching, and P-type high doping implantation is performed on contact hole 15.

[0069] L, front metal 13 is sputtered, photolithographically etched and etched to form front metal 13;

[0070] M, passivation layer deposition, photolithography and etching, to form passivation layer lead windows;

[0071] N, the back metal 10 evaporates, forming the back metal 10.

[0072] It should be noted that the terminal additional groove 12A can also be a closed series of groove rings.

[0073] In summary, this invention improves the device's avalanche breakdown resistance and avalanche withstand capability (EAS) by adding an additional terminating trench structure between the last trench ring and the trench stop ring of a conventional shielded gate power MOSFET, thereby reducing the current intensity and density of the total avalanche hole current in the source region.

[0074] At the same time, it reduces the reverse recovery time and increases the operating frequency of the device, thereby reducing the power consumption and temperature rise of the device during operation.

[0075] This invention reduces one N+ lithography step compared to conventional shielded gate power MOSFET fabrication methods, thereby reducing chip throughput and chip manufacturing costs.

[0076] Under the same chip area conditions, the present invention reduces the on-resistance and improves the performance of the product.

[0077] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A structure for a shielded gate power MOSFET, characterized in that, The structure includes an N+ substrate (1), an N- epitaxial layer (2), a trench field oxide layer (3), an isolation oxide layer (4) between the shielding gate and the control gate, a gate oxide layer (5), an N-type shielding gate (6), a P-well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), an N-type control gate (11), a trench (12), a front metal (13), a terminal trench polysilicon (14), and a contact hole (15); the contact hole (15) contains source metal; the contact hole (15) is implanted with P-type high doping; the terminal trench polysilicon (14) and the contact hole (15) are spaced apart; the number of trenches (12) is at least two; the structure of the shielding gate power MOSFET includes a terminal avalanche enhancement structure; the terminal avalanche enhancement structure is located between the last trench ring and the trench stop ring; the terminal avalanche enhancement structure is a terminal additional trench (12A); the terminal additional trench (12A) is deposited with additional N-type polysilicon; When the devices in the inductive circuit are turned off, the load inductor generates a reverse spike voltage applied to the drain of the device. The terminating trench ring withstands the withstand voltage, and the trench ring generates an electric field that repels avalanche holes. No avalanche holes are generated around the field oxide layer of the terminating trench ring. The electric field generated by the additional N-type polysilicon in the terminating avalanche enhancement structure, i.e., the terminating additional trench (12A), points from all sides towards the additional N-type polysilicon. Under the action of the electric field generated by the additional N-type polysilicon in the terminating additional trench (12A), avalanche holes are attracted to the additional N-type polysilicon. Around the field oxide layer (3A) of the trench; the hole current flows to the terminal additional trench (12A) in addition to being discharged through the source region; around the avalanche tolerance enhancement structure, i.e. the additional trench structure, the direction of the transverse electric field is horizontal and points to the polysilicon in the additional trench structure; when the device in the inductive circuit is turned off, part of the avalanche hole current flows to the source region, enters the P-well (7) and is discharged to the source region metal, and the other part of the avalanche hole current is adsorbed on the sidewall of the additional trench field oxide and the bottom of the additional trench field oxide under the action of the transverse electric field; When the devices in the inductive circuit are turned on, the electron current flowing down from the N+ source region (8) enters the region between the last trench ring and the trench (12) cutoff ring, and then disappears after recombinating with the avalanche hole current around the avalanche enhancement structure in that region.

2. The structure of the shielded gate power MOSFET according to claim 1, characterized in that, The avalanche enhancement structure, namely the terminal additional groove (12A) structure, is composed of grooves (12) arranged at equal intervals.

3. A method for manufacturing the shielded gate power MOSFET structure according to claim 1, characterized in that, The manufacturing method includes the following steps: A. An N- epitaxial layer (2) is formed on an N+ substrate (1); B. Perform trench (12) photolithography and etching on the N-epitaxial layer (2) to form trench (12) and terminal additional trench (12A) of avalanche resistance enhancement structure. During this process, the terminal additional trench (12A) is formed simultaneously. C. A field oxide layer and an additional trench field oxide layer (3A) are grown on the sidewall of the trench (12), and the additional trench field oxide layer (3A) is formed simultaneously during this process; D. Polycrystalline silicon is deposited and polycrystalline phosphorus is diffused to form N-type polycrystalline silicon. During this process, terminal additional trench polycrystalline silicon (14A) is formed simultaneously. E. Polycrystalline lithography and etching form an N-type shielding gate; F. Forming the isolation oxide layer (4): Deposit the oxide film using chemical vapor deposition, and then etch the oxide film back to the specified depth of the isolation oxide film thickness. At this time, there is no oxide layer on the sidewall of the trench (12) above the isolation oxide layer (4). G. A gate oxide layer (5) is formed above the trench (12) by thermal oxidation. H. Deposit N-type polysilicon and etch it back to form a control gate; I. Boron implantation and diffusion are performed to form a P-well (7), and arsenic implantation and diffusion are performed directly without N+ photolithography to form an N+ source region (8); J. Form a dielectric layer (9), which is made of USG layer and PSG layer; K. Contact holes (15) are formed by photolithography and etching, and P-type high doping implantation is performed on the contact holes (15); L, front metal (13) is sputtered, photolithographically and etched to form front metal (13); M, passivation layer deposition, photolithography and etching, to form passivation layer lead windows; N, the back metal (10) evaporates to form the back metal (10); The terminal trench polysilicon (14) and the contact hole (15) are spaced apart.

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