Detection panel, detection device and image processing method

Abstract

The invention provides a detection panel, a detection device and an image processing method, and relates to the field of photoelectric sensing. Each pixel comprises a photosensitive device and a thin film transistor; a plurality of pixel arrays are arranged to form a pixel array; the pixel array comprises a plurality of areas; the at least one target area comprises a first pixel and a second pixel; the thin film transistor in the first pixel is a first transistor; in the first direction, the overlapping width of the grid electrode of the first transistor and the first pole is a first width, and the overlapping width of the grid electrode of the first transistor and the second pole is a second width; the first width is greater than the second width; the thin film transistor in the second pixel is a second transistor; in the second direction, the overlapping width of the grid electrode of the second transistor and the first electrode is a third width, and the overlapping width of the grid electrode of the first transistor and the second electrode is a fourth width; the third width is smaller than the fourth width; the first direction is opposite to the second direction. Fixed mode noise is reduced, and imaging quality is improved.

Description

A detection panel, a detection device, and an image processing method Technical Field

[0001] This application relates to the field of photoelectric sensing technology, and in particular to a detection panel, a detection device, and an image processing method. Background Technology

[0002] Flat panel detectors are widely used in medical image acquisition, industrial non-destructive testing, scientific research and other fields. Flat panel detectors typically use complementary metal-oxide-semiconductor (CMOS) detector panels or detector panels manufactured using thin-film transistor (TFT) technology.

[0003] Compared to CMOS probe panels, TFT probe panels have significant advantages in manufacturing cost and large-area feasibility. However, due to differences in process precision, the imaging quality and noise level of TFT probe panels are significantly inferior to those of CMOS probe panels. During the manufacturing of TFT probe panels, alignment deviations between film layers are unavoidable due to fluctuations in the exposure process and alignment accuracy.

[0004] In related technologies, ideally, the overlap area between the gate (G), source (S), and drain (D) electrodes in a TFT should be the same as that between the gate (G) and drain (GD). However, unequal overlap areas indicate alignment misalignment, such as left or right offset. Right offset results in higher dark-state grayscale values, while left offset results in lower dark-state grayscale values. This causes differences in dark-state grayscale values ​​between different areas of the panel, leading to fixed-mode noise and affecting the imaging quality of the detection panel.

[0005] Summary of the Invention

[0006] This application provides a detection panel, a detection device, and an image processing method, which can solve the problem that the fixed pattern noise caused by the alignment deviation between the film layers of the existing TFT detection panel affects the imaging quality of the detection panel.

[0007] In a first aspect, this application provides a detection panel, the detection panel comprising: a plurality of pixels; each pixel comprising a photosensitive device and a thin-film transistor connected to the photosensitive device;

[0008] The plurality of pixel arrays are arranged to form a pixel array; the pixel array includes multiple regions; among the plurality of regions, at least one target region includes a first pixel and a second pixel;

[0009] The thin-film transistor in the first pixel is a first transistor; in a first direction, the overlap width between the gate and the first electrode of the first transistor is a first width; in the first direction, the overlap width between the gate and the second electrode of the first transistor is a second width; the first width is greater than the second width;

[0010] The thin-film transistor in the second pixel is a second transistor; in the second direction, the overlap width between the gate of the second transistor and the first electrode is a third width; in the second direction, the overlap width between the gate of the first transistor and the second electrode is a fourth width; the third width is smaller than the fourth width.

[0011] The first direction is the direction from the first electrode of the first transistor to the second electrode; the second direction is the direction from the first electrode of the first transistor to the second electrode; the first direction is opposite to the second direction.

[0012] Optionally, in the first direction, the alignment offset of the gate of the first transistor between the first electrode and the second electrode is a first offset; the first offset is half the difference between the first width and the second width;

[0013] In the second direction, the alignment offset of the gate of the second transistor between the first and second electrodes is the second offset; the second offset is half the difference between the fourth width and the third width;

[0014] The first offset is approximately equal to the second offset.

[0015] Optionally, the target area includes multiple pixel rows; the multiple pixel rows include a first pixel row and a second pixel row;

[0016] The pixels in the first pixel row are the first pixels; the pixels in the second pixel row are the second pixels.

[0017] Optionally, the pixel array includes a plurality of the target regions;

[0018] The number of targets corresponding to multiple target regions is equal; the number of targets is the total number of pixel rows in the target region.

[0019] Optionally, the target region includes a plurality of first pixel rows and a plurality of second pixel rows;

[0020] Multiple rows of the first pixel are continuously distributed in the column direction to form a first sub-array; the first sub-array is disposed between multiple rows of the second pixel.

[0021] Optionally, in the column direction, the number of second pixel rows located on both sides of the first pixel row is equal, or the difference in the number of second pixel rows located on both sides of the first pixel row is 1.

[0022] Optionally, the detection panel further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns;

[0023] In the first pixel row, the first electrode of the first transistor in the target first pixel is connected to the nth read line; wherein, the target first pixel is the first pixel located in the (n+1)th pixel column; n is greater than 0 and n is less than N;

[0024] In the second pixel row, the first electrode of the second transistor in the target second pixel is connected to the m-th read line; wherein, the target second pixel is the second pixel located in the m-th pixel column; m is greater than 0 and m is less than or equal to N.

[0025] Optionally, the target region includes at least one special pixel pair; the special pixel pair includes a first pixel and a second pixel adjacent to the first pixel;

[0026] The first pixel and the second pixel in the special pixel pair are located in the same pixel row.

[0027] Optionally, the pixel array includes multiple target regions in the row direction.

[0028] And / or, the pixel array includes a plurality of the target regions in the column direction.

[0029] Optionally, in the row direction, the number of target pixels located on both sides of the special pixel pair is equal, or the difference in the number of target pixels located on both sides of the special pixel pair is 1;

[0030] The target pixel is the second pixel in the pixel row where the special pixel pair is located that is not paired with the first pixel.

[0031] Optionally, the detection panel further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns;

[0032] The first electrode of the first transistor in the target first pixel is connected to the i-th read line; wherein, the target first pixel is the first pixel located in the i-th pixel column;

[0033] The first electrode of the second transistor in the target second pixel is connected to the i-th read line; wherein the target second pixel is the second pixel paired with the target first pixel, and the target second pixel is located in the (i+1)-th pixel column; wherein i is greater than or equal to 1 and i is less than N.

[0034] Secondly, this application provides a detection device, which includes a detection panel as described in the first aspect.

[0035] Thirdly, this application provides an image processing method, the method comprising:

[0036] Read the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel;

[0037] Based on the first detection data and the second detection data, the standard dark grayscale value of the detection panel is determined.

[0038] Optionally, reading the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel includes:

[0039] The first detection data and the second detection data are read from the read lines connected to the first transistor and the second transistor, respectively.

[0040] The step of determining the standard dark-state grayscale value of the detection panel based on the first detection data and the second detection data includes:

[0041] The first grayscale value corresponding to the first pixel is obtained based on the first detection data, and the second grayscale value corresponding to the second pixel is obtained based on the second detection data;

[0042] The standard dark grayscale value is determined based on the first grayscale value and the second grayscale value.

[0043] Optionally, the method further includes:

[0044] Obtain the dark grayscale value corresponding to the neighboring pixels of the edge pixel; wherein, the edge pixel is the first pixel located in the first pixel column of the first pixel row;

[0045] The third gray level value corresponding to the edge pixel is determined based on the dark gray level value corresponding to the neighboring pixel;

[0046] Determining the standard dark grayscale value based on the first grayscale value and the second grayscale value includes:

[0047] The standard dark grayscale value is determined based on the first grayscale value, the second grayscale value, and the third grayscale value.

[0048] Optionally, reading the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel includes:

[0049] Target detection data is obtained by simultaneously reading the first detection data and the second detection data from the read line that is connected to the first transistor and the second transistor.

[0050] The step of determining the standard dark-state grayscale value of the detection panel based on the first detection data and the second detection data includes:

[0051] The target grayscale value at a specific pixel pair is determined based on the target detection data, and the standard dark grayscale value is determined based on the target grayscale value.

[0052] The detection panel, detection device, and image processing method provided in this application have at least the following advantages:

[0053] The detection panel includes multiple pixels; each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device; multiple pixels are arranged in an array to form a pixel array; the pixel array includes multiple regions; among the multiple regions, at least one target region includes a first pixel and a second pixel. Since the thin-film transistor in the first pixel is a first transistor; in a first direction, the overlapping area of ​​the gate and the first electrode of the first transistor is a first area; in the first direction, the overlapping area of ​​the gate and the second electrode of the first transistor is a second area; the first area is larger than the second area; the first direction is the direction from the first electrode of the first transistor to the second electrode. Thus, the first transistor is shifted in alignment towards the first direction. Since the thin-film transistor in the second pixel is a second transistor; in a second direction, the overlapping area of ​​the gate and the first electrode of the second transistor is a third area; in the second direction, the overlapping area of ​​the gate and the second electrode of the first transistor is a fourth area; the third area is smaller than the fourth area; the second direction is the direction from the first electrode of the first transistor to the second electrode. Thus, the second transistor is shifted in alignment towards the opposite direction of the second direction. Since the first direction is opposite to the second direction, the dark grayscale value corresponding to one thin film transistor increases, while the dark grayscale value corresponding to the other thin film transistor decreases. In other words, the effect of the alignment offset of the first and second transistors on the dark grayscale value can be partially offset, thereby reducing the dark grayscale difference of the detection panel caused by the alignment offset of the thin film transistor process. This can reduce the fixed mode noise of the detection panel and improve the imaging quality.

[0054] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 is a pixel circuit structure diagram of an amorphous silicon TFT probe panel in the related technology;

[0057] Figure 2 is a pixel planar structure diagram of an amorphous silicon TFT probe panel in the related technology;

[0058] Figure 3 is a schematic diagram of TFT process alignment offset in related technologies;

[0059] Figure 4 is a schematic diagram of the dark grayscale corresponding to the alignment offset in the TFT process in the related technology.

[0060] Figure 5 is a schematic diagram of the structure of a detection panel provided in an embodiment of this application;

[0061] Figure 6 is a schematic diagram of a TFT capacitor provided in an embodiment of this application;

[0062] Figure 7 is a circuit structure diagram of a target area in a detection panel provided in an embodiment of this application;

[0063] Figure 8 is a planar structural diagram of a target area in a detection panel provided in an embodiment of this application;

[0064] Figure 9 is an enlarged view of the pixel structure in the target region shown in Figure 8;

[0065] Figure 10 is a schematic diagram of a detection device provided in an embodiment of this application;

[0066] Figure 11 is a circuit structure diagram of a target area in a detection panel provided in an embodiment of this application;

[0067] Figure 12 is a planar structural diagram of the target area in another detection panel provided in an embodiment of this application;

[0068] Figure 13 is an enlarged view of the pixel structure in the target region shown in Figure 12;

[0069] Figure 14 is a schematic diagram of another detection device provided in an embodiment of this application;

[0070] Figure 15 is a flowchart of the steps of an image processing method provided in an embodiment of this application. Specific Implementation

[0071] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0072] In the field of medical image acquisition, X-ray flat panel detectors are widely used. In recent years, there has been a strong demand for high-precision, low-damage diagnostics. Achieving high-precision, low-damage X-ray image acquisition requires extremely low-dose, single-frame imaging, meaning the detector panel needs to be able to distinguish useful diagnostic information within a limited grayscale range. This places higher demands on the noise level of the detector panel. Furthermore, a reduction in radiation dose means a decrease in image signal strength. Therefore, to achieve the requirement of "obtaining high-quality images with minimal radiation damage," it is necessary to reduce image noise to obtain dynamic images with a higher signal-to-noise ratio (SNR) and better quality.

[0073] Noise in flat panel detectors is categorized into fixed pattern noise and transient noise. Fixed pattern noise is time-independent and arises from pixel inconsistencies across different detector panels. For the same flat panel detector, fixed pattern noise is spatially related but varies between different detectors. Fixed pattern noise typically originates from two sources: offset due to dark signal non-uniformity (DSNU) and sensitivity differences caused by photon response non-uniformity (PRNU).

[0074] Figure 1 is a pixel circuit structure diagram of an amorphous silicon (a-Si) TFT detector panel in related technologies. As shown in Figure 1, the pixel includes a photodiode and a TFT connected in series. The detector panel includes scan lines / gate lines, read lines / drain lines, and bias voltage lines. The anode of the photodiode is connected to the bias voltage line, which provides a negative bias voltage to the photodiode, enabling it to operate in a reverse-biased state where photoelectric conversion can occur. When the photodiode is illuminated, it continuously undergoes photoelectric conversion, accumulating photogenerated carriers through the capacitance formed between the upper and lower plates of the photodiode.

[0075] Figure 2 is a pixel planar structure diagram of an a-Si TFT detector panel in related technologies. As shown in Figure 2, the gate of the TFT is connected to the scan line, the drain is connected to the read line, and the source is connected to the cathode of the photodiode. The TFT can be turned on or off by the signal transmitted through the scan line. When the TFT is on, the photogenerated carriers accumulated in the photodiode are detected and read through the read line. When the TFT is off, the photodiode accumulates photogenerated carriers, waiting to be released through the read line when the TFT is turned on. The TFT plays the role of controlling the switching of the entire pixel.

[0076] Figure 3 is a schematic diagram of TFT process alignment offset in related technologies. As shown in Figure 3(a), under ideal normal TFT alignment, the GS overlap area is the same as the GD overlap area. However, due to the micrometer-level precision of TFT processes, alignment deviations as shown in Figures 3(b) and 3(c) are unavoidable in some areas of the probe panel. Specifically, when the GS overlap is greater than the GD overlap, as shown in Figure 3(b), the TFT alignment is right-biased; when the GS overlap is less than the GD overlap, as shown in Figure 3(c), the alignment is left-biased. Figure 4 is a schematic diagram of the relationship between TFT process alignment offset and dark grayscale value in related technologies. As shown in Figure 4, when the TFT has right-biased alignment, the dark grayscale value is higher than the normal value; when the TFT has left-biased alignment, the dark grayscale value is lower than the normal value.

[0077] For smaller TFT probe panels, due to the smaller length and width span of the exposure field in the photolithography process, alignment deviations are usually limited to either left or right, and the degree of deviation is relatively minor. However, for larger TFT probe panels, the length and width span of the corresponding exposure field is larger. If there is poor control over Total Pitch during the manufacturing process, both left and right alignment deviations may occur simultaneously within a single probe panel, and the degree of deviation can be significant. Total Pitch refers to the position and shape of the marking panel pattern on the glass, and it is related to the amount of exposure deviation.

[0078] Figure 5 is a schematic diagram of the structure of a detection panel 10 provided in an embodiment of this application. As shown in Figure 5, the detection panel 10 includes: a plurality of pixels; each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device.

[0079] Multiple pixel arrays are arranged to form a pixel array; the pixel array includes multiple regions; among the multiple regions, at least one target region includes a first pixel 101 and a second pixel 102;

[0080] The thin-film transistor in the first pixel 101 is a first transistor; in a first direction, the overlap width between the gate and the first electrode of the first transistor is a first width; in a first direction, the overlap width between the gate and the second electrode of the first transistor is a second width; the first width is greater than the second width.

[0081] The thin-film transistor in the second pixel 102 is a second transistor; in the second direction, the overlap width between the gate of the second transistor and the first electrode is a third width; in the second direction, the overlap width between the gate of the first transistor and the second electrode is a fourth width; the third width is less than the fourth width.

[0082] The first direction is the direction from the first terminal of the first transistor to the second terminal; the second direction is the direction from the first terminal of the first transistor to the second terminal; the first direction is opposite to the second direction.

[0083] In this embodiment, the detection panel 10 can be applied to photoelectric detection in fields such as medical image acquisition, industrial non-destructive testing, and scientific research, for example, as an X-ray flat panel detector. Specifically, the detection panel 10 can be an X-ray detection panel 10 based on a-Si TFT technology, used for X-ray image acquisition. Multiple pixel arrays are arranged in the detection panel 10 to form multiple pixel rows and columns, constituting a pixel array. Each pixel includes a pixel circuit consisting of a photosensitive device and a thin-film transistor connected in series. The photosensitive device can be a device with photoelectric conversion capabilities, capable of converting light signals into electrical signals when illuminated. For example, the pixel circuit shown in Figure 1 includes a photodiode and a TFT connected in series. The thin-film transistor can be an N-type TFT or a P-type TFT. This is merely an example, and this embodiment does not limit the scope of the application.

[0084] In this embodiment, the pixel array of the detection panel 10 is divided into multiple regions, each region including multiple pixels. Specifically, among the multiple regions, there is at least one target region, which includes a first pixel 101 and a second pixel 102. The alignment offset directions of the thin-film transistors in the first pixel 101 and the second pixel 102 are opposite. For example, if the thin-film transistor in the first pixel 101 is left-biased, then the alignment offset direction of the thin-film transistor in the second pixel 102 is right-biased.

[0085] In this embodiment, the first electrode of the thin-film transistor can be either the source or the drain, and correspondingly, the second electrode can be either the drain or the source. This embodiment does not impose any limitations on this. The direction from the first electrode of the first transistor to the second electrode is the first direction. Wherein, if the first electrode of the first transistor is the source, then the second electrode is the drain, and the first direction is the direction from the source to the drain. As shown in Figure 1, the first direction can be parallel to the scan line and point from the source to the drain of the TFT. Similarly, the direction from the first electrode of the second transistor to the second electrode is the second direction, which can be the direction from the source to the drain, and will not be elaborated further here.

[0086] In this embodiment, the first direction and the second direction are opposite, that is, the directions from the first electrode to the second electrode in the two thin-film transistors are opposite. The positions of the gate and source in the first transistor and the second transistor are different. If the source is on the left side of the gate and the drain is on the right side of the gate in the first transistor, then the source is on the right side of the gate and the drain is on the left side of the gate in the second transistor. The positions of the source / drain in the first transistor and the second transistor are symmetrical.

[0087] In this embodiment, the first transistor is offset in a first direction. Specifically, in the first transistor, there is a first overlapping region between the gate and the first electrode, and a second overlapping region between the gate and the second electrode. The areas of the first overlapping region and the second overlapping region are not equal, meaning the first transistor is offset. The overlap width between the gate and the first electrode of the first transistor, i.e., the first width, can be the average width of the first overlapping region in the first direction. For example, if the first overlapping region has two opposite sides in the first direction, the first width can be the average width between these two opposite sides. Similarly, the second width can be the average width of the gate and the second electrode of the first transistor in the first direction. Wherein, in the first direction, i.e., the direction from the first electrode to the second electrode, the first width is greater than the second width, that is, the width of the first overlapping region is greater than the width of the second overlapping region, and the offset direction of the first transistor is the first direction.

[0088] For example, the first transistor is a TFT as shown in Figure 3(b), with the first electrode being the source and the second electrode being the drain. There is a first overlapping region between the gate and the source, namely the GS overlapping region, and the overlap width between the gate and the source, i.e., the first width, is L + ΔL′. There is a second overlapping region between the gate and the drain, namely the GD overlapping region, and the overlap width between the gate and the drain, i.e., the second width, is L - ΔL′. Therefore, in the direction from the source to the drain, i.e., the first direction, the width of the GS overlapping region is greater than the width of the GD overlapping region, resulting in a rightward alignment of the TFT. This is merely an example, and the embodiments of this application do not impose limitations on this.

[0089] In this embodiment, the second transistor is offset in the opposite direction to the second direction. Specifically, in the second transistor, there is a third overlapping region between the gate and the first electrode, and a fourth overlapping region between the gate and the second electrode. The areas of the third overlapping region and the fourth overlapping region are not equal, meaning the second transistor is offset. Specifically, in the second direction (the direction from the first electrode to the second electrode), the third width is smaller than the fourth width, meaning the width of the third overlapping region is smaller than the width of the fourth overlapping region. The offset direction of the first transistor is the opposite direction to the second direction.

[0090] For example, the second transistor is a TFT as shown in Figure 3(c), with the first electrode being the source and the second electrode being the drain. The width of the GS overlapping region in the direction from the source to the drain is smaller than the width of the GD overlapping region, and the TFT is shifted to the left. This is merely an example, and the embodiments of this application do not impose any limitations on it.

[0091] In this embodiment, the detection panel 10 includes multiple pixels; each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device; the multiple pixel arrays are arranged to form a pixel array; the pixel array includes multiple regions; among the multiple regions, at least one target region includes a first pixel 101 and a second pixel 102. Since the thin-film transistor in the first pixel 101 is a first transistor; in a first direction, the overlapping area of ​​the gate and the first electrode of the first transistor is a first area; in the first direction, the overlapping area of ​​the gate and the second electrode of the first transistor is a second area; the first area is larger than the second area; the first direction is the direction from the first electrode of the first transistor to the second electrode. Thus, the first transistor is shifted in the first direction. Since the thin-film transistor in the second pixel 102 is a second transistor; in a second direction, the overlapping area of ​​the gate and the first electrode of the second transistor is a third area; in the second direction, the overlapping area of ​​the gate and the second electrode of the first transistor is a fourth area; the third area is smaller than the fourth area; the second direction is the direction from the first electrode of the first transistor to the second electrode. Thus, the second transistor is shifted in the opposite direction of the second direction. Since the first direction is opposite to the second direction, the dark gray level value corresponding to one thin film transistor increases, while the dark gray level value corresponding to the other thin film transistor decreases. In other words, the effect of the alignment offset of the first transistor and the second transistor on the dark gray level value can be partially offset, thereby reducing the dark gray level difference of the detection panel 10 caused by the process alignment offset of the thin film transistor. This can reduce the fixed mode noise of the detection panel 10 and improve the imaging quality.

[0092] Optionally, in the first direction, the alignment offset of the gate of the first transistor between the first electrode and the second electrode is a first offset; the first offset is half the difference between the first width and the second width;

[0093] In the second direction, the alignment offset of the gate of the second transistor between the first and second electrodes is the second offset; the second offset is half the difference between the fourth width and the third width.

[0094] The first offset is approximately equal to the second offset.

[0095] In some embodiments, the alignment offset refers to the distance the thin-film transistor is offset relative to normal alignment. It can be defined as the increase in width of the first overlapping region or the decrease in width of the second overlapping region relative to the normal alignment overlap region. Specifically, the first offset can be obtained by subtracting the first width corresponding to the first overlapping region from the second width corresponding to the second overlapping region, and then using half of the difference as the first offset. The second offset for the second transistor is obtained similarly; the second offset can be obtained by subtracting the fourth width corresponding to the fourth overlapping region from the third width corresponding to the third overlapping region, and then using half of the difference as the second offset.

[0096] In some embodiments, the first offset and the second offset are approximately equal, so the influence of the first transistor and the second transistor on the dark grayscale value is also approximately equal. Here, "approximately equal" means that the difference between the first offset and the second offset does not exceed a preset fluctuation range. For example, in TFT manufacturing, the recognition accuracy for line width and line spacing is 0.1 mm, which is typically 10% of the alignment offset of the thin-film transistor. Therefore, the preset fluctuation range can be 10%, meaning that the difference between the first offset and the second offset is less than 10% of the first offset, or less than 10% of the second offset, in which case the first offset and the second offset can be considered approximately equal. Furthermore, since the first direction is opposite to the second direction, the dark grayscale value corresponding to one thin-film transistor increases, while the dark grayscale value corresponding to the other thin-film transistor decreases, and the degree of change in the dark grayscale value is approximately equal. Therefore, the influence of the alignment offset of the first transistor and the second transistor on the dark grayscale value can cancel each other out, thereby eliminating the dark grayscale difference, improving the fixed-mode noise of the detection panel 10, and improving the imaging quality.

[0097] In this embodiment of the application, the quantitative effect of TFT process alignment offset on dark gray level can be referred to the following formulas (1) to (4):

[0098] Where Q represents the charge value accumulated by the feedback capacitor of the integrator in the readout IC (ROIC) corresponding to the detection panel 10, that is, the value at which the pixel converts the light signal into an electrical signal. C F This represents the feedback capacitor value of the integrator. V ref This represents the integrator reference voltage of the readout circuit. (V) AFE.min This indicates the minimum output voltage of the integrator.

[0099] Where, ΔV g This represents the difference between the TFT's turn-on voltage and turn-off voltage, for example, V. GH V is the TFT turn-on voltage.GL ΔV is the TFT turn-off voltage. g =V GH -V GL I PIN I represents the leakage current of the diode. TFT.off This represents the leakage current of the TFT. Misalignment of the gate, source, and drain film layers in the TFT does not affect I. PIN and I TFT.off It has an impact.

[0100] As shown in Figure 6, C gs.off This represents the gate-source capacitance when the TFT is off. (C) gs.on and C gd.on These represent the gate-source capacitance and gate-drain capacitance when the TFT is turned on, respectively. C gdx This refers to the overlapping capacitance formed by the perpendicular intersection of scan lines and read lines. In a TFT, misalignment of the gate, source, and drain film layers does not affect C. gdx It has an impact.

[0101] Among them, C gs.off C gs.on and C gd.on The calculation formulas are shown in formulas (5) to (6):

[0102] Where ε0 represents the vacuum permittivity, ε gi+si ε represents the dielectric constant of the gate insulating layer and the active layer as a whole. gi t represents the dielectric constant of the gate insulating layer. gi t represents the thickness of the gate insulation layer. si The values ​​W, W′, L, and L′ represent the active layer thickness. As shown in Figure 3, W represents the width of the GS / GD overlap region of the TFT in the direction perpendicular to the source-drain connection; W′ represents the shortest distance between the edge of the GS / GD overlap region and the edge of the gate region in the direction perpendicular to the source-drain connection; L represents the shortest distance between the GS overlap region and the GD overlap region in the direction parallel to the source-drain connection; and L′ represents the width of the GS / GD overlap region in the direction parallel to the source-drain connection.

[0103] C gs.off C gs.on and C gd.on Substituting into formula (4), the result is shown in formula (7) below:

[0104] When the TFT is aligned to the right, and the offset relative to the normal alignment of the TFT as shown in Figure 3(a) is ΔL, C gs.off C gs.on and C gd.onAs shown in the following formulas (8) to (10):

[0105] Among them, C gs.on +C gd.on Overall, it remains unchanged and is still... Therefore, it can be concluded that the TFT alignment shift is only affected by C. gs.off It affects the grayscale value of the dark state.

[0106] For example, when W is 12 micrometers (μm) and L′ is 2 μm, the dark grayscale value of a properly aligned TFT is approximately 2900 LSB. If the alignment is shifted to the left with ΔL of 0.5 μm, the dark grayscale value is approximately 2700 LSB. If the alignment is shifted to the right with ΔL of 0.5 μm, the dark grayscale value is approximately 3100 LSB. Here, LSB represents the least significant bit. Therefore, even a small offset can significantly affect the dark grayscale value. In practice, the alignment deviation of a TFT is typically ±0.5 to 1 μm, which can easily lead to differences in dark grayscale values ​​in different areas of the probe panel 10.

[0107] In this embodiment, based on the principle of dark grayscale values ​​of the detection panel 10, and by analyzing the generation mechanism of fixed pattern noise, a detection panel 10 array arrangement is proposed. By dividing the pixel array of the detection panel 10 into multiple regions, and setting two types of pixels, namely a first pixel 101 and a second pixel 102, in at least one target region of the multiple regions, the dark grayscale differences in different regions of the detection panel 10 are eliminated, the fixed pattern noise caused by the inconsistency of dark signals is improved, and the imaging quality of the detection panel 10 is improved.

[0108] In this embodiment, the first pixel 101 and the second pixel 102 can be located in different pixel rows in the target area, or they can be located in the same pixel row. The number of first pixels 101 can be one or more, and the number of second pixels 102 can also be one or more. For example, a first pixel row in the target area may include one or more first pixels 101, and all pixels other than the first pixels 101 are second pixels 102. First pixels 101 and second pixels 102 located in adjacent pixel columns can have their detection data read by two separate read lines, or they can have their detection data read by the same read line. For example, first pixels 101 located in a first pixel row and second pixels 102 located in a second pixel row can have their detection data read by two separate read lines, while first pixels 101 and second pixels 102 in a special pixel pair can have their detection data read by the same read line.

[0109] In some embodiments, the detection data can be processed using image processing algorithms to obtain the standard dark-state grayscale value corresponding to the detection panel 10, ultimately resulting in an image with lower noise and more uniform and smooth grayscale. The method for obtaining the standard dark-state grayscale value can be referred to the relevant descriptions in the image processing method embodiments. This is merely an illustrative example, and the embodiments of this application do not impose limitations on it.

[0110] Optionally, the target area includes multiple pixel rows; the multiple pixel rows include a first pixel row and a second pixel row;

[0111] The pixel in the first pixel row is the first pixel 101; the pixel in the second pixel row is the second pixel 102.

[0112] In some embodiments, the pixel array can be divided into regions according to pixel rows, and the target region includes multiple pixel rows. At least one first pixel row is provided among the multiple pixel rows, and all pixels in the first pixel row are first pixels 101. The other pixel rows besides the first pixel row can all be second pixel rows, and all pixels in the second pixel rows are second pixels 102. The first pixel row can include multiple pixel rows continuously distributed in the target region, or the first pixel row can be interspersed with the second pixel row; this embodiment does not limit this.

[0113] In the first pixel row, the first transistors of the first pixel 101 are arranged in the same way; specifically, the first transistors point to the second transistors in the same direction. Similarly, in the second pixel row, the second transistors of the second pixel 102 are arranged in the same way; specifically, the first transistors point to the second transistors in the same direction. Since the first and second directions are opposite, the transistor arrangement of the entire first pixel row is opposite to that of the entire second pixel row.

[0114] It should be noted that the pixel arrangement in the current detector panel 10 is consistent, and the direction of the source electrode pointing to the drain electrode in the TFT of the pixel array is the same. Under the same arrangement, within a certain area of ​​the detector panel 10, the alignment offset direction of the TFT in all pixels is consistent.

[0115] Figure 7 is a circuit structure diagram of a target area in a detection panel 10 according to an embodiment of this application. As shown in Figure 7, the target area includes a first pixel row and multiple second pixel rows. In the first pixel row, the first direction is the direction from the source (S) of the first transistor to the drain (D), and in the second pixel row, the second direction is the direction from the source (S) of the second transistor to the drain (D). Referring to Figure 7, the first and second directions are opposite, and the first pixel row can be considered as obtained by mirroring the second pixel row about the central axis of the column direction of the target area.

[0116] Figure 8 is a planar structural diagram of a target area in a detection panel 10 provided in an embodiment of this application. As shown in Figure 8, in the first pixel row, the overlap width between the gate and source of the first transistor is greater than the overlap width between the gate and drain. The first transistor is offset in the direction from the source to the drain, that is, it is offset in the first direction. In the second pixel row, the overlap width between the gate and source of the second transistor is less than the overlap width between the gate and the drain. The second transistor is offset in the direction from the drain to the source, that is, it is offset in the opposite direction of the second direction.

[0117] Figure 9 is an enlarged view of the pixel structure within the dashed box in the target area shown in Figure 8. As shown in Figure 9, the alignment offset of the gate of the first transistor in the first pixel 101 between the source and drain is the first offset, and the alignment offset of the gate of the second transistor in the second pixel 102 between the source and drain is the second offset. The first offset and the second offset are approximately equal. It should be noted that, referring to Figure 9, both the first transistor and the second transistor are offset to the left of Figure 9. Therefore, from the overall perspective of the detection panel 10, both the first transistor and the second transistor have a left-biased alignment problem.

[0118] According to the relevant descriptions in formulas (8) to (10), C for each pixel gs.on +C gd.on Overall, it remains unchanged and is still... The alignment offset of the TFT is only affected by C gs.off The dark grayscale value is affected. In the case of left offset of TFT alignment, if the alignment offset is ΔL, the following formula (11) applies to the first pixel 101 and the following formula (12) applies to the second pixel 102. According to formulas (11) and (12), formula (7) can be transformed into formula (13), and then formula (14) can be obtained according to formula (13).

[0119] visible, The expression completely eliminates the influence of the TFT alignment offset ΔL, and then, referring to formula (1), C gs.off1 and C gs.off2 Taking the average value can also eliminate the influence of the alignment offset ΔL on the dark grayscale value. Therefore, the average dark grayscale value of the first pixel 101 and the second pixel 102 can be used as the standard dark grayscale value when the TFT is properly aligned.

[0120] In some embodiments, the dark grayscale values ​​corresponding to multiple first pixels 101 or all first pixels 101 can be averaged or medianized to obtain a dark grayscale mean. Similarly, the dark grayscale values ​​corresponding to multiple second pixels 102 or all second pixels 102 can be averaged or medianized to obtain a dark grayscale mean. Then, the two dark grayscale means are averaged, and the result is used as the standard dark grayscale value.

[0121] For example, the mean or median of the dark grayscale values ​​corresponding to multiple first pixels 101 in the first pixel row can be calculated, or the mean dark grayscale value of the entire row of first pixels 101 can be calculated. The same applies to the second pixel row, which will not be elaborated here. The more first pixels 101 and second pixels 102 involved in the calculation, the more accurate the standard dark grayscale mean value is obtained, but the image processing computation will increase. Conversely, the fewer data involved in the calculation, the less image processing computation is required, and the faster the image processing speed. An appropriate method for calculating the standard dark grayscale value can be selected according to the actual application needs. This is merely an illustrative example, and the embodiments of this application do not impose limitations on this.

[0122] Optionally, the pixel array includes multiple target regions;

[0123] The number of targets corresponding to multiple target regions is equal; the number of targets is the total number of pixel rows in the target region.

[0124] In some embodiments, the multiple regions divided by the pixel array may include multiple target regions, each target region having a first pixel 101 and a second pixel 102. For example, each target region includes a first pixel row and a second pixel row. The total number of pixel rows in the multiple target regions is equal. However, the number of first pixel rows in different target regions may be equal or unequal, and the arrangement of the first pixel rows and second pixel rows in different target regions may be the same or different; this application does not impose any limitations on this.

[0125] In some embodiments, the total number of pixel rows corresponding to other regions in multiple regions can be equal to the target number, that is, equal to the total number of pixel rows in the target region. In other words, the pixel array is evenly divided into regions to obtain multiple target regions and other regions.

[0126] In some embodiments, the multiple regions divided into the pixel array can all be target regions, meaning that each region is equipped with a first pixel 101 and a second pixel 102. For example, each region can have a first pixel row and a second pixel row, meaning that the pixel array is divided into target regions every few rows, and a first pixel row is set in each target region. This uniform division of the pixel array helps reduce image processing time.

[0127] Optionally, the target area includes multiple first pixel rows and multiple second pixel rows;

[0128] Multiple first pixel rows are continuously distributed in the column direction to form a first subarray; the first subarray is set between multiple second pixel rows.

[0129] In this embodiment, the plurality of first pixel rows include a plurality of pixel rows continuously distributed in the target region, and a first sub-array formed by the plurality of continuously distributed first pixel rows is located between a plurality of second pixel rows. Specifically, the number of second pixel rows located on one side of the first sub-array in the column direction can be one or more. In this way, the first pixels 101 in the plurality of first pixel rows are concentrated in several rows continuously distributed in the target region, so that the first pixels 101 are structurally similar and the dark grayscale values ​​corresponding to the first pixels 101 are not significantly different. For example, a plurality of second pixel rows are arranged above the first sub-array in the column direction, and a plurality of second pixel rows are arranged below the second sub-array. This is only an example, and this embodiment does not limit the scope of the invention.

[0130] It should be noted that the closer the pixels on the detection panel 10 are, the smaller the structural differences between them. For example, two adjacent pixels located in the same pixel row / column have smaller differences. During image processing, the image of the detection panel 10 can be divided into several regions of fixed length and width, and the center pixel of the region can be selected as the reference because the total distance from the center pixel to other pixels is the smallest. If a pixel in one corner of the region is selected as the reference, its difference from a pixel in another corner may be larger.

[0131] Optionally, in the column direction, the number of second pixel rows located on both sides of the first pixel row is equal, or the difference in the number of second pixel rows located on both sides of the first pixel row is 1.

[0132] In some embodiments, the first pixel 101 in the target area can be set at the center of the target area, for example, the first pixel row is set in the middle of multiple second pixel rows in the target area. In this way, the differences between the first pixels 101 located at the center of the target area are small, and the sum of the distances between each first pixel 101 and other second pixels 102 is minimized. Based on this, the standard dark grayscale value calculated by averaging is more accurate.

[0133] In some embodiments, if the number of second pixel rows in the target region is even, the number of second pixel rows on both sides of the first subarray in the column direction is equal. If the number of second pixel rows is odd, the number of second pixel rows on both sides of the first subarray in the column direction is unequal, and the difference between the two sides is 1. Specifically, for each first pixel row in the first subarray, regardless of its position within the first subarray, the number of second pixel rows on both sides of that first pixel row in the column direction is approximately equal.

[0134] Optionally, the detection panel 10 further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns;

[0135] In the first pixel row, the first electrode of the first transistor in the target first pixel 101 is connected to the nth read line; wherein, the target first pixel 101 is the first pixel 101 located in the (n+1)th pixel column; n is greater than 0 and n is less than N;

[0136] In the second pixel row, the first electrode of the second transistor in the target second pixel 102 is connected to the m-th read line; wherein, the target second pixel 102 is the second pixel 102 located in the m-th pixel column; m is greater than 0 and m is less than or equal to N.

[0137] In some embodiments, the pixel array of the detection panel 10 includes N pixel columns, each pixel column corresponding to a readout line, i.e., the detection panel 10 includes N readout lines. The readout lines are electrically connected to the first electrode of the thin-film transistor (TFT) of each pixel in the corresponding pixel column, and are also electrically connected to the readout circuit corresponding to the detection panel 10. For example, the readout lines are electrically connected to the drain of the TFT. When the TFT is turned on, the readout circuit can read the photogenerated carriers accumulated in the photodiodes of each pixel through the readout lines to obtain the detection data corresponding to each pixel.

[0138] Referring to Figure 7, the first direction and the second direction are opposite. The first pixel row can be considered as a mirror image of the second pixel row about the central axis of the target region column direction. Specifically, for the m-th second pixel 102 in the second pixel row, that is, the second pixel 102 located in the m-th pixel column in the second pixel row, it is connected to the m-th readout line corresponding to the m-th pixel column. Therefore, the detection data corresponding to the target second pixel 102 is read out by the m-th readout line.

[0139] As shown in Figure 7, the connection relationship between the first transistor and the readout line of the first pixel 101 in the first pixel row is different from that in the second pixel row. For the (n+1)th first pixel 101 in the first pixel row, that is, the first pixel 101 located in the (n+1)th pixel column in the first pixel row, this first pixel 101 is connected to the nth readout line. For example, the second first pixel 101 is connected to the first readout line. In the image processing process, the dark grayscale value corresponding to all first pixels 101 in the first pixel row is shifted one position to the right, as shown in the following formula (15): LSB 1，n+1 =LSB 1，n (15)

[0140] Among them, LSB 1,n+1 This represents the dark grayscale value corresponding to the (n+1)th first pixel 101, LSB 1,nThis represents the dark grayscale value corresponding to the nth first pixel 101. Specifically, the first first pixel 101 in the first pixel row is not connected to the readout line. Its dark grayscale value can be obtained by assigning it the dark grayscale value corresponding to the neighboring pixels during image processing. Since the first first pixel 101 is located at the edge of the pixel array in the detection panel 10, its impact on the detection image is minimal and can be almost ignored.

[0141] Figure 10 is a schematic diagram of a detection device provided in an embodiment of this application. As shown in Figure 10, the detection device includes a detection panel 10, and multiple row scanning circuits and multiple reading circuits connected to the detection panel 10. The pixel array of the detection panel 10 is divided into regions every X pixel rows, resulting in multiple target regions. An enlarged view of one of the target regions is shown in Figure 7. This target region includes a first pixel row and multiple second pixel rows. Specifically, a first pixel row is set at the center position of every X pixel rows in the pixel array, for example, at X / 2 or X / 2+1 rows.

[0142] As shown in Figure 10, multiple row scanning circuits are connected to the right side of the detection panel 10, and multiple readout circuits are connected to the bottom of the detection panel 10. Specifically, X can be a multiple of 8, with common values ​​being 32, 64, 128, and 256. This matches the number of channels in the row scanning circuits, allowing one or more row scanning circuits to be connected to a target area. Referring to Figure 7, the detection panel 10 may include scan lines extending along the row direction and readout lines extending along the column direction. The scan lines are connected to the channels of the row scanning circuits, and the readout lines are connected to the channels of the readout circuits. In addition, the detection panel 10 may also include bias voltage lines, which are connected to the anode of the photodiode in the pixel to provide a negative bias voltage to the photodiode.

[0143] In related technologies, the problem of inconsistent dark signals due to differences in dark grayscale levels across different regions of the detection panel 10 is typically addressed using a flat-field correction algorithm. Specifically, the statistical average of dark grayscale levels for all or some pixels of the detection panel 10 can be obtained. However, this statistical average is not a theoretical benchmark for the dark grayscale levels of a pixel. When the TFTs of a pixel have different alignment offset directions and different alignment offset amounts, the statistical average of dark grayscale levels will also change accordingly. This leads to significant differences in the results of on-chip correction for a single detection panel 10 or inter-chip correction for different detection panels 10 based on this flat-field correction algorithm, which is detrimental to the consistency of the detection results.

[0144] It should be noted that even though the existing detector panel 10 can improve the difference in dark gray levels and reduce fixed pattern noise through the flat field correction algorithm, making the image more uniform and smooth, the results of the flat field correction algorithm for inter-panel correction of different detector panels 10 are quite different, and inter-panel gray level differences may still exist between different detector panels 10.

[0145] Based on the detection panel 10 provided in this application embodiment, the standard dark grayscale value obtained according to the dark grayscale values ​​corresponding to the first pixel 101 and the second pixel 102 refers to the ideal / theoretical value under the condition of normal TFT alignment, i.e., no alignment offset. Therefore, image processing based on this standard dark grayscale value is applicable to both intra-chip correction of a single detection panel 10 and inter-chip correction of multiple detection panels 10. Unlike existing flat-field correction algorithms, which are based on the statistical average of intra-chip grayscale and can only reduce intra-chip dark signal inconsistency (DSNU).

[0146] Referring to Figure 10, in practical applications, slight differences may exist between different ROICs, and even between different read channels of the same ROIC. The detection panel 10 provided in this embodiment, by setting multiple target areas and / or setting multiple first pixels 101 in each area, can perform mean or median calculations based on the dark grayscale values ​​of multiple pixels to obtain a standard dark grayscale value. This reduces the differences between different ROICs, as well as the differences between different channels within each ROIC.

[0147] Optionally, the target area includes at least one special pixel pair; the special pixel pair includes a first pixel 101 and a second pixel 102 adjacent to the first pixel 101;

[0148] The first pixel 101 and the second pixel 102 in the special pixel pair are located in the same pixel row.

[0149] In some embodiments, the first pixel 101 and the second pixel 102 can be arranged in pairs, referred to as special pixel pairs. Specifically, a special pixel pair includes a pair of adjacent first pixels 101 and second pixels 102 in the same pixel row. The target region may include multiple special pixel pairs, which may be located in the same pixel row or in different pixel rows. That is, a pixel row in the target region may include one or more special pixel pairs, or may not include any special pixel pairs. This is only an example, and the embodiments of this application do not impose any limitations on this. The arrangement of the first transistor in the first pixel 101 is opposite to the arrangement of the second transistor in the second pixel 102; for example, the direction from the source to the drain of the first transistor and the second transistor are opposite.

[0150] Figure 11 is a circuit structure diagram of a target area in a detection panel 10 provided in another embodiment of this application. As shown in Figure 11, the target area includes a special pixel pair, which includes a pair of adjacent first pixels 101 and second pixels 102 located in the same pixel row. The first pixel row has a first direction in which the source (S) of the first transistor points to the drain (D), and the second pixel row has a second direction in which the source (S) of the second transistor points to the drain (D). Referring to Figure 11, the first and second directions are opposite, and the first pixel 101 can be regarded as obtained by mirroring the second pixel 102 about the central axis of the column direction of the target area.

[0151] Figure 12 is a planar structural diagram of the target area in another detection panel 10 provided in this application embodiment. As shown in Figure 12, the overlap width between the gate and source of the first transistor in the first pixel 101 is greater than the overlap width between the gate and drain. The first transistor is offset in the direction from the source to the drain, that is, it is offset in the first direction. The overlap width between the gate and source of the second transistor in the second pixel 102 is less than the overlap width between the gate and the drain. The second transistor is offset in the direction from the drain to the source, that is, it is offset in the opposite direction of the second direction.

[0152] Figure 13 is an enlarged view of the pixel structure within the dashed box in the target area shown in Figure 12. As shown in Figure 13, the alignment offset of the gate of the first transistor in the first pixel 101 between the source and drain is the first offset, and the alignment offset of the gate of the second transistor in the second pixel 102 between the source and drain is the second offset. The first offset and the second offset are approximately equal. It should be noted that, referring to Figure 13, both the first transistor and the second transistor are offset to the left of Figure 13. Therefore, from the overall perspective of the detection panel 10, both the first transistor and the second transistor have a leftward alignment problem.

[0153] Referring to the aforementioned descriptions of formulas (11) to (14), for C gs.off1 and C gs.off2 Taking the average value can also eliminate the influence of the alignment offset ΔL on the dark grayscale value. Therefore, the average dark grayscale value of the first pixel 101 and the second pixel 102 can be used as the standard dark grayscale value when the TFT is properly aligned.

[0154] In some embodiments, the dark grayscale values ​​corresponding to the first pixel 101 and the second pixel 102 in a special pixel pair are averaged or medianized to obtain the dark grayscale mean of the special pixel pair. If the target region includes multiple special pixel pairs, the dark grayscale mean of the multiple special pixel pairs can be averaged or medianized. If the pixel array includes multiple target regions, the dark grayscale mean of the multiple target regions can be averaged or medianized. The more first pixels 101 and second pixels 102 involved in the calculation, the more accurate the obtained standard dark grayscale mean, but the image processing computation load increases. Conversely, the fewer data involved in the calculation, the less image processing computation is required, and the faster the image processing speed. An appropriate method for calculating the standard dark grayscale value can be selected according to the actual application needs. This is merely an illustrative example, and the embodiments of this application do not impose limitations.

[0155] Optionally, the pixel array includes multiple target regions in the row direction.

[0156] And / or, the pixel array includes multiple target regions in the column direction.

[0157] In some embodiments, the pixel array can be divided into regions according to pixel rows and / or pixel columns, meaning the divided regions do not necessarily consist of entire rows or columns of pixels. This results in smaller region areas and fewer pixels per region compared to dividing regions by entire rows. Multiple target regions can be defined within these multiple regions. These target regions can be distributed along the row and / or column directions. That is, the pixel array includes multiple target regions in the row direction, and / or, the pixel array includes multiple target regions in the column direction.

[0158] In some embodiments, the number and position of special pixel pairs in multiple target regions may be the same or different, and this application does not impose any restrictions on this. Multiple regions divided by the pixel array can also all be target regions, each target region including at least one special pixel pair. The number and position of special pixel pairs included in different target regions can be the same, thus uniformly dividing the pixel array into multiple target regions in both the row and column directions. This uniform division of the pixel array helps reduce image processing time.

[0159] Optionally, in the row direction, the number of target pixels on both sides of a special pixel pair is equal, or the difference in the number of target pixels on both sides of a special pixel pair is 1;

[0160] The target pixel is the second pixel 102 that is not paired with the first pixel 101 in the pixel row where the special pixel pair is located.

[0161] In some embodiments, since the first pixel 101 and the second pixel 102 in a special pixel pair are adjacent pixels in the same pixel row, their structural differences are relatively small. The special pixel pair can be placed at the center of its pixel row. If a pixel row includes multiple special pixel pairs, these pairs can be continuously distributed and located at the center of the pixel row. This allows for more accurate standard dark grayscale values ​​obtained by averaging or medianing the dark grayscale values ​​of multiple special pixel pairs.

[0162] In some embodiments, if the number of target pixels in a pixel row is even, the number of target pixels on both sides of a special pixel pair in the row direction is equal. If the number of target pixels is odd, the number of target pixels on both sides of a special pixel pair in the row direction is not equal, and the difference between the two sides is 1. Specifically, for multiple consecutive special pixel pairs in a pixel row, the number of target pixels on both sides of any one of the special pixel pairs in the row direction is approximately equal.

[0163] Optionally, the detection panel 10 further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns;

[0164] The first electrode of the first transistor in the target first pixel 101 is connected to the i-th read line; wherein, the target first pixel 101 is the first pixel 101 located in the i-th pixel column;

[0165] The first electrode of the second transistor in the target second pixel 102 is connected to the i-th read line; wherein, the target second pixel 102 is the second pixel 102 paired with the target first pixel 101, and the target second pixel 102 is located in the (i+1)-th pixel column; wherein, i is greater than or equal to 1 and i is less than N.

[0166] In some embodiments, the pixel array of the detection panel 10 includes N pixel columns, each pixel column corresponding to a readout line, i.e., the detection panel 10 includes N readout lines. The readout lines are electrically connected to the first electrode of the thin-film transistor of each pixel in the corresponding pixel column, and are also electrically connected to the readout circuit corresponding to the detection panel 10. Referring to FIG11, the first pixel 101 can be considered as obtained by mirroring the second pixel 102 about the central axis of the target region column direction. The first pixel 101 and the second pixel 102 in the special pixel pair are located in the same pixel row and are adjacent to each other. Therefore, the first transistor in the first pixel 101 and the second transistor in the second pixel 102 are connected to the same readout line, and the detection data of the special pixel pair is read out by one readout line. Therefore, in the actual image, the position of the special pixel pair is a bright spot with a higher dark grayscale value, and half of the dark grayscale value of that point can be used as the standard dark grayscale value.

[0167] In this case, for a specific pixel pair, the dark grayscale values ​​corresponding to the original first pixel 101 and the second pixel 102 are missing one pixel's corresponding dark grayscale value after being read from the same readout line. This missing dark grayscale value can be obtained by assigning it the dark grayscale value corresponding to the neighboring pixels during image processing. However, since the missing dark grayscale value is located in the center of the detection image, it has a slightly larger impact on the detection image.

[0168] In some embodiments, the i-th first pixel 101 and its adjacent second pixel 102 in a pixel row are both connected to the i-th readout line. That is, the first pixel 101 located in the i-th pixel column and the second pixel 102 located in the (i+1)-th pixel column in a pixel row are both read and detected by the i-th readout line. Specifically, in the first pixel 101, the first electrode of the first transistor is connected to the i-th readout line, and in the second pixel 102, the first electrode of the second transistor is connected to the i-th readout line.

[0169] Figure 14 is a schematic diagram of another detection device provided in an embodiment of this application. As shown in Figure 14, the detection device includes a detection panel 10, and multiple row scanning circuits and multiple reading circuits connected to the detection panel 10. Each X row and each Y column in the pixel array of the detection panel 10 is divided into a region, and the resulting multiple regions are all target regions. An enlarged view of one of the target regions is shown in Figure 11, where a special pixel pair is set at the center position. Specifically, a pair of first pixels 101 and second pixels 102 is set at the center position of each X row and each Y column in the pixel array, such as rows X / 2 and X / 2+1, and columns Y / 2 and Y / 2+1.

[0170] As shown in Figure 14, multiple row scanning circuits are connected to the right side of the detection panel 10, and multiple readout circuits are connected to the bottom of the detection panel 10. Specifically, X and Y can be multiples of 8, with common values ​​being 32, 64, 128, and 256. This matches the number of channels in the row scanning circuits and readout circuits, allowing one target area to be connected to one or more row scanning circuits and one or more readout circuits. Referring to Figure 11, the detection panel 10 may include scan lines extending along the row direction and readout lines extending along the column direction. The scan lines are connected to the channels of the row scanning circuits, and the readout lines are connected to the channels of the readout circuits. In addition, the detection panel 10 may also include bias voltage lines, which are connected to the anode of the photodiode in the pixel to provide a negative bias voltage to the photodiode.

[0171] Referring to Figure 14, in practical applications, slight differences may exist between different line scanning ICs, and even between different line channels of the same line scanning IC. The detection panel 10 provided in this embodiment, by setting multiple target areas and / or setting multiple first pixels 101 in each area, can perform mean or median calculations based on the dark grayscale values ​​of multiple pixels to obtain a standard dark grayscale value. This reduces the differences between different line scanning ICs, as well as the differences between different channels within each line scanning IC.

[0172] This application also provides a detection device, which includes a detection panel 10 as described in the foregoing embodiments.

[0173] In some embodiments, the detection device includes a detection panel 10, and multiple row scanning circuits and multiple readout circuits connected to the detection panel 10. The detection device can be applied to photoelectric detection in fields such as medical image acquisition, industrial non-destructive testing, and scientific research. For example, the detection device can be an X-ray flat panel detector, including an X-ray detection panel 10 based on a-Si TFT technology, for X-ray image acquisition.

[0174] The detection device provided in this application embodiment can achieve the same or identical effect as the detection panel 10, which will not be described in detail here.

[0175] Figure 15 is a flowchart of the steps of an image processing method provided in an embodiment of this application. As shown in Figure 15, the image processing method includes:

[0176] Step S1: Read the first detection data corresponding to the first pixel 101 and the second detection data corresponding to the second pixel 102;

[0177] Step S2: Determine the standard dark grayscale value of the detection panel 10 based on the first detection data and the second detection data.

[0178] In some embodiments, the image processing method can be applied to the readout circuit of the detection device, that is, the readout circuit connected to the readout line of the detection panel 10 in the detection device. The readout circuit can read the photogenerated carriers accumulated in the photodiode of the first pixel 101 through the readout line as the first detection data, and read the photogenerated carriers accumulated in the photodiode of the second pixel 102 through the readout line as the second detection data.

[0179] In some embodiments, the dark grayscale value corresponding to a pixel can be referred to the relevant descriptions in formulas (1) to (6) in the aforementioned embodiments. The readout circuit includes an integrator, and the readout circuit can be based on the integrator reference voltage V. ref Minimum output voltage V of integrator AFE.min The feedback capacitor value C of the integrator FThe dark grayscale value of the pixel is obtained by calculating the average or median dark grayscale value of the first pixel 101 and the second pixel 102, as well as the charge value accumulated by the feedback capacitor of the integrator, i.e., the value at which the pixel converts the light signal into an electrical signal. Then, the standard dark grayscale value of the dark grayscale average detection panel 10 is obtained by calculating the average or median dark grayscale value of the first pixel 101 and the second pixel 102. This is only an example and the embodiments of this application are not limited thereto.

[0180] Optionally, step S1 may include the following steps:

[0181] Sub-step A1: Read the first detection data and the second detection data from the read lines connected to the first transistor and the second transistor, respectively;

[0182] Step S2 may include:

[0183] Sub-step B1: Obtain the first grayscale value corresponding to the first pixel 101 based on the first detection data, and obtain the second grayscale value corresponding to the second pixel 102 based on the second detection data;

[0184] Sub-step B2: Determine the standard dark grayscale value based on the first grayscale value and the second grayscale value.

[0185] In some embodiments, the reading circuit can read the detection data corresponding to the first pixel 101 and the second pixel 102 respectively through two reading lines. For example, the first pixel 101 located in the first pixel row can read the first detection data through the reading line connected to the first transistor of the first pixel 101, and the second pixel 102 located in the second pixel row can read the second detection data through the reading line connected to the second transistor of the second pixel 102. Then, for the first detection data and the second detection data, the dark grayscale value is calculated according to the relevant descriptions of formulas (1) to (6), and the dark grayscale value corresponding to the first pixel 101 is taken as the first grayscale value. The second grayscale value is calculated in the same way. Finally, the average of the first grayscale value and the second grayscale value can be calculated, and the average dark grayscale value is taken as the standard dark grayscale value of the detection panel 10.

[0186] Optionally, the method further includes:

[0187] Step S3: Obtain the dark grayscale value corresponding to the neighboring pixels of the edge pixel; wherein, the edge pixel is the first pixel 101 located in the first pixel column of the first pixel row;

[0188] Step S4: Determine the third gray level value corresponding to the edge pixel based on the dark gray level value corresponding to the neighboring pixel;

[0189] Sub-step B2 may include the following steps:

[0190] The standard dark gray level value is determined based on the first gray level value, the second gray level value, and the third gray level value.

[0191] In some embodiments, the first pixel 101 located in the first pixel column of the first pixel row is referred to as an edge pixel because it is located at the edge of the pixel array in the detection panel 10. The neighboring pixels of the edge pixel can include, but are not limited to, pixels in the fields of 4-neighborhood, diagonal neighborhood, and 8-neighborhood. For example, the first pixel 101 located in the second pixel column of the first pixel row can be used as a neighboring pixel of the edge pixel. The number of neighboring pixels can be one or more, and this embodiment does not limit this.

[0192] In some embodiments, when calculating the standard dark grayscale value of the detection panel 10, the dark grayscale value of the edge pixel can be assigned to obtain the third grayscale value corresponding to the edge pixel. Together with the dark grayscale values ​​corresponding to the first pixel 101 and the second pixel 102, the dark grayscale mean is calculated by means or median operation based on the first grayscale value, the second grayscale value and the third grayscale value, and is used as the standard dark grayscale value of the detection panel 10.

[0193] Optionally, step S1 may also include the following steps:

[0194] Sub-step A2: Simultaneously read the first detection data and the second detection data from the read line that is connected to the first transistor and the second transistor to obtain the target detection data;

[0195] Step S2 may also include:

[0196] Sub-step B3: Determine the target grayscale value at the specific pixel pair based on the target detection data, and determine the standard dark grayscale value based on the target grayscale value.

[0197] In some embodiments, the readout circuit can read the detection data of the first pixel 101 and the second pixel 102 together through the same readout line. For example, if the first pixel 101 and the second pixel 102 in a special pixel pair are read from the same readout line, then the target detection data read from the special pixel pair includes the first detection data and the second detection data, and the target detection data is twice the detection data of a single pixel. Then, for the target detection data, referring to the relevant descriptions of formulas (1) to (6), the dark grayscale value is calculated as the target grayscale value at the special pixel pair. Finally, half of the target grayscale value can be used as the standard dark grayscale value of the detection panel 10.

[0198] The image processing method provided in this application embodiment can achieve the same or similar effect as the detection panel 10, which will not be described in detail here.

[0199] The detection panel 10, detection device, and image processing method provided in this application embodiment are applicable to low-dose, dynamic, and other X-ray imaging scenarios. The fabrication process of the detection panel 10 is compatible with the mass production process of a-Si TFT optoelectronic sensor panels, requiring no additional steps or development costs; only the location of the photolithographic pattern is different. The image processing method requires only a few simple additional processing steps, with negligible impact on image processing time.

[0200] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0201] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0202] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A detection panel, wherein, The detection panel includes: a plurality of pixels; each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device; The plurality of pixel arrays are arranged to form a pixel array; the pixel array includes multiple regions; among the plurality of regions, at least one target region includes a first pixel and a second pixel; The thin-film transistor in the first pixel is a first transistor; in a first direction, the overlap width between the gate and the first electrode of the first transistor is a first width; in the first direction, the overlap width between the gate and the second electrode of the first transistor is a second width; the first width is greater than the second width; The thin-film transistor in the second pixel is a second transistor; in the second direction, the overlap width between the gate of the second transistor and the first electrode is a third width; in the second direction, the overlap width between the gate of the first transistor and the second electrode is a fourth width; the third width is smaller than the fourth width. The first direction is the direction from the first electrode of the first transistor to the second electrode; the second direction is the direction from the first electrode of the first transistor to the second electrode; the first direction is opposite to the second direction.

2. The detection panel according to claim 1, wherein, In the first direction, the alignment offset of the gate of the first transistor between the first electrode and the second electrode is a first offset; the first offset is half the difference between the first width and the second width; In the second direction, the alignment offset of the gate of the second transistor between the first and second electrodes is the second offset; the second offset is half the difference between the fourth width and the third width; The first offset is approximately equal to the second offset.

3. The detection panel according to claim 1 or 2, wherein, The target region comprises multiple pixel rows; the multiple pixel rows include a first pixel row and a second pixel row; The pixels in the first pixel row are the first pixels; the pixels in the second pixel row are the second pixels.

4. The detection panel according to claim 3, wherein, The pixel array includes multiple target regions; The number of targets corresponding to multiple target regions is equal; The target number is the total number of pixel rows in the target region.

5. The detection panel according to claim 3, wherein, The target region includes multiple first pixel rows and multiple second pixel rows; Multiple rows of the first pixel are continuously distributed in the column direction to form a first sub-array; the first sub-array is disposed between multiple rows of the second pixel.

6. The detection panel according to claim 5, wherein, In the column direction, the number of second pixel rows located on both sides of the first pixel row is equal, or the difference in the number of second pixel rows located on both sides of the first pixel row is 1.

7. The detection panel according to claim 3, wherein, The detection panel further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns; In the first pixel row, the first electrode of the first transistor in the target first pixel is connected to the nth read line; wherein, the target first pixel is the first pixel located in the (n+1)th pixel column; n is greater than 0 and n is less than N; In the second pixel row, the first electrode of the second transistor in the target second pixel is connected to the m-th read line; wherein, the target second pixel is the second pixel located in the m-th pixel column; m is greater than 0 and m is less than or equal to N.

8. The detection panel according to claim 1 or 2, wherein, The target region includes at least one special pixel pair; the special pixel pair includes a first pixel and a second pixel adjacent to the first pixel; The first pixel and the second pixel in the special pixel pair are located in the same pixel row.

9. The detection panel according to claim 8, wherein, The pixel array includes multiple target regions in the row direction. And / or, the pixel array includes a plurality of the target regions in the column direction.

10. The detection panel according to claim 8, wherein, In the row direction, the number of target pixels on both sides of the special pixel pair is equal, or the difference in the number of target pixels on both sides of the special pixel pair is 1; The target pixel is the second pixel in the pixel row where the special pixel pair is located that is not paired with the first pixel.

11. The detection panel according to claim 8, wherein, The detection panel further includes: N readout lines; the readout lines extend along the column direction; the pixel array includes N pixel columns; The first electrode of the first transistor in the target first pixel is connected to the i-th read line; wherein, the target first pixel is the first pixel located in the i-th pixel column; The first electrode of the second transistor in the target second pixel is connected to the i-th read line; wherein the target second pixel is the second pixel paired with the target first pixel, and the target second pixel is located in the (i+1)-th pixel column; wherein i is greater than or equal to 1 and i is less than N.

12. A detection device, wherein, The detection device includes a detection panel as described in any one of claims 1-11.

13. An image processing method, wherein, The method includes: Read the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel; Based on the first detection data and the second detection data, the standard dark grayscale value of the detection panel is determined.

14. The image processing method according to claim 13, wherein, The step of reading the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel includes: The first detection data and the second detection data are read from the read lines connected to the first transistor and the second transistor, respectively. The step of determining the standard dark-state grayscale value of the detection panel based on the first detection data and the second detection data includes: The first grayscale value corresponding to the first pixel is obtained based on the first detection data, and the second grayscale value corresponding to the second pixel is obtained based on the second detection data; The standard dark grayscale value is determined based on the first grayscale value and the second grayscale value.

15. The image processing method according to claim 14, wherein, The method further includes: Obtain the dark grayscale value corresponding to the neighboring pixels of the edge pixel; wherein, the edge pixel is the first pixel located in the first pixel column of the first pixel row; The third gray level value corresponding to the edge pixel is determined based on the dark gray level value corresponding to the neighboring pixel; Determining the standard dark grayscale value based on the first grayscale value and the second grayscale value includes: The standard dark grayscale value is determined based on the first grayscale value, the second grayscale value, and the third grayscale value.

16. The image processing method according to claim 13, wherein, The step of reading the first detection data corresponding to the first pixel and the second detection data corresponding to the second pixel includes: Target detection data is obtained by simultaneously reading the first detection data and the second detection data from the read line that is connected to the first transistor and the second transistor. The step of determining the standard dark-state grayscale value of the detection panel based on the first detection data and the second detection data includes: The target grayscale value at a specific pixel pair is determined based on the target detection data, and the standard dark grayscale value is determined based on the target grayscale value.

Images