Portable signal measurement system for multi-scene requirements

Abstract

The invention provides a portable signal measurement system for multi-scene requirements, and belongs to the technical field of signal testing and measurement, and the system comprises a front-end signal dual-channel sampling module which is used for collecting multiple paths of independent analog electric signals at the same time; the edge artificial intelligence reasoning module is used for analyzing the analog electric signals in real time; the touch module is used for performing man-machine interaction according to the analog electric signal and / or an analysis result of the analog electric signal; the dual-mode shared cache module is used for providing a unified data storage and access interface for the front-end signal dual-channel sampling module, the edge artificial intelligence reasoning module and the touch module; the front-end signal dual-channel sampling module, the edge artificial intelligence reasoning module, the touch module and the dual-mode sharing cache module are all integrated on a single printed circuit board. By the adoption of the technical scheme, the requirements of various industries for multifunctional and portable testing tools can be met.

Description

Technical Field

[0001] This application relates to the field of signal testing and measurement technology, and in particular to a portable signal measurement system for multi-scenario needs. Background Technology

[0002] Currently, multifunctional test and measurement systems, as key core components in modern electronic technology, have widely penetrated various sub-sectors such as communications, medical, industrial automation, automotive manufacturing, and consumer electronics, becoming an important support for ensuring the smooth operation of product research and development, production testing, and maintenance. With the accelerated iteration of technologies across industries, the functional requirements of test and measurement systems are also increasing. In addition to demanding the integration of more test modules, higher requirements are being placed on the system's flexibility and adaptability to different scenarios, making the portability of test and measurement instruments one of the important development directions for these systems.

[0003] In related technologies, multifunctional test and measurement instruments are mainly desktop devices. Although they can meet the basic test function requirements, they are generally bulky and heavy, making them inconvenient to carry and move. They are difficult to adapt to mobile test scenarios such as on-site debugging, outdoor operations, and field exploration, and thus cannot meet the urgent needs of various industries for multifunctional and portable test tools. Summary of the Invention

[0004] The main purpose of this application is to propose a portable signal measurement system for multi-scenario needs, at least to solve the problem that traditional test and measurement instruments cannot meet the needs of various industries for multifunctional and portable test tools.

[0005] To achieve the above objectives, the first aspect of this application proposes a portable signal measurement system for multi-scenario needs, the system comprising:

[0006] A dual-channel front-end signal sampling module is used to simultaneously acquire multiple independent analog electrical signals; An edge AI inference module is used for real-time analysis of the analog electrical signals; The touch module is used for human-computer interaction based on the analog electrical signal and / or the analysis results obtained by real-time analysis of the analog electrical signal; The dual-mode shared cache module is used to provide a unified data storage and access interface for the front-end signal dual-channel sampling module, the edge artificial intelligence inference module, and the touch module; The front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module are all integrated on a single printed circuit board.

[0007] In some embodiments, the system further includes: A field-programmable gate array (FPGA) hardware gesture state machine is used to parse user gesture signals collected by the touch module during human-computer interaction.

[0008] In some embodiments, the user gesture signal includes at least one of the following: a single-finger swipe gesture signal representing time base scaling, a two-finger pinch gesture signal representing amplitude scaling, a triple-tap gesture signal representing waveform pause, and a long-press gesture signal representing a virtual knob.

[0009] In some embodiments, the field-programmable gate array hardware gesture state machine also employs 512-point parallel template matching and derivative template dual-channel voting hardware to output waveform category labels within a preset time after the sampling completion interruption to drive trigger control or alarm.

[0010] In some embodiments, the field-programmable gate array hardware gesture state machine includes: A pool of multiple distributed static random access memory blocks is used to perform real-time storage status management operations on the same clock edge. The real-time storage status management operations include dynamically selecting storage unit addresses, real-time counting of the number of occupied storage units, and indicating whether the maximum storage capacity has been reached.

[0011] In some embodiments, the multi-block distributed static random access memory pool uses cyclic shifting to balance the load of each block, or the multi-block distributed static random access memory pool uses priority encoding to allocate the load of each block concurrently in one go.

[0012] In some embodiments, when the saturation monitoring results of the multiple distributed static random access memory pools meet preset conditions, the system automatically triggers mode switching or generates a shutdown signal. The preset conditions include continuous saturated blocks and insufficient available resources.

[0013] In some embodiments, the front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module operate in the same 50 MHz global clock domain.

[0014] In some embodiments, the system further includes: The Bluetooth remote control module is used to move the parameter settings for automated testing of the system to the user graphical interface of the remote device to run the oscilloscope's automated test mode.

[0015] To achieve the above objectives, a second aspect of this application provides an electronic device comprising the portable signal measurement system for multi-scenario needs described in the first aspect.

[0016] This application proposes a portable signal measurement system and electronic device for multi-scenario needs. It simultaneously acquires multiple independent analog electrical signals through a front-end dual-channel sampling module, performs real-time analysis of the analog electrical signals through an edge AI inference module, provides human-computer interaction through a touch module based on the analog electrical signals and / or the analysis results obtained from the real-time analysis, and provides a unified data storage and access interface for the front-end dual-channel sampling module, the edge AI inference module, and the touch module through a dual-mode shared buffer module. This allows for the testing and measurement of relevant signals for various scenarios. Furthermore, this application integrates the front-end dual-channel sampling module, the edge AI inference module, the touch module, and the dual-mode shared buffer module all onto a single printed circuit board, effectively reducing the overall thickness and size of the device. Experiments have shown that the electronic device (such as a multi-functional oscilloscope) provided by this application is 2.5 times smaller in overall size than a traditional oscilloscope.

[0017] In other words, the portable signal measurement system and electronic device proposed in this application, which are designed for multiple scenarios, can meet the needs of signal measurement in multiple scenarios. Moreover, its overall size is small, easy to carry and move, so it can be adapted to mobile testing scenarios such as on-site debugging, outdoor operations, and field exploration. This meets the urgent needs of various industries for multifunctional and portable testing tools, thus solving the problem that traditional test and measurement instruments cannot meet the needs of various industries for multifunctional and portable testing tools. Attached Figure Description

[0018] Figure 1 The portable signal measurement system for multi-scenario needs provided in the embodiments of this application is illustrated in some embodiments with a human-computer interaction interface. Figure 2 A schematic diagram of the structure of a portable signal measurement system for multi-scenario needs provided in some embodiments of this application; Figure 3 A 3D modeling schematic diagram of the outer casing of the portable signal measurement system for multi-scenario needs provided in the embodiments of this application; Figure 4 A schematic diagram of the overall system framework of the portable signal measurement system for multi-scenario needs provided in the embodiments of this application, in a complete embodiment; Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] First, the technical terms used in the embodiments of this application will be explained.

[0023] Analog-to-Digital Converter (ADC): A circuit that quantizes continuous analog voltage into a discrete digital code stream. In the embodiments of this application, the ADC used in the system can be AD9226, 12-bit, 65 MSPS.

[0024] Mega-Sample Per Second (MSPS): A unit characterizing the sampling rate of an ADC; the system equivalent rate in differential alternation mode reaches 130 MSPS.

[0025] Low-Noise Amplifier (LNA): Noise figure <0.8 nV / √Hz, gain 40 dB, used to amplify weak signals in the 50 μV range to the effective range of the ADC.

[0026] Coordinate Rotation Digital Computer (CORDIC): This algorithm uses only shift-addition iterations to complete trigonometric function and vector rotations, making it suitable for implementation in Field Programmable Gate Array (FPGA) hardware.

[0027] Fast Fourier Transform (FFT): An algorithm that efficiently converts discrete-time signals into frequency-domain representations; in this embodiment, the system uses Radix-2 1024-point pipelined FFT IP.

[0028] Total Harmonic Distortion (THD): the percentage of harmonic energy to fundamental energy; in this embodiment, the system calculates the 5th harmonic using a 1024-point windowed FFT with an error ≤0.1%.

[0029] First-In-First-Out (FIFO) queue: A data buffering and scheduling mechanism that processes elements in the order they enter.

[0030] Random Access Memory (RAM): refers to memory in which the time required to read or write data is independent of the physical address of the data.

[0031] Priority Encoder: A combinational logic circuit that takes multiple signal lines as input and outputs a binary code of the highest priority valid input signal.

[0032] Window Function: Weighting of time-domain data before FFT to suppress spectral leakage; THD measurement uses Hann window with 31 dB sidelobe attenuation.

[0033] Spectral Leakage: Energy diffusion is caused by non-integer period truncation of the sampling window; by using the Hann window function for weighting, the sidelobe attenuation is increased from -13 dB to -31 dB, significantly reducing leakage error.

[0034] Machine Learning (ML): Utilizes data and statistical methods to automatically improve system performance without explicit programming; in this embodiment, the system employs hardware-level template matching.

[0035] Derivative Template: The original template is first-order differencing and then normalized to enhance the distinction between sine and triangular waves in the high-frequency band.

[0036] Next, the overall concept of this application will be explained.

[0037] Multifunctional test and measurement systems, as a key component of modern electronic technology, are widely used in various fields such as communications, medical, industrial automation, automotive manufacturing, and consumer electronics, and the functional requirements they need to meet are constantly increasing. However, traditional instruments are generally bulky, creating an urgent need for a portable oscilloscope that integrates multiple functions.

[0038] In related technologies, taking cache management + traditional benchtop oscilloscope as an example, the oscilloscope and dynamic cache management adopt separate, offline, or unidirectional link solutions at the four levels of "cache-sampling-artificial intelligence (AI)-expansion," specifically manifested as follows: Cache layer: It adopts a two-level structure of "FIFO free pointer queue + index RAM linked list". The next available pointer address can only be read in the first clock cycle. In subsequent cycles, the head of the linked list needs to be written back, the tail pointer updated and the remaining counter updated.

[0039] Without a real-time "used space" comparator for SRAM blocks and without global saturation monitoring, local congestion often occurs in multi-port random write scenarios, where "one block is full while the others are still idle." When a sudden large frame arrives at multiple ports at the same time, the allocation decision requires sequential traversal of the linked list, and the worst-case latency increases linearly with the number of blocks.

[0040] During periods of high load (with less than 20% of blocks remaining), the same sequential strategy is still used, which cannot provide all available block addresses concurrently at once, resulting in a sharp drop in throughput.

[0041] Sampling layer: Desktop oscilloscopes typically use 2 to 4 independent ADC daughter cards. Each daughter card is connected to the main ARM processor via FMC or a custom parallel bus. Channel synchronization relies on an external sampling clock distribution chip and PCB traces of equal length. A difference of 5 cm in trace length can introduce 170 ps jitter, limiting the accuracy of phase measurement.

[0042] Expanding channels requires adding an equal number of daughter cards and connectors, resulting in a linear increase in motherboard area with each channel. Once the mechanical structure is fixed, hot-swapping is not possible. The parallel bus speed is limited by the 400 MHz connector, leaving little room for bandwidth improvement.

[0043] After the multi-channel data is aggregated to the ARM, it needs to go through three steps: DDR writing, reading and display. The waveform capture rate is generally <1wf / s, making it impossible to observe occasional glitches.

[0044] Artificial intelligence (AI) recognition layer: High-end desktop computers only offer two offline analysis modes: "acquisition-transfer-USB drive" or "Ethernet upload". FFT and waveform classification are run in MATLAB or Python on Windows, with a typical latency of 50 ms to 2 s.

[0045] Without hardware-level trigger feedback, the identification results cannot stop sampling or control GPIO in real time; when the user needs to "capture abnormal waveforms and stop immediately", the file must be scanned back afterward, resulting in a loss of real-time performance.

[0046] Algorithms such as template matching and neural networks run on x86 CPUs, consuming more than 65W, making them unsuitable for embedding in battery-powered portable devices.

[0047] Extension layer: Traditional instruments use PCIe Gen2×8 or Gigabit Ethernet cascading, with a single-hop delay of 2 μs to 200 μs, which increases with the addition of software protocol stacks; phase coherence measurement requires inter-channel error of <100 ns, which cannot be met by related solutions.

[0048] Rigid topology: PCIe only supports star topology and requires an external switch; Ethernet is tree topology, loops require RSTP blocking ports, the number of channels is fixed at the factory configuration, and user-side hot expansion is not possible.

[0049] The link layer lacks automatic clock compensation, requiring an additional clock recovery module for long-distance transmission, increasing hardware costs by 30%.

[0050] Based on the above-mentioned separate, offline, or unidirectional link solutions, it can be seen that the relevant technologies have at least the following drawbacks: Regarding caching: Local congestion resulted in an overall cache utilization rate of less than 70%. Tests showed that in a scenario with 16 ports and 32 SRAM blocks, the oscilloscope system using the above solution entered the "resource exhaustion" state 25% earlier. Without an adaptive strategy, the linked list still needs to be traversed sequentially under high load, and the allocation efficiency decreases linearly as the remaining blocks decrease. Lacking single-cycle concurrent output capability, it cannot meet the impact of a write request every 7.7 ns generated by 130 MSPS sampling.

[0051] Regarding sampling: The parallel bus exhibits large synchronization jitter, with a phase measurement error >1°@1 MHz; Expanding the channel requires adding daughter cards and connectors, which simultaneously increases the motherboard area, weight, and power consumption, contradicting the concept of "portability." Waveform capture rate <1 wf / s, low probability of capturing occasional anomalies; Without hardware-level differential alternating sampling, the sampling rate remains at 65 MSPS, making it impossible to achieve 130 MSPS using dual ADCs.

[0052] In terms of AI: The identification process is completed on the host side, with a delay of milliseconds, thus losing the value of real-time triggering. There is no hardware-level template matching; the CPU solution has high power consumption and large size, and cannot be embedded in battery devices. The recognition results cannot be fed back to the FPGA trigger unit, thus failing to form a closed loop of "sampling-recognition-shutdown".

[0053] Expansion aspects: PCIe / LAN link delay >200 μs, phase coherence measurement error increases by three orders of magnitude; The topology is rigid, the number of channels is fixed at the factory, and users cannot hot-swap expansions; Clock compensation requires an additional chip, increasing cost and area, making it unsuitable for single-board solutions.

[0054] To address the shortcomings of the aforementioned related technologies, this application proposes a portable signal measurement system and electronic device for multi-scenario needs. This portable signal measurement system can be a multi-functional oscilloscope system that is "integrated on a single board, small in size, and fully touch-enabled," aiming to solve the pain points of traditional oscilloscopes such as "large size, numerous buttons, offline AI, and high buffer latency." Furthermore, this application's portable signal measurement system and electronic device for multi-scenario needs are primarily hardware-based, for example, implemented in application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). The design extensively employs synchronous logic and well-defined combinational logic paths, which facilitates high-speed and stable operation in hardware. The single-cycle operation design simplifies the complexity of timing convergence.

[0055] This application proposes a portable signal measurement system and electronic device for multi-scenario needs. It simultaneously acquires multiple independent analog electrical signals through a front-end dual-channel sampling module, performs real-time analysis of the analog electrical signals through an edge AI inference module, provides human-computer interaction through a touch module based on the analog electrical signals and / or the analysis results obtained from the real-time analysis, and provides a unified data storage and access interface for the front-end dual-channel sampling module, the edge AI inference module, and the touch module through a dual-mode shared buffer module. This allows for the testing and measurement of relevant signals for various scenarios. Furthermore, this application integrates the front-end dual-channel sampling module, the edge AI inference module, the touch module, and the dual-mode shared buffer module all onto a single printed circuit board, effectively reducing the overall thickness and size of the device. Experiments have shown that the electronic device (such as a multi-functional oscilloscope) provided by this application is 2.5 times smaller in overall size than a traditional oscilloscope.

[0056] In other words, the portable signal measurement system and electronic device proposed in this application, which are designed for multiple scenarios, can meet the needs of signal measurement in multiple scenarios. Moreover, its overall size is small, easy to carry and move, so it can be adapted to mobile testing scenarios such as on-site debugging, outdoor operations, and field exploration. This meets the urgent needs of various industries for multifunctional and portable testing tools, thus solving the problem that traditional test and measurement instruments cannot meet the needs of various industries for multifunctional and portable testing tools.

[0057] Furthermore, the portable signal measurement system and electronic device proposed in this application, designed for multiple scenarios, can also provide touch interaction with zero physical keys, i.e.: Figure 1 As shown, the design implements a pop-up operation interface, including pause and afterglow buttons, menu buttons for switching between various functions such as parameter measurement, spectrum analysis, weak signal detection, alternating sampling, data interpolation, AI-assisted recognition, and automatic test mode. It also features four-channel selection management and pop-up windows displaying the results of each measurement function on the right.

[0058] Furthermore, the portable signal measurement system and electronic device proposed in this application, which are designed for multiple scenarios, can also achieve single-cycle dual-mode buffer management. Specifically, it constructs a distributed SRAM pool of 32 blocks inside the FPGA and merges the three core operations of "address selection - used count - saturation flag" into the same clock edge (10 ns). For normal loads, it uses cyclic shift to balance the load of each block, and for high loads, it uses priority coding to allocate all available blocks concurrently at once. The single-cycle delay is reduced by 50% compared to the prior art.

[0059] Furthermore, the portable signal measurement system and electronic device proposed in this application, which are designed for multi-scenario needs, can also provide a scalable synchronous single-board architecture. That is, all functional modules operate in the same 50 MHz global clock domain, and the number of ports, the number of SRAM blocks, and the template depth are all defined using parameterized Verilog. It can be quickly tailored to a smaller packaged FPGA and reused in a multi-channel SoC to achieve IP-level portability.

[0060] Furthermore, the portable signal measurement system and electronic device proposed in this application, which are designed for multiple scenarios, can also enhance the robustness and controllability of the system. Specifically, it integrates real-time monitoring of SRAM saturation state and automatically triggers mode switching or generates clear shutdown signals based on preset conditions (such as continuous saturation blocks or insufficient available resources), providing clear status feedback and control interface for the system.

[0061] Furthermore, the portable signal measurement system and electronic device proposed in this application, designed for multi-scenario needs, can also provide real-time µs edge AI recognition. Specifically, using 512-point parallel template matching + derivative template dual-channel voting hardware, it outputs "sine / square / triangle wave" category labels within 6.6 µs after the sampling is interrupted, directly driving triggering / alarms. The recognition latency is reduced by three orders of magnitude compared to PC-based solutions.

[0062] Based on the overall concept of this application, specific embodiments of a portable signal measurement system and an electronic device for multi-scenario needs are proposed. First, specific embodiments of the portable signal measurement system for multi-scenario needs are described in detail.

[0063] It should be noted that the embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that utilize digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0064] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0065] Furthermore, in various specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent is obtained first. Moreover, the collection, use, and processing of this data comply with relevant laws, regulations, and standards. Additionally, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user is obtained through pop-ups or redirects to confirmation pages. Only after explicitly obtaining the user's separate permission or consent is the necessary user-related data for the proper functioning of these embodiments acquired.

[0066] Furthermore, the portable signal measurement system and electronic device provided in this application, which are designed for multiple scenarios, can be applied to field-programmable gate arrays (FPGAs), ADC data acquisition devices, and other communication devices that require high-speed data packet buffering and forwarding.

[0067] For ease of understanding and explanation, the following text will use a multi-functional oscilloscope system (in some embodiments, it will be referred to as an oscilloscope system, system, or oscilloscope) as an example for detailed description. The implementation of any of the above-mentioned themes can be referred to the operation process of the multi-functional oscilloscope system described below.

[0068] Please refer to Figure 2 , Figure 2 The diagram shows the structure of the portable signal measurement system for multi-scenario needs provided in some embodiments of this application.

[0069] like Figure 2 As shown in the embodiments of this application, the portable signal measurement system for multi-scenario needs may include: a front-end dual-channel signal sampling module, an edge artificial intelligence inference module, a touch module, and a dual-mode shared buffer module. Wherein: A dual-channel front-end signal sampling module is used to simultaneously acquire multiple independent analog electrical signals; An edge AI inference module is used for real-time analysis of the analog electrical signals; The touch module is used for human-computer interaction based on the analog electrical signal and / or the analysis results obtained by real-time analysis of the analog electrical signal; The dual-mode shared cache module is used to provide a unified data storage and access interface for the front-end signal dual-channel sampling module, the edge artificial intelligence inference module, and the touch module; The front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module are all integrated on a single printed circuit board.

[0070] It's important to note that the dual-channel front-end signal sampling module is the core of the oscilloscope system's front-end signal acquisition, determining the accuracy and bandwidth limits of signal measurements. Furthermore, the edge AI inference module is the oscilloscope system's intelligent analysis engine, providing automated and intelligent signal diagnostic capabilities. Additionally, the dual-mode shared buffer module serves as the oscilloscope system's data hub and scheduling center, resolving data transmission and storage bottlenecks between high-speed sampling, AI analysis, and display output. Finally, the touch module, also known as the touch panel, is the oscilloscope system's human-machine interface, serving as the carrier for user operation and data presentation.

[0071] In some embodiments, the front-end signal dual-channel sampling module can be a dual-channel 130 MSPS sampling chain. Its core function is to complete the analog-to-digital signal conversion (A / D conversion), providing raw data for subsequent digital analysis and serving as the data input source for the entire system. In the dual-channel 130 MSPS sampling chain, two dual-channel sampling chips support the simultaneous acquisition of four independent analog electrical signals (such as voltage and current signals), enabling synchronous observation and comparative analysis of four signals (e.g., synchronous testing of input / output signals of an autonomous driving controller). The 130 MSPS sampling rate means acquiring 130 million sample points per second. The higher the sampling rate, the stronger the reproduction of high-speed changing signals, and the more accurately it can capture the transient characteristics of the signal (such as glitches, pulses, rising / falling edge distortion).

[0072] In some embodiments, the edge AI inference module can perform real-time analysis of the digital signals output by the sampling chain based on a pre-trained AI model, and realize functions such as automatic identification of signal anomalies (such as glitches, overshoot, and noise), signal type classification, and automatic measurement of parameters (such as amplitude, period, and duty cycle).

[0073] In this embodiment, the digital signal output by the sampling chain is analyzed in real time by the edge artificial intelligence (AI) inference module, which eliminates the need for manual setting of measurement parameters or identification of anomalies, thereby greatly improving testing efficiency; and it can be applied to the rapid localization problem in complex scenarios (such as the diagnosis of high-frequency interference signals of autonomous vehicle sensors).

[0074] In some embodiments, the touch module can be a 7-inch touch module, which may include a display layer and an operation layer. The display layer is used to present the real-time waveform of the sampled data and the analysis results of AI inference (such as anomaly markers and parameter reports); the operation layer is used to set sampling parameters (such as sampling rate and trigger conditions), switch cache modes, and start AI analysis functions through touch commands; it also supports users to save, export, and share data.

[0075] In this embodiment, the interaction between the oscilloscope system and the user is achieved through a touch module. Compared with traditional button operation, touch-based interaction provides users with a more intuitive and efficient way to interact, making it suitable for rapid on-site debugging scenarios.

[0076] In some embodiments, the dual-mode shared cache module can temporarily store massive amounts of digital signals output from the sampling chain, provide data to be analyzed for the edge AI inference module, and transmit waveforms and analysis results to be displayed to the touch module. Simultaneously, the dual-mode shared cache module can also support data backtracking and secondary analysis.

[0077] In some embodiments, the dual-mode shared cache module may include two operating modes: a real-time cache mode (low depth, high bandwidth, for real-time waveform display) and a deep cache mode (high depth, low bandwidth, for long-term signal recording and offline analysis), which can be flexibly switched according to testing requirements. Furthermore, the dual-mode shared cache module can provide a unified data storage and access interface for the sampling chain, edge AI inference module, and touch module, avoiding data redundancy and transmission delays caused by independent storage by each module.

[0078] For example, during the operation of a multi-functional oscilloscope system, the modules form a closed-loop collaboration around the core process of "signal acquisition → data processing → interactive presentation," and the specific flow path of data and control commands is as follows: A dual-channel 130 MSPS sampling chain, based on two dual-channel sampling chips, simultaneously acquires four independent analog signals. After A / D conversion, the digital signals are written to a dual-mode shared buffer module. The edge AI inference module reads the digital signals from the shared buffer, executes AI algorithms such as anomaly detection and parameter measurement, and writes the analysis results back to the shared buffer. A 7-inch touch module retrieves the original waveforms and AI analysis results from the shared buffer for visualization. Users can issue operation commands (such as adjusting the sampling rate or switching buffer modes) through the touch module. These commands are transmitted to the sampling chain, buffer module, or AI module to update parameter configurations. In other words, during operation, the sampling chain is the data source, the shared buffer is the data hub, the edge AI is the intelligent core, and the touch module is the interaction window. Each component works together to achieve the core capabilities of the multi-functional oscilloscope system: high-precision acquisition, intelligent analysis, and convenient operation.

[0079] In some embodiments, the printed circuit board can be a six-layer HDI PCB (11 cm × 6 cm × 1.5 cm), which is the core hardware carrier and electrical interconnection hub of the entire system. It is the basic hardware platform for realizing dual-channel 130 MSPS sampling chain, edge AI inference, dual-mode shared cache and physical integration of 7-inch touch module, high-speed signal transmission, and stable functional collaboration. The six layers refer to the number of conductive layers on the PCB, including signal layers, power layers, and ground layers, which are laminated together through insulating dielectric layers. The multi-layer structure allows for functional partitioning routing, improving signal integrity and electromagnetic compatibility. High Density Interconnect (HDI) refers to a high-precision PCB manufacturing technology characterized by microvias, fine lines, and narrow spacing, enabling high-density layout and interconnection of a large number of components within a limited space, suitable for miniaturized, high-performance electronic systems. The 11 cm × 6 cm × 1.5 cm dimensions of the PCB reflect the miniaturized design of the system, balancing portability and functional integration.

[0080] For example, a six-layer HDI PCB can adopt an alternating arrangement of "signal layer-power layer-ground layer", with a total of 6 layers. The functions and characteristics of each layer are as follows, ensuring high-speed signal impedance matching, power supply stability, and electromagnetic compatibility (EMC): Layer 1 (signal layer): This layer mainly houses low-speed signal interfaces and peripheral devices, including the MIPI interface for the 7-inch touch module, power interface (AC / DC input), indicator lights, and button circuits. It also reserves pads for peripheral matching devices (such as filter capacitors and termination resistors) for the FPGA and high-speed ADC to ensure a compact device layout.

[0081] Inner Layer 1 (Layer 2, Power Layer): As a digital power layer, it provides stable power to the FPGA core, edge AI inference module, and dual-mode shared cache (DDR chip). It is divided into two independent power supply areas of 3.3V and 1.2V, and adopts large-area copper plating to reduce power ripple and adapt to the high current requirements of digital modules.

[0082] Inner Layer 2 (Layer 3, Ground Layer): Serves as a digital ground reference plane, forming a "power-ground" coupling pair with the Inner Layer 1 digital power layer, providing a low-impedance reference path for digital signals in the top layer and Inner Layer 3; at the same time, an independent ground island is set up for the logic ground of the FPGA distributed SRAM pool, reducing digital signal crosstalk.

[0083] Inner Layer 3 (Layer 4, Signal Layer): The core high-speed signal layer, which includes high-speed ADC output lines with a dual-channel 130 MSPS sampling chain, interconnect buses between the FPGA and the distributed SRAM pool, and control signal lines between the FPGA and the edge AI module; it adopts impedance control design to ensure low-latency transmission of 130 MSPS sampled data.

[0084] Inner Layer 4 (Layer 5, Ground Layer): As an analog ground reference plane, it provides a reference ground for the analog signal path of the dual-channel sampling chain and the analog input terminal of the ADC. It is isolated from the analog power layer to prevent digital ground noise from intruding into the analog circuit. It is a key layer to ensure sampling accuracy.

[0085] Layer 6 (signal layer + analog power layer): Part of the area serves as the analog power layer, providing high-precision 2.5V power to the ADC analog section. Star wiring is used to reduce power supply interference. The remaining area is used to lay out low-speed analog signal lines and test points to facilitate production debugging and troubleshooting.

[0086] Furthermore, based on the signal characteristics and functional interrelationships of each module in the oscilloscope system, the PCB can be divided into multiple independent functional areas to achieve "signal isolation, functional aggregation, and routing optimization." The boundaries of each area are marked with silkscreen for easy production assembly and maintenance. 1. Analog signal acquisition area (left center of PCB, approximately 2 cm × 3 cm), housing the high-speed ADC chip with a dual-channel 130MSPS sampling chain and analog front-end circuitry; 2. Edge AI inference area (right center of PCB, approximately 2 cm × 2.5 cm), housing the edge AI inference module (located here if it is a standalone chip, or a dedicated logic area if integrated into an FPGA) and computational auxiliary circuitry; 3. Dual-mode shared cache area (lower center of PCB, approximately 2 cm × 2 cm), housing the DDR memory chip and interface circuitry for the dual-mode shared cache; 4. Touch module interface area (top of PCB, approximately 1 cm × 6 cm), housing the interface chip (such as a MIPI to LVDS chip) and interconnect lines for the 7-inch touch module.

[0087] Finally, to accommodate high-speed signals and system stability, the PCB can utilize HDI technology for high-density routing. Critical signals (such as FPGA-SRAM pool interconnection and ADC output) should employ blind vias to avoid signal reflection and EMC issues caused by through-holes. The via diameter should be controlled between 0.15-0.2 mm to accommodate fine-line routing requirements. Line widths can be designed according to current and signal type: power lines (digital / analog) should have a width ≥ 0.8 mm to meet high current demands; high-speed signal lines should have a width of 0.2-0.3 mm to control impedance; and low-speed signal lines should have a width ≥ 0.2 mm to ensure reliability. Furthermore, analog and digital grounds can use a "single-point connection" method, achieving equipotential bonding between the two ground planes through grounding vias to avoid ground loop noise. Cross-regional connections between analog and digital grounds are prohibited to prevent noise intrusion into analog circuits.

[0088] This embodiment simultaneously acquires multiple independent analog electrical signals through a front-end dual-channel sampling module, performs real-time analysis of the analog electrical signals through an edge AI inference module, provides human-computer interaction through a touch module based on the analog electrical signals and / or the analysis results obtained from the real-time analysis of the analog electrical signals, and provides a unified data storage and access interface for the front-end dual-channel sampling module, the edge AI inference module, and the touch module through a dual-mode shared buffer module. This allows for testing and measurement of relevant signals to meet various scenario requirements. Furthermore, this application integrates the front-end dual-channel sampling module, the edge AI inference module, the touch module, and the dual-mode shared buffer module all onto a single printed circuit board, effectively reducing the overall thickness and size of the device. Experiments have shown that the electronic device (such as a multi-functional oscilloscope) provided by this application is 2.5 times smaller in overall size than a traditional oscilloscope. For example, by using the above-mentioned functional partitioning and wiring design on a six-layer HDI PCB, high-density integration of various modules of the oscilloscope system is achieved within a space of 11 cm × 6 cm × 1.5 cm, combined with... Figure 3 The casing shown allows the entire device to have a size of 19cm × 5cm × 15cm, with a volume ≤ 1500cm². 3 It is 2.5 times smaller than a traditional portable oscilloscope.

[0089] In other words, the portable signal measurement system and electronic device proposed in this application, which are designed for multiple scenarios, can meet the needs of signal measurement in multiple scenarios. Moreover, its overall size is small, easy to carry and move, so it can be adapted to mobile testing scenarios such as on-site debugging, outdoor operations, and field exploration. This meets the urgent needs of various industries for multifunctional and portable testing tools, thus solving the problem that traditional test and measurement instruments cannot meet the needs of various industries for multifunctional and portable testing tools.

[0090] In some embodiments, the portable signal measurement system for multi-scenario needs provided in this application may further include: A field-programmable gate array (FPGA) hardware gesture state machine is used to parse user gesture signals collected by the touch module during human-computer interaction.

[0091] It should be noted that the field-programmable gate array (FPGA) hardware gesture state machine can serve as the hardware-level core control and scheduling hub of a multi-functional oscilloscope system. It forms a "control-controlled", "scheduling-scheduled", and "interactive-cooperative" relationship with the front-end dual-channel signal sampling module, edge artificial intelligence inference module, touch module, and dual-mode shared buffer module. Its core value is to ensure low-latency and high-synchronization collaborative operation of each functional module through hardware-level timing logic and parallel processing capabilities.

[0092] In some embodiments, the FPGA hardware gesture state machine does not directly undertake business functions such as signal acquisition, AI analysis, and interactive display. Instead, it serves as the "hardware nerve center" of the multi-functional oscilloscope system. Through hardware-level timing control, task scheduling, and interface adaptation, it closely links the "data input" of the dual-channel sampling chain, the "data storage" of the dual-mode shared buffer, the "intelligent analysis" of edge AI inference, and the "human-computer interaction" of the touch module. This solves the high-speed, synchronization, and low-latency requirements that are difficult to meet by software control and is the core hardware support for realizing the "multi-functional, high-precision, and intelligent" oscilloscope.

[0093] In some embodiments, an FPGA core control area (approximately 3 cm × 3 cm in area) may be located in the central region of a six-layer HDI PCB to house the FPGA chip and peripheral matching circuits, thereby using the FPGA hardware gesture state machine as the system control and data processing hub.

[0094] In some embodiments, the user gesture signal includes at least one of the following: a single-finger swipe gesture signal representing time base scaling, a two-finger pinch gesture signal representing amplitude scaling, a triple-tap gesture signal representing waveform pause, and a long-press gesture signal representing a virtual knob.

[0095] The oscilloscope system can reduce the recognition latency of all gestures such as "single-finger swipe - time base scaling, two-finger pinch - amplitude scaling, triple-click - waveform pause, long press - virtual knob" to <16 ms by using an FPGA hardware gesture state machine. This allows the elimination of all mechanical knobs / buttons and saves 40% of the front panel area.

[0096] In some embodiments, the field-programmable gate array hardware gesture state machine also employs 512-point parallel template matching and derivative template dual-channel voting hardware to output waveform category labels within a preset time after the sampling completion interruption to drive trigger control or alarm.

[0097] The oscilloscope system can use an FPGA hardware gesture state machine with 512-point parallel template matching + derivative template dual-channel voting hardware to output "sine / square / triangle wave" category labels within a preset time (e.g., 6.6 µs) after the sampling completion interruption, directly driving trigger / alarm. The recognition delay is reduced by three orders of magnitude compared to desktop PC solutions.

[0098] In some embodiments, the field-programmable gate array hardware gesture state machine includes: A pool of multiple distributed static random access memory blocks is used to perform real-time storage status management operations on the same clock edge. The real-time storage status management operations include dynamically selecting storage unit addresses, real-time counting of the number of occupied storage units, and indicating whether the maximum storage capacity has been reached.

[0099] In some embodiments, the multi-block distributed static random access memory pool can be a 32-block distributed SRAM pool.

[0100] The oscilloscope system can build a 32-block distributed SRAM pool inside the FPGA, and combine the three core operations of "address selection - used count - saturation flag" into the same clock edge (10 ns) to dynamically select the memory cell address, count the number of occupied memory cells in real time, and indicate whether the maximum storage capacity has been reached.

[0101] For example, in the core control area of ​​an FPGA in a six-layer HDI PCB design, the FPGA chip can be placed in the center and surrounded by related logic units of the distributed SRAM pool (storage modules based on LUT reconstruction), thereby shortening the interconnection path between the FPGA and the SRAM pool and ensuring nanosecond-level data interaction latency.

[0102] In some embodiments, the multi-block distributed static random access memory pool uses cyclic shifting to balance the load of each block, or the multi-block distributed static random access memory pool uses priority encoding to allocate the load of each block concurrently in one go.

[0103] The oscilloscope system can use an FPGA hardware gesture state machine to balance the load of each block under normal load by using cyclic shifting, and to use priority coding to concurrently allocate all available blocks to balance the load under high load.

[0104] This embodiment constructs a distributed SRAM pool of 32 blocks inside the FPGA, merging the three core operations of "address selection - used count - saturation flag" into the same clock edge (10 ns). For normal loads, the load of each block is balanced by cyclic shifting, and for high loads, all available blocks are allocated concurrently at once by priority coding. This can reduce the single-cycle latency by 50% in practice compared to related technologies.

[0105] In some embodiments, when the saturation monitoring results of the multiple distributed static random access memory pools meet preset conditions, the system automatically triggers mode switching or generates a shutdown signal. The preset conditions include continuous saturated blocks and insufficient available resources.

[0106] The oscilloscope system can integrate real-time monitoring of SRAM saturation status and automatically trigger mode switching or generate explicit stop signals based on preset conditions, thus providing clear status feedback and a control interface for the system. Specifically, it can automatically trigger mode switching when the saturation status monitoring results of multiple distributed static random access memory (SRAM) pools indicate consecutive saturated blocks. Alternatively, it can generate a stop signal when the saturation status monitoring results indicate insufficient available resources.

[0107] In some embodiments, the front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module operate in the same 50 MHz global clock domain.

[0108] The oscilloscope system can control the front-end signal dual-channel sampling module, edge AI inference module, touch module, dual-mode shared buffer module, and field-programmable gate array hardware gesture state machine, all running in the same 50 MHz global clock domain. Furthermore, the number of ports, SRAM blocks, and template depth are all defined using parameterized Verilog. This allows for rapid scaling to smaller FPGA packages and reuse in multi-channel SoCs, enabling IP-level portability.

[0109] In some embodiments, the portable signal measurement system for multi-scenario needs provided in this application may further include: The Bluetooth remote control module is used to move the parameter settings for automated testing of the system to the user graphical interface of the remote device to run the oscilloscope's automated test mode.

[0110] In terms of communication, oscilloscope systems can incorporate Bluetooth remote control modules to achieve automated testing modes. This means that the automated test parameter settings can be moved to the user's graphical user interface (GUI) on a remote device via the Bluetooth remote control module. This saves space on the oscilloscope's user interface, overcomes distance limitations, and enables a one-click automated testing process.

[0111] Next, a complete embodiment of the portable signal measurement system for multi-scenario needs provided in this application is presented.

[0112] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the overall system framework of the portable signal measurement system for multi-scenario needs provided in an embodiment of this application.

[0113] like Figure 4 As shown, the oscilloscope can be built on the Ziguang MES2L676-200H platform to create a portable dual-channel digital oscilloscope integrating multiple modes such as weak signal detection mode, differential acquisition mode, AI-assisted judgment mode, Bluetooth remote control, and automated testing mode. Among them: The AD9226 module achieves high-precision dual-channel signal acquisition of 65MSPS. Utilizing an extended mode combining a low-noise amplifier (LNA) and a digital lock-in amplifier, it extracts amplitude and phase information of weak signals submerged in noise, enhancing the system's ability to detect weak signals after acquisition. Next, the parameter detection module extracts complex signal features, obtaining waveform parameters including amplitude, frequency, duty cycle, and THD. The FFT module then calculates the real-time spectrum, increasing the dimensionality of waveform signal analysis. The HDMI display module drives a 600×1024 LCD touchscreen, enabling visualized results and interactive touch feedback on a custom-designed UI.

[0114] In terms of communication, oscilloscopes can incorporate Bluetooth remote control modules to enable automated testing modes.

[0115] In some embodiments, the oscilloscope can also achieve four-channel sampling using four ADC modules, resulting in an analog bandwidth of 350MHz and a waveform capture rate of 1.6wf / s. It supports diverse functions such as real-time channel selection display, spectrum display, data interpolation, and waveform pause, enabling high-performance weak signal detection and AI-assisted recognition modes to enhance the oscilloscope's performance. Furthermore, the innovative alternating sampling method increases the oscilloscope's maximum sampling rate from 65MSPS to 260MSPS.

[0116] In this embodiment, the oscilloscope can achieve extremely low latency and high throughput by completing core management operations in a single clock cycle, thereby meeting the stringent requirements of future high-speed networks (such as 400G, 800G and above) for packet buffering. Simultaneously, the oscilloscope can achieve both load balancing under normal random traffic and rapid allocation capabilities under resource constraints through a dual-mode adaptive design.

[0117] This application also provides an electronic device, which includes the portable signal measurement system for multi-scenario needs described in any of the above embodiments. This electronic device can be an ADC data acquisition device or other communication devices requiring high-speed data packet buffering and forwarding, specifically such as AR devices, smartphones, tablets, laptops, desktop computers, and other terminal devices.

[0118] Please see Figure 5 , Figure 5 This illustration shows the hardware structure of an electronic device according to one embodiment. The electronic device includes: The processor 501 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 502 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called and executed by the processor 501 to execute a method for simulating the visual state of a patient with visual impairment using AR collaborative simulation according to an embodiment of this application. The input / output interface 503 is used to implement information input and output; The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504); The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0119] The embodiments described above are for the purpose of more clearly illustrating the technical solutions of this application and do not constitute a limitation on the technical solutions provided in the embodiments of this application. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in this application are also applicable to similar technical problems.

[0120] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0121] The embodiments of this application described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0122] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0123] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0124] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0126] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0128] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A portable signal measurement system for multi-scenario needs, characterized in that, The system includes: A dual-channel front-end signal sampling module is used to simultaneously acquire multiple independent analog electrical signals; An edge AI inference module is used for real-time analysis of the analog electrical signals; The touch module is used for human-computer interaction based on the analog electrical signal and / or the analysis results obtained by real-time analysis of the analog electrical signal; The dual-mode shared cache module is used to provide a unified data storage and access interface for the front-end signal dual-channel sampling module, the edge artificial intelligence inference module, and the touch module; The front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module are all integrated on a single printed circuit board.

2. The system according to claim 1, characterized in that, The system also includes: A field-programmable gate array (FPGA) hardware gesture state machine is used to parse user gesture signals collected by the touch module during human-computer interaction.

3. The system according to claim 2, characterized in that, The user gesture signals include at least one of the following: a single-finger swipe gesture signal representing time base scaling, a two-finger pinch gesture signal representing amplitude scaling, a triple-tap gesture signal representing waveform pause, and a long-press gesture signal representing a virtual knob.

4. The system according to claim 2, characterized in that, The field-programmable gate array hardware gesture state machine also employs 512-point parallel template matching and derivative template dual-channel voting hardware. After the sampling is completed and interrupted, it outputs waveform category labels within a preset time to drive trigger control or alarm.

5. The system according to claim 2, characterized in that, The field-programmable gate array hardware gesture state machine includes: A pool of multiple distributed static random access memory blocks is used to perform real-time storage status management operations on the same clock edge. The real-time storage status management operations include dynamically selecting storage unit addresses, real-time counting of the number of occupied storage units, and indicating whether the maximum storage capacity has been reached.

6. The system according to claim 5, characterized in that, The multi-block distributed static random access memory pool uses cyclic shifting to balance the load of each block, or the multi-block distributed static random access memory pool uses priority encoding to allocate the load of each block concurrently in one go.

7. The system according to claim 5, characterized in that, When the saturation monitoring results of the multiple distributed static random access memory pools meet preset conditions, the system automatically triggers mode switching or generates a shutdown signal. The preset conditions include consecutive saturated blocks and insufficient available resources.

8. The system according to claim 1, characterized in that, The front-end signal dual-channel sampling module, the edge artificial intelligence inference module, the touch module, and the dual-mode shared cache module all operate in the same 50 MHz global clock domain.

9. The system according to any one of claims 1 to 8, characterized in that, The system also includes: The Bluetooth remote control module is used to move the parameter settings for automated testing of the system to the user graphical interface of the remote device to run the oscilloscope's automated test mode.

10. An electronic device, characterized in that, The electronic device includes a portable signal measurement system for multi-scenario needs as described in any one of claims 1 to 9.

Images