Gate oxide layer state monitoring method and circuit of field effect transistor

Abstract

The invention relates to a gate oxide state monitoring method and circuit of a field effect transistor, and belongs to the technical field of power electronics, and the method comprises the steps: obtaining a drain current signal of a to-be-monitored field effect transistor in a switching-on transient process; determining the current rise time of a field effect transistor based on the drain current signal; wherein the current rising time is the time that the drain current rises from the flowing start time to the load current time; and comparing the current rise time with a preset health reference time, and outputting an indication signal reflecting the reliability state of the gate oxide layer based on a comparison result. According to the method provided by the invention, non-intrusive online real-time monitoring is realized by taking the current rise time as a gate oxide degradation specificity monitoring parameter, collecting the drain current signal in the device turn-on transient state and comparing the drain current signal with the health reference time.

Description

Technical Field

[0001] This application belongs to the field of power electronics technology and relates to a method and circuit for monitoring the state of the gate oxide layer of a field-effect transistor. Background Technology

[0002] Field-effect transistors (FETs), as core components of power electronics, have broad application prospects in power electronic circuits for renewable energy generation, rail transportation, electric vehicles, and aerospace. The reliability of these devices directly determines the operational stability and lifespan of power electronic systems, with the reliability of the gate oxide layer being a key bottleneck restricting the long-term stable operation of these devices.

[0003] The gate oxide layer of a field-effect transistor (FET) is a key structure for controlling the gate voltage and drain current switching. Its degradation mainly stems from the trapping of electrons and holes by interface and near-interface trap charges, as well as the accumulation of oxide trap charges under high temperature and high electric field conditions. These charges can cause threshold voltage drift, leading to problems such as increased on-resistance, increased losses, and parasitic conduction, and even gate oxide breakdown and system failure. Therefore, gate oxide reliability status monitoring is an important means of achieving predictive maintenance and improving system reliability.

[0004] Therefore, there is an urgent need to develop a low-cost, online-implementable field-effect transistor gate oxide reliability status monitoring technology to address the shortcomings of existing technologies. Summary of the Invention

[0005] This application provides a method and circuit for monitoring the gate oxide state of a field-effect transistor. By using the current rise time as a specific monitoring parameter for gate oxide degradation, the transient drain current signal during device turn-on is collected and compared with the health reference time, achieving non-invasive online real-time monitoring. This solves the shortcomings of existing technologies, such as requiring specific test conditions, high invasiveness, high cost, and easy interference with normal circuit operation.

[0006] In a first aspect, this application provides a method for monitoring the state of the gate oxide layer of a field-effect transistor, comprising: acquiring the drain current signal of the field-effect transistor under monitoring during the turn-on transient process; determining the current rise time of the field-effect transistor based on the drain current signal; wherein the current rise time is the time taken for the drain current to rise from the moment it begins to flow to the moment the load current rises; comparing the current rise time with a preset health reference time, and outputting an indication signal reflecting the reliability state of the gate oxide layer based on the comparison result.

[0007] In some embodiments of this application, the method for obtaining the drain current signal includes: connecting a detection resistor in series with the source of a field-effect transistor, and obtaining a drain current signal proportional to the detection voltage by detecting the detection voltage signal across the detection resistor.

[0008] In some embodiments of this application, the method for determining the current rise time includes: presetting a first reference voltage and a second reference voltage; wherein the second reference voltage is set according to the value of the load current; detecting changes in the detection voltage signal using a first comparator and a second comparator; taking the moment when the detection voltage reaches the first reference voltage as the moment when the drain current begins to flow; taking the moment when the detection voltage reaches the second reference voltage as the moment when the drain current rises to the load current; and calculating the time difference between the moment when the detection voltage reaches the first reference voltage and the moment when the detection voltage reaches the second reference voltage as the current rise time.

[0009] In some embodiments of this application, the method for monitoring the gate oxide state of a field-effect transistor further includes: inputting a detection voltage signal and a first reference voltage signal to the input terminal of the first comparator, and outputting a first comparison signal; triggering a monostable pulse generator by the transition edge of the first comparison signal, causing the monostable pulse generator to generate a square wave pulse; wherein the pulse width of the square wave pulse is the same as the health reference time; inputting the square wave pulse and a second comparison signal output by the second comparator into a logic AND operation circuit, wherein the logic AND operation circuit outputs an intermediate signal reflecting the reliability state of the gate oxide layer.

[0010] In some embodiments of this application, the method for monitoring the gate oxide state of a field-effect transistor further includes: when the current rise time is less than or equal to the health reference time, the rising edge of the second comparison signal falls during the high level period of the square wave pulse, and the logic AND operation circuit outputs a high-level pulse intermediate signal reflecting the health of the gate oxide layer; when the current rise time is greater than the health reference time, the rising edge of the second comparison signal falls during the low level period of the square wave pulse, and the logic AND operation circuit outputs a low-level intermediate signal reflecting the degradation of the gate oxide layer.

[0011] In some embodiments of this application, the method for monitoring the state of the gate oxide layer of a field-effect transistor further includes: inputting an intermediate signal output by the logic AND operation circuit into a pulse shaping circuit; when the intermediate signal is a periodic short-term high-level pulse, the pulse shaping circuit converts the periodic short-term high-level pulse into a constant high-level intermediate signal; when the intermediate signal is a continuous low level, the pulse shaping circuit maintains the output of a constant low-level intermediate signal.

[0012] In some embodiments of this application, the method for monitoring the state of the gate oxide layer of a field-effect transistor further includes: calculating a filtered current rise time value based on multiple detected current rise times using a digital filtering algorithm; calculating a gate oxide degradation index of the gate oxide layer based on the current rise time value and the current rise time value under the healthy state of the gate oxide layer; and outputting an indication signal reflecting the reliability state of the gate oxide layer based on the magnitude of the gate oxide degradation index.

[0013] In some embodiments of this application, the method for monitoring the gate oxide state of a field-effect transistor further includes: presetting a first gate oxide degradation threshold and a second gate oxide degradation threshold, wherein the first gate oxide degradation threshold is less than the second gate oxide degradation threshold; and outputting an indication signal based on the relationship between the gate oxide degradation index and the first and second gate oxide degradation thresholds: when the gate oxide degradation index is less than or equal to the first gate oxide degradation threshold, outputting a signal reflecting the health of the gate oxide layer; when the gate oxide degradation index is greater than the first gate oxide degradation threshold and less than or equal to the second gate oxide degradation threshold, outputting a signal reflecting the degradation of the gate oxide layer; and when the gate oxide degradation index is greater than the second gate oxide degradation threshold, outputting a signal reflecting the degradation of the gate oxide layer and a signal indicating that the circuit containing the field-effect transistor is shut down.

[0014] In some embodiments of this application, the method for monitoring the gate oxide state of a field-effect transistor further includes: the detected voltage signal is amplified and noise suppressed by a differential amplifier before being input to the first comparator and the second comparator.

[0015] Secondly, this application provides a gate oxide state monitoring circuit for implementing the above method of a field-effect transistor, comprising: a signal extraction circuit for acquiring the drain current signal of the field-effect transistor under test during the turn-on transient process; a comparison circuit for extracting the current rise time of the field-effect transistor and comparing the current rise time with a preset health reference time; and a state output circuit for outputting an indication signal reflecting the reliability state of the gate oxide layer according to the comparison result.

[0016] The gate oxide state monitoring method and circuit of the field-effect transistor provided in this application have at least the following beneficial effects:

[0017] High monitoring specificity: With current rise time as the core parameter, its change is only related to gate oxide degradation, which can accurately target and reflect the state of the gate oxide layer and avoid interference factors from affecting the monitoring results.

[0018] Non-invasive online monitoring: By sampling the drain current signal through a series detection resistor, no changes to the main circuit topology or insertion of additional test components are required. It does not interfere with the normal operation of the field-effect transistor and can achieve real-time dynamic monitoring.

[0019] Accurate parameter extraction and anti-interference: The design adopts dual comparator collaborative detection, differential amplifier noise reduction, digital filtering and other features, combined with hysteresis voltage configuration and electrical isolation measures, to effectively resist electromagnetic interference and noise and ensure the accuracy of current rise time extraction.

[0020] The state judgment logic is simple and reliable: timing comparison is achieved through a monostable pulse generator and a logic AND operation circuit, and a stable signal is output by a pulse shaping circuit. No complex signal processing is required, and the state distinction is intuitive and clear.

[0021] Tiered early warning is more suitable for operation and maintenance: Based on the gate oxide degradation index, multiple thresholds are set to support tiered status management of healthy, mild degradation and severe degradation, providing a quantitative basis for differentiated predictive maintenance, and taking into account both reliability and economy.

[0022] Low cost and easy integration: It reuses existing microcontroller resources, and the core circuit only requires general-purpose components, resulting in low hardware costs. It can be flexibly integrated into existing converters or designed as an independent module, making it highly practical for engineering applications.

[0023] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more apparent, specific embodiments of this application are given below. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating the gate oxide state monitoring method for the field-effect transistor of this application. Detailed Implementation

[0026] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0027] The prefixes such as "first" and "second" used in this application embodiment are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this application embodiment does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not constitute unnecessary restrictions due to the use of such prefixes. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0028] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0029] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0030] Field-effect transistors (FETs), as core components of power electronics, have broad application prospects in power electronic circuits for renewable energy generation, rail transportation, electric vehicles, and aerospace. The reliability of these devices directly determines the operational stability and lifespan of power electronic systems, with the reliability of the gate oxide layer being a key bottleneck restricting the long-term stable operation of these devices.

[0031] The gate oxide layer of a field-effect transistor (FET) is a key structure for controlling the gate voltage and drain current switching. Its degradation mainly stems from the trapping of electrons and holes by interface and near-interface trap charges, as well as the accumulation of oxide trap charges under high temperature and high electric field conditions. These charges can cause threshold voltage drift, leading to problems such as increased on-resistance, increased losses, and parasitic conduction, and even gate oxide breakdown and system failure. Therefore, gate oxide reliability status monitoring is an important means of achieving predictive maintenance and improving system reliability.

[0032] In recent years, although some gate oxide state detection methods have emerged in this field, they still have significant shortcomings: monitoring parameters (such as threshold voltage, gate leakage current, and gate capacitance) require specific test conditions, making it difficult to achieve online real-time monitoring, and may interfere with the normal operation of the circuit; the monitoring methods are invasive, requiring the insertion of additional test components or circuits, increasing circuit complexity and cost, and affecting circuit performance stability; they rely on high-precision test instruments and complex circuits, resulting in high hardware and calibration maintenance costs, which restricts large-scale application.

[0033] Therefore, to address the shortcomings of existing technologies, this embodiment proposes a method for monitoring the gate oxide state of a field-effect transistor, comprising: Acquire the drain current signal of the field-effect transistor under test during the turn-on transient process; Based on the drain current signal, the current rise time of the field-effect transistor is determined; where the current rise time is the time it takes for the drain current to rise from the moment it starts flowing to the moment the load current is reached. The current rise time is compared with a preset health reference time, and based on the comparison result, an indication signal reflecting the reliability status of the gate oxide layer is output.

[0034] This method uses current rise time as the monitoring parameter, which can accurately reflect the degradation of gate oxide, supports online non-intrusive monitoring without interfering with the operation of the main circuit, and can achieve monitoring by reusing existing microcontroller resources. It has low hardware cost and is easy to integrate, and provides clear status indication, which can effectively help predictive maintenance and improve the reliability of power electronic systems.

[0035] Compared to traditional silicon-based semiconductor materials, SiC MOSFETs (silicon carbide metal-oxide-semiconductor field-effect transistors), as a wide bandgap material, possess advantages such as a higher band gap, greater breakdown electric field strength, and better thermal conductivity, making them promising for applications in power electronic circuits in renewable energy generation, rail transportation, electric vehicles, and aerospace. Based on this, this embodiment will use SiC MOSFETs as a specific application to provide a detailed explanation of the technical solution for monitoring the gate oxide state of field-effect transistors.

[0036] In the above method, the drain current signal during the turn-on transient process is the waveform of the current change from the drain to the source during the brief process of the SiC MOSFET changing from off to on. The load current is the rated operating current flowing from the drain to the source of the SiC MOSFET during normal operation. The threshold voltage is the minimum gate voltage at which a conductive channel is formed inside the SiC MOSFET and the device begins to conduct.

[0037] The principle of the turn-on transient process of SiC MOSFET is as follows: When SiC MOSFET is turned on, the gate power supply voltage needs to charge the input capacitor first, and the charging speed is determined by the size of the input capacitor; when the gate voltage rises to the threshold voltage, a conductive channel is formed inside the SiC MOSFET, and the drain current begins to flow to the source; when the drain current rises from the beginning of the flow to the load current, the SiC MOSFET becomes conductive.

[0038] Calculate the circuit rise time using a computational formula: Time for the gate voltage to reach the threshold voltage t 1 is: ,in, R G C iss The charging time constant. V GS This is the gate power supply voltage. V TH This is the threshold voltage.

[0039] The time from when the gate supply voltage begins to charge the input capacitor until the drain current rises to the load current. t 2 is: ,in, V MP This is the Miller plateau voltage.

[0040] Current rise time t ir for: .

[0041] Therefore, it can be concluded that the current rise time is related to the threshold voltage. The degradation of the gate oxide layer of SiC MOSFET will cause the threshold voltage to drift. Therefore, the degradation of the gate oxide layer of SiC MOSFET can be monitored by monitoring the current rise time.

[0042] In some embodiments, the method for obtaining a drain current signal includes: connecting a detection resistor in series with the source of a field-effect transistor, and obtaining a drain current signal proportional to the detection voltage through the detection voltage signal across the detection resistor.

[0043] In some embodiments, to accurately extract the current rise time that reflects the gate oxide degradation state, this scheme designs a parameter extraction logic based on the proportional relationship between drain current and detection voltage, using dual comparators for collaborative detection. The method for determining the current rise time includes: A first reference voltage and a second reference voltage are preset; wherein, the second reference voltage is set according to the value of the load current; Changes in the detection voltage signal are detected by a first comparator and a second comparator. The moment when the detected voltage reaches the first reference voltage is taken as the moment when the drain current begins to flow; the moment when the detected voltage reaches the second reference voltage is taken as the moment when the drain current rises to the load current. The time difference between the moment when the detected voltage reaches the first reference voltage and the moment when the detected voltage reaches the second reference voltage is calculated as the current rise time.

[0044] This method achieves non-invasive signal acquisition by using series sampling of the detection resistor and collaborative detection with dual comparators. It has strong anti-interference capabilities, high monitoring accuracy, and can track the grid oxide degradation process in real time, significantly reducing monitoring costs and integration difficulty, and improving the operational reliability of power electronic systems.

[0045] In some embodiments, the detected voltage signal is amplified and noise-suppressed by a differential amplifier before being input to the first and second comparators. A differential amplifier with a high common-mode rejection ratio is selected, its function being to accurately extract weak, effective signals related to the drain current in complex power electronic environments.

[0046] In some embodiments, after determining the specific current rise time, it needs to be compared with a health reference time to determine the reliability status of the gate oxide layer. After the first comparator receives the detection voltage signal and the first reference voltage signal at its input terminal, it outputs the first comparison signal. The monostable pulse generator is triggered by the rising edge of the first comparison signal, causing it to generate a square wave pulse; wherein the pulse width of the square wave pulse is the same as the healthy reference time. The square wave pulse and the second comparison signal output by the second comparator are input into the logic AND operation circuit, and the logic AND operation circuit outputs an intermediate signal reflecting the reliability status of the gate oxide layer.

[0047] The above method triggers a square wave pulse matching the health reference time by the edge of the first comparison signal, and performs a logical AND operation with the second comparison signal to output an intermediate status signal. The comparison logic is simple and accurate, with strong anti-interference ability. It does not require complex hardware and signal processing, is low-cost and easy to integrate, and can quickly provide feedback on the gate oxide reliability status.

[0048] In some embodiments, the AND logic circuit uses AND gates as its core functional element, and its operational logic is as follows: When the current rise time is less than or equal to the health reference time, the rising edge of the second comparison signal falls during the high level period of the square wave pulse. According to the logic rule of AND gate "output high level when both inputs are high level", the logic AND operation circuit outputs a high-level pulse intermediate signal reflecting the health of the gate oxide layer. When the current rise time is greater than the health reference time, and the rising edge of the second comparison signal falls during the low level period of the square wave pulse, according to the logic rule of AND gate "output low level when any input is low level", the logic AND operation circuit outputs a low level intermediate signal reflecting the degradation of the gate oxide layer.

[0049] In some embodiments, in order to provide a stable, jitter-free status indication signal to drive an alarm device or for reading by a control module, the output signal needs to be shaped. Specific methods include: The intermediate signal output from the AND operation circuit is input into the pulse shaping circuit; When the intermediate signal is a periodic short high-level pulse, the pulse shaping circuit converts the periodic short high-level pulse into a constant high-level intermediate signal; when the intermediate signal is a continuous low level, the pulse shaping circuit maintains the output of a constant low-level intermediate signal.

[0050] In some embodiments, the constant-level intermediate signal output by the pulse shaping circuit can be directly input to LED indicators, optocouplers, and the general-purpose input / output (GPIO) pins of the microcontroller. The LED indicators visually represent the gate oxide status of the device (e.g., green indicates health, red indicates degradation); the optocouplers provide electrical isolation and level matching for the signal; and the microcontroller can further process the signal (e.g., linking to system alarms, recording degradation data). This flexibly meets the status indication, signal isolation, or subsequent control requirements of different application scenarios, improving the interface compatibility and practical adaptability of the monitoring system.

[0051] In some embodiments, to further improve the reliability of gate oxide state monitoring, the current rise time sequence measured during multiple turn-on processes of the SiC MOSFET is digitally filtered using algorithms such as moving average filtering or median filtering to calculate the filtered current rise time value, thereby eliminating occasional interference pulses. ;in, This is the filtered current rise time value. This is a sample of the current rise time. This represents the number of samples taken during the current rise time.

[0052] Furthermore, after determining the current rise time value, the gate oxide degradation index (GODI) of the gate oxide layer is calculated based on the filtered current rise time value and the current rise time value under healthy gate oxide conditions. ,in, This represents the current rise time value under healthy gate oxide conditions. Based on the magnitude of the gate oxide degradation index, an indication signal reflecting the reliability status of the gate oxide layer is output.

[0053] By calculating the gate oxide degradation index periodically (or in each monitoring cycle), a trend curve showing how the index changes with operating time or the number of power cycle stress accumulations can be plotted, intuitively presenting the degradation evolution of the gate oxide layer of SiC MOSFET. This enables precise tracking and dynamic control of the gate oxide degradation process, providing continuous and reliable data support for subsequent predictive maintenance.

[0054] In some embodiments, accelerated aging experiments can be conducted on the gate oxide of SiC MOSFETs in the early stages to establish a failure model that correlates the gate oxide degradation index with the degree of gate oxide degradation and remaining lifetime. Subsequently, based on this model, multiple grading thresholds can be set to accurately classify the gate oxide layer into healthy, mildly degraded, and severely degraded states, enabling graded identification and dynamic control of the gate oxide state. This provides precise quantitative data support for developing differentiated predictive maintenance strategies, balancing equipment reliability and maintenance economy. Specific methods include: A first gate oxide degradation threshold and a second gate oxide degradation threshold are preset, wherein the first gate oxide degradation threshold is less than the second gate oxide degradation threshold; Based on the relationship between the gate oxide degradation index and the first and second gate oxide degradation thresholds, the following indication signals are output: when the gate oxide degradation index is less than or equal to the first gate oxide degradation threshold, a signal reflecting the health of the gate oxide layer is output; when the gate oxide degradation index is greater than the first gate oxide degradation threshold and less than or equal to the second gate oxide degradation threshold, a signal reflecting the degradation of the gate oxide layer is output; when the gate oxide degradation index is greater than the second gate oxide degradation threshold, a signal reflecting the degradation of the gate oxide layer and a signal indicating that the circuit containing the field-effect transistor is shut down are output.

[0055] For example, taking a first gate oxide degradation threshold of 0.1 and a second gate oxide degradation threshold of 0.2 as an application scenario, when the gate oxide degradation index is less than or equal to 0.1, For example, the first gate oxide degradation threshold is set to 0.1, and the second gate oxide degradation threshold is set to 0.2, thereby accurately dividing the three-level state of the gate oxide layer: When GODI≤0.1, it is judged as "healthy state", indicating that there is no obvious degradation of the gate oxide layer, the device performance is stable, and it can maintain normal operation rhythm, only needing to be continuously tracked according to the regular monitoring cycle; when 0.1<GODI≤0.2, it is judged as "mild degradation state", indicating that the gate oxide layer has begun to accumulate initial defects. Although it has not affected the normal operation of the current device, it is necessary to start the enhanced monitoring mechanism, shorten the monitoring cycle, track the degradation rate changes in real time, and simultaneously assess the impact of the operating load on the degradation process to provide data support for the formulation of preventive maintenance plans; when GODI>0.2, it is judged as "severe degradation state", meaning that the gate oxide layer defects have accumulated in large quantities, and problems such as threshold voltage drift and increased drain current are approaching the critical value that affects the safe operation of the circuit. At this time, an alarm signal needs to be triggered immediately, and the entire system should be linked to start the shutdown protection or device switching process to avoid circuit failure, equipment damage, or even more serious safety risks due to gate oxide failure.

[0056] In some embodiments, to accurately capture the nanosecond-level current change frontier, the comparator is selected from the TLV3501 series, which has short propagation delay and fast response speed. Its high-speed response characteristics can ensure accurate positioning of the start time and peak time of current rise, providing a reliable timing basis for subsequent time difference calculation and gate oxide degradation index derivation.

[0057] In some embodiments, to resist electromagnetic noise interference generated during switching and to avoid false triggering of the comparator, a reasonable hysteresis voltage needs to be configured for the first comparator and the second comparator. Specifically, a positive feedback resistor network is built between the output terminal and the non-inverting input terminal of the comparator. Through this network, a stable threshold hysteresis characteristic is formed, ensuring that the comparator only generates a level flip when the input signal meets the actual triggering condition, which significantly improves the circuit's anti-interference capability.

[0058] In addition, to completely isolate the high voltage and high current interference of the main power circuit, the power supply system of the monitoring circuit must adopt an independent isolation power supply module. At the same time, the electrical isolation between the monitoring signal and the main system signal is achieved through a signal isolator, and its signal ground and the main power circuit ground must also be strictly separated. This isolation design is a core technical measure to ensure the safe and stable operation of the main power system, avoid power-side interference coupling to sensitive monitoring circuits, and ensure the accuracy of monitoring data.

[0059] In some embodiments, this application also provides a gate oxide state monitoring circuit for implementing the above method of a field-effect transistor, comprising: The signal extraction circuit is used to acquire the drain current signal of the field-effect transistor under test during the turn-on transient process. The comparator circuit is used to extract the current rise time of the field-effect transistor and compare the current rise time with a preset health reference time. The status output circuit is used to output an indication signal reflecting the reliability status of the gate oxide layer based on the comparison result.

[0060] By setting up the gate oxide state monitoring circuit and method for the aforementioned field-effect transistors, the entire monitoring system adopts a periodic operating mechanism, which can be seamlessly embedded into the control flow of the power converter without modifying the original control logic and hardware topology, ensuring the continuity and stability of the main system operation. The circuit's hardware architecture is simple and cost-effective, relying on only a few mature and commonly used electronic components in its core components, eliminating the need for customized dedicated chips or high-precision, expensive equipment. It also possesses strong adaptability, facilitating direct integration into existing power converter hardware platforms or being designed independently as a standardized modular device to flexibly meet the deployment needs of different application scenarios. Ultimately, this provides a complete solution with scientific, economic, and engineering practical value for real-time health assessment and degradation process tracking of SiC MOSFET gate oxide states, as well as for improving the overall reliability of power electronic systems, and can be directly applied to real-world industrial scenarios.

[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be covered. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for monitoring the state of the gate oxide layer of a field-effect transistor, characterized in that, include: Acquire the drain current signal of the field-effect transistor under test during the turn-on transient process; Based on the drain current signal, the current rise time of the field-effect transistor is determined; wherein, the current rise time is the time taken for the drain current to rise from the moment it begins to flow to the moment the load current rises. The current rise time is compared with a preset health reference time, and based on the comparison result, an indication signal reflecting the reliability status of the gate oxide layer is output.

2. The method for monitoring the gate oxide state of a field-effect transistor according to claim 1, characterized in that, The method for obtaining the drain current signal includes: A detection resistor is connected in series with the source of a field-effect transistor. By detecting the detection voltage signal across the detection resistor, a drain current signal proportional to the detection voltage is obtained.

3. The method for monitoring the gate oxide state of a field-effect transistor according to claim 2, characterized in that, The method for determining the current rise time includes: A first reference voltage and a second reference voltage are preset; wherein, the second reference voltage is set according to the value of the load current; The change in the detection voltage signal is detected by a first comparator and a second comparator; The moment when the detection voltage reaches the first reference voltage is taken as the moment when the drain current begins to flow; the moment when the detection voltage reaches the second reference voltage is taken as the moment when the drain current rises to the load current. The time difference between the moment when the detected voltage reaches the first reference voltage and the moment when the detected voltage reaches the second reference voltage is calculated as the current rise time.

4. The method for monitoring the gate oxide state of a field-effect transistor according to claim 3, characterized in that, include: After the first comparator receives the detection voltage signal and the first reference voltage signal at its input terminal, it outputs the first comparison signal. The monostable pulse generator is triggered by the rising edge of the first comparison signal, causing the monostable pulse generator to generate a square wave pulse; wherein the pulse width of the square wave pulse is the same as the health reference time; The square wave pulse and the second comparison signal output by the second comparator are input into the logic AND operation circuit, and the logic AND operation circuit outputs an intermediate signal reflecting the reliability status of the gate oxide layer.

5. The method for monitoring the gate oxide state of a field-effect transistor according to claim 4, characterized in that, include: When the current rise time is less than or equal to the health reference time, the rising edge of the second comparison signal falls during the high level of the square wave pulse, and the logic AND operation circuit outputs a high-level pulse intermediate signal reflecting the health of the gate oxide layer. When the current rise time is greater than the health reference time, and the rising edge of the second comparison signal falls during the low level period of the square wave pulse, the logic AND operation circuit outputs a low-level intermediate signal reflecting the degradation of the gate oxide layer.

6. The method for monitoring the gate oxide state of a field-effect transistor according to claim 5, characterized in that, include: The intermediate signal output from the logic AND operation circuit is input into the pulse shaping circuit; When the intermediate signal is a periodic short high-level pulse, the pulse shaping circuit converts the periodic short high-level pulse into a constant high-level intermediate signal. When the intermediate signal is continuously low, the pulse shaping circuit maintains a constant low-level intermediate signal output.

7. The method for monitoring the gate oxide state of a field-effect transistor according to claim 3, characterized in that, include: Based on the multiple current rise times obtained from detection, the filtered current rise time value is calculated using a digital filtering algorithm. The gate oxide degradation index of the gate oxide layer is calculated based on the current rise time value and the current rise time value under healthy gate oxide conditions. Based on the magnitude of the gate oxide degradation index, an indication signal reflecting the reliability status of the gate oxide layer is output.

8. The method for monitoring the gate oxide state of a field-effect transistor according to claim 7, characterized in that, include: A first gate oxide degradation threshold and a second gate oxide degradation threshold are preset, wherein the first gate oxide degradation threshold is less than the second gate oxide degradation threshold; Based on the relationship between the gate oxide degradation index and the first and second gate oxide degradation thresholds, an indication signal is output: When the gate oxide degradation index is less than or equal to the first gate oxide degradation threshold, a signal reflecting the health of the gate oxide layer is output. When the gate oxide degradation index is greater than the first gate oxide degradation threshold and less than or equal to the second gate oxide degradation threshold, a signal reflecting the degradation of the gate oxide layer is output. When the gate oxide degradation index is greater than the second gate oxide degradation threshold, a signal reflecting the degradation of the gate oxide layer and a signal indicating that the circuit containing the field-effect transistor is shut down are output.

9. The method for monitoring the gate oxide state of a field-effect transistor according to claim 3, characterized in that, include: The detected voltage signal is amplified and noise suppressed by a differential amplifier before being input to the first comparator and the second comparator.

10. A gate oxide state monitoring circuit for implementing the method of any one of claims 1-9 of a field-effect transistor, characterized in that, include: The signal extraction circuit is used to acquire the drain current signal of the field-effect transistor under test during the turn-on transient process. A comparator circuit is used to extract the current rise time of a field-effect transistor and compare the current rise time with a preset health reference time. The status output circuit is used to output an indication signal reflecting the reliability status of the gate oxide layer based on the comparison result.

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