A method for determining the effective channel length of a device

Abstract

This application provides a method for determining the effective channel length of a device. Based on the correspondence between capacitance and voltage for multiple gate lengths, the inversion layer charge concentration for each gate length is obtained through integration. By linearly fitting (vs) the ratio of inversion layer charge concentration to gate-channel capacitance and the inversion layer charge concentration, the gate oxide capacitance per unit area for each gate length is determined based on the fitting slope. Since capacitance directly affects the channel potential distribution, it is less affected by non-ideal carrier transport factors, achieving accurate extraction. Based on this, the effective channel length of the target device can be determined. This combines advanced extraction technology with a physical model for effective channel length extraction, accurately determining and calculating the effective channel length, thus achieving reliable and accurate characterization of the effective channel length.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for determining the effective channel length of a device. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve and device dimensions shrink, novel structures such as fully depleted silicon-on-insulator (FDSOI) have attracted widespread attention due to their excellent segment channel effect suppression capabilities and low power consumption. In these advanced devices, to further improve performance and reduce power consumption, low-doped or even near-intrinsic channel regions are commonly used, while the equivalent oxide thickness (EOT) of the gate oxide has also been reduced to ultra-thin scales. This characteristic presents new challenges to the accurate extraction of key device parameters, leading to a shift in the traditional effective channel length (FCL). The determination of ) has a large error, which makes it difficult to meet the increasingly higher requirements of process monitoring and device modeling. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a method for determining the effective channel length of a device, which achieves reliable and accurate characterization of the effective channel length.

[0004] This application provides a method for determining the effective channel length of a device, the method comprising:

[0005] The gate channel capacitance of the device under test with different gate lengths is tested under different gate voltages to obtain the capacitance-voltage correspondence for the multiple gate lengths respectively.

[0006] Based on the capacitor-voltage correspondence, an integral operation based on the gate voltage is performed on the gate-channel capacitance to obtain the inversion layer charge concentration corresponding to the plurality of gate lengths respectively;

[0007] By linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, the gate oxide capacitance per unit area corresponding to the plurality of gate lengths is determined based on the fitting slope.

[0008] Based on the plurality of gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area, the actual inversion layer capacitance corresponding to each of the plurality of gate lengths is calculated.

[0009] By performing a linear fit on the actual inversion layer capacitance and the plurality of gate lengths, the error between the gate length and the effective channel length under the plurality of gate lengths is determined based on the fitting intercept.

[0010] For the target device in the device under test, the target device has a first length among the plurality of gate lengths, and the effective channel length of the target device is determined based on the first length and the error amount corresponding to the first length.

[0011] As one possible implementation, the step of calculating the actual inversion layer capacitance corresponding to each of the plurality of gate lengths based on the plurality of gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area includes:

[0012] For the second length among the plurality of gate lengths, the product of the second length, the channel width of the device under test, and the gate oxide capacitance per unit area corresponding to the second length is taken as the actual inversion layer capacitance corresponding to the second length.

[0013] As one possible implementation, the step of determining the gate oxide capacitance per unit area corresponding to each of the plurality of gate lengths based on the slope of linear fitting of the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration includes:

[0014] By linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, the reciprocal of the fitting slope is used as the gate oxide capacitance per unit area corresponding to the plurality of gate lengths.

[0015] In one possible implementation, the device under test includes a plurality of first devices, the gate length of each of the first devices being the third of the plurality of gate lengths, and the correspondence of the capacitor voltages under the plurality of gate lengths being the correspondence of the capacitor voltages of a single device under the plurality of gate lengths.

[0016] The step of performing gate channel capacitance tests on devices under test with different gate lengths at different gate voltages to obtain the capacitance-voltage correspondences for the multiple gate lengths includes:

[0017] The gate channel capacitance of the multiple first devices connected in parallel is tested under different gate voltages to obtain the total capacitance-voltage relationship under the third length.

[0018] Based on the correspondence between the number of the first devices and the total capacitor voltage, the correspondence between the capacitor voltage of a single device under the third length is determined.

[0019] In one possible implementation, in the plurality of first devices connected in parallel, the gates of the plurality of first devices are connected together, the sources of the plurality of first devices are connected together, and the drains of the plurality of first devices are connected together.

[0020] As one possible implementation, the third length is less than or equal to 200 nm.

[0021] As one possible implementation, the third length is less than or equal to 100 nm.

[0022] In one possible implementation, the device under test includes a substrate, a buried oxide layer and a channel layer sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source electrode and a drain electrode located on opposite sides of the channel layer.

[0023] As one possible implementation, the thickness of the buried oxide layer ranges from 20-25 nm, and / or the thickness of the channel layer is less than or equal to 12 nm, and / or the doping concentration of the channel layer ranges from 1 × 10⁻⁶. 15 ~1×10 16 cm - ³.

[0024] As one possible implementation, the gate voltage ranges from -0.2V to 1V.

[0025] This application provides a method for determining the effective channel length of a device, which involves applying different gate voltages to devices under test with different gate lengths. Gate channel capacitance under ) ) tests were conducted to obtain multiple gate lengths ( The corresponding capacitance-voltage relationship (e.g., CV curve) is used to determine the gate-channel capacitance (GCC). ) based on gate voltage ( The integral operation yields the inversion layer charge concentrations corresponding to multiple gate lengths. By analyzing the ratio of inversion layer charge concentration to gate channel capacitance (...) ), and inversion layer charge concentration ( Perform linear fitting ( vs Based on the fitting slope, the gate oxide capacitance per unit area corresponding to multiple gate lengths is determined. Thus, due to the direct influence of capacitance on the channel potential distribution, the effects of non-ideal carrier transport factors are relatively small, making it easier to determine the accurate inversion layer charge concentration in short-channel devices. ) and gate oxide capacitance per unit area ( This effectively avoids the gate oxide capacitance per unit area caused by the inability of the CV curve to saturate. Extraction error.

[0026] Based on this, the actual inversion layer capacitance corresponding to each of the multiple gate lengths can be calculated according to the multiple gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area. ), by performing linear fitting on the actual inversion layer capacitance and multiple gate lengths ( vs Based on the fitted intercept, the gate length is determined under multiple gate lengths. ) and effective channel length ( The error between ) (Δ L Furthermore, for the target device in the device under test, the target device has a first length among multiple gate lengths. Based on the first length and the error amount corresponding to the first length, the effective channel length of the target device is determined. This enables the calculation of the effective channel length of the device. This allows for the calculation of the advanced gate oxide capacitance per unit area (…). By combining the extraction technology with the physical model for effective channel length extraction, the accurate gate oxide capacitance per unit area can be determined. Based on this, the accurate effective channel length can be calculated, thus realizing a reliable and accurate characterization of the effective channel length, which is of great significance for improving process control, optimizing device models and accelerating product development. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A flowchart of a method for determining the effective channel length of a device according to an embodiment of this application is shown;

[0029] Figure 2 A schematic diagram of multiple first devices connected in parallel, provided for an embodiment of this application;

[0030] Figure 3 A schematic diagram of a CV curve provided for an embodiment of this application;

[0031] Figure 4 An embodiment provided in this application vs A schematic diagram of the fitting process;

[0032] Figure 5 This application provides a schematic diagram of fitting results for gate oxide capacitances corresponding to multiple gate lengths in an embodiment of the present application.

[0033] Figure 6 An embodiment provided in this application vs Draw a schematic diagram of the curve. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] Currently, in order to further improve performance and reduce power consumption, these advanced devices commonly employ low-doped or even near-intrinsic channel regions, while the equivalent oxide thickness (EOT) of the gate oxide has also been reduced to an ultra-thin scale. This characteristic brings new challenges to the accurate extraction of key device parameters, resulting in significant errors in the traditional determination of the effective channel length, making it difficult to meet the increasingly demanding requirements of process monitoring and device modeling.

[0038] Extracting the effective channel length from the current-voltage (IV) characteristics ( Classical methods such as the shift-and-ratio method, the Y-function method, and the transmission line method (TLM) suffer from significant limitations in accuracy when applied to short-channel FDSOI devices. This is primarily because, with extremely short channel lengths, the effective mobility and threshold voltage of the device are highly sensitive to changes in channel length, exhibiting a strong short-channel dependence. This non-ideal characteristic causes severe deviations in traditional IV extraction models based on long-channel assumptions or constant electrical parameters (constant threshold voltage and mobility, etc.), leading to… The extraction results have significant errors and are difficult to meet the ever-increasing accuracy requirements of process monitoring and device modeling.

[0039] Taking the Y-function method as an example, it is a method for transferring characteristic curves from the linear region ( - Extracting the threshold voltage () ) and low field mobility ( The classic method, and can be indirectly used to evaluate In the formulation of this model, the function Y and Maintaining a linear dependency, as shown in Equation 1:

[0040] (Formula 1)

[0041] in, This refers to the drain current. Transconductance. It has low-field mobility. W represents the gate oxide capacitance per unit area, and W represents the channel width. This is the drain voltage relative to the source voltage. For the effective channel length, This refers to the gate voltage. This is the threshold voltage.

[0042] Slope extracted by linear fitting Assuming the mask defines the gate length ( ) and effective channel length Maintaining a constant error (ΔL), linear fitting is used. and The X-intercept of its linear fit is ΔL, which leads to the following: –ΔL.

[0043] However, this approach strongly relies on low field mobility. The classical method of the Y-function assumes a constant. In short-channel devices, mobility is strongly dependent on the channel length due to factors such as high field effects, velocity saturation, reduced impurity scattering, and low-temperature characteristics. This violates the premise of the Y-function method, leading to… and Significant errors occurred during extraction.

[0044] In contrast, extracting from CV characteristics The physical basis of this method lies in the direct response of the capacitor to the channel potential distribution, which is relatively less affected by non-ideal factors in carrier transport and is theoretically more suitable for advanced devices with small feature sizes and complex electrical behavior. In capacitance-voltage (CV) characteristic measurements, the intrinsic channel capacitance of a MOSFET (… In the strongly inverted state, the effective channel length As shown in Formula 2, the positive equation is positive.

[0045] (Formula 2)

[0046] in, This is the total inversion layer capacitance, the true total capacitance from the gate to the inversion layer channel, and also the true intrinsic channel capacitance, typically the saturation capacitance shown in the CV curve. This is achieved by separating the overlay capacitance (…). ), and you can get Capacitance is the response of charge to voltage and is independent of transport mechanisms such as carrier mobility and velocity saturation, thus avoiding the fundamental difficulties of the IV method in short channels.

[0047] However, due to the limited channel carrier concentration caused by the low-doped channel and the enhanced quantum confinement and tunneling effects brought about by the ultra-thin EOT, even at a larger gate voltage ( Under bias, the capacitance in the accumulation region or strong inversion region is also difficult to reach the saturation plateau expected by traditional theory. This "non-saturation" phenomenon in the CV curve directly affects the capacitance per unit area of ​​the gate oxide layer. The precise calibration of the EOT value is crucial, as these two parameters form the basis for extracting many subsequent electrical parameters, including those based on differential or integral capacitance. The extraction thus affects The accuracy of extraction.

[0048] Therefore, the industry urgently needs an effective channel length extraction method that can overcome the aforementioned limitations and is suitable for advanced node FDSOI FETs. This method can properly handle the unsaturated characteristics of the CV curve and establish a more accurate... Extracting models improves the accuracy and reliability of parameter extraction, providing a more solid data foundation for process development, device modeling, and circuit design. In practice, this may require... Even under unknown circumstances, it can still reliably reduce the total capacitance ( The overlay capacitance and intrinsic channel capacitance are separated from the )

[0049] Based on the above technical problems, this application provides a method for determining the effective channel length of a device. This method involves testing the gate channel capacitance of devices under test with different gate lengths at different gate voltages to obtain multiple gate lengths. The corresponding capacitance-voltage relationship (e.g., CV curve) is used to calculate the gate-channel capacitance based on the gate voltage, yielding the inversion layer charge concentration corresponding to each gate length. By analyzing the ratio of inversion layer charge concentration to gate channel capacitance (...) ), and inversion layer charge concentration ( Perform linear fitting ( vs Based on the fitting slope, the gate oxide capacitance per unit area corresponding to multiple gate lengths is determined. Thus, due to the direct influence of capacitance on the channel potential distribution, the effects of non-ideal carrier transport factors are relatively small, making it easier to determine the accurate inversion layer charge concentration in short-channel devices. ) and gate oxide capacitance per unit area ( This effectively avoids the gate oxide capacitance per unit area caused by the inability of the CV curve to saturate. Extraction error.

[0050] Based on this, the actual inversion layer capacitance corresponding to each of the multiple gate lengths can be calculated according to the multiple gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area. ), by performing linear fitting on the actual inversion layer capacitance and multiple gate lengths ( vs Based on the fitted intercept, the gate length is determined under multiple gate lengths. ) and effective channel length ( The error between ) (Δ LFurthermore, for the target device in the device under test, the target device has a first length among multiple gate lengths. Based on the first length and the error amount corresponding to the first length, the effective channel length of the target device is determined. This enables the calculation of the effective channel length of the device. This allows for the calculation of the advanced gate oxide capacitance per unit area (…). By combining the extraction technology with the physical model for effective channel length extraction, the accurate gate oxide capacitance per unit area can be determined. Based on this, the accurate effective channel length can be calculated, thus realizing a reliable and accurate characterization of the effective channel length, which is of great significance for improving process control, optimizing device models and accelerating product development.

[0051] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0052] refer to Figure 1 The diagram shown is a flowchart of a method for determining the effective channel length of a device according to an embodiment of this application. This method may include:

[0053] S101, for those with different gate lengths ( The device under test (DUT) is subjected to different gate voltages. Gate channel capacitance under ) The test yielded the corresponding relationship between the capacitor voltage for each gate length.

[0054] In this embodiment of the application, the device under test can be tested. Specifically, different gate voltages can be input to the device under test. ), thereby allowing for different gate voltages ( Gate channel capacitance under ) The gate-channel capacitance (GCC) is tested to obtain the corresponding relationship between the capacitance and voltage. This relationship can be represented by a CV curve, a CV table, or other methods. This can be obtained through LCR table testing.

[0055] Multiple devices under test (DUTs) may be included, and these DUTs can have multiple different gate lengths, allowing for separate calculations and overall consideration of devices with different gate lengths. The DUTs share other common parameters, such as channel width and gate oxide thickness. If there are multiple effective channel length tests for different channel widths, tests can be performed separately for each channel width. DUTs with the same channel width can be grouped together, and their effective channel lengths can be calculated subsequently.

[0056] In this design, the direction of the connection between the source and drain is taken as the first direction, the gate length is the dimension in the first direction, and the channel width is the dimension in the second direction perpendicular to the first direction. Both the first and second directions are within the extension plane of the channel layer.

[0057] The device under test (DUT) includes a substrate, a buried oxide (BOX) layer and a channel layer sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and source and drain electrodes located on opposite sides of the channel layer. The substrate can be a semiconductor substrate to provide support for the layers on it; for example, it can be a silicon substrate or a germanium substrate. The buried oxide layer is an insulating layer used to isolate the channel layer from the substrate and prevent carriers in the channel layer from leaking from the substrate during device operation. The buried oxide layer can be, for example, silicon oxide or germanium oxide. The channel layer can be made of silicon or germanium.

[0058] In advanced devices, the channel layer is doped at a low concentration or left undoped to ensure complete depletion. The doping concentration of the channel layer ranges from 1 × 10⁻⁶. 15 ~1×10 16 cm - ³. The thickness of the buried oxide layer ranges from 20-25 nm, and the thickness of the channel layer is less than or equal to 12 nm. The gate length is less than or equal to 200 nm, at which point a short-channel effect exists, affecting the accuracy of extracting the effective channel length based on IV characteristics. Specifically, the gate length can be less than or equal to 100 nm, at which point the short-channel effect is very significant, severely affecting the accuracy of extracting the effective channel length based on IV characteristics. Of course, in actual operation, different process nodes may have different device sizes. For example, at the 28 nm process node, the channel layer thickness ranges from 7-12 nm, and the gate length is 28 nm; at the 22 nm process node, the channel layer thickness ranges from 6-8 nm, and the gate length is 22 nm; at the 14 nm process node, the channel layer thickness ranges from 5-7 nm, and the gate length is 22 nm.

[0059] The device under test (DUT) can be a device at various standard process nodes or a device with other freely designed parameters. In this embodiment, the DUT may include at least one DUT with a diameter less than 200 nm and at least one DUT with a diameter greater than 200 nm to achieve higher detection accuracy. The following assumes a gate length of 9 nm for the DUT. Let's take 20nm as an example to illustrate.

[0060] In this embodiment of the application, the device under test includes multiple first devices, and the gate length of each first device is the third length among the multiple gate lengths. The correspondence between the capacitor voltages under the multiple gate lengths is the correspondence between the capacitor voltages of a single device under the multiple gate lengths. Therefore, for devices with different gate lengths ( The device under test (DUT) is subjected to different gate voltages. Gate channel capacitance under ) The test obtains the corresponding capacitance voltage relationship for the multiple gate lengths. Specifically, the gate channel capacitance of multiple parallel first devices is tested under different gate voltages to obtain the total capacitance voltage relationship under the third length. Based on the number of first devices and the total capacitance voltage relationship, the capacitance voltage relationship of a single device under the third length is determined.

[0061] In other words, multiple first devices can be connected in parallel for gate channel capacitance testing, resulting in a larger total capacitance voltage correlation compared to the capacitance voltage correlation of a single device. In the testing of small-sized MOSFET devices, the gate channel capacitance of a single device is relatively small. Therefore, by connecting multiple first devices in parallel for gate channel capacitance testing, relatively higher accuracy can be obtained compared to testing a single device.

[0062] In practice, when the third length is less than or equal to 200 nm, a short-channel effect exists, and this method of determining the effective channel offers greater accuracy. Specifically, the third length can be less than or equal to 100 nm, where the short-channel effect is very pronounced, and this method of determining the effective channel offers even greater accuracy. As an example, the third length can be 20 nm.

[0063] refer to Figure 2 The diagram shown is a parallel connection schematic of multiple first devices according to an embodiment of this application. The upper circuit connection diagram indicates that N first devices are connected in parallel, and the lower device structure diagram indicates that the gate length of the multiple first devices is... Multiple first devices can share a gate, that is, the gates of multiple first devices are connected together, the sources (left or right electrodes) of multiple first devices can be connected together through the same conductive structure, and the drains (right or left electrodes) of multiple first devices can be connected together through the same conductor structure. In this way, the sources, drains and gates of multiple first devices are connected to each other, realizing the parallel connection between multiple first devices.

[0064] refer to Figure 3 The image shown is a schematic diagram of a CV curve provided in an embodiment of this application, where the horizontal axis represents the gate voltage (…). The vertical axis represents the gate-channel capacitance ( ), The channel width is 10µm, and the gate length of the device under test is 9µm. At 20nm, the gate voltage ranges from -0.2V to 1V. The gate-channel capacitance is normalized based on the channel area, which is determined by the gate length and channel width. Essentially, this gate-channel capacitance is the capacitance per unit area. Theoretically, this gate-channel capacitance has an error compared to the saturation capacitance. This error arises because the transistor oxide layer capacitance cannot reach saturation, even when... = 1V ( = 1V), but it also cannot reach the saturation value (there is an error of about 10% compared with the subsequent accurate value).

[0065] S102, based on the capacitor voltage correspondence, adjusts the gate-channel capacitance ( ) based on gate voltage ( The integral operation of ) yields multiple gate lengths ( The corresponding inversion layer charge concentrations () ).

[0066] In this embodiment of the application, the gate channel capacitance ( ) based on gate voltage ( The integral operation of ) yields multiple gate lengths ( The corresponding inversion layer charge concentrations () ), here the inversion layer charge concentration ( The value is determined based on the actual CV correspondence, thus possessing high accuracy. Therefore, due to the direct influence of capacitance on the channel potential distribution, it is relatively less affected by non-ideal carrier transport factors, making it easier to determine the accurate inversion layer charge concentration in short-channel devices. ) and gate oxide capacitance per unit area ( This effectively avoids the gate oxide capacitance per unit area caused by the inability of the CV curve to saturate. Extraction error.

[0067] Among them, the inversion layer charge concentration ( Specifically, it is expressed as: .

[0068] S103, by controlling the inversion layer charge concentration ( ) and gate-channel capacitance ( The ratio of ) and the inversion layer charge concentration ( Linear fitting is performed, and multiple gate lengths are determined based on the fitting slope. The gate oxide capacitance per unit area corresponding to each of the following ( ) ).

[0069] In this embodiment of the application, the inversion layer charge concentration ( ) and gate-channel capacitance ( The ratio of ) ), and inversion layer charge concentration ( Perform linear fitting ( vs Based on the fitting slope, the gate oxide capacitance per unit area corresponding to multiple gate lengths is determined. This is equivalent to saying that there is a linear relationship between the ratio and the inversion layer charge concentration.

[0070] The process of determining the gate oxide capacitance per unit area described above is based on Boltzmann statistical distribution. Specifically, it can be represented by a model based on Boltzmann statistical distribution, proposed by Mohamad in 2015, as follows:

[0071] (Formula 3)

[0072] in, Boltzmann correction factor, inversion layer charge concentration ( ) and gate-channel capacitance ( The ratio of ) ), and inversion layer charge concentration ( In the linear relationship of ), The slope It is a constant. This model accurately describes... The dependence on the inversion layer charge concentration also describes even In larger cases, Will limit The curve cannot reach saturation.

[0073] Based on this, the ratio of inversion layer charge concentration to gate channel capacitance... , with inversion layer charge concentration The fitted slope is Therefore, the reciprocal of the fitted slope can be used as the gate oxide capacitance per unit area corresponding to multiple gate lengths. ). refer to Figure 4 As shown, this is an embodiment provided in this application. vs The fitting diagram shows that the gate length is 9. hour, When the gate length is 20 nm, With a gate length of 9 time Bring back Figure 3 From this, it can be seen that the gate-channel capacitance ( The maximum value of ) is less than ,and In comparison, there is an error of about 10%.

[0074] Thus, since the capacitor directly affects the channel potential distribution, it is less affected by non-ideal factors in carrier transport, making it easier to determine the accurate inversion layer charge concentration in short-channel devices. ) and gate oxide capacitance per unit area ( This effectively avoids the gate oxide capacitance per unit area caused by the inability of the CV curve to saturate. Extraction error.

[0075] S104, based on multiple gate lengths ( The channel width (W) of the device under test and the gate oxide capacitance per unit area (W) Multiple gate lengths were calculated respectively. The actual inversion layer capacitances corresponding to these values ​​are as follows: ).

[0076] Given a given gate oxide capacitance per unit area ( After research, the inventors discovered that the gate oxide capacitance per unit area ( In fact, ΔL was not considered (i.e., the use of ΔL was not considered). Corrected This is obtained under the condition that the gate oxide capacitance per unit area is ( Theoretically, it should correspond of, rather than In other words, what was obtained The uncorrected capacitance corresponds to the gate length, while the corrected capacitance corresponds to... capacitor and uncorrected The relationship between them can be expressed as Formula 4:

[0077] (Formula 4)

[0078] refer to Figure 5 The figure shows a schematic diagram of the fitting results of the corrected gate oxide capacitance corresponding to multiple gate lengths provided in an embodiment of this application. The horizontal axis represents the channel length, and the vertical axis represents the corrected gate oxide capacitance (referred to as oxide capacitance). As can be seen from the figure, when the gate length is less than or equal to 200 nm, a short-channel effect exists, affecting the gate oxide capacitance and causing its actual value to be smaller. When the gate length is less than or equal to 100 nm, the short-channel effect is very obvious, severely affecting the gate oxide capacitance and causing its actual value to be even more drastically smaller.

[0079] Based on the uncorrected The actual inversion layer capacitance corresponding to each of the multiple gate lengths can be calculated based on the multiple gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area. ).

[0080] Specifically, for the second length among multiple gate lengths, the product of the second length, the channel width of the device under test, and the gate oxide capacitance per unit area corresponding to the second length can be used as the actual inversion layer capacitance corresponding to the second length.

[0081] In other words, the actual inversion layer capacitance It can be represented as:

[0082] (Formula 5)

[0083] because All are known, therefore according to formula 5 Partially, the actual inversion layer capacitance can be calculated. .

[0084] S105, through the actual inversion layer capacitor ( ) and the plurality of gate lengths ( Linear fitting is performed, and multiple gate lengths are determined based on the fitting intercept. At this point, the gate length ( ) and effective channel length ( The error amount (ΔL) between ).

[0085] In this embodiment of the application, due to the gate oxide capacitance per unit area ( The result is accurate, therefore the error between the calculated gate length and the effective channel length is also accurate.

[0086] refer to Figure 6 As shown, this is an embodiment provided in this application. vs This diagram illustrates the plotting of a curve. The left side shows the complete curve, while the right side is a magnified view of the intercept on the horizontal axis of the left curve. This magnified view is the lower left gray area of ​​the left half of the diagram. As can be seen from the diagram, the plotting... vs Then, a new ΔL can be obtained by linear extrapolation, compared with the traditional method. This method can provide immunity. Error caused by curve unsaturation. The fitting intercept is the fitting intercept on the coordinate axis corresponding to the gate length.

[0087] S106, for the target device in the device under test, the target device has a first length among multiple gate lengths, and the effective channel length of the target device is determined according to the first length and the error amount corresponding to the first length.

[0088] After determining the error amount ΔL, the effective channel length of the target device can be determined based on the first length of the target device and the corresponding error amount. Here, the first length is the length of the target device whose effective channel length needs to be calculated; it can be greater than or equal to 200 nm, or less than 200 nm. –ΔL.

[0089] This will enable advanced gate oxide capacitance per unit area ( By combining the extraction technology with the physical model for effective channel length extraction, the accurate gate oxide capacitance per unit area can be determined. Based on this, the accurate effective channel length can be calculated. Given the non-saturated characteristics of the CV curves of advanced node FDSOI devices, this method overcomes the limitations of traditional IV and classical CV methods, achieving reliable and accurate characterization of the effective channel length. It is applicable to FDSOI processes at nodes of 14nm and below, and is of great significance for improving process control, optimizing device models, and accelerating product development.

[0090] This application provides a method for determining the effective channel length of a device, which involves applying different gate voltages to devices under test with different gate lengths. Gate channel capacitance under ) ) tests were conducted to obtain multiple gate lengths ( The corresponding capacitance-voltage relationship (e.g., CV curve) is used to determine the gate-channel capacitance (GCC). ) based on gate voltage ( The integral operation yields the inversion layer charge concentrations corresponding to multiple gate lengths. By analyzing the ratio of inversion layer charge concentration to gate channel capacitance (...) ), and inversion layer charge concentration ( Perform linear fitting ( vs Based on the fitting slope, the gate oxide capacitance per unit area corresponding to multiple gate lengths is determined. Thus, due to the direct influence of capacitance on the channel potential distribution, the effects of non-ideal carrier transport factors are relatively small, making it easier to determine the accurate inversion layer charge concentration in short-channel devices. ) and gate oxide capacitance per unit area ( This effectively avoids the gate oxide capacitance per unit area caused by the inability of the CV curve to saturate. Extraction error.

[0091] Based on this, the actual inversion layer capacitance corresponding to each of the multiple gate lengths can be calculated according to the multiple gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area. ), by performing linear fitting on the actual inversion layer capacitance and multiple gate lengths ( vs Based on the fitted intercept, the gate length is determined under multiple gate lengths. ) and effective channel length ( The error between ) (Δ L Furthermore, for the target device in the device under test, the target device has a first length among multiple gate lengths. Based on the first length and the error amount corresponding to the first length, the effective channel length of the target device is determined. This enables the calculation of the effective channel length of the device. This allows for the calculation of the advanced gate oxide capacitance per unit area (…). By combining the extraction technology with the physical model for effective channel length extraction, the accurate gate oxide capacitance per unit area can be determined. Based on this, the accurate effective channel length can be calculated, thus realizing a reliable and accurate characterization of the effective channel length, which is of great significance for improving process control, optimizing device models and accelerating product development.

[0092] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for determining the effective channel length of a device, characterized in that, The method includes: Gate channel capacitance tests were performed on devices under test with different gate lengths at different gate voltages to obtain the capacitance-voltage correspondence for multiple gate lengths. Based on the capacitor-voltage correspondence, an integral operation based on the gate voltage is performed on the gate-channel capacitance to obtain the inversion layer charge concentration corresponding to the plurality of gate lengths respectively; By linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, the gate oxide capacitance per unit area corresponding to the plurality of gate lengths is determined based on the fitting slope. Based on the plurality of gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area, the actual inversion layer capacitance corresponding to each of the plurality of gate lengths is calculated. By performing a linear fit on the actual inversion layer capacitance and the plurality of gate lengths, the error between the gate length and the effective channel length under the plurality of gate lengths is determined based on the fitting intercept. For the target device in the device under test, the target device has a first length among the plurality of gate lengths, and the effective channel length of the target device is determined based on the first length and the error amount corresponding to the first length.

2. The method of claim 1, wherein, The step of calculating the actual inversion layer capacitance corresponding to each of the plurality of gate lengths based on the plurality of gate lengths, the channel width of the device under test, and the gate oxide capacitance per unit area includes: For the second length among the plurality of gate lengths, the product of the second length, the channel width of the device under test, and the gate oxide capacitance per unit area corresponding to the second length is taken as the actual inversion layer capacitance corresponding to the second length.

3. The method of claim 1, wherein, The step of determining the gate oxide capacitance per unit area corresponding to each of the plurality of gate lengths by linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, based on the fitting slope, includes: By linearly fitting the ratio of the inversion layer charge concentration to the gate channel capacitance and the inversion layer charge concentration, the reciprocal of the fitting slope is used as the gate oxide capacitance per unit area corresponding to the plurality of gate lengths.

4. The method according to claim 1, characterized in that, The device under test includes a plurality of first devices, the gate length of each of the first devices is the third length among the plurality of gate lengths, and the correspondence of the capacitor voltage under the plurality of gate lengths is the correspondence of the capacitor voltage of a single device under the plurality of gate lengths. The step of performing gate channel capacitance tests on devices under test with different gate lengths at different gate voltages to obtain the capacitance-voltage correspondences for the multiple gate lengths includes: The gate channel capacitance of the multiple first devices connected in parallel is tested under different gate voltages to obtain the total capacitance-voltage relationship under the third length. Based on the correspondence between the number of the first devices and the total capacitor voltage, the correspondence between the capacitor voltage of a single device under the third length is determined.

5. The method according to claim 4, characterized in that, In the plurality of first devices connected in parallel, the gates of the plurality of first devices are connected together, the sources of the plurality of first devices are connected together, and the drains of the plurality of first devices are connected together.

6. The method according to claim 4, characterized in that, The third length is less than or equal to 200 nm.

7. The method according to claim 5, characterized in that, The third length is less than or equal to 100 nm.

8. The method according to any one of claims 1-7, characterized in that, The device under test includes a substrate, a buried oxide layer and a channel layer stacked sequentially on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source electrode and a drain electrode located on both sides of the channel layer, respectively.

9. The method according to claim 8, characterized in that, The thickness of the buried oxide layer ranges from 20 to 25 nm, and / or the thickness of the channel layer is less than or equal to 12 nm, and / or the doping concentration of the channel layer ranges from 1 × 10⁻⁶. 15 ~1×10 16 cm - ³.

10. The method according to any one of claims 1-7, characterized in that, The gate voltage range is -0.2V to 1V.

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