Detector based on multi-chip tiling and signal processing method

Abstract

The application discloses a kind of based on multi-chip splicing's detector and signal processing method related to the technical field of synchrotron radiation and X-ray spectroscopy, detector includes: detector array module includes a plurality of semiconductor detection chips arranged on substrate, to seamlessly splicing mode arrangement forms continuous detection surface, for converting received incident radiation signal into charge signal;Packaging module is used to provide temperature control and environmental isolation for detector array module Working environment;Readout circuit module is electrically connected to detector array module, for preamplification to the charge signal output by detector array module and conversion into voltage signal;Digital signal processing module is used for digital processing to voltage signal, and is configured with parallel processing logic respectively for executing pulse pile-up discrimination and energy extraction processing.The surface array detector and signal processing method can realize stable collection and high-precision energy information acquisition of incident radiation signal under high count rate conditions.

Description

Technical Field

[0001] This invention relates to the fields of synchrotron radiation and X-ray spectroscopy, and in particular to a detector and signal processing method based on multi-chip splicing. Background Technology

[0002] In the field of synchrotron radiation research, techniques such as X-ray absorption fine structure spectroscopy (XAFS) and X-ray fluorescence spectroscopy (XRF) have become important tools for investigating the microstructure and elemental composition of matter. As related research develops towards high time resolution, in-situ dynamic observation, and fine micro-area analysis, higher requirements are placed on detectors in terms of energy resolution, count rate, and long-term stability. Detector performance has become one of the key factors restricting the quality of experimental data and the accuracy of analysis.

[0003] Among related technologies, silicon drift detectors (SDDs) have certain advantages in energy resolution. However, their structure is usually implemented as a single module, and under high-flux radiation conditions, their effective count rate is limited by the detection area and signal processing capabilities. When the incident photon flux is high, pulse overlap is prone to occur, leading to energy spectrum distortion and increased quantitative analysis errors. On the other hand, to improve counting capability, some technical solutions use scintillators combined with photoelectric converters to construct large-area detection structures. Although this improves photon reception efficiency to some extent, its energy resolution is relatively low, making it difficult to effectively distinguish characteristic spectral lines with similar energies, thus limiting its application in fine energy spectrum analysis.

[0004] Furthermore, with the increasing demand for multi-channel detection, detectors in related technologies still have shortcomings in terms of inter-channel consistency, background noise control, and long-term operational stability. Response differences between different channels can further affect the accuracy of measurement results. In the development of related technologies in China, high-performance detectors still lag behind in core structural design and system integration, particularly in balancing high count rates and high energy resolution. There is a lack of effective hardware implementation paths, which to some extent restricts the in-depth application of synchrotron radiation technology in the study of complex physicochemical processes. Summary of the Invention

[0005] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the purpose of this invention is to propose a detector and signal processing method based on multi-chip splicing, so as to achieve both high count rate acquisition of incident radiation signals and high-precision energy information acquisition.

[0006] To achieve the above objectives, a first aspect of the present invention provides a detector based on multi-chip splicing, comprising:

[0007] The detector array module includes multiple semiconductor detector chips disposed on a substrate; the multiple semiconductor detector chips are arranged in a seamless splicing manner to form a continuous detection surface, which is used to convert the received incident radiation signal into a charge signal;

[0008] The encapsulation module is used to provide a working environment for temperature control and environmental isolation for the detector array module;

[0009] The readout circuit module is electrically connected to the detector array module and is used to pre-amplify the charge signal output by the detector array module and convert it into a voltage signal.

[0010] The digital signal processing module is used to digitize the voltage signal and is configured with parallel processing logic; the parallel processing logic is used to perform pulse accumulation discrimination and energy extraction processing respectively.

[0011] In addition, the method of the above embodiments of the present invention may also have the following additional technical features:

[0012] According to one embodiment of the present invention, the semiconductor detection chip is a silicon drift detector (SDD) chip with a concentric ring cathode structure; an anode is provided at the center of the semiconductor detection chip; the diameter of the anode is... ~ .

[0013] According to one embodiment of the present invention, adjacent semiconductor detector chips are joined edge-to-edge, and the physical distance between them is less than [missing information]. The thickness of the semiconductor detector chip is set to... .

[0014] According to one embodiment of the present invention, the packaging module includes a vacuum cavity with an incident window, and a semiconductor cooler disposed within the vacuum cavity; the semiconductor cooler is used to maintain the operating temperature of the detector array module at a certain level. .

[0015] According to one embodiment of the present invention, the parallel processing logic includes:

[0016] The fast-track processing unit is configured to perform time recognition on the input signal based on the first forming time and generate a timestamp.

[0017] The slow channel processing unit is configured to perform trapezoidal forming processing on the input signal based on the second forming time to obtain a trapezoidal pulse signal, and extract pulse amplitude information from the trapezoidal pulse signal;

[0018] A logic control unit, connected to the fast channel processing unit and the slow channel processing unit respectively, is used to perform pulse stacking discrimination on the trapezoidal pulse signal based on the timestamp, and process the pulse amplitude information according to the pulse stacking discrimination result; wherein, the first forming time is less than the second forming time.

[0019] According to one embodiment of the present invention, the digital signal processing module includes an analog-to-digital converter and a field-programmable gate array (FPGA).

[0020] The analog-to-digital converter is used to convert the voltage signal into a digital sampling signal, and input the digital sampling signal to the FPGA;

[0021] The fast-channel processing unit, the slow-channel processing unit, and the logic control unit are all configured inside the FPGA.

[0022] According to one embodiment of the present invention, the substrate is a low-temperature co-fired ceramic (LTCC) substrate; the coefficient of thermal expansion of the substrate matches the coefficient of thermal expansion of the silicon material of the semiconductor detector chip.

[0023] According to one embodiment of the present invention, the readout circuit module includes a multi-channel low-noise application-specific integrated circuit (ASIC), which is electrically connected to the detector array module by wire bonding.

[0024] According to one embodiment of the present invention, the incident window is a beryllium window or an ultrathin silicon nitride window.

[0025] To achieve the above objectives, a second aspect of the present invention provides a signal processing method for a multi-chip stitched area array detector, applied to the multi-chip stitched area array detector proposed in the first aspect embodiment. The method includes:

[0026] The detector array module converts the received incident radiation signal into a charge signal, and the readout circuit module amplifies the charge signal to obtain a voltage signal.

[0027] The voltage signal is digitally sampled to obtain a digital sampled signal;

[0028] The digital sampling signal is synchronously input into the fast channel processing unit and the slow channel processing unit, which are set up in parallel.

[0029] The fast channel processing unit performs time identification on the input digital sampling signal based on the first forming time and generates a timestamp, while the slow channel processing unit performs trapezoidal forming processing on the input digital sampling signal based on the second forming time and extracts pulse amplitude information.

[0030] The logic control unit performs pulse stacking discrimination based on the timestamp, and processes the pulse amplitude signal according to the pulse stacking discrimination result; wherein the first forming time is less than the second forming time.

[0031] The detector and signal processing method based on multi-chip splicing in this invention constructs a continuous detection surface by seamlessly splicing multiple semiconductor detector chips. This increases the overall effective detection area without significantly increasing the load on individual detector units, thereby improving the system's count rate tolerance. Simultaneously, the packaging module provides stable temperature control and environmental isolation, helping to reduce noise interference and improve detector stability. In signal processing, the readout circuit module pre-amplifies the charge signal, and combined with parallel processing logic in the digital signal processing module, the signal is digitized and subsequently analyzed. This allows pulse accumulation detection and energy extraction to be performed collaboratively, enabling relatively accurate energy information even at high count rates. Overall, this improves the detector's applicability and measurement performance in high-flux radiation environments. Attached Figure Description

[0032] Figure 1 This is a structural block diagram of a multi-chip spliced ​​area array detector in one embodiment;

[0033] Figure 2 This is a cross-sectional view of the overall packaging structure of a multi-chip spliced ​​area array detector in one embodiment;

[0034] Figure 3 This is a schematic diagram of the detector array module in one embodiment;

[0035] Figure 4 This is a schematic diagram of the data flow inside the area array detector in one embodiment;

[0036] Figure 5 This is a schematic diagram of the signal processing flow in one embodiment.

[0037] Figure label:

[0038] Detector array module 10, packaging module 20, readout circuit module 30, digital signal processing module 40, vacuum chamber 1, incident window 2, heat dissipation structure 3, semiconductor cooler 4, substrate 5, detector array 6, splicing gap 7, bonding wire 8, center anode 9. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] The implementation details of the technical solutions of the embodiments of the present invention are described in detail below.

[0041] Figure 1 This is a block diagram of a multi-chip spliced ​​area array detector. Figure 2 This is a cross-sectional view of the overall packaging structure of a multi-chip spliced ​​area array detector. Figure 3 This is a schematic diagram of the detector array module. The following section combines... Figure 1 , Figure 2 and Figure 3 The working principle of the multi-chip splicing area array detector of the present invention will be described in detail through different embodiments.

[0042] The area array detector includes a detector array module 10, used for effectively receiving incident radiation signals and converting them into electrical signals. In this embodiment, the overall structure of the area array detector is disposed on the substrate 5. Figure 3 In this array, the detector array module 10 includes a detector array 6 composed of multiple semiconductor detector chips disposed on the substrate 5. Adjacent detector chips are seamlessly spliced ​​together, significantly reducing the physical gaps between chips and thus forming a continuous detection surface. This structure expands the effective area of ​​the detection region while maintaining spatial resolution, allowing incident radiation signals to be effectively received over a wider range. It also avoids detection blind spots caused by splicing gaps 7, thereby improving the spatial continuity and integrity of the detection results.

[0043] In terms of structural arrangement, multiple semiconductor detector chips can be arranged in a preset array configuration, such as a two-dimensional array on the surface of substrate 5. Figure 3 The method used in China is The array structure forms a regular area array structure. The positional relationship of each semiconductor detector chip in the array is defined by the wiring structure and mounting position on the substrate 5, thereby realizing arrayed output so that the detector array module 10 can adapt to the signal acquisition requirements under high-throughput incident radiation conditions.

[0044] In actual operation, when the incident radiation signal illuminates the detector array module 10, each semiconductor detector chip responds to the incident radiation in its corresponding area and converts the received incident radiation signal into a charge signal for output. Multiple charge signals are output in an array and then transmitted to the subsequent readout circuit module 30 for further processing. The charge signals output from each channel correspond to radiation information at different spatial locations. Through comprehensive processing of multi-channel signals, the detection and characterization of the overall incident radiation signal can be achieved.

[0045] The area array detector includes a packaging module 20, which provides a temperature-controlled and environmentally isolated operating environment for the detector array module 10 to reduce the impact of external temperature changes and environmental factors on the detector's operation. Figure 2 As shown, the encapsulation module 20 is configured as a low-temperature vacuum encapsulation structure and is disposed outside the detector array module 10, forming a sealed fit with the detector array module 10.

[0046] In practical applications, the encapsulation module 20 isolates the detector array module 10 from the external gas and humidity environment by constructing a relatively isolated internal environment, thereby reducing the interference of environmental factors on the detector operation. Environmental isolation reduces the heat conduction effect involving gases and weakens the impact of external condition fluctuations on the detection process, which is beneficial for maintaining a stable signal acquisition state.

[0047] Meanwhile, the packaging module 20 is also used to regulate the temperature of the detector array module 10, ensuring it operates under controlled temperature conditions. By regulating the operating temperature, the generation of thermally excited charge carriers in the semiconductor material can be suppressed, thereby reducing dark current and associated noise levels, and improving signal stability and detectability.

[0048] In terms of structural implementation, the encapsulation module 20 defines and fixes the position of the detector array module 10, enabling it to maintain a stable working state in a controlled environment. With the combined effect of environmental isolation and temperature regulation, it reduces the impact of external interference and thermal noise on the signal acquisition process, thereby providing support for the operation of the detector under high sensitivity and high resolution conditions.

[0049] The area array detector includes a readout circuit module 30, which is electrically connected to the detector array module 10 and is used to receive the charge signal output by the detector array module 10.

[0050] The readout circuit module 30 pre-amplifies the charge signal and converts it into a voltage signal for output, thus achieving the conversion from charge signal to voltage signal to meet the input signal format requirements of the subsequent digital signal processing module 40. Pre-amplification increases the signal amplitude and reduces signal attenuation during transmission, thereby improving signal detectability.

[0051] In terms of structural layout, such as Figure 2 As shown, the readout circuit module 30 is located on the side of the packaging module 20 away from the detector array module 10 and is electrically connected to the detector array module 10. This structural arrangement allows the readout circuit module 30 to process signals under relatively stable environmental conditions. Combined with the low temperature and environmental isolation provided by the packaging module 20, the impact of external noise and thermal noise on the readout circuit can be reduced, thus enabling the preamplification process to occur in a low-noise environment, which is beneficial for improving the signal-to-noise ratio and energy resolution.

[0052] The array detector includes a digital signal processing module 40, which is electrically connected to the readout circuit module 30 and is used to receive the voltage signal after pre-amplification.

[0053] The digital signal processing module 40 digitizes the voltage signal and processes it based on parallel processing logic to achieve pulse stacking discrimination and energy extraction. Specifically, the digital signal processing module 40 performs digital sampling processing on the voltage signal, and shapes and extracts features from the sampled signal to obtain information for characterizing the incident radiation energy.

[0054] Under high count rates, multiple incident events may overlap in time, leading to pulse accumulation. The digital signal processing module 40 uses parallel processing logic to analyze the signal in real time, identify potentially overlapping pulses, and extract the valid signal, thereby improving counting accuracy and time resolution. Through this processing method, the detector can maintain stable signal processing performance under high-flux radiation conditions.

[0055] In one embodiment, the semiconductor detector chip employs a concentric ring cathode structure SDD, with concentric ring electrodes of micron-level precision distributed on its surface to establish a radial drift electric field within the chip. Through the action of this radial electric field, charge carriers generated within the chip can be guided radially and gradually migrate towards the central region.

[0056] Structurally, the semiconductor detector chip has an anode at its center for collecting charge carriers; the effective diameter of the anode is [missing information]. to Within this size range, it is possible to control the anode capacitance at a low level while ensuring effective carrier collection, thereby reducing the impact of electronic noise on the signal.

[0057] Through the synergistic effect of the concentric annular cathode structure and the central anode 9, charge carriers are concentrated in the central region for collection under the action of the electric field. This allows the charge carriers to gradually converge to the tiny anode in the central region during radial drift, thereby achieving a spatial focusing effect of charge at the structural level and effectively reducing the equivalent capacitance of the anode. This helps to improve signal readout characteristics and enhance energy resolution.

[0058] In practical applications, when the effective diameter of the anode is approximately Performance is optimal at a size comparable to that of a magnet, achieving a good balance between reducing capacitance and ensuring collection efficiency. If the anode size is further increased, the anode capacitance rises, introducing higher electronic noise and affecting energy resolution. Conversely, if the anode size is too small, higher requirements are placed on micro / nano fabrication precision and alignment processes, potentially leading to unstable electric field distribution and affecting effective carrier focusing and collection. Therefore, limiting the anode diameter to a certain size is crucial. to Within this range, it is beneficial to achieve a balance between device structure implementation and performance.

[0059] In one embodiment, adjacent semiconductor detector chips are arranged in an edge-to-edge splicing manner, so that the edges of adjacent chips are directly connected, thereby forming a tightly packed array structure. The splicing gap 7 between adjacent chips is controlled to be less than [missing value]. Within the range, by reducing the physical size of the splicing gap 7, the invalid area in the array can be effectively reduced, the fill factor of the overall detection surface can be improved, and the detection dead zone introduced by the splicing gap 7 can be reduced.

[0060] Through the above-described splicing structure, multiple semiconductor detector chips can form a large-area continuous detection region, thereby increasing the total effective detection area of ​​the array (e.g., greater than). to This enables it to meet the application requirements under high-flux radiation conditions.

[0061] In terms of thickness design, the thickness of the semiconductor probe chip is set to... Within this thickness range, the detector chip can effectively absorb incident radiation within a certain energy range, while avoiding the problems of increased bias voltage and leakage current caused by excessive thickness. Furthermore, it maintains a certain level of mechanical strength even with a thinner thickness, thus contributing to the structural stability of the chip during splicing and packaging. In practical applications, when the chip thickness is significantly greater than... While this enhances the absorption of high-energy rays, it significantly increases the bias voltage required for complete device depletion, leading to increased leakage current and affecting noise levels. Conversely, when the chip thickness is significantly smaller than... At that time, the absorption efficiency of X-rays above 5keV will decrease significantly, making it difficult to meet the requirements of hard X-ray detection. Moreover, the thin chip is prone to mechanical damage during seamless splicing and handling, thereby reducing the reliability of device processing and assembly.

[0062] By coordinating the control of the splicing spacing and chip thickness, the detector array can ensure high detection efficiency while taking into account structural reliability and fabrication feasibility, thus contributing to the stable performance of the overall system.

[0063] In one embodiment, such as Figure 2 As shown, the packaging module 20 includes a vacuum chamber 1 with an incident window 2 and a semiconductor cooler 4 disposed within the vacuum chamber 1. The vacuum chamber 1 serves as a sealed body, maintaining a vacuum environment inside, with a vacuum level superior to... This isolates the detector array module 10 from the external moisture and gas environment and reduces the thermal noise caused by gas heat transfer.

[0064] The detector array module 10 is located at the cold end of the thermoelectric cooler 4 and is entirely encapsulated inside the vacuum chamber 1. The thermoelectric cooler 4 regulates the temperature of the detector array module 10, maintaining its operating temperature within the range of -25°C to -45°C. In practical applications, the thermoelectric cooler 4 is connected to a closed-loop PID temperature control circuit to achieve stable control of the operating temperature.

[0065] Structurally, the hot end of the semiconductor cooler 4 is connected to the heat dissipation structure 3 to dissipate the heat generated during the cooling process, thereby maintaining cooling efficiency and system stability. This structural arrangement enables the detector array module 10 to operate in a low-temperature and vacuum-coordinated environment, effectively suppressing leakage current caused by thermally excited charge carriers in the silicon material.

[0066] In practical applications, the thermally excited charge carriers (i.e. leakage current) of silicon materials increase exponentially with increasing temperature.

[0067] When the operating temperature exceeds -20°C, shot noise generated by the sodium-ampere level leakage current increases significantly and interferes with weak signals, leading to a severe deterioration in energy resolution. Controlling the temperature within this range reduces the impact of this type of noise on the signal. However, further temperature reduction places higher demands on vacuum sealing performance and cooling power consumption, potentially increasing system size and energy consumption. By controlling the temperature within the aforementioned range, a balance is struck between noise suppression effectiveness and system implementation cost, ensuring stable detector operation under high-resolution conditions.

[0068] In one embodiment, the incident window 2 is located at the front end of the vacuum cavity 1 to allow external radiation signals to enter the vacuum cavity 1 and act on the detector array module 10. The incident window 2 is made of beryllium material or ultra-thin silicon nitride material to achieve transmission of incident radiation while ensuring the cavity's sealing performance.

[0069] By using the above-mentioned materials to construct the incident window 2, the energy loss of incident radiation during the process of passing through the window can be reduced, thereby improving the transmission capability of low-energy X-rays, enabling the incident signal to reach the detector array module 10 with a higher intensity, and thus improving the overall detection efficiency.

[0070] In one embodiment, the readout circuit module 30 includes an ASIC, which is electrically connected to the detector array module 10 via wire bonding. Specifically, as shown... Figure 2 As shown, the ASIC establishes an electrical connection with each detection channel in the detector array module 10 through the bonding wire 8, so as to realize the synchronous reception and processing of charge signals from multiple channels.

[0071] The ASIC is used to pre-amplify the charge signal from the detector array module 10 and output the corresponding voltage signal. By adopting a multi-channel integrated structure, parallel processing of multiple signals can be achieved within a single chip, thereby improving the system integration and reducing the signal transmission path length.

[0072] Electrical connections achieved through wire bonding shorten signal transmission distances and reduce the impact of parasitic capacitance and inductance on signals, thus helping to maintain signal integrity. Combined with the low-noise characteristics of ASICs, electronic noise during the readout process can be reduced at the hardware level. Through this structural design, the readout circuit module 30 achieves miniaturization, high stability, and low-noise operation while ensuring multi-channel processing capabilities.

[0073] In one embodiment, substrate 5 is an LTCC substrate, and the coefficient of thermal expansion of substrate 5 matches the coefficient of thermal expansion of silicon material in the semiconductor detector chip. Specifically, the coefficient of thermal expansion of the LTCC substrate can be [missing information]. to By matching the thermal expansion coefficients as described above, the thermal mismatch stress between the substrate 5 and the semiconductor detector chip can be reduced during temperature changes.

[0074] Under low-temperature operating conditions, if the coefficient of thermal expansion of the substrate material differs significantly from that of silicon, the difference in shrinkage between the substrate 5 and the detector chip during cooling from room temperature to operating temperature will generate substantial shear stress. This stress may cause the conductive layer at the interface to peel off or the wire bonding structure to break, leading to electrical connection failure. Further increases in stress may also cause mechanical damage or even breakage of the detector chip, thus affecting the reliability of the detector.

[0075] By using an LTCC substrate with a thermal expansion coefficient that matches that of silicon, the consistency of structural dimensional changes can be maintained at low temperatures, thereby reducing mechanical stress caused by temperature changes, avoiding connection failures and chip damage, and improving the structural stability and long-term reliability of the detector under low-temperature operating conditions.

[0076] In one embodiment, the parallel processing logic includes a fast-channel processing unit, a slow-channel processing unit, and a logic control unit.

[0077] The fast-track processing unit is configured based on the first forming time (e.g., forming time). The input signal is processed. The shaping time characterizes the time scale by which the signal shaping circuit filters and responds to the input pulse; the shorter the shaping time, the faster the circuit responds to signal changes. By using a shaping operation with a short time constant, a rapid response to the signal is achieved, enabling time identification of incident events and generating corresponding timestamp information. Simultaneously, it allows for preliminary judgment of potential overlap trends in the signal, thus enabling rapid identification of pulse accumulation events at high count rates.

[0078] The slow-channel processing unit is configured based on a second forming time (e.g., forming time). The input signal is processed by performing a trapezoidal shaping operation with a relatively long time constant to obtain a stable trapezoidal pulse signal. The shaping process involves combining integration and differentiation of the original pulse signal to produce an output signal with a trapezoidal waveform featuring a flat-top region. The amplitude of the flat-top region of the trapezoidal pulse signal corresponds to the charge of the input pulse, thus stably representing the energy information of the incident radiation. Pulse amplitude information is extracted from the obtained trapezoidal pulse signal to represent the energy of the incident radiation, thereby achieving high-precision energy extraction (resolution better than 130 eV) through a slow-channel processing unit.

[0079] The logic control unit is connected to both the fast-channel processing unit and the slow-channel processing unit, and is used to perform pulse accumulation detection on the slow-channel output signal based on timestamp information. When pulse accumulation is determined not to exist, the corresponding pulse amplitude information is retained. When pulse accumulation is determined to exist, suppression or correction processing is performed on the corresponding signal to reduce the impact of overlapping pulses on the energy extraction results.

[0080] By using the parallel processing structure of the fast and slow channels described above, the time information and energy information of the signal can be separated and acquired. The two types of information are then processed collaboratively by the logic control unit, thereby achieving both time resolution and energy resolution under high count rate conditions.

[0081] In one embodiment, the digital signal processing module 40 includes an analog-to-digital converter (ADC) and an FPGA. The ADC is electrically connected to the readout circuit module 30, and the FPGA is electrically connected to the ADC.

[0082] An analog-to-digital converter (ADC) is used to sample voltage signals at high speed and convert them into digital sampled signals, thus realizing the conversion of signals from the analog domain to the digital domain. The converted digital sampled signals are then input into an FPGA for further processing.

[0083] The FPGA has an internal parallel processing architecture, with fast-channel processing units, slow-channel processing units, and logic control units all configured within the FPGA. The FPGA processes signals in parallel based on digital sampling signals, distributing the input signals to different processing paths to perform time identification and energy extraction-related processing respectively.

[0084] By employing a structure combining an analog-to-digital converter and an FPGA, high-speed digital sampling and subsequent parallel processing of voltage signals can be achieved, enabling the signal processing process to have high real-time performance and flexibility, thereby meeting the requirements for signal processing speed and accuracy under high count rate conditions.

[0085] Reference Figure 4 As shown, Figure 4 The diagram illustrates the data flow inside the array detector, covering the complete link from radiation signal detection to the final energy spectrum output.

[0086] First, X-ray photons are incident on the front end of a detector located in a vacuum cryogenic environment. Multiple SDD chips in the detector array module 10 convert the incident photons into a weak charge signal. In practical applications, the readout circuit module 30 includes an ASIC chip located in the vacuum cryogenic region and an ASIC chip located in the room-temperature signal processing region. This charge signal is first input to the ASIC chip located adjacent to the vacuum cryogenic region, where it undergoes low-noise pre-amplification processing in the vacuum cryogenic environment and is converted into a voltage signal output. The voltage signal can be transmitted in single-ended or differential form to improve anti-interference capability and maintain signal integrity during the transition from the vacuum environment to the room-temperature signal processing region.

[0087] In the room-temperature signal processing region, the voltage signal is further conditioned by an ASIC chip located in the room-temperature region before being input to the ADC for digital sampling, thereby obtaining a digital sampled signal reflecting the characteristics of the pulse waveform. This digital sampled signal is transmitted to the FPGA in real time. The FPGA internally constructs a parallel processing architecture based on a hardware description language, synchronously distributing the same input digital sampled signal to independent and parallel fast-channel processing units and slow-channel processing units to achieve parallel extraction of time and energy information.

[0088] Specifically, the fast-track processing unit is configured as a short forming time circuit, and its forming time can be [missing information]. The fast channel rapidly captures the arrival time of the incident pulse using a high-time-resolution algorithm and generates a high-precision timestamp. Its core function is to identify pulse accumulation events that are prone to occur under high count rate conditions in real time. Meanwhile, the slow channel processing unit is configured as a long forming time circuit, and its forming time is preferably [missing information]. The slow channel utilizes a digital trapezoidal shaping algorithm to refine the pulse signal, aiming to extract accurate pulse amplitude information through a longer integration time. This ensures that the detector maintains an energy resolution better than 130 eV while possessing high count rate processing capabilities.

[0089] The logic control unit, acting as the scheduling center of the signal processing system, is electrically connected to both the fast-channel and slow-channel processing units. Based on the timestamp information output from the fast channel, the logic control unit dynamically identifies the trapezoidal pulse signal being processed by the slow channel in real time. When multiple timestamps are detected within a preset time window and the adjacent time interval is less than a set discrimination threshold, it is determined that pulse accumulation exists in the corresponding signal, and suppression or correction processing is performed on the pulse amplitude information output from the slow channel. When no such situation is detected, it is determined to be a valid single-pulse event, and the corresponding pulse amplitude information is retained. Simultaneously, baseline recovery processing is combined to obtain stable energy data. Finally, the processed energy data is transmitted to the host computer via a high-speed interface to generate corresponding energy spectrum data, providing high-throughput, high-resolution real-time data support for experiments such as XAFS and X-ray emission spectroscopy (XES) in synchrotron radiation.

[0090] After explaining the structural modules of the array detector as described above, the following section will combine... Figure 5 The schematic diagram of the signal processing flow illustrates the signal processing method corresponding to the array detector in detail. This method is based on the collaborative operation of the aforementioned functional modules and is used to acquire, convert, and process incident radiation signals.

[0091] Step S101: Obtain the charge signal output by the detector array module based on the received incident radiation signal, and perform pre-amplification processing on the charge signal through the readout circuit module to obtain the voltage signal.

[0092] In practical operation, X-rays pass through the incident window 2 and are absorbed by the semiconductor detector chip in the detector array module 10, generating electron-hole pairs and forming an electron cloud. Under the action of the radial electric field formed by the concentric ring electrode structure, the charge carriers in the charge cloud drift towards the central anode 9 and are collected, thereby forming a charge pulse signal, which in turn converts the received incident radiation signal into a charge signal.

[0093] The charge signal output by the detector array module 10 is processed by the charge-sensitive pre-amplifier of the readout circuit module 30 and converted into a corresponding voltage signal output. The voltage signal is in the form of a voltage step that changes with time, providing the input basis for subsequent digital processing.

[0094] Step S102: The voltage signal is digitally sampled to obtain a digital sampled signal.

[0095] High-speed digital sampling processing of voltage signals converts analog voltage step signals into discrete digital sampled signals, enabling the signals to be processed on a digital processing platform, thereby achieving high-precision representation and subsequent analysis of the signals.

[0096] Step S103: The digital sampling signal is synchronously input into the fast channel processing unit and the slow channel processing unit that are set in parallel.

[0097] After the digital sampled signal enters the digital signal processing module 40, it is copied and synchronously sent to the fast channel processing unit and the slow channel processing unit through the data distribution mechanism. This allows the two processing paths to process the same input signal under the same time reference, thereby avoiding time and energy information deviations caused by input asynchrony. This ensures that the signal processing order in the two channels is consistent and maintains the timing consistency of the processing process.

[0098] By using the parallel input method described above, the fast channel side can focus on extracting the temporal features of the signal, while the slow channel side focuses on extracting the amplitude features of the signal, thus providing a basis for subsequent joint discrimination.

[0099] In step S104, the fast channel processing unit performs time identification on the input digital sampling signal based on the first forming time and generates a timestamp, while the slow channel processing unit performs trapezoidal forming processing on the input digital sampling signal based on the second forming time and extracts pulse amplitude information.

[0100] The fast-channel processing unit uses a short shaping time to quickly filter and respond to the input digital sampled signal, for example, shaping the signal with a time constant of 50ns. By shortening the signal shaping time constant, the response speed to signal changes is improved, thereby enabling rapid detection of the arrival time of the incident event. When the detected signal exceeds a preset threshold, corresponding timestamp information is generated to mark the arrival time of an event. The preset threshold is used to distinguish between valid radiation event signals and system background noise. When the signal amplitude exceeds the preset threshold, it indicates that the current signal strength is higher than the noise baseline and corresponds to a valid radiation event trigger. Simultaneously, during fast-channel processing, a preliminary judgment can be made on whether there is an overlap trend in the signals based on the triggering situation within a continuous time window.

[0101] The slow-channel processing unit uses a longer forming time to perform trapezoidal forming processing on the input digital sampled signal, for example... The time constant is used to form a trapezoidal waveform. By combining integration and filtering operations on the signal, the output signal is made into a trapezoidal pulse waveform with a stable flat-top region. The amplitude of the flat-top region corresponds to the input charge, thus reflecting the energy information of the incident radiation. Based on this, the amplitude of the trapezoidal pulse signal is extracted to obtain pulse amplitude information for energy analysis.

[0102] By setting the first forming time to be shorter than the second forming time, the fast channel side achieves higher time resolution, while the slow channel side achieves higher amplitude stability, thus structurally realizing the separate acquisition of time information and energy information.

[0103] Step S105: The logic control unit performs pulse accumulation discrimination based on the timestamp, and processes the pulse amplitude signal according to the pulse accumulation discrimination result.

[0104] The logic control unit receives the timestamp information output by the fast channel processing unit and, in conjunction with the interval relationship between the timestamps, determines whether there are multiple overlapping events within the slow channel processing cycle, thereby determining whether pulse accumulation has occurred.

[0105] When it is determined that there is no pulse accumulation, the logic control unit retains the pulse amplitude information output by the slow channel processing unit as valid energy data and uses it for subsequent energy spectrum statistics.

[0106] When pulse accumulation is detected, the logic control unit performs processing operations on the corresponding signal, including discarding the pulse amplitude information, baseline correction, or separating overlapping pulses, in order to reduce the impact of the accumulation effect on the energy measurement results.

[0107] By using the above-mentioned discrimination based on time information and selective processing of energy information, effective suppression of overlapping pulses under high count rate conditions is achieved, thereby improving the accuracy and reliability of the overall energy spectrum data.

[0108] In the above embodiments, the area array detector integrates detection, packaging, readout, and digital processing in its overall architecture. Multiple semiconductor detection chips are seamlessly joined to form a continuous detection surface, effectively expanding the detection area while maintaining spatial resolution, thereby enhancing the ability to receive high-throughput incident radiation signals. The packaging module, by providing a controlled temperature environment and isolating external interference, helps reduce thermal and environmental noise during device operation, improving signal stability. The readout circuit module pre-amplifies the charge signal and converts it into a voltage signal, improving the detectability of weak signals and providing stable input for subsequent processing. The digital signal processing module digitizes the signal and performs pulse stacking discrimination and energy extraction through parallel processing logic, enabling the coordinated acquisition of time and energy information, thus balancing the accuracy and stability of signal processing under high count rates. Therefore, through the cooperation of these modules, the detector's overall counting capability and energy resolution performance in high-throughput applications can be improved, enhancing the stability and reliability of the system operation.

[0109] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0111] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A multi-chip spliced ​​area array detector, characterized in that, include: The detector array module includes multiple semiconductor detector chips disposed on a substrate; Multiple semiconductor detector chips are arranged in a seamless manner to form a continuous detection surface, used to convert the received incident radiation signal into a charge signal; each semiconductor detector chip is a silicon drift detector chip with a concentric ring cathode structure; adjacent semiconductor detector chips are spliced ​​edge-to-edge, and the physical distance between them is less than [missing information]. The thickness of the semiconductor detector chip is set to... ; A packaging module is used to provide a temperature-controlled and environmentally isolated operating environment for the detector array module; the packaging module includes a vacuum cavity with an incident window, and a semiconductor cooler disposed within the vacuum cavity; the semiconductor cooler is used to maintain the operating temperature of the detector array module at a certain level. ; The readout circuit module is electrically connected to the detector array module and is used to pre-amplify the charge signal output by the detector array module and convert it into a voltage signal. A digital signal processing module is used to digitize the voltage signal and is configured with parallel processing logic; the parallel processing logic is used to perform pulse accumulation detection and energy extraction processing respectively; wherein, the parallel processing logic includes: The fast-track processing unit is configured to perform time recognition on the input signal based on the first forming time and generate a timestamp. The slow channel processing unit is configured to perform trapezoidal forming processing on the input signal based on the second forming time to obtain a trapezoidal pulse signal, and extract pulse amplitude information from the trapezoidal pulse signal; A logic control unit, connected to the fast channel processing unit and the slow channel processing unit respectively, is used to perform pulse stacking discrimination on the trapezoidal pulse signal based on the timestamp, and process the pulse amplitude information according to the pulse stacking discrimination result; wherein, the first forming time is less than the second forming time.

2. The multi-chip splicing area array detector according to claim 1, characterized in that, The semiconductor detector chip has an anode at its center; the diameter of the anode is... ~ .

3. The multi-chip splicing area array detector according to claim 1, characterized in that, The digital signal processing module includes an analog-to-digital converter and a field-programmable gate array (FPGA); The analog-to-digital converter is used to convert the voltage signal into a digital sampling signal, and input the digital sampling signal to the FPGA; The fast-channel processing unit, the slow-channel processing unit, and the logic control unit are all configured inside the FPGA.

4. The multi-chip splicing area array detector according to claim 2, characterized in that, The substrate is a low-temperature co-fired ceramic (LTCC) substrate; the coefficient of thermal expansion of the substrate matches the coefficient of thermal expansion of the silicon material of the semiconductor detector chip.

5. The multi-chip splicing area array detector according to claim 1, characterized in that, The readout circuit module includes a multi-channel low-noise application-specific integrated circuit (ASIC), which is electrically connected to the detector array module via wire bonding.

6. The multi-chip splicing area array detector according to claim 1, characterized in that, The incident window is a beryllium window or an ultrathin silicon nitride window.

7. A signal processing method for a multi-chip spliced ​​area array detector, characterized in that, The method, applied to the area array detector according to any one of claims 1 to 6, comprises: The detector array module converts the received incident radiation signal into a charge signal, and the readout circuit module amplifies the charge signal to obtain a voltage signal. The voltage signal is digitally sampled to obtain a digital sampled signal; The digital sampling signal is synchronously input into the fast channel processing unit and the slow channel processing unit, which are set up in parallel. The fast channel processing unit performs time identification on the input digital sampling signal based on the first forming time and generates a timestamp, while the slow channel processing unit performs trapezoidal forming processing on the input digital sampling signal based on the second forming time and extracts pulse amplitude information. The logic control unit performs pulse stacking discrimination based on the timestamp, and processes the pulse amplitude information according to the pulse stacking discrimination result; wherein the first forming time is less than the second forming time.

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