Instruction prefetch method and apparatus, electronic device, and computer-readable storage medium

Abstract

An instruction prefetching method, an instruction prefetching device, an electronic device and a computer readable storage medium. The instruction prefetching method comprises: in response to receiving an instruction read request from any instruction cache, determining whether to perform an instruction prefetching operation for the instruction read request; if it is determined to perform the instruction prefetching operation, determining a prefetching step of the instruction prefetching operation; and based on the prefetching step, prefetching instructions from a target memory and caching. The method can improve the hit rate of requests from the instruction cache in the last level cache and reduce the performance loss caused by instruction missing.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an instruction prefetching method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In the fields of modern computer systems, network communication, and data processing, caching technology is a core optimization method for alleviating memory access latency and improving system throughput.

[0003] Figure 1 A schematic diagram of a processor's cache architecture is shown. (For example...) Figure 1 As shown, a GPGPU (General-purpose computing on graphics processing) includes multiple computing units. Each computing unit includes multiple computing cores, an L1 cache (Level 1 cache), and an L2 cache (Level 2 cache). Multiple computing cores share the L1 and L2 caches, while multiple computing units share the L3 cache. The L1 cache is the cache closest to the processor cores. It is the fastest but has the smallest capacity. The instruction cache stores instructions that the computing cores are about to execute, and the data cache stores data that is about to be processed. The L2 cache has a larger capacity than the L1 cache but is slightly slower, serving as a supplement to the L1 cache. The L3 cache has the largest capacity of the three levels of cache but is also relatively slower. It is located in a shared area within the processor chip, and its core function is to coordinate data sharing among multiple computing units, avoiding data redundancy and wasted memory bandwidth. When a computing core issues a data or instruction request, it searches in the order of "cache → memory → disk": first checking the L1 cache; if a match is found, it returns directly; if not, it checks the L2 cache, and so on. Data will only be read from memory and written to the cache if all caches are missed, in preparation for the next access.

[0004] In a CPU (Central Processing Unit), the L1 cache is usually integrated inside the CPU core, with each core having its own dedicated cache. Similarly, the L2 cache is also dedicated to each CPU core and is usually located inside or near the core. The L3 cache is shared by all CPU cores and is located in a shared area inside the CPU chip. Summary of the Invention

[0005] At least one embodiment of this disclosure provides an instruction prefetching method for a last-level cache, the last-level cache being used to process memory access requests from at least one instruction cache and at least one data cache, wherein the method includes: in response to receiving an instruction read request from any of the instruction caches, the last-level cache determining whether to perform an instruction prefetch operation for the instruction read request; if it is determined that the instruction prefetch operation should be performed, determining a prefetch step size for the instruction prefetch operation; and prefetching instructions from a target memory and caching them based on the prefetch step size.

[0006] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a prefetch field; wherein, determining whether to perform an instruction prefetching operation for the instruction read request includes: determining to perform the instruction prefetching operation in response to the prefetch field being a first value.

[0007] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a step size field; wherein, determining the prefetch step size of the instruction prefetching operation includes: determining the prefetch step size based on the step size field.

[0008] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a target address, the value of the step field is determined according to the address segment where the target address is located, and multiple values ​​of the step field correspond to different address segments.

[0009] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, determining the prefetch step size of the instruction prefetching operation includes: determining the memory access distance parameter corresponding to the last-level cache, and determining the prefetch step size based on the memory access distance parameter; wherein, the memory access distance parameter characterizes the transmission distance from the last-level cache to the target memory.

[0010] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, determining the prefetch step size based on the step size field includes: determining the first step size corresponding to the step size field based on the correspondence between the step size field and the step size value; determining the second step size based on the memory access distance parameter corresponding to the last-level cache; and summing the first step size and the second step size as the prefetch step size.

[0011] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the at least one instruction cache includes a first instruction cache; wherein, prefetching and caching instructions from the target memory based on the prefetch step size includes: recording the number of cache lines occupied by the prefetched instructions corresponding to the first instruction cache in the last-level cache; and if the number of cache lines exceeds a number threshold, in response to receiving a new prefetched instruction corresponding to the first instruction cache, replacing the instructions in the cache lines occupied by the first instruction cache with the new prefetched instruction.

[0012] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a virtual address; wherein, prefetching and caching instructions from the target memory based on the prefetch step size includes: determining the physical address corresponding to the virtual address; determining the physical address of the instruction to be prefetched based on the physical address and the prefetch step size; and prefetching and caching instructions from the target memory based on the physical address of the instruction to be prefetched.

[0013] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, prefetching and caching instructions from the target memory based on the physical address of the instruction to be prefetched includes: determining whether the physical address of the instruction to be prefetched exceeds the storage range of the last-level cache; if it does not exceed the storage range, generating an instruction prefetching request based on the physical address of the instruction to be prefetched, and placing the instruction prefetching request into an instruction prefetching queue; arbitrating a request from the instruction prefetching queue and the memory access request queue as a pending request; and when the pending request is an instruction prefetching request, prefetching and caching instructions from the target memory.

[0014] For example, in the instruction prefetching method provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a prefetch field, and the at least one instruction cache includes a second instruction cache; the method further includes: stopping the instruction prefetching operation for the second instruction cache in response to the prefetch field in the instruction read request sent by the second instruction cache being a second value, wherein the prefetch field is set to the second value when the current program segment is executed to the end.

[0015] At least one embodiment of this disclosure provides an instruction prefetching apparatus for a last-level cache, the last-level cache being used to process memory access requests from at least one instruction cache and at least one data cache, wherein the apparatus includes a first determining unit, a second determining unit, and a prefetching unit. The first determining unit is configured to determine, in response to receiving an instruction read request from any of the instruction caches, whether to perform an instruction prefetch operation for the instruction read request; the second determining unit is configured to determine a prefetch step size for the instruction prefetch operation if it is determined that the instruction prefetch operation will be performed; the prefetching unit is configured to prefetch instructions from a target memory and cache them based on the prefetch step size.

[0016] For example, in the instruction prefetching apparatus provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a prefetch field; wherein, the first determining unit is further configured to: determine to perform the instruction prefetching operation in response to the prefetch field being a first value.

[0017] For example, in the instruction prefetching apparatus provided in at least one example of the above embodiments of this disclosure, the instruction read request includes a step size field; wherein, the second determining unit is further configured to: determine the prefetching step size based on the step size field.

[0018] At least one embodiment of this disclosure provides an electronic device, including a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the instruction prefetching method provided in any embodiment of this disclosure.

[0019] At least one embodiment of this disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions, which, when executed by a computer, can implement the instruction prefetching method provided in any embodiment of this disclosure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A schematic diagram of a processor's cache architecture is shown;

[0022] Figure 2 This illustrates an application scenario where the instruction prefetching method of the present disclosure embodiments can be applied;

[0023] Figure 3 A flowchart of an instruction prefetching method provided in at least one embodiment of the present disclosure is shown;

[0024] Figure 4 A schematic diagram illustrating the prefetch behavior of the last-level cache provided in at least one embodiment of this disclosure is shown;

[0025] Figure 5 A schematic diagram of the processing flow of a last-level cache provided in at least one embodiment of the present disclosure is shown;

[0026] Figure 6 A schematic block diagram of an instruction prefetching apparatus provided in at least one embodiment of the present disclosure is shown;

[0027] Figure 7 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;

[0028] Figure 8 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown; and

[0029] Figure 9 A schematic diagram of a computer-readable storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0032] Last Level Cache (LLC), also known as the last-level cache, is the cache closest to main memory. It is the highest-level (largest and slowest) cache in the processor's memory hierarchy. It is the last cache located between the processor core and main memory (RAM) and is typically shared by all cores on the processor package or chip. Figure 1 In the caching architecture shown, the last-level cache is the L3 cache. In some very complex server architectures (such as those using multi-chip module packaging), there may even be an L4 cache (Level 4 cache), in which case the last-level cache is the L4 cache. Some GPUs may only have two levels of cache (L1 cache and L2 cache) and no L3 cache, in which case the last-level cache is the L2 cache.

[0033] LLC serves both the L1 instruction cache and the L1 data cache. Its internal cache lines can contain either instructions or data. It may not distinguish whether a request originates from fetching instructions (from the L1 instruction cache) or reading / writing data (from the L1 data cache); to the LLC, these requests are all read operations targeting memory addresses. In some GPGPUs and other typical processors, the data within the LLC is distributed according to physical addresses, and the hardware module cannot determine whether a cache line contains instructions or data.

[0034] In some implementations, by predicting data or instructions that may be accessed in the future and preloading the target data or instructions into the cache before the actual request occurs, the cache miss rate can be significantly reduced, processor wait time can be decreased, and thus system throughput and response speed can be improved. For LLC (Limited Cache), since it does not distinguish between instructions and data stored in cache lines, all memory access requests are processed indiscriminately. Therefore, for both instructions and data, either no prefetching is performed, or all are prefetched according to the same rules. However, in current GPGPU and other processor implementations, due to increasingly diverse application scenarios, the number of parallel threads and branches is greater. Therefore, instructions require lower memory access latency compared to data. Existing technologies, because LLC does not distinguish between instructions and data, cannot optimize for instructions while maintaining the same overall latency, thus limiting the application scenarios supported by the chip.

[0035] At least one embodiment of this disclosure provides an instruction prefetching method, an instruction prefetching apparatus, an electronic device, and a computer-readable storage medium. The instruction prefetching method includes: in response to receiving an instruction read request from any instruction cache, the last-level cache determines whether to perform an instruction prefetch operation for the instruction read request; if it is determined that an instruction prefetch operation should be performed, it determines a prefetch step size for the instruction prefetch operation; and based on the prefetch step size, prefetches instructions from a target memory and caches them.

[0036] In this instruction prefetching method, the last-level cache can distinguish between instruction requests from the instruction cache and data requests from the data cache, and perform instruction prefetching operations on read requests from the instruction cache. On one hand, instructions are usually stored sequentially and contiguously, and instruction fetching is also typically sequential. Therefore, this method of prefetching instructions within the LLC can significantly improve the hit rate of requests from the instruction cache in the last-level cache, reducing performance loss caused by instruction misses. On the other hand, since memory access speed is much lower than that of the LLC, prefetching instructions to the LLC can save the time spent reading from and returning from memory. Without increasing hardware costs, it significantly reduces instruction read latency, improves software running speed, avoids pauses caused by instruction misses, and is more suitable for application scenarios sensitive to instruction overhead.

[0037] This instruction prefetching method is used for the last-level cache, which handles memory access requests from at least one instruction cache and at least one data cache. The last-level cache (LLC) is the furthest level of the processor's memory hierarchy from the cores, has the largest capacity, and is relatively the slowest to access; it is shared by all computing cores on the processor chip. For more information on the last-level cache, please refer to the descriptions above; they will not be repeated here. This instruction prefetching method is applicable to various processors, including CPUs and GPUs.

[0038] Figure 2 An application scenario in which the instruction prefetching method of the present disclosure embodiments can be applied is shown.

[0039] like Figure 2In the illustrated GPGPU architecture, multiple instruction level 1 caches are distributed across the entire chip, each shared by multiple compute cores (four compute cores are shown in the figure). On the other hand, multiple instruction caches send memory access requests to multiple last level caches to read cache line data. With the software configuration allowing, each instruction cache can access every last level cache. The address ranges between last level caches are independent, and each last level cache independently interfaces with a memory storage. In this architecture, the overhead of the instruction cache reading cache lines from the last level cache is significant, including the time spent on the on-chip bus, the time spent traversing the last level cache, the time spent reading data from memory in the event of a miss, and the return time. To optimize the read request performance of the instruction cache, this embodiment uses prefetching to increase the probability of a request from the instruction cache hitting the last level cache, eliminating the time spent reading from memory and returning from memory, thus reducing instruction read latency and improving software running speed.

[0040] Figure 3 A flowchart of an instruction prefetching method provided in at least one embodiment of the present disclosure is shown.

[0041] like Figure 3 As shown, the method may include steps S310 to S330.

[0042] Step S310: The last-level cache responds to receiving an instruction read request from any instruction cache and determines whether to perform an instruction prefetch operation in response to the instruction read request;

[0043] Step S320: If it is determined that an instruction prefetch operation will be performed, then determine the prefetch step size of the instruction prefetch operation; and

[0044] Step S330: Based on the prefetch step size, prefetch instructions from the target memory and cache them.

[0045] For example, a read request sent from the instruction cache to the last-level cache carries a request origin field (e.g., field name: from_instruction_cache, size: 1 bit). Upon receiving the read request, the last-level cache decodes it. If it resolves to from_instruction_cache = 1, it indicates a read request from the instruction cache; conversely, if it resolves to from_instruction_cache = 0, it indicates a read request not from the instruction cache. Based on this method, the last-level instruction can distinguish which requests originate from the instruction cache and then perform optimization operations on requests from the instruction cache.

[0046] For example, in step S310, when the last-level cache resolves that a request is an instruction read request from the instruction cache, if the instruction to be read by the request is not found in the last-level cache, the instruction is read from memory, and it is further determined whether to perform an instruction prefetch operation for the instruction read request.

[0047] For example, the instruction read request also includes a prefetch field (e.g., the field name is prefetch_enable, and the size is 1 bit). In step S310, determining whether to perform an instruction prefetch operation for the instruction read request includes: in response to the prefetch field being a first value, determining to perform the instruction prefetch operation. For example, if prefetch_enable=1 is parsed in the instruction read request, an instruction prefetch request is generated for that instruction read request to perform the instruction prefetch operation; conversely, if prefetch_enable=0 is parsed in the instruction read request, the instruction prefetch operation is not performed. Based on this approach, the software can configure fields to specify which requests perform prefetching and which do not, making the prefetch operation more flexible and aligned with actual needs.

[0048] For example, besides the methods described above, other strategies can be set to determine whether to perform instruction prefetching. In some embodiments, instruction prefetching can be performed for any read request from the instruction cache, which can significantly improve the instruction hit rate and reduce pauses caused by missing instructions. In other embodiments, the prefetching operation can be determined based on the number of reads from each instruction cache. Within a certain period, when the instruction cache reads an instruction from the last-level cache for the first time (or the first n times, where n is an integer greater than 1) and misses, instruction prefetching can be performed. If prefetching is not performed when the instruction cache reads for the first time (or the first n times) and misses, subsequent instructions will also miss. Prefetching in advance can increase the hit rate of subsequent instructions and reduce latency. In other embodiments, prefetching can be performed on instruction read requests from a specific instruction cache or a specific computing unit. In still other embodiments, the prefetching operation can be determined based on the accessed address.

[0049] For example, in step S320, after determining that an instruction prefetch operation needs to be performed, the prefetch step size is further determined. The prefetch step size refers to the offset of the next address to be accessed relative to the current address. Based on the prefetch step size, it is possible to determine how many bytes to skip forward each time to fetch data in advance. The number of bytes corresponding to one step size can be consistent with the storage size of the cache line in the last-level cache, and the amount of data prefetched each time is also consistent with the storage size of the cache line, that is, the instructions of one cache line are prefetched each time. If the storage size of each cache line is 1024 bytes, then the number of bytes corresponding to one step size is also 1024 bytes. In this case, if the prefetch step size is 1, then 1024 bytes are skipped each time to fetch data, and the amount of data fetched each time is also 1024 bytes; if the prefetch step size is 2, then 2048 bytes are skipped each time to fetch data, and the amount of data fetched each time is 1024 bytes.

[0050] For example, the instruction fetch request includes a target address, which is a virtual address. In step S330, prefetching and caching instructions from the target memory based on a prefetch step size includes: determining the physical address corresponding to the virtual address; determining the physical address of the instruction to be prefetched based on the physical address and the prefetch step size; and prefetching and caching the instruction from the target memory based on the physical address of the instruction to be prefetched. For example, the target memory is the main memory (i.e., RAM).

[0051] For example, for instruction cache, cache line numbers are based on virtual addresses and are consecutive in the virtual address space. For example, cache lines k to k+4 are five consecutive cache line numbers based on virtual addresses. For last-level cache, cache lines that are originally consecutive in the virtual address space may be interleaved in the last-level cache. For example, a chip includes four LLCs (LLC[0] to LLC[3]), k is in LLC[0], k+1 is in LLC[1], k+2 is in LLC[2], k+3 is in LLC[3], and k+4 is in LLC[0]. For LLC[0], its data is distributed according to physical addresses. Cache line k and cache line k+4 may be consecutive or non-consecutive in the physical address space. If cache line k is stored at position j in LLC[0], k+4 may be at position j+1 or not. Generally speaking, the mapping relationship between virtual address and physical address is determined by both hardware and software. In order to improve cache performance, instruction data is still adjacent to instruction data in the physical address space of LLC.

[0052] For example, after the last-level cache resolves to the virtual address of the instruction fetch request, the corresponding physical address (hereinafter referred to as the initial physical address) can be determined based on the address mapping relationship. The instruction is then fetched from memory based on this physical address. Simultaneously, an instruction prefetch request is generated based on this physical address and the prefetch stride. The prefetched physical address is the initial physical address plus the prefetch stride. Since consecutive instructions are usually stored contiguously at physical addresses, performing instruction prefetching based on the physical address and the prefetch stride can effectively prefetch the instructions that are about to be accessed.

[0053] For example, after generating an instruction prefetch request, the last-level cache can access memory based on the prefetched physical address to read the instruction stored at that physical address and store the instruction in the cache line, waiting for the instruction cache to read it.

[0054] According to at least one embodiment of this disclosure, the last-level cache can distinguish between instruction requests from the instruction cache and data requests from the data cache, and perform instruction prefetching for read requests from the instruction cache. On one hand, instructions are typically stored sequentially and contiguously, and instruction fetching is usually also sequential. Therefore, this method of prefetching instructions within the LLC can significantly improve the hit rate of requests from the instruction cache in the last-level cache, reducing performance loss due to instruction misses. On the other hand, since memory access speed is much lower than that of the LLC, prefetching instructions to the LLC can save the time spent reading from and returning from memory. Without increasing hardware costs, it significantly reduces instruction read latency, improves software running speed, avoids pauses caused by instruction misses, and is more adaptable to application scenarios sensitive to instruction overhead.

[0055] Figure 4 A schematic diagram of the prefetch behavior of the last-level cache provided in at least one embodiment of the present disclosure is shown.

[0056] like Figure 4 As shown, the instruction cache sends a read request to the Last Level Cache, which only reads the data from cache line [k]. If this request is the first read from the instruction cache, a miss will generally occur in the Last Level Cache. After this request, if prefetching is not performed, a miss will occur again when the instruction cache reads cache line [k+1]. In at least one embodiment of this disclosure, when the instruction cache sends a read request to the Last Level Cache, the Last Level Cache not only processes the read request but also generates a prefetch request to read the (k+m)th cache line, where m is the prefetch step size. If m=1, the next adjacent cache line is fetched. The method for determining the prefetch step size is described in the following embodiments.

[0057] For example, in some embodiments, the instruction read request also includes a step size field (e.g., the field name is group_id). In step S320, determining the prefetch step size of the instruction prefetch operation includes: determining the prefetch step size based on the step size field.

[0058] For example, the step size field can be configured with multiple values ​​(e.g., four), each corresponding to a different prefetch step size. For instance, the group_id can have values ​​of 0, 1, 2, and 3. When group_id=0, the prefetch step size is 2; when group_id=1, it's 4; when group_id=2, it's 6; and when group_id=3, it's 8. The prefetch step size for each value can be directly configured by the software in the last-level cache via registers. After the last-level cache parses the group_id value, it can determine the prefetch step size corresponding to that group_id and perform the prefetch operation based on that step size. This approach allows the software to set the prefetch step size as needed to meet different instruction prefetch requirements.

[0059] For example, an instruction fetch request includes a target address, and the value of the step field is determined based on the address segment where the target address is located. Multiple values ​​for the step field correspond to different address segments. The target address included in the instruction fetch request is a virtual address. When the address of the instruction to be fetched is located in the first address segment, a larger prefetch step can be set; when the address of the instruction to be fetched is located in the second address segment, a smaller prefetch step can be set. Different code segments in a program may use instructions from different address segments. Setting different prefetch steps for different address segments is equivalent to setting different prefetch steps for different code segments. Therefore, this method of determining the step can adapt to the instruction storage layout and execution flow characteristics of different code segments, thereby improving prefetch accuracy and instruction cache hit rate, and reducing cache pollution and bus bandwidth waste caused by invalid prefetching.

[0060] For example, a larger prefetch step size can be used for code segments with continuous instruction fetching scenarios such as loop bodies, while a smaller prefetch step size can be used for code segments with dense branch jumps, thereby improving prefetch accuracy and instruction cache hit rate, and reducing cache pollution and bus bandwidth waste caused by invalid prefetches.

[0061] Furthermore, when a code segment is expected to execute slowly (e.g., sharing the same computing core with other code segments), engineers can determine that memory access requests from the instruction cache to the last-level cache will be slower when this code segment is executed. In this case, a smaller prefetch stride can be set for this code segment, for example, less than a predetermined stride threshold. This is because a smaller stride means that the last-level instruction only prefetches a small number of instructions that will be used immediately for that instruction's cache. These prefetched instructions will not be evicted from the cache due to excessive waiting time, and sufficient hardware resources can be reserved for faster-executing code segments, thus preserving performance.

[0062] For example, in some embodiments, step S320, determining the prefetch step size of the instruction prefetch operation, includes: determining the memory access distance parameter corresponding to the last-level cache, and determining the prefetch step size based on the memory access distance parameter; wherein, the magnitude of the memory access distance parameter characterizes the length of the transmission distance from the last-level cache to the target memory. For example, a larger memory access distance parameter indicates a longer transmission distance.

[0063] For example, in some processor chips, LLCs (Limited Controllers) use distributed storage. Different LLCs are located at different points on the chip, resulting in varying transmission distances between each LLC and external memory (such as main memory), and consequently, different times required to retrieve data from external memory. Furthermore, in some processor chips, to reduce memory access latency, LLCs located near the compute core are used as front storage for distant LLCs. These front LLCs store a copy of the data from the distant LLCs. In this case, the front LLC needs to access the distant LLCs and main memory, which takes even longer. Therefore, when the memory access distance is large, the access time is long. If the prefetch step size is set too small, the required instruction may not be prefetched in time. Therefore, a larger prefetch step size can be set to ensure that the instruction is prefetched into the last level cache when it is read. Conversely, when the memory access distance is small, the access time is short, and the instruction can be prefetched quickly. Therefore, a smaller prefetch step size can be set, which reduces the amount of instruction data stored in the last level cache and instruction cache, saving cache space. For example, in terms of transmission distance, LLC[0] is farther from memory than LLC[1]. The memory access distance parameter of LLC[1] is set to 1, and the corresponding prefetch step size is 2. The memory access distance parameter of LLC[0] is set to 2, and the corresponding prefetch step size is 4.

[0064] For example, in other embodiments, both the step size field and the memory access distance parameter are referenced when determining the prefetch step size; that is, the prefetch step size is determined based on the step size field and the memory access distance parameter. The first step size corresponding to the step size field is determined based on the correspondence between the step size field and the step size value, and the second step size is determined based on the memory access distance parameter corresponding to the last-level cache. The sum of the first step size and the second step size is used as the prefetch step size.

[0065] For example, LLC[0] receives an instruction read request from the instruction cache. When determining the prefetch step size for the prefetch operation, it first parses the step size field carried by the instruction read request. For example, if the step size field group_id=1, the corresponding first step size is 4. The memory access distance parameter of LLC[0] corresponds to the second step size of 4. Then, the prefetch step size = first step size + second step size = 8. In this way, both the step size required for different address segments and the influence of memory access distance on the step size are considered, thus combining the effects of the two methods mentioned above.

[0066] For example, at least one instruction cache connected to the last-level cache includes a first instruction cache. Step S330 further includes: recording the number of cache lines occupied by the prefetch instruction corresponding to the first instruction cache in the last-level cache; and if the number of cache lines exceeds a threshold, in response to receiving a new prefetch instruction corresponding to the first instruction cache, replacing the instructions in the cache lines occupied by the first instruction cache with the new prefetch instruction.

[0067] For example, the cache line occupied by the prefetched instruction corresponding to the instruction cache in the last level cache is called a prefetch cache line. The index of any prefetch cache line in the last level cache is the same as the index of the instruction cache corresponding to the instruction stored in that prefetch cache line. For example, if prefetch cache line j contains instructions prefetched for instruction cache C1, then the index of prefetch cache line j is the same as the index of instruction cache C1. To prevent program jumps from causing a large number of invalid prefetches, thus leading to LLC cache pollution, an instruction cache prefetch count function is added to the last level cache. This counting function supports counting for all on-chip instruction caches simultaneously. Each count represents the number of prefetch cache lines occupied by a certain instruction cache in the current LLC (prefetch count). In any LLC, when an instruction prefetch request needs to replace other cache lines, it can first be determined whether the prefetch count of the corresponding instruction cache (such as instruction cache C1) has reached the upper limit. If it has, then the instruction retrieved by the instruction prefetch request will preferentially replace the prefetch cache line with the same index as the instruction cache (such as instruction cache C1) corresponding to the request. In this way, setting a prefetch occupancy limit for each instruction cache in the last-level cache can prevent LLC cache pollution caused by a large number of invalid prefetches due to program jumps.

[0068] For example, S330 further includes: determining whether the physical address of the instruction to be prefetched exceeds the storage range of the last-level cache; if it does not exceed the storage range, generating an instruction prefetch request based on the physical address of the instruction to be prefetched, and placing the instruction prefetch request into the instruction prefetch queue; arbitrating a request from the instruction prefetch queue and the memory access request queue as a pending request; and when the pending request is an instruction prefetch request, prefetching the instruction from the target memory and caching it.

[0069] Figure 5A schematic diagram of the processing flow of a last-level cache provided in at least one embodiment of this disclosure is shown. The content within the dashed box represents the hardware implementation flow of the last-level cache.

[0070] like Figure 5 As shown, when a memory access request arrives, it first enters the memory access request queue 501 within the cache. Requests retrieved from queue 501 are then decoded. This process filters out invalid requests and parses certain fields of valid requests. For example, when `from_instruction_cache = 1` is parsed, it indicates a read request from the instruction cache, and this field is set by the instruction cache. If further parsing reveals `prefetch_enable = 1`, it means the instruction cache wants the last-level cache to prefetch based on this read request. If the instruction cache determines it doesn't need the data following a read request, it can set `prefetch_enable = 0`, thus preventing the last-level cache from prefetching. If it is confirmed that the request needs to be prefetched, the request information can be stored in the cache line prefetch module 502 at the same time the original request is received by the pending request queue 504. The cache line prefetch module 502 first determines the prefetch step size (the pre-parameter in the figure is the memory access distance parameter mentioned above) from the configuration register 503 based on the group_id. Then it calculates the prefetch address and checks whether the address is out of bounds. If it is not out of bounds, the prefetch request is ready. The prefetch request can be arbitrated with the ordinary request in the main path. If the arbitrated request is successful, it can be sent to the pending request queue 504 for hit detection. The request output by the pending request queue 504 enters the hit detection module 505. If the request is not hit in the last-level cache, the instruction or data is read from memory through the request scheduling module 506. In addition, in the cache line replacement stage of the hit detection module 505, an instruction cache prefetch counting function is added to set the prefetch occupancy limit for each instruction cache.

[0071] For example, at least one instruction cache connected to the last-level cache includes a second instruction cache. When the prefetch field in an instruction read request sent by the second instruction cache is a second value, instruction prefetching operations for the second instruction cache are stopped, wherein the prefetch field is set to the second value when the current program segment reaches the end of execution.

[0072] For example, when the instruction cache reaches the end of program execution, setting `prefetch_enable` to 0 will stop the last-level cache from prefetching instruction data, thus avoiding fetching irrelevant data. If the prefetched data happens to be different from the required instruction data, the function still works correctly because it simply moves the memory data to the last-level cache, which is equivalent to performing an invalid memory move, but it does not affect program operation.

[0073] For example, in some embodiments, the last-level cache can also set its own enable field for each step field (group_id) to determine whether to enable prefetching behavior for the corresponding step field. For example, when the enable field corresponding to group_id is 0, it means that prefetching behavior for requests for that group_id is not enabled; when the enable field corresponding to group_id is 1, it means that prefetching behavior for requests for that group_id is enabled.

[0074] Figure 6 A schematic block diagram of an instruction prefetching apparatus 600 provided in at least one embodiment of the present disclosure is shown.

[0075] For example, such as Figure 6 As shown, the instruction prefetching device 600 includes a first determining unit 610, a second determining unit 620, and a prefetching unit 630. These components are interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, these modules can be implemented by hardware (e.g., circuit) modules, software modules, or any combination of both, as is the case in the following embodiments, and will not be repeated here. For example, these units can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), a tensor processor (TPU), a field-programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, along with corresponding computer instructions. It should be noted that... Figure 6 The components and structure of the instruction prefetching device 600 shown are merely exemplary and not limiting. The instruction prefetching device 600 may also have other components and structures as needed.

[0076] The first determining unit 610 is configured to determine, in response to receiving an instruction read request from any of the instruction caches, whether to perform an instruction prefetch operation for the instruction read request. The first determining unit 610 may, for example, perform... Figure 3 Step S310 is described.

[0077] The second determining unit 620 is configured to determine the prefetch step size of the instruction prefetch operation if it is determined that the instruction prefetch operation will be performed. For example, the second determining unit 620 may execute... Figure 3 Step S320 is described.

[0078] The prefetch unit 630 is configured to prefetch instructions from the target memory and cache them based on the prefetch step size. The prefetch unit 630 may, for example, perform... Figure 3 Step S330 is described.

[0079] For example, in some embodiments, the instruction read request includes a prefetch field, and the first determining unit 610 is further configured to: determine to perform the instruction prefetch operation in response to the prefetch field being a first value.

[0080] For example, in some embodiments, the instruction read request includes a step size field, and the second determining unit 620 is further configured to determine the prefetch step size based on the step size field.

[0081] For example, in some embodiments, the instruction read request includes a target address, and the value of the step field is determined according to the address segment in which the target address is located, with multiple values ​​of the step field corresponding to different address segments.

[0082] For example, in some embodiments, the second determining unit 620 is further configured to: determine the memory access distance parameter corresponding to the last-level cache, and determine the prefetch step size based on the memory access distance parameter; wherein the memory access distance parameter characterizes the transmission distance from the last-level cache to the target memory.

[0083] For example, in some embodiments, the second determining unit 620 is further configured to: determine the first step length corresponding to the step length field based on the correspondence between the step length field and the step length value; determine the second step length based on the memory access distance parameter corresponding to the last-level cache; and sum the first step length and the second step length as the prefetch step length.

[0084] For example, in some embodiments, the at least one instruction cache includes a first instruction cache, and the prefetch unit 630 is further configured to: record the number of cache lines occupied by the prefetch instruction corresponding to the first instruction cache in the last-level cache; and if the number of cache lines exceeds a number threshold, in response to receiving a new prefetch instruction corresponding to the first instruction cache, replace the instruction in the cache line occupied by the first instruction cache with the new prefetch instruction.

[0085] For example, in some embodiments, the instruction read request includes a virtual address, and the prefetch unit 630 is further configured to: determine the physical address corresponding to the virtual address; determine the physical address of the instruction to be prefetched based on the physical address and the prefetch step size; and prefetch the instruction from the target memory and cache it based on the physical address of the instruction to be prefetched.

[0086] For example, in some embodiments, the prefetch unit 630 is further configured to: determine whether the physical address of the instruction to be prefetched exceeds the storage range of the last-level cache; if it does not exceed the storage range, generate an instruction prefetch request based on the physical address of the instruction to be prefetched, and place the instruction prefetch request into an instruction prefetch queue; arbitrate a request from the instruction prefetch queue and the memory access request queue as a pending request; and when the pending request is an instruction prefetch request, prefetch the instruction from the target memory and cache it.

[0087] For example, in some embodiments, the instruction read request includes a prefetch field, and the at least one instruction cache includes a second instruction cache; the first determining unit is further configured to: stop executing the instruction prefetch operation for the second instruction cache in response to the prefetch field in the instruction read request sent by the second instruction cache being a second value, wherein the prefetch field is set to the second value when the current program segment reaches the end of execution.

[0088] For example, the first determining unit 610, the second determining unit 620, and the prefetching unit 630 can be hardware, software, firmware, or any feasible combination thereof. For example, the first determining unit 610, the second determining unit 620, and the prefetching unit 630 can be dedicated or general-purpose circuits, chips, or devices, or they can be a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the above-mentioned units.

[0089] For example, the first determining unit 610, the second determining unit 620, and the prefetching unit 630 may include code and programs stored in memory; the processor may execute the code and programs to implement some or all of the functions of the first determining unit 610, the second determining unit 620, and the prefetching unit 630 as described above. For example, the first determining unit 610, the second determining unit 620, and the prefetching unit 630 may be dedicated hardware devices used to implement some or all of the functions of the first determining unit 610, the second determining unit 620, and the prefetching unit 630 as described above. For example, the first determining unit 610, the second determining unit 620, and the prefetching unit 630 may be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In embodiments of this disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) processor-executable firmware stored in memory.

[0090] It should be noted that in the embodiments of this disclosure, each unit of the instruction prefetching device 600 corresponds to each step of the aforementioned instruction prefetching method. For the specific functions of the instruction prefetching device 600, please refer to the relevant description of the instruction prefetching method, which will not be repeated here. Figure 6 The components and structure of the instruction prefetching device 600 shown are exemplary and not limiting. The instruction prefetching device 600 may include other components and structures as needed. The instruction prefetching device 600 may include more or fewer circuits or units, and the connection relationships between the various circuits or units are not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited; it can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0091] At least one embodiment of this disclosure also provides an electronic device including a processor and a memory storing one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the instruction prefetching method described above.

[0092] Figure 7 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. For example... Figure 7 As shown, the first electronic device 700 includes a processor 710 and a memory 720. The memory 720 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to execute the non-transitory computer-readable instructions, which, when executed by the processor 710, perform one or more steps in the instruction prefetching method described above. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For specific implementations and explanations of the various steps of the instruction prefetching method, please refer to the embodiments of the instruction prefetching method described above; repetitions will not be repeated here.

[0093] It should be noted that Figure 7 The components of the first electronic device 700 shown are merely exemplary and not limiting. The first electronic device 700 may also have other components depending on the actual application requirements.

[0094] For example, the processor 710 and the memory 720 can communicate with each other directly or indirectly.

[0095] For example, the processor 710 and the memory 720 can communicate via a network. The network can include a wireless network, a wired network, and / or any combination of wireless and wired networks. The processor 710 and the memory 720 can also communicate with each other via a system bus, and this disclosure is not limiting in this regard.

[0096] For example, the processor 710 and memory 720 can be located on the server side (or in the cloud).

[0097] For example, processor 710 can control other components in the first electronic device 700 to perform desired functions. For example, processor 710 can be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an x86 or ARM architecture. Processor 710 can be a general-purpose processor or a special-purpose processor, and can control other components in the first electronic device 700 to perform desired functions.

[0098] For example, memory 720 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 710 may run one or more computer program modules to implement various functions of the first electronic device 700. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0099] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the first electronic device 700 can be referred to the description of the instruction prefetching method above, and will not be repeated here.

[0100] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The second electronic device 800 is, for example, suitable for implementing the instruction prefetching method provided in embodiments of the present disclosure. The second electronic device 800 may be a terminal device, etc. It should be noted that... Figure 8 The second electronic device 800 shown is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments of this disclosure.

[0101] like Figure 8As shown, the second electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 810, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. The RAM 830 also stores various programs and data required for the operation of the second electronic device 800. The processing device 810, ROM 820, and RAM 830 are interconnected via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0102] Typically, the following devices can be connected to I / O interface 850: input devices 860 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 870 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 880 including, for example, magnetic tapes, hard disks, etc.; and communication devices 890. Communication device 890 allows the second electronic device 800 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 8 A second electronic device 800 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the second electronic device 800 may alternatively implement or have more or fewer devices.

[0103] For example, according to embodiments of this disclosure, the instruction prefetching method described above can be implemented as a computer software program. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing the instruction prefetching method described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 890, or installed from a storage device 880, or installed from a ROM 820. When the computer program is executed by the processing device 810, the functions defined in the instruction prefetching method provided by embodiments of this disclosure can be implemented.

[0104] At least one embodiment of this disclosure also provides a computer-readable storage medium storing non-transitory computer-readable instructions that, when executed by a computer, can implement the instruction prefetching method described above.

[0105] Figure 9 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 9 As shown, storage medium 900 stores non-transitory computer-readable instructions 910. For example, when the non-transitory computer-readable instructions 910 are executed by a computer, one or more steps in the instruction prefetching method described above are performed.

[0106] For example, the storage medium 900 can be used in the first electronic device 700 described above. For example, the storage medium 900 can be... Figure 7 The memory 720 in the first electronic device 700 shown. For example, a description of the storage medium 900 can be found here. Figure 7 The corresponding description of the memory 720 in the first electronic device 700 shown will not be repeated here.

[0107] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0108] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0109] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0110] The following points should be noted regarding this disclosure:

[0111] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0112] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An instruction prefetching method for a last-level cache, wherein the last-level cache is used to handle memory access requests for at least one instruction cache and at least one data cache, characterized in that, The method includes: The last-level cache, in response to receiving an instruction read request from any of the instruction caches, determines whether to perform an instruction prefetch operation for the instruction read request; If it is determined that the instruction prefetch operation will be performed, then the prefetch step size of the instruction prefetch operation is determined; and Based on the prefetch step size, prefetch instructions from the target memory and cache them; Wherein, the last-level cache, in response to receiving an instruction read request from any of the instruction caches, determines whether to perform an instruction prefetch operation for the instruction read request, including: The last-level cache, in response to receiving a read request, determines whether the read request originates from the at least one instruction cache or from the at least one data cache based on the request source field carried by the read request; and In response to the read request being an instruction read request, determine whether to perform an instruction prefetch operation for the instruction read request.

2. The instruction prefetching method according to claim 1, characterized in that, The instruction read request includes a prefetch field; The process of determining whether to perform an instruction prefetch operation for the instruction read request includes: In response to the prefetch field being a first value, the instruction prefetch operation is determined to be performed.

3. The instruction prefetching method according to claim 1, characterized in that, The instruction read request includes a step size field; Determining the prefetch step size of the instruction prefetch operation includes: determining the prefetch step size based on the step size field.

4. The instruction prefetching method according to claim 3, characterized in that, The instruction read request includes a target address, and the value of the step field is determined according to the address segment where the target address is located. The multiple values ​​of the step field correspond to different address segments.

5. The instruction prefetching method according to claim 1, characterized in that, Determining the prefetch step size of the instruction prefetch operation includes: Determine the memory access distance parameter corresponding to the last-level cache, and determine the prefetch step size based on the memory access distance parameter; The memory access distance parameter represents the transmission distance from the last-level cache to the target memory.

6. The instruction prefetching method according to claim 3, characterized in that, Determining the prefetch step size based on the step size field includes: Based on the correspondence between the step size field and the step size value, the first step size corresponding to the step size field is determined; Based on the memory access distance parameter corresponding to the last-level cache, determine the second step size; and The sum of the first step length and the second step length is used as the prefetch step length.

7. The instruction prefetching method according to any one of claims 1-6, characterized in that, The at least one instruction cache includes a first instruction cache; Specifically, based on the prefetch step size, prefetching and caching instructions from the target memory includes: Record the number of cache lines occupied by the prefetch instruction corresponding to the first instruction cache in the last-level cache; and If the number of occupied cache lines exceeds a threshold, in response to receiving a new prefetch instruction corresponding to the first instruction cache, the instructions in the occupied cache lines of the first instruction cache are replaced with the new prefetch instruction.

8. The instruction prefetching method according to any one of claims 1-6, characterized in that, The instruction read request includes a virtual address; Specifically, based on the prefetch step size, prefetching and caching instructions from the target memory includes: Determine the physical address corresponding to the virtual address; Based on the physical address and the prefetch step size, determine the physical address of the instruction to be prefetched; and Instructions are prefetched from the target memory and cached based on the physical address of the instruction to be prefetched.

9. The instruction prefetching method according to claim 8, characterized in that, Prefetching and caching instructions from the target memory based on the physical address of the instruction to be prefetched includes: Determine whether the physical address of the instruction to be prefetched exceeds the storage range of the last-level cache; If the storage range is not exceeded, an instruction prefetch request is generated based on the physical address of the instruction to be prefetched, and the instruction prefetch request is placed in the instruction prefetch queue. A request is arbitrated from the instruction prefetch queue and the memory access request queue as a pending request; and When the pending request is an instruction prefetch request, the instruction is prefetched from the target memory and cached.

10. The instruction prefetching method according to any one of claims 1-6, characterized in that, The instruction read request includes a prefetch field, and the at least one instruction cache includes a second instruction cache; The method further includes: In response to the instruction read request sent by the second instruction cache having a prefetch field of a second value, the instruction prefetch operation for the second instruction cache is stopped, wherein the prefetch field is set to the second value when the current program segment reaches the end of execution.

11. An instruction prefetching apparatus for a last-level cache, the last-level cache being used to process memory access requests for at least one instruction cache and at least one data cache, characterized in that, The device includes: The first determining unit is configured to determine whether to perform an instruction prefetch operation in response to receiving an instruction read request from any of the instruction caches; The second determining unit is configured to determine the prefetch step size of the instruction prefetch operation if it is determined that the instruction prefetch operation will be performed; and The prefetch unit is configured to prefetch instructions from the target memory and cache them based on the prefetch step size; The first determining unit is further configured as follows: The last-level cache, in response to receiving a read request, determines whether the read request originates from the at least one instruction cache or from the at least one data cache based on the request source field carried by the read request; and In response to the read request being an instruction read request, determine whether to perform an instruction prefetch operation for the instruction read request.

12. The instruction prefetching apparatus according to claim 11, characterized in that, The instruction read request includes a prefetch field; The first determining unit is further configured to: determine to perform the instruction prefetch operation in response to the prefetch field being a first value.

13. The instruction prefetching apparatus according to claim 11, characterized in that, The instruction read request includes a step size field; The second determining unit is further configured to: determine the prefetch step size based on the step size field.

14. An electronic device, characterized in that, include: processor; Memory, which stores one or more computer program modules; The one or more computer program modules are configured to be executed by the processor to implement the instruction prefetching method according to any one of claims 1-10.

15. A computer-readable storage medium, characterized in that, The device stores non-transitory computer-readable instructions that, when executed by a computer, can implement the instruction prefetching method according to any one of claims 1-10.

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