Solid state disk starting method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a solid state disk starting method, electronic equipment and a storage medium, and the method comprises the steps: responding to the situation that any NAND particle parameter is not matched in a preset NAND particle parameter library after the solid state disk is powered on, and carrying out the communication establishment of NAND particles of the solid state disk and a master control one by one according to a plurality of preset loading strategies; and in response to successful establishment of the communication between the NAND particle and the master control, performing firmware loading on the NAND particle through a target loading strategy used when the communication is successfully established. According to the embodiment of the invention, the fault tolerance of firmware loading can be improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of storage technology, and particularly to a boot method for a solid-state drive, an electronic device, and a storage medium. Background Technology

[0002] In related technologies, the booting process of a Solid State Drive (SSD) involves the SSD's internal controller correctly loading firmware from NAND flash memory. However, due to design and supply chain cost issues, different models use NAND flash memory chips from different manufacturers. These NAND chips from different manufacturers differ in timing and instruction sets. To ensure successful firmware loading, in traditional solutions, the SSD controller has a pre-set database containing known chip parameters, which is used to compare the required NAND chip parameters.

[0003] However, in practical applications, due to power timing deviations, hardware interference, or overly sensitive parameter library matching algorithms, even if the current NAND flash memory chip actually has corresponding chip parameters in a database containing known chip parameters, it may be misjudged as not having corresponding chip parameters, thus causing firmware loading to be interrupted and the solid-state drive to fail to boot. Summary of the Invention

[0004] This application provides a boot method for a solid-state drive, an electronic device, and a storage medium that can improve the fault tolerance of firmware loading.

[0005] On one hand, embodiments of this application provide a method for booting a solid-state drive, including: In response to the fact that no NAND chip parameter is matched in the preset NAND chip parameter library after the solid-state drive is powered on, communication is established between the NAND chips and the controller of the solid-state drive one by one according to multiple preset loading strategies. In response to the successful establishment of communication between the NAND flash chip and the main controller, firmware is loaded onto the NAND flash chip using the target loading strategy used when the communication was successfully established.

[0006] In one embodiment, the method further includes: If the number of times the solid-state drive successfully establishes communication between the NAND flash memory and the controller through the target loading strategy is not less than a preset threshold, the target loading strategy is determined as the optimal boot strategy used by the controller. In response to the solid-state drive being powered on again and no NAND chip parameter being matched in the NAND chip parameter library after power-on, communication between the NAND chip and the controller is established according to the optimal boot strategy.

[0007] In one embodiment, the method further includes: In response to the failure to establish communication between the NAND flash chip and the controller according to the optimal boot strategy, communication is established between the NAND flash chip and the controller one by one according to the remaining multiple loading strategies; In response to the successful establishment of communication between the NAND flash memory and the controller, the loading strategy used when the communication was successfully established is determined as the new target loading strategy, and communication between the NAND flash memory and the controller is established according to the new target loading strategy.

[0008] In one embodiment, the method further includes: In response to the fact that the number of times the solid-state drive successfully establishes communication between the NAND flash and the controller through the target loading strategy and the new target loading strategy is not less than the preset threshold, the number of times the target loading strategy is used and the number of times the new target loading strategy is used are compared. In response to the difference in the number of times the target loading strategy is used and the number of times the new target loading strategy is used, the optimal startup strategy is corrected based on the one that is used the most among the target loading strategy and the new target loading strategy.

[0009] In one embodiment, establishing communication between the NAND flash memory chips and the controller of the solid-state drive according to multiple preset loading strategies includes: For each loading strategy, the main controller is driven to read the firmware of the NAND chip and verify the read firmware according to the current loading strategy. In response to the failure to verify the firmware read according to the current loading strategy, the main controller is driven to read the firmware of the NAND chip according to the next loading strategy. In response to the successful read verification corresponding to the current loading strategy, the current loading strategy is determined as the target loading strategy.

[0010] In one embodiment, the method further includes: In response to the failure to establish communication between the NAND flash chip and the controller through each of the aforementioned loading strategies, additional stored boot information is obtained; Repair the communication between the NAND flash memory chip and the controller according to the guidance information; Start the solid-state drive.

[0011] In one embodiment, booting the solid-state drive includes: In response to the successful repair of communication between the NAND flash memory chip and the controller, the solid-state drive is restarted; Communication between the NAND flash memory chip and the main controller is established based on the boot information, and firmware is loaded onto the NAND flash memory chip.

[0012] In one embodiment, booting the solid-state drive includes: In response to the failure to repair communication between the NAND flash chip and the main controller, a startup feedback message is output through the boot information; In response to receiving a forced boot command, the solid-state drive is forcibly booted according to the boot information.

[0013] On the other hand, embodiments of this application also provide an electronic device, including: at least one processor; at least one memory for storing at least one program; and implementing the solid-state drive boot method as described above when at least one of the programs is executed by at least one of the processors.

[0014] On the other hand, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions, characterized in that the computer-executable instructions are used to execute the boot method of the solid-state drive as described above.

[0015] On the other hand, embodiments of this application also provide a computer program product, including a computer program or computer instructions, the computer program or computer instructions being stored in a computer-readable storage medium, a processor of an electronic device reading the computer program or computer instructions from the computer-readable storage medium, and the processor executing the computer program or computer instructions to cause the electronic device to execute the solid-state drive boot method as described above.

[0016] This application provides a boot method for a solid-state drive (SSD), an electronic device, and a storage medium. The method includes, in response to the SSD being powered on and not finding any NAND flash memory parameters matched in a preset NAND flash memory parameter library, establishing communication between the SSD's NAND flash memory and the controller one by one according to multiple preset loading strategies; and, in response to successful communication between the NAND flash memory and the controller, loading firmware onto the NAND flash memory using the target loading strategy used when successful communication was established. By attempting to establish communication between the SSD's NAND flash memory and the controller one by one according to multiple loading strategies after finding any NAND flash memory parameters matched in the preset NAND flash memory parameter library, communication fault tolerance between the NAND flash memory and the controller can be established. Furthermore, by loading firmware onto the NAND flash memory using the target loading strategy used when successful communication was established after successful communication, the SSD can still boot successfully even if there are internal identification anomalies. This effectively improves the firmware loading fault tolerance of the SSD and reduces the possibility of the SSD failing to boot due to internal identification anomalies even though the firmware is actually normal. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a solid-state drive boot method provided in one embodiment of this application; Figure 2 This is a flowchart illustrating a solid-state drive boot method according to another embodiment of this application; Figure 3 This is a flowchart illustrating a solid-state drive boot method according to another embodiment of this application; Figure 4 This is a flowchart illustrating a solid-state drive boot method provided in another embodiment of this application; Figure 5 This is a flowchart illustrating a solid-state drive boot method provided in yet another embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be executed in a different order than that shown in the flowchart. In the description of the embodiments of this application, "multiple" (or more than) means two or more, "greater than," "less than," and "exceeding" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. If "first," "second," etc., are described, they are only used to distinguish technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated. Furthermore, in the description of the embodiments of this application, the various values ​​mentioned (such as first value, second value, etc.) can be flexibly represented as a single numeric code or an enumerated type value.

[0020] In related technologies, the booting process of a Solid State Drive (SSD) involves the SSD's internal controller correctly loading firmware from NAND flash memory. However, due to design and supply chain cost issues, different models use NAND flash memory chips from different manufacturers. These NAND flash chips from different manufacturers differ in timing and instruction sets, which needs to be addressed to ensure successful firmware loading.

[0021] In traditional solutions, the controller of a solid-state drive (SSD) has a pre-set database containing known NAND flash memory parameters and the NAND flash memory ID corresponding to each parameter. The controller first reads the NAND flash memory ID and then compares it with the database one by one. Only when a matching NAND flash memory ID is found in the database can firmware be loaded using the corresponding NAND flash memory parameters. Otherwise, the firmware loading process is immediately interrupted.

[0022] However, in practical applications, due to power timing deviations, hardware interference, or overly sensitive parameter library matching algorithms, even if the current NAND flash memory chip actually has corresponding chip parameters in a database containing known chip parameters, it may be misjudged as not having corresponding chip parameters, thus causing firmware loading to be interrupted and the solid-state drive to fail to boot.

[0023] To improve the fault tolerance of firmware loading, embodiments of this application provide a boot method for a solid-state drive, an electronic device, a computer-readable storage medium, and a computer program product. Specifically, the method may first respond to the situation where no NAND chip parameter is matched in a preset NAND chip parameter library after the solid-state drive is powered on, and then establish communication between the NAND chips and the controller of the solid-state drive one by one according to multiple preset loading strategies; in response to the successful establishment of communication between the NAND chips and the controller, the firmware is loaded onto the NAND chips according to the target loading strategy used when the communication was successfully established.

[0024] See Figure 1 , Figure 1 The flowchart illustrates a boot method for a solid-state drive (SSD) according to an embodiment of this application. One embodiment of this application provides a boot method for a solid-state drive (SSD), which may include the following steps.

[0025] Step 110: In response to the fact that no NAND chip parameter is matched in the preset NAND chip parameter library after the solid-state drive is powered on, communication is established between the NAND chips of the solid-state drive and the controller one by one according to multiple preset loading strategies. Step 120: In response to the successful establishment of communication between the NAND flash chip and the controller, the firmware is loaded onto the NAND flash chip using the target loading strategy used when the communication was successfully established.

[0026] In one embodiment, the situation where the solid-state drive (SSD) fails to find any NAND chip parameter in the preset NAND chip parameter library after power-on means that after the SSD powers on, the controller reads the NAND chip ID and compares it with the NAND chip parameter library, but cannot find a match for the read NAND chip ID in the NAND chip parameter library. Specifically, this situation may include: an error in the controller's process of reading the NAND chip ID resulting in the controller obtaining an incorrect NAND chip ID; the preset NAND chip parameter library not storing or having lost the NAND chip parameter corresponding to the read NAND chip ID, etc., etc., without further limitation.

[0027] In one embodiment, the loading strategy refers to a combination of command configurations used to read the NAND flash memory firmware. The loading strategy may include interface modes such as Toggle DDR and ONFI 3.0, and command sequences consisting of vendor-specific commands such as entering / exiting SLC mode, pre-fetching, and random data output. Furthermore, multiple loading strategies may be constructed based on the NAND flash memory model used in the solid-state drive product's Bill of Materials (BOM), or may include different targeted command configuration combinations configured according to different manufacturers, etc., and the specifics are not limited here.

[0028] In one embodiment, establishing communication between the NAND flash memory chips and the controller of the solid-state drive (SSD) according to multiple preset loading strategies means sequentially attempting to establish communication between the NAND flash memory chips and the controller according to the order of the preset loading strategies. The communication between the NAND flash memory chips and the controller refers to the physical layer connection established between the controller and the NAND flash memory, including matching timing, control voltage, and corresponding operation commands.

[0029] In one embodiment, the target loading strategy used when communication is successfully established refers to a loading strategy that enables communication between the NAND flash memory chip and the controller. It should be noted that the target loading strategy may be a loading strategy corresponding to the NAND flash memory chip model, a loading strategy that does not correspond to the NAND flash memory chip model but corresponds to the NAND flash memory chip manufacturer, or a loading strategy that does not correspond to the NAND flash memory chip manufacturer, etc., and is not specifically limited here. Specifically, due to the order of loading strategies, it is inevitable that loading strategies that do not correspond to the NAND flash memory model but correspond to the NAND flash memory manufacturer will be placed before loading strategies that correspond to the NAND flash memory model, or vice versa. In both cases, communication is established tentatively in sequence. If communication between the flash memory and the controller is successfully established using a loading strategy that does not correspond to the NAND flash memory model, then even if the loading strategy that corresponds to the NAND flash memory model is placed later, it will not be used. In this way, communication between the NAND flash memory and the controller can be established through loading strategies that do not correspond to the NAND flash memory model, thus ensuring that communication between the NAND flash memory and the controller is not limited to loading strategies that correspond to the NAND flash memory model, thereby effectively providing fault tolerance for firmware loading.

[0030] In one embodiment, during the process of establishing communication between the NAND flash memory chips and the controller of the solid-state drive one by one according to multiple preset loading strategies, specifically for each loading strategy, the controller is driven to read the firmware of the NAND flash memory chip and verify the read firmware according to the current loading strategy. In response to the failure of firmware verification according to the current loading strategy, the controller is driven to read the firmware of the NAND flash memory chip according to the next loading strategy. In response to the successful read verification corresponding to the current loading strategy, the current loading strategy is determined as the target loading strategy.

[0031] It should be noted that the specific reasons for firmware verification failure under the current loading strategy are varied. For example, the loading strategy may read incorrect firmware binary data, or the loading strategy may be unable to read complete firmware binary data, etc. The specific reasons are not limited here.

[0032] In one embodiment, firmware loading of the NAND flash memory using the target loading strategy used when communication is successfully established means that after successfully establishing communication between the NAND flash memory and the main controller according to the target loading strategy, the firmware of the NAND flash memory is read according to the interface mode and command combination included in the target loading strategy, and the read firmware is verified in the main controller. When the verification of the read firmware is successful, the loading operation is performed in the main controller.

[0033] See Figure 2 , Figure 2 The flowchart of a solid-state drive boot method according to another embodiment of this application is shown. In one embodiment, the solid-state drive boot method may further include the following steps.

[0034] Step 210: In response to the fact that the number of times the solid-state drive successfully establishes communication between the NAND flash and the controller through the target loading strategy is not less than a preset threshold, the target loading strategy is determined as the optimal boot strategy used by the controller. Step 220: In response to the solid-state drive being powered on again and no NAND chip parameter being matched in the NAND chip parameter library after power-on, establish communication between the NAND chip and the controller according to the optimal boot strategy.

[0035] In one embodiment, the optimal startup strategy refers to the loading strategy that the controller will try first when it attempts to establish communication between the NAND flash memory and the controller through various loading strategies after failing to find a match for any NAND flash memory parameter in the NAND flash memory parameter library.

[0036] It is important to note that regardless of whether the SSD successfully established the NAND flash memory and controller through one of the multiple loading strategies during the last power-on, the standard process still needs to be followed after the current power-on. This means first reading the NAND ID in the NAND flash memory, and then comparing it one by one in the database using the NAND ID.

[0037] By determining the target loading strategy as the optimal boot strategy for the controller when the number of successful communication establishments between the NAND flash memory and the controller through the target loading strategy is no less than a preset threshold, the priority of the target loading strategy can be adjusted to the highest among multiple loading strategies. In this way, if no NAND flash memory parameter is matched in the NAND flash memory parameter library after power-on, the optimal boot strategy with the highest success rate can be directly used to attempt to establish communication between the NAND flash memory and the controller. This helps to quickly establish communication between the NAND flash memory and the controller, thereby enabling the solid-state drive to have the ability to quickly handle and identify anomalies.

[0038] See Figure 3 , Figure 3The flowchart of a solid-state drive (SSD) boot method according to another embodiment of this application is shown. In one embodiment, the SSD boot method may further include the following steps.

[0039] Step 310: In response to the failure to establish communication between the NAND flash chip and the controller according to the optimal boot strategy, establish communication between the NAND flash chip and the controller one by one according to the remaining multiple loading strategies; Step 320: In response to the successful establishment of communication between the NAND flash memory and the controller, the loading strategy used when the communication was successfully established is determined as the new target loading strategy, and communication between the NAND flash memory and the controller is established according to the new target loading strategy.

[0040] In one embodiment, establishing communication between the NAND flash memory chip and the controller one by one according to the remaining multiple loading strategies means attempting to establish communication between the NAND flash memory chip and the controller of the solid-state drive sequentially according to the order of the multiple loading strategies other than the current optimal boot strategy among the preset multiple loading strategies.

[0041] In one embodiment, the new target loading strategy refers to a loading strategy among a plurality of preset loading strategies that, in addition to the previous target loading strategy, can also establish communication between the NAND flash memory chip and the controller. It should be noted that the new target loading strategy may be a loading strategy corresponding to the NAND flash memory chip model, a loading strategy that does not correspond to the NAND flash memory chip model but corresponds to the NAND flash memory chip manufacturer, or a loading strategy that does not correspond to the NAND flash memory chip manufacturer, etc., and is not specifically limited here.

[0042] In one embodiment, during the process of establishing communication between the NAND flash memory chip and the controller one by one according to the remaining multiple loading strategies, specifically for the remaining loading strategies, the controller can be driven to read the firmware of the NAND flash memory chip according to the current loading strategy and verify the read firmware. In response to the failure of firmware verification according to the current loading strategy, the controller can be driven to read the firmware of the NAND flash memory chip according to the next loading strategy. In response to the successful read verification corresponding to the current loading strategy, the current loading strategy is determined as the new target loading strategy.

[0043] In one embodiment, establishing communication between the NAND flash memory chip and the controller according to the new target loading strategy means that after successfully establishing communication between the NAND flash memory chip and the controller according to the new target loading strategy, the firmware of the NAND flash memory chip is read according to the interface mode and command combination included in the new target loading strategy, and the firmware is verified in the controller. When the verification of the firmware is successful, the loading operation is performed in the controller.

[0044] During SSD boot, the internal operating environment of the controller and NAND flash memory is not fixed. Therefore, the operating environment may differ from the previous boot, and the target loading strategy used last time may not be compatible with this new environment. This can lead to situations where communication between the controller and NAND flash memory was successfully established last time, but fails this time. Therefore, if the optimal boot strategy fails to establish communication between the NAND flash memory and controller, the remaining loading strategies can be used to attempt to establish communication one by one. This improves the flexibility of communication establishment between the NAND flash memory and controller, effectively enhancing the fault tolerance of firmware loading.

[0045] See Figure 4 , Figure 4 The flowchart of a solid-state drive (SSD) boot method according to another embodiment of this application is shown. In one embodiment, the SSD boot method may further include the following steps.

[0046] Step 410: In response to the fact that the number of times the solid-state drive successfully established communication between the NAND flash and the controller through the target loading strategy and the new target loading strategy is not less than a preset threshold, the number of times the target loading strategy is used and the number of times the new target loading strategy is used are compared. Step 420: In response to the difference in the number of times the target loading strategy is used and the number of times the new target loading strategy is used, the optimal startup strategy is corrected based on the one that is used the most among the target loading strategy and the new target loading strategy.

[0047] In one embodiment, the number of times the solid-state drive (SSD) successfully establishes communication between the NAND flash memory and the controller using both the target loading strategy and the new target loading strategy is not less than a preset threshold. This means that within a certain period of time, the number of times the SSD successfully establishes communication between the NAND flash memory and the controller using both the target loading strategy and the new target loading strategy is greater than or equal to the preset threshold. The number of times the SSD successfully establishes communication between the NAND flash memory and the controller using the target loading strategy and the new target loading strategy can be equal or unequal; no specific limitation is made here.

[0048] In one embodiment, correcting the optimal startup strategy based on the most frequently used target loading strategy and the new target loading strategy means determining the target loading strategy as the optimal startup strategy when the target loading strategy is used most frequently, and determining the new target loading strategy as the optimal startup strategy when the new target loading strategy is used most frequently.

[0049] In one embodiment, in response to the same number of times the target loading strategy is used and the number of times the new target loading strategy is used, one of the number of times the target loading strategy is used and the new target loading strategy is randomly determined as the optimal startup strategy.

[0050] By dynamically changing the priority of the target loading strategy and the new target loading strategy among multiple loading strategies based on their usage frequency, the optimal boot strategy can be dynamically changed to the loading strategy with the highest communication establishment success rate, thereby further improving the efficiency of firmware loading fault tolerance for solid-state drives.

[0051] See Figure 5 , Figure 5 The flowchart of a solid-state drive (SSD) boot method according to yet another embodiment of this application is shown. In one embodiment, the SSD boot method may further include the following steps.

[0052] Step 510: In response to the failure to establish communication between the NAND flash chip and the controller through each loading strategy, obtain additional storage boot information; Step 520: Repair the communication between the NAND flash memory and the controller based on the boot information; Step 530: Start the solid-state drive.

[0053] In one embodiment, the additionally stored boot information refers to external storage information used to guide the controller to perform communication repair on the NAND flash memory, force the controller to boot the solid-state drive, and generate boot feedback information. This boot information can be stored in additional flash memory.

[0054] In one embodiment, repairing the communication between the NAND flash memory chip and the controller based on the boot information refers to resetting the communication parameters and interface modes used between the controller and the NAND flash memory chip based on the boot information, and dynamically reconfiguring the communication parameters and interface modes to rebuild the effective physical connection between the controller and the NAND flash memory chip.

[0055] In one embodiment, booting the solid-state drive (SSD) refers to determining the boot method based on the effect of repairing the communication between the NAND flash memory chip and the controller using boot information, and then booting the SSD according to the determined boot method.

[0056] In one embodiment, during the boot process of the solid-state drive (SSD), specifically in response to the successful repair of communication between the NAND flash memory chip and the controller, the SSD is restarted. Then, communication between the NAND flash memory chip and the controller is established based on the boot information, and firmware is loaded onto the NAND flash memory chip. By rebuilding the communication between the NAND flash memory chip and the controller through the boot information before loading the firmware, the SSD possesses a certain degree of firmware loading fault tolerance even when communication between the NAND flash memory chip and the controller cannot be established using existing loading strategies, effectively improving the fault tolerance of firmware loading.

[0057] In one embodiment, during the boot process of the solid-state drive (SSD), specifically in response to a failure to repair communication between the NAND flash memory and the controller, boot feedback information is output via boot information. In response to receiving a forced boot command, the SSD is forcibly booted according to the boot information. After reconstructing communication between the NAND flash memory and the controller using the boot information, feedback is sent to the user. This allows the SSD to be forcibly booted manually when communication between the NAND flash memory and the controller cannot be established, thus providing data recovery and fault tolerance for the user.

[0058] By setting boot information, the SSD can still use the boot information to repair communication when it is unable to establish communication between the NAND flash memory and the controller through the existing loading strategy. This allows the SSD to boot regardless of whether the repair is successful or not, improving boot fault tolerance and effectively reducing the probability of the SSD failing to boot and becoming unusable due to momentary failure.

[0059] The following examples illustrate the application scenarios of the embodiments of this application.

[0060] It should be noted that the solid-state drive boot method provided in this application embodiment can be applied to cloud database management application scenarios. The following description takes cloud database management application scenarios as an example.

[0061] For example, in cloud databases, the power-on and power-off of the numerous solid-state drives (SSDs) in the storage system providing hardware services to the cloud database are strictly controlled, adhering to the principle of "no power-off unless absolutely necessary." Therefore, when a cloud database system needs to power down an SSD, it generally indicates a critical power-off scenario. Since cloud database systems store large amounts of data, after troubleshooting and power-on, the system needs to be able to provide data services to database users normally as before. This requires ensuring that the SSDs boot normally after power-on. However, the operation and management of cloud database systems are complex and prone to timing mismatches, voltage fluctuations, and other issues, severely affecting the firmware loading of SSDs. If the firmware of the NAND flash memory cannot be loaded correctly, it can lead to serious accidents.

[0062] To address this, if the SSD fails to find any NAND flash memory parameters in the preset NAND flash memory parameter library after power-on, it can establish communication between the SSD's NAND flash memory and the controller one by one according to multiple preset loading strategies. Upon successful establishment of communication between the NAND flash memory and the controller, firmware is loaded onto the NAND flash memory using the target loading strategy employed during successful communication. In this process, because the cloud database system can establish communication between the SSD's NAND flash memory and the controller one by one using multiple preset loading strategies even when no NAND flash memory parameters are found in the preset NAND flash memory parameter library after power-on, communication fault tolerance between the NAND flash memory and the controller is established. Furthermore, after successful communication, firmware is loaded onto the NAND flash memory using the target loading strategy employed during successful communication. This allows the SSD to boot successfully even with internal identification anomalies, effectively improving the firmware loading fault tolerance of the SSD. This reduces the likelihood of the SSD failing to boot due to internal identification anomalies even when the firmware is actually correct, thus contributing to the normal operation of the cloud database system after power-on.

[0063] In addition to the embodiments described above, one embodiment of this application also provides an electronic device. See also Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application. Figure 6 As shown, the electronic device includes a memory 1100 and a processor 1200. The number of memories 1100 and processors 1200 can be one or more. Figure 6 Taking a memory 1100 and a processor 1200 as an example; Figure 6 The memory 1100 and processor 1200 can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0064] The memory 1100, as a computer-readable storage medium, can be used to store one or more software programs, computer-executable programs, and modules, such as the program, instructions, or modules corresponding to the solid-state drive boot method provided in any embodiment of this application. The processor 1200 implements the solid-state drive boot method provided in any embodiment of this application by executing one or more computer programs, instructions, and modules stored in the memory 1100.

[0065] The memory 1100 may primarily include a program storage area and a data storage area, wherein the program storage area may store the operating system and computer programs required for at least one function. Furthermore, the memory 1100 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 1100 may further include memory remotely located relative to the processor 1200, and these remote memories can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0066] In addition to the embodiments described above, one embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for executing the boot method of a solid-state drive as described in any of the preceding embodiments.

[0067] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of an electronic device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the electronic device to perform the solid-state drive boot method as described in any of the preceding embodiments.

[0068] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0069] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method for booting a solid-state drive, characterized in that, include: In response to the fact that no NAND chip parameter is matched in the preset NAND chip parameter library after the solid-state drive is powered on, communication is established between the NAND chips and the controller of the solid-state drive one by one according to multiple preset loading strategies. In response to the successful establishment of communication between the NAND flash chip and the main controller, firmware is loaded onto the NAND flash chip using the target loading strategy used when the communication was successfully established.

2. The method according to claim 1, characterized in that, The method further includes: If the number of times the solid-state drive successfully establishes communication between the NAND flash memory and the controller through the target loading strategy is not less than a preset threshold, the target loading strategy is determined as the optimal boot strategy used by the controller. In response to the solid-state drive being powered on again and no NAND chip parameter being matched in the NAND chip parameter library after power-on, communication between the NAND chip and the controller is established according to the optimal boot strategy.

3. The method according to claim 2, characterized in that, The method further includes: In response to the failure to establish communication between the NAND flash chip and the controller according to the optimal boot strategy, communication is established between the NAND flash chip and the controller one by one according to the remaining multiple loading strategies; In response to the successful establishment of communication between the NAND flash memory and the controller, the loading strategy used when the communication was successfully established is determined as the new target loading strategy, and communication between the NAND flash memory and the controller is established according to the new target loading strategy.

4. The method according to claim 3, characterized in that, The method further includes: In response to the fact that the number of times the solid-state drive successfully establishes communication between the NAND flash and the controller through the target loading strategy and the new target loading strategy is not less than the preset threshold, the number of times the target loading strategy is used and the number of times the new target loading strategy is used are compared. In response to the difference in the number of times the target loading strategy is used and the number of times the new target loading strategy is used, the optimal startup strategy is corrected based on the one that is used the most among the target loading strategy and the new target loading strategy.

5. The method according to claim 1, characterized in that, The step of establishing communication between the NAND flash memory chips and the controller of the solid-state drive one by one according to multiple preset loading strategies includes: For each loading strategy, the main controller is driven to read the firmware of the NAND chip and verify the read firmware according to the current loading strategy. In response to the failure to verify the firmware read according to the current loading strategy, the main controller is driven to read the firmware of the NAND chip according to the next loading strategy. In response to the successful read verification corresponding to the current loading strategy, the current loading strategy is determined as the target loading strategy.

6. The method according to claim 1, characterized in that, The method further includes: In response to the failure to establish communication between the NAND flash chip and the controller through each of the aforementioned loading strategies, additional stored boot information is obtained; Repair the communication between the NAND flash memory chip and the controller according to the guidance information; Start the solid-state drive.

7. The method according to claim 6, characterized in that, The process of booting the solid-state drive includes: In response to the successful repair of communication between the NAND flash memory chip and the controller, the solid-state drive is restarted; Communication between the NAND flash memory chip and the main controller is established based on the boot information, and firmware is loaded onto the NAND flash memory chip.

8. The method according to claim 6, characterized in that, The process of booting the solid-state drive includes: In response to the failure to repair communication between the NAND flash chip and the main controller, a startup feedback message is output through the boot information; In response to receiving a forced boot command, the solid-state drive is forcibly booted according to the boot information.

9. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; The solid-state drive boot method as described in any one of claims 1 to 8 is implemented when at least one of the programs is executed by at least one of the processors.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the boot method of the solid-state drive as described in any one of claims 1 to 8.

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