Data processing method and device, processor chip and computer system

Abstract

The invention relates to a data processing method and device, a processor chip and a computer system, and belongs to the technical field of computers. According to the method, a proxy cache of a system memory in a chip testing stage is provided through a data processing device, a source device sends a read-write request for chip testing to the data processing device, and the data processing device replaces a data read-write operation on the system memory with a data read-write operation on the proxy cache according to the received read-write request. According to the technical scheme, the processor chip does not need to perform data read-write operation on the system memory, testing of most functions in the processor chip does not need to depend on the system memory and does not need to be performed after debugging of the system memory is completed, and therefore the duration of the chip testing stage can be shortened, and the testing time before mass production of the processor chip can be saved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method, apparatus, processor chip, and computer system. Background Technology

[0002] Current computer systems generally include processor chips and system memory. Before processor chips are put into actual mass production, they need to undergo a lot of functional testing, most of which require the processor chip to perform data read and write operations on the system memory.

[0003] The component in a processor chip that initiates a read / write request is called the source device. The process of a processor chip performing data read / write operations on system memory relies on the access link of "source device in processor chip - coherence controller in processor chip - system memory". Therefore, most tests of the processor chip depend on this access link. Since the last node of this access link is system memory, most tests of the processor chip can only be performed after the system memory has been debugged and can be accessed normally. Debugging the system memory to be accessible normally is quite complex and takes a long time, which leads to a low chip test rate and a long chip test period during the chip testing phase, i.e., a long testing time before mass production of the processor chip. Summary of the Invention

[0004] This disclosure provides a data processing method, apparatus, processor chip, and computer system to at least solve the problem of the long testing phase in related technologies. The technical solution of this disclosure is as follows: According to a first aspect of the embodiments of this disclosure, a data processing method is provided. The method, applied in a data processing apparatus for a processor chip, includes: Receive a read / write request from a source device in a computer system, the read / write request instructing a data read / write operation on the system memory in the computer system, the read / write request being used to test the processor chip; Based on the read / write request, data read / write operations are performed on the first cache of the data processing device, where the first cache is a proxy for the system memory during the chip testing phase; In response to the completion of the data read / write operation on the first cache, a read / write response is sent to the source device, the read / write response indicating that the read / write request has been completed.

[0005] Optionally, the read / write request is a write request, which indicates that test data is written to the system memory, and the test data is used to test the processor chip; The data read / write operation on the first cache of the data processing device based on the read / write request includes: Based on the write request, the test data is written to the first cache.

[0006] Optionally, the read / write request is a read request, which indicates that test data is read from the system memory, and the test data is used to test the processor chip; Before receiving the read / write request from the source device in the processor chip, the method further includes: Receive a write request from the source device, the write request instructing the test data to be written to the system memory; Based on the write request, the test data is written to the first cache; The data read / write operation on the first cache of the data processing device based on the read / write request includes: Based on the read request, the test data is read from the first cache.

[0007] Optionally, the data processing device further includes a second cache, which provides data caching services for read and write requests during chip usage.

[0008] Optionally, the data processing device is a consistency controller or a memory controller in the processor chip, wherein the memory controller is used to control the system memory, and the consistency controller is a higher-level controller of the memory controller.

[0009] According to a second aspect of the present disclosure, a data processing apparatus is provided, comprising: The first cache acts as a proxy for the system memory during the chip testing phase; The control circuit is configured to perform the data processing method described in the first aspect or any possible implementation of the first aspect.

[0010] According to a third aspect of the present disclosure, a processor chip is provided, the processor chip including a processor core and the data processing apparatus provided in the second aspect above.

[0011] According to a fourth aspect of the present disclosure, a computer system is provided, the computer system including a system memory and a processor chip, the processor chip including the data processing apparatus provided in the second aspect above.

[0012] The aforementioned data processing method provides a proxy cache for the system memory during the chip testing phase through a data processing device. The source device in the computer system can send read / write requests for chip testing to the data processing device. Upon receiving the read / write request, the data processing device replaces the data read / write operations on the system memory with data read / write operations on the proxy cache. After completing the data read / write operations on the proxy cache, it can return a read / write response to the source device. This eliminates the need for the processor chip to perform data read / write operations on the system memory. Therefore, the testing of most functions within the processor chip does not depend on the system memory and does not require waiting for the system memory to be debugged and accessible. Furthermore, most functional tests can be performed in parallel. Thus, the chip testing rate during the chip testing phase can be improved, the chip testing time can be reduced, and testing time before mass production of the processor chip can be saved.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0015] Figure 1 This is a schematic diagram of a computer system according to an exemplary embodiment; Figure 2 This is a schematic diagram of the structure of a data processing apparatus according to an exemplary embodiment; Figure 3 This is a schematic diagram of the structure of a consistency controller 14 according to an exemplary embodiment; Figure 4 This is a flowchart illustrating a data processing method according to an exemplary embodiment; Figure 5 This is a flowchart illustrating a data processing method for a write request according to an exemplary embodiment; Figure 6 This is a flowchart illustrating a data processing method for a read request according to an exemplary embodiment. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0017] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0018] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the read / write requests or data involved in this application were obtained with full authorization.

[0019] In response, it is used to indicate the conditions or states on which the operation performed depends. When the conditions or states on which it depends are met, one or more operations performed can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0020] In some embodiments, the meaning of A and / or B includes three cases: A and B, and A and B.

[0021] First, the following is an introduction to some of the terms used in this disclosure.

[0022] Network on chip (NOC) is an on-chip interconnect architecture for complex Systems on a Chip (SoC) with multiple cores / processors. Borrowing from the layered design principles of computer networks, it abstracts various on-chip functional modules (processor cores, memory controllers, I / O devices, proxy devices, consistency controllers, etc.) as "nodes." Through predefined topologies and communication protocols, it enables efficient, scalable, and low-latency data interaction between nodes. In other words, NOC is a network-based communication subsystem within an integrated circuit chip used to transmit data, interrupts, and other information between multiple nodes.

[0023] Cache consistency is a set of technical principles and protocols in multi-core / multi-processor systems that ensure logical consistency of the same shared data across multiple cache copies (distributed across caches on different processor cores) and memory. Its core objective is to ensure that when any node (processor core or I / O device) performs a read or write operation on shared data, other nodes accessing that data can obtain the latest valid version, avoiding data races, logical errors, or distortion of calculation results caused by asynchronous cache copies.

[0024] The Home Node / Home Agent is an abstracted consistency controller, a core component for maintaining cache consistency across multi-core processors. It manages data ownership, coordinates inter-core communication, and resolves cache conflicts. It receives read and write requests from multiple processor cores, handles cache line permission allocation (e.g., exclusive, shared, invalid states), and prevents data conflicts caused by concurrent access from multiple processor cores. It implements consistency protocols (e.g., directory protocols, listener protocols) and maintains the global cache state through message broadcasting or directory tables.

[0025] This disclosure relates to a computer system, which includes a processor chip and system memory. The system memory is the memory of the computer system and is used to provide data storage services. System memory can also be called main memory or RAM. The computer system has at least one processor chip, which can also be called a processor, such as a central processing unit (CPU).

[0026] The processor chip includes a coherence controller, a memory controller, and at least one processor core. The processor core is the computational core of the processor chip, responsible for executing instructions and processing data; a processor core, such as a CPU core, is an example. Optionally, the processor chip also includes at least one acceleration computing core, which is heterogeneous with the processor core and used for accelerating computation. Optionally, the processor chip also includes Direct Memory Access (DMA). Optionally, the processor chip also includes other components besides the processor, acceleration computing core, and DMA device that can access system memory; however, no limitations are placed on these other components.

[0027] The memory controller is used to control the system memory, and it is responsible for the data exchange between the system memory and the processor chip. The memory controller can also be called a memory controller.

[0028] The consistency controller is the consistency master node. Any component in the processor chip that needs to read or write data to the system memory (such as the processing core, accelerated computing core, or DMA device) can initiate a read / write request to the consistency controller, which will then process the requests and complete the data read / write operations on the system memory. The consistency controller is the next-level controller above the memory controller, and it can perform data read operations on the system memory through the memory controller.

[0029] Figure 1 This is a schematic diagram illustrating a computer system according to an exemplary embodiment, such as... Figure 1 As shown, the computer system includes at least one processor cluster 10, at least one processor agent device 11, at least one input / output (I / O) device 12, at least one I / O agent device 13, multiple consistency controllers 14, multiple directory snooping filters 15, multiple system memories 16, multiple memory controllers 17, at least one accelerated computing core 18, at least one accelerated computing core agent device 19, at least one DMA device 20, at least one DMA agent device 21, and a transport network 22.

[0030] For ease of description, the processor proxy device 11, IO proxy device 13, accelerated computing core proxy device 19, and DMA proxy device 21 in the computer system are referred to as proxy devices in the computer system. Each proxy device in the computer system and the consistency controller 14 are connected to the transmission network 22, so that these proxy devices and the consistency controller 14 can interact with each other through the transmission network 22.

[0031] The transport network 22 includes multiple interconnected transport nodes. Each agent device and the consensus controller 14 in the computer system are connected to the transport nodes in the transport network 22, thus interconnecting the agent devices, consensus controller 14, and transport nodes in the computer system to form a Network of Consensus (NOC). The NOC contains the agent devices, consensus controller 14, and transport nodes in the transport network 22. Each piece of hardware in the NOC (such as an agent device or consensus controller 14) is abstracted (or virtualized) as a node. Therefore, in some embodiments, the agent devices, consensus controller 14, and transport nodes in the transport network 22 are respectively referred to as agent nodes, consensus master nodes (or consensus nodes), and transport nodes. The nodes in the NOC are connected via a bus. To meet functional requirements such as cache consistency and memory consistency, as well as performance requirements such as bandwidth, latency, and power consumption, the nodes in the NOC interact with each other through a consensus on-chip network bus protocol for requests, responses, and data exchange.

[0032] The computer system includes at least one processor chip X, and each processor chip X includes at least one processor core, a processor agent device 11, a cache (such as a level 1 cache, a level 2 cache, and a level 3 cache), a coherence controller 14, a directory snooping filter 15, a memory controller 17, an accelerated computing core 18, an accelerated computing core agent device 19, a DMA device 20, and a DMA agent device 21.

[0033] Each processor cluster 10 includes multiple processor cores, and each processor cluster 10 is a logical unit composed of multiple processor cores. For example... Figure 1 As shown, processor cores in the same processor cluster 10 may originate from the same processor chip. In other embodiments, processor cores in the same processor cluster 10 may also originate from multiple processor chips X.

[0034] Each processor cluster 10 has its own cache, which serves as an intermediate layer between the processor cluster 10 and system memory, used to accelerate data access by the processor cores within the processor cluster 10. From a hierarchical perspective, the cache of any processor cluster 10 is divided into private caches and shared caches. Private caches are independent caches for each processor core within the processor cluster 10, belonging to a single processor core; examples include the Level 1 (L1) cache and Level 2 (L2) cache in processor chip X. Shared caches are caches shared by multiple processor cores within the processor cluster 10, belonging to the processor cluster 10, and used for sharing data among multiple processor cores; examples include the Last Level Cache (LLC) in processor chip X, such as the Level 3 cache.

[0035] Each processor cluster 10 corresponds to a processor proxy device 11. The processor proxy device 11 is a proxy node for the corresponding processor cluster 10 and is responsible for proxying the read and write transmissions generated by the corresponding processor cluster 10. The processor cluster 10 can interact with the consistency controller 14 through the corresponding processor proxy device 11. The processor proxy device 11 can be a hardware module independent of the processor cluster 10, or it can be a hardware module integrated into the processor core of the processor cluster 10.

[0036] The coherence controller 14 is the core component in processor chip X that implements the cache coherence protocol and is responsible for managing cache data coherence across processor clusters 10. For example, when a processor core in one processor cluster 10 requests to read data that is in the cache of another processor cluster 10, the coherence controller 14 can coordinate the data read and return the data in the cache of the other processor cluster 10 to the requesting processor core.

[0037] The consistency controller 14 is a hardware or logical component that coordinates cache data consistency operations in a multi-core / multi-processor (i.e., multi-processor cluster 10), and its form and implementation may vary depending on the computer system architecture.

[0038] The consistency controller 14 maintains cache consistency across multiple processor clusters 10 based on a cache consistency protocol, such as the MESI (Modified Exclusive Shared Invalid) protocol. Different consistency controllers 14 are responsible for maintaining cache consistency between their respective processor clusters 10.

[0039] Each consistency controller 14 corresponds to a directory listener filter 15, and the consistency controller 14 is connected to the corresponding directory listener filter 15. Each directory listener filter 15 is used to store a consistency directory, which records data caching information, including but not limited to: data owner information, data consistency status, etc. The data owner information indicates the storage location of the data, such as the processor core and / or processor cluster 10 to which the cache storing the data belongs. The data consistency status refers to the consistency status of the data among multiple processor clusters 10, such as modified state, exclusive state, shared state, invalid state, etc. The consistency controller 14 and the corresponding directory listener filter 15 work together. The consistency controller 14 obtains the data owner information and consistency status, etc., by querying the consistency directory in the directory listener filter 15.

[0040] For data access initiated by processor cores within the same processor cluster 10, if the data accessed by a processor core exists only in the cache of its own processor cluster 10 and not in the cache of the processor core, the processor core can directly perform data read and write operations in the cache of its own processor cluster 10 to complete the data access; if the data accessed by a processor core is not in the cache of its own processor cluster 10 but in the cache of another processor cluster 10, then the consistency controller 14 needs to query the consistency directory to obtain the owner information and consistency status information of the data. Then, the consistency controller 14 transmits the data from the cache of the other processor cluster 10 to the requesting processor core through the transmission network 17 and the corresponding proxy node. Then, the consistency controller 14 updates the cache information of the relevant data in the consistency directory to ensure cache consistency for subsequent accesses.

[0041] The state of data in the cache of processor cluster 10 is called the cache state of the data. The cache state of the data includes states such as the data having only a single copy in the caches of multiple processor clusters 10, the data having multiple copies in the caches of multiple processor clusters 10, or the data existing only in memory. Directory listener filter 15 can track the cache state of data and store the tracked cache state. When directory listener filter 15 discovers a consistent transaction through listening, it will query the cache state of the data it is tracking and issue corresponding probes to complete cache consistency maintenance.

[0042] It should be understood that the consistency controller 14 performs cache consistency maintenance for certain data, including: maintaining the cache information of the data in the consistency directory, and / or, listening to the cache status of the data through the directory listening filter 15. Specifically, the consistency controller performs cache consistency maintenance for certain data, which means performing cache consistency maintenance for the memory address corresponding to the data. The memory address corresponding to the data is the memory address in the memory space (i.e., system memory 16) used to store the data.

[0043] System memory 16 is the main memory (i.e., RAM) in the computer system, used to store data. Each system memory 16 corresponds to a memory controller 17, which is used to control the corresponding system memory 16.

[0044] Each consistency controller 14 corresponds to a memory controller 17. Each consistency controller 14 is connected to the corresponding memory controller 17. The consistency controller 14 accesses the system memory 16 through the corresponding memory controller 17.

[0045] Each I / O device 12 corresponds to an I / O proxy device 13. The I / O proxy device 13 is a proxy node for the corresponding I / O device 12 and is responsible for proxying the read and write transmissions generated by the corresponding I / O device 12. The I / O proxy device 13 can be a hardware module independent of the I / O device 12, or it can be a hardware module integrated into the I / O device 12.

[0046] Each accelerated computing core 18 corresponds to an accelerated computing core proxy device 19. The accelerated computing core proxy device 19 is a proxy node for the corresponding accelerated computing core 18 and is responsible for proxying the read and write transmissions generated by the corresponding computing core 18. The accelerated computing core proxy device 19 can be a hardware module independent of the accelerated computing core 18, or it can be a hardware module integrated into the accelerated computing core 18. Figure 1The processor chip X includes an accelerated computing core 18 and an accelerated computing core proxy device 19 as an example. In some embodiments, the processor chip X does not include the accelerated computing core 18 and the accelerated computing core proxy device 19, and the accelerated computing core 18 and the accelerated computing core proxy device 19 are located outside the processor chip X.

[0047] Each DMA device 20 corresponds to a DMA proxy device 21. The DMA proxy device 21 is a proxy node for the corresponding DMA device 20 and is responsible for proxying the read and write transfers generated by the corresponding DMA device 20. The DMA proxy device 21 can be a hardware module independent of the accelerated DMA device 20, or it can be a hardware module integrated into the DMA device 20. Figure 1 The processor chip X includes a DMA device 20 and a DMA proxy device 21 as an example. In some embodiments, the processor chip X does not include the DMA device 20 and the DMA proxy device 21, and the DMA device 20 and the DMA proxy device 21 are located outside the processor chip X.

[0048] For ease of description, the component in a computer system that can initiate read and write requests is called the source device. For example, the processor core, I / O device 12, accelerated computing core 18, or DMA device 20 in processor cluster 10 can all be used as source devices.

[0049] Any source device in the computer system can send its read / write requests to the system memory 16 to its proxy node. The proxy node receives the read / write requests from the source device and forwards them to the consistency controller 14 via the transmission network 22. The consistency controller 14 receives the read / write requests from the source device, processes them, and returns the processing results to the proxy node of the source device. The proxy node then returns the processing results from the consistency controller 14 to the source device.

[0050] The read / write request from the source device includes a target memory address, indicating that data read / write operations should be performed on the memory space indicated by the target memory address in the system memory 16. The consistency controller 14 processes the read / write request from the source device by: performing cache consistency maintenance on the target memory address; sending a new read / write request to the corresponding memory controller 17 based on the read / write request, the new read / write request including the target memory address; the memory controller 17 receiving the new read / write request, performing data read / write operations on the memory space indicated by the target memory address in the corresponding system memory 16 based on the new read / write request, and returning the data read / write operation result to the consistency controller 14; the consistency controller 14 receiving the data read / write operation result and returning it as the processing result of the read / write request from the source device to the proxy node of the source device.

[0051] The I / O device 12, the accelerated computing core 18, the DMA device 20, and the directory listening filter 15 are all optional devices. In some embodiments, the computer system does not include at least one of the I / O device 12, the accelerated computing core 18, the DMA device 20, and the directory listening filter 15.

[0052] The computer system described above can be applied to electronic devices, which can be terminals or servers. Terminals include, but are not limited to, mobile phones, computers, wearable devices, music players, smart home devices, and vehicles.

[0053] The phase of functional testing of processor chips before actual mass production is called the chip testing phase. During this phase, numerous functional tests are performed on the processor chip, most of which require the processor chip to perform data read and write operations to system memory. These tests, which require the processor chip to perform data read and write operations to system memory, include, but are not limited to: testing whether the source devices in the processor chip can perform correct data read and write operations to system memory; testing whether the communication links between the source devices in the processor chip and system memory can communicate normally; and testing whether the communication links between the various source devices in the computer system and the consistency controller in the processor chip can communicate normally.

[0054] During chip testing, not only must normal access to system memory be debugged, but also many functions within the processor chip must be tested. However, debugging system memory to achieve normal access is complex and time-consuming. In related technologies, testing most functions within the processor chip relies on the "source device-coherence controller-system memory" access link. Therefore, testing most functions within the processor chip must wait until system memory debugging is complete and normal access to system memory is possible. This results in a low chip test rate and a long testing period, meaning a significant pre-mass production testing time for the processor chip. If testing most functions within the processor chip did not depend on system memory, these tests could be performed in parallel, thereby increasing the chip test rate, reducing the testing period, and ultimately saving pre-mass production testing time.

[0055] Based on this, the present disclosure provides a data processing apparatus that can be applied to a processor chip, i.e., the processor chip includes the data processing apparatus. Figure 2 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this disclosure, as shown below. Figure 2As shown, the data processing device includes a control circuit 201 and a first buffer 202, which are connected together. The control circuit 201 can be implemented using at least one of the following hardware forms: Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), and Application Specific Integrated Circuit (ASIC). The implementation method of the control circuit 201 is not limited here. The first buffer 202 is a storage circuit used to store data.

[0056] The first cache 202 acts as a proxy for the system memory during the chip testing phase. The storage space of the first cache 202 is much smaller than that of the system memory, sufficient to meet the data read / write requirements of the processor chip during the chip testing phase. The control circuit 201 is configured to execute the method steps performed by the data processing apparatus in the data processing method provided in the embodiments of this disclosure. During the chip testing phase, the control circuit 201 can be used to execute the method steps performed by the data processing device in the data processing method provided in the following embodiments of the present disclosure. In this method, after obtaining the read / write request of the source device in the computer system, the control circuit 201 uses the first cache 202 as a proxy node of the system memory and performs data reading operations on the first cache 202 based on the read / write request to replace the data read / write operations on the system memory. Therefore, the processor chip does not need to perform data read / write operations on the system memory, and there is no need for the processor chip to interact with the system memory. Thus, the testing of most functions within the processor chip does not depend on the system memory, and there is no need to wait for the system memory to be debugged and the system memory to be accessible normally before it can be performed. Moreover, the testing of most functions can be performed in parallel. Therefore, the chip testing rate during the chip testing phase can be improved, the chip testing time can be reduced, and the testing time before the mass production of the processor chip can be saved.

[0057] Optionally, the data processing apparatus further includes a second cache, which provides data caching services for read and write requests during the chip usage phase. The chip usage phase refers to the phase in which the processor chip is actually used in an electronic device.

[0058] In some embodiments, the data processing apparatus described above is a consistency controller in a computer system. Figure 3 Taking the consistency controller 14 shown as an example, as Figure 3As shown, the consistency controller 14 includes a control circuit 141, a control circuit 201, a first cache 202, and a second cache 142, wherein the control circuit 141 is connected to the control circuit 201, the first cache 202, and the second cache 142. The control circuit 141 can be implemented in at least one hardware form of FPGA, PLA, or ASIC, and the implementation method of the control circuit 141 is not limited here.

[0059] Control circuit 141 and control circuit 201 are two different control circuits, which can be referred to as the second control circuit and the first control circuit, respectively. In some embodiments, control circuit 201 can also be integrated into control circuit 141 as a circuit module within control circuit 141.

[0060] The control circuit 141 is the master controller in the consistency controller 14, used to control and coordinate data reading and writing, requesting, responding and frame listening behaviors in the computer system.

[0061] The first cache 202 and the second cache 142 are different storage circuits, both used for storing data. The first cache 202 acts as a proxy for the system memory during the chip testing phase. The second cache 142 is used to provide data caching services for read and write requests during the chip usage phase, for example, caching data to be written to or read from the system memory during the chip usage phase.

[0062] It should be understood that the control circuit 201 and the first cache 202 are used to decouple the system memory. The consistency controller 14 has a system memory decoupling function, which means replacing data read and write operations on the system memory with data read and write operations on the first cache 202.

[0063] During the chip testing phase, users can enable the decoupled system memory function through configuration. When the decoupled system memory function is enabled, the control circuit 201 and the first cache 202 are enabled. For read and write requests from the source device, the control circuit 201 performs data read operations on the first cache 202.

[0064] After the chip testing phase, the user disables the decoupled system memory function by configuring it, and the control circuit 201 and the first cache 202 are not enabled (i.e., turned off). During the chip usage phase, the decoupled system memory function is turned off, and both the control circuit 201 and the first cache 202 are turned off. For read and write requests from the source device, the control circuit 141 uses the data requested for reading and writing that is cached in the second cache 142.

[0065] To distinguish between the data requested for reading and writing during the chip testing phase and the chip usage phase, the data requested for reading and writing during the chip testing phase is referred to as test data, and the data requested for reading and writing during the chip usage phase is referred to as business data. That is, the first cache 202 is used to cache test data, and the second cache 142 is used to cache business data. Since the first cache 202 is enabled (i.e., turned on) during the chip testing phase, the system memory does not need to store test data during this phase.

[0066] In some embodiments, the consistency controller 14 further includes other circuit modules, such as request queues, listener queues, and completion queues. The request queue stores information related to each read / write request received by the consistency controller 14. The completion queue stores completion information for each read / write request received by the consistency controller 14. The listener queue stores multiple listener results from the directory listener filter. These queues are storage circuits capable of storing data in the form of queues.

[0067] In some embodiments, the data processing apparatus described above is a memory controller in a computer system. That is, in addition to its inherent main controller and cache, the memory controller also includes the aforementioned control circuit 201 and first cache 202. The cache inherent in the memory controller itself is a second cache.

[0068] In some embodiments, the data processing device is a component in the processing chip that is independent of the consistency controller and the memory controller. For example, the data processing device is connected to the transmission network 22 in the computer system, or the data processing device is connected in series between the consistency controller and the memory controller.

[0069] Next, combined Figure 4 The flow of the data processing method provided in the embodiments of this disclosure will be described.

[0070] Figure 4 This is a flowchart illustrating a data processing method according to an exemplary embodiment, see [link to flowchart]. Figure 4 The data processing method includes the following steps.

[0071] 401. A source device in a computer system sends a read / write request to a data processing device in a processor chip. The read / write request instructs the system memory in the computer system to perform data read / write operations. The read / write request is used to test the processor chip.

[0072] The computer system refers to the computer system where the processing chip is located. This computer system can be any of the computer systems described above. The source device is any device in the computer system that initiates a read / write request, such as any I / O device 12, any accelerated computing core 18, any DMA device 20, or any processor core in any processor cluster 10. The processor chip is any of the processor chips described above, and the data processing device is any of the data processing devices described above.

[0073] A read / write request includes a target memory address, which is the memory address of the memory space requested to be accessed. This memory space can be a block of storage space in the system memory 16 (i.e., main memory) of the computer system, and the target memory address indicates that memory space. Therefore, a read / write request indicates that data read / write operations be performed on the memory space indicated by the target memory address in the system memory.

[0074] A read / write request can be either a read request or a write request. A read request indicates data to be read from system memory, specifically data to be read from the memory space indicated by the target memory address in system memory. A write request indicates data to be written to system memory, specifically data to be written to the memory space indicated by the target memory address in system memory. Read / write requests are triggered during the chip testing phase. Therefore, when a read request is a read request, the data requested to be read is test data; when a write request is a write request, the data requested to be written is test data; when a write request is a write request, the data requested to be written is test data; the write request also includes the test data to be written.

[0075] During the chip testing phase, after powering on the computer system, the various components of the computer system (such as...) Figure 1 The various components shown begin to run and function, and the user enables the decoupled system memory function of the data processing device through configuration.

[0076] The component in a computer system that initiates a read / write request is called the source device (IO device, accelerated computing core, DMA device, or a processor core within a processor cluster). After the decoupled system memory function of the data processing device is enabled, in order to test the processor chip, a source device in the computer system sends a read / write request to the data processing device to instruct it to perform data read / write operations on the system memory.

[0077] With data processing device as Figure 1Taking the consistency controller 14 in the computer system shown as an example, the source device sends a read / write request to the agent node of the source device in the computer system. The agent node of the source device receives the read / write request of the source device and sends the read / write request of the source device to the consistency controller 14 through the transmission network 22. The consistency controller 14 receives the read / write request of the source device.

[0078] Taking a data processing device as an example, separate from the consistency controller and memory controller in a computer system, assuming the data processing device is connected to transmission network 22, the source device sends a read / write request to the proxy node of the source device in the computer system. The proxy node of the source device receives the read / write request and sends it to the data processing device through transmission network 22. The data processing device receives the request from the source device. At this time, the consistency controller will receive the read / write request from the source device.

[0079] 402. The data processing device receives read / write requests from the source device.

[0080] The read / write request is the read / write request sent by the source device in step 401.

[0081] 403. Based on the read / write request, the data processing device performs data read / write operations on the first cache of the data processing device. The first cache is a proxy for the system memory during the chip testing phase.

[0082] The first cache is a component in the data processing device, such as the first cache 202 described above.

[0083] The data processing device performs data read and write operations on the first cache in different ways depending on the type of read and write request. Next, we will introduce the data processing device's methods for performing data read and write operations on the first cache when the read and write requests are write requests and read requests, respectively, in conjunction with (1) and (2) below.

[0084] (1) A read / write request is a write request. A write request indicates that test data is written to the system memory. A write request includes the target memory address and the test data to be written.

[0085] When the read / write request is a write request, the data processing device writes test data to the first cache based on the write request. For example, the data processing device parses the target memory address and test data from the write request, writes the test data to the first cache, generates target mapping information based on the target memory address and the cache address of the cache space where the test data is located in the first cache, and stores the target mapping information. The target mapping information indicates the mapping relationship between the target memory address and the cache address, so as to indicate that the read / write operation on the memory space indicated by the target memory address is converted into a read / write operation on the cache space indicated by the cache address.

[0086] (2) The read / write request is a read request. The read request indicates that test data is read from the system memory. The read request includes the target memory address.

[0087] In the case of a read request, before receiving the read request, the source device sends a write request to the data processing device. The write request instructs the writing of test data to the system memory. The write request includes the target memory address and the test data to be written. The data processing device receives the write request and writes the test data to the first cache based on the write request. The writing method is as described in (1) above. After the data processing device writes the test data to the first cache, it generates and stores the target mapping information described above for use when reading the test data later.

[0088] Subsequently, upon receiving a read request indicating that the test data should be read from system memory, the data processing device reads the test data from the first cache based on the read request. For example, it parses the target memory address from the read request, queries the target mapping information from various stored mapping information based on the target memory address, obtains the cache address mapped to the target memory address from the target mapping information, and reads the test data from the cache space indicated by that cache address in the first cache. Each mapping information indicates a mapping relationship between a memory address in system memory and a cache address in the first cache, signifying that a data read / write operation on the memory space indicated by a memory address is converted into a read / write operation on the data cache space indicated by a cache address.

[0089] When the data processing device is a consistency controller, for the read / write request, the data processing device first performs cache consistency maintenance on the target memory address, and then executes this step 403.

[0090] In step 403, the data read / write operations of the processor chip on the system memory are converted into data read / write operations of the data processing device on the first cache, thereby eliminating the need to perform data read / write operations on the system memory.

[0091] 404. In response to the completion of the data read / write operation on the first cache, the data processing device sends a read / write response to the source device, indicating that the read / write request has been completed.

[0092] Specifically, when the read / write request is a write request, the read / write response is a write response, indicating that the write request has been completed. When the read / write request is a read request, the read / write response is a read response, indicating that the read request has been completed, and the read response includes the test data that was read.

[0093] Taking a read / write request as an example, the data processor writes all the test data into the first cache, completes the write operation on the first cache, generates a write response, and sends the write response to the source device.

[0094] Taking a read request as an example, the data processor reads the test data from the first cache, completes the data read operation on the first cache, generates a read response based on the read test data, and sends the read response to the source device.

[0095] Taking the data processing device as a consistency controller as an example, the way to send read and write responses to the source device can be as follows: the consistency controller sends read and write responses to the agent node of the source device through the transmission network 22, the agent node receives the read and write responses, sends read and write responses to the source device, and the source device receives the read and write responses.

[0096] The processor chip provided in this disclosure includes a data processing device, which provides a proxy cache (i.e., a first cache) for the system memory during the chip testing phase. During the chip testing phase, the source device in the computer system sends read / write requests for chip testing to the data processing device. Upon receiving the read / write request, the data processing device replaces the data read / write operation on the system memory with a data read / write operation on the proxy cache. After completing the data read / write operation on the proxy cache, it returns a read / write response to the source device. This eliminates the need for the processor chip to perform data read / write operations on the system memory. Therefore, the testing of most functions within the processor chip does not depend on the system memory and does not require waiting for the system memory to be debugged and accessible. Furthermore, most function tests can be performed in parallel. This improves the chip testing rate and reduces the duration of the chip testing phase, thereby saving testing time before mass production of the processor chip.

[0097] In some embodiments, after the data processing device receives a read / write request from the source device, if the data processing device has enabled the decoupling system memory function, the data processing device performs the above step 403; if the data processing device has not enabled the decoupling system memory function, the data processing device performs data read / write operations on the system memory based on the data read / write request.

[0098] Taking the data processing device as the consistency controller and the read / write requests from the source device as write requests as an example, such as... Figure 5 As shown, the consistency controller receives a write request from the source device. The write request includes the target memory address and the data to be written (such as test data). The consistency controller performs cache consistency maintenance for the target memory address and determines whether the decoupled system memory function is enabled. If the decoupled system memory function is enabled, the consistency controller writes the data to be written to the first cache, returns a write response to the source device, and the data write operation of the processing chip to the system memory ends. If the decoupled system memory function is not enabled, the consistency controller writes the data to be written to the system memory, returns a write response to the source device after the write is complete, and the data write operation of the processing chip to the system memory ends.

[0099] Taking the data processing device as the consistency controller and the read / write requests from the source device as read requests as an example, such as... Figure 6 As shown, the consistency controller receives a read request from the source device. The read request includes the target memory address. The consistency controller performs cache consistency maintenance for the target memory address and determines whether the decoupled system memory function is enabled. If the decoupled system memory function is enabled, the consistency controller reads data (such as test data) from the first cache based on the target memory address and returns a read response to the source device. The read response includes the read data, and the data read operation of the processing chip on the system memory ends. If the decoupled system memory function is not enabled, the consistency controller reads data from the system memory based on the target memory address, returns a read response to the source device based on the read data, and the read response includes the read data. The data write operation of the processing chip on the system memory ends.

[0100] Figure 5 This example illustrates a write request that includes the data to be written. In some embodiments, the write request does not include the data to be written, and the data to be written is sent separately. Figure 6 This example illustrates the use of a read response that includes the read data. In some embodiments, the read response does not include the read data, which is sent separately.

[0101] It should be understood that after the chip testing phase is completed, the user can configure the decoupled system memory function of the consistency controller so that during the chip usage phase, the consistency controller performs data read and write operations on the system memory based on the read and write requests of the source device, and uses its own second cache to cache the data read or written in the data read and write operation request.

[0102] In some embodiments, the data processing device is a memory controller. The difference from the example above is that the consistency controller receives read / write requests from the source device via the transport network 22, and the memory controller receives read / write requests from the source device via the consistency controller. Exemplarily, after receiving a read / write request from the source device, the consistency controller sends a new read / write request to the memory controller based on the source device's read / write request. The memory controller receives the new read / write request, which has the same request type as the source device's read / write request. The new read / write request includes a target memory address and indicates that data read / write operations should be performed on the memory space indicated by the target memory address in the computer system. For the memory controller, the new read / write request is a read / write request from the source device. Accordingly, based on the new read / write request, the memory controller performs data read / write operations on the first cache in the memory controller. In response to the completion of the data read / write operation, the memory controller sends a read / write response to the consistency controller. The consistency controller, based on the read / write response returned by the memory controller, sends a read / write response to the source device for the source device's read / write request. It should be understood that since the memory controller does not perform cache consistency maintenance, it does not perform cache consistency maintenance operations on the received read / write requests.

[0103] In some embodiments, the data processing device is connected in series between the memory controller and the consistency controller. When the data processing device enables the decoupled system memory function, the consistency controller sends the aforementioned new read / write request to the data processing device. Based on the received read / write request, the consistency controller performs data read / write operations on the first cache in the data processing device. In response to the completion of the data read / write operation, the consistency controller sends a read / write response to the consistency controller. Based on the read / write response returned by the data processing device, the consistency controller sends a read / write response to the source device for the read / write request.

[0104] In an exemplary embodiment, a processor chip (such as a CPU) is also provided, the processor chip including a data processing device and at least one processor core (CPU core), the data processing device being configured to execute the various method steps performed by the data processing device in the above-described data processing method.

[0105] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0106] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0107] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data processing method, characterized in that, The method, applied in a data processing apparatus for a processor chip, includes: Receive a read / write request from a source device in a computer system, the read / write request instructing a data read / write operation on the system memory in the computer system, the read / write request being used to test the processor chip; Based on the read / write request, data read / write operations are performed on the first cache of the data processing device, where the first cache is a proxy for the system memory during the chip testing phase; In response to the completion of the data read / write operation on the first cache, a read / write response is sent to the source device, the read / write response indicating that the read / write request has been completed.

2. The method according to claim 1, characterized in that, The read / write request is a write request, which indicates that test data is written to the system memory, and the test data is used to test the processor chip; The data read / write operation on the first cache of the data processing device based on the read / write request includes: Based on the write request, the test data is written to the first cache.

3. The method according to claim 1, characterized in that, The read / write request is a read request, which indicates that test data is read from the system memory, and the test data is used to test the processor chip; Before receiving the read / write request from the source device in the processor chip, the method further includes: Receive a write request from the source device, the write request instructing the test data to be written to the system memory; Based on the write request, the test data is written to the first cache; The data read / write operation on the first cache of the data processing device based on the read / write request includes: Based on the read request, the test data is read from the first cache.

4. The method according to any one of claims 1-3, characterized in that, The data processing device further includes a second cache, which provides data caching services for read and write requests during chip usage.

5. The method according to claim 4, characterized in that, The data processing device is a consistency controller or a memory controller in the processor chip. The memory controller is used to control the system memory, and the consistency controller is the next level controller of the memory controller.

6. A data processing apparatus, characterized in that, include: The first cache acts as a proxy for the system memory during the chip testing phase; A control circuit is configured to perform the method according to any one of claims 1-3.

7. The data processing apparatus according to claim 6, characterized in that, The data processing device further includes a second cache, which provides data caching services for read and write requests during chip usage.

8. The data processing apparatus according to claim 7, characterized in that, The data processing device is a consistency controller or a memory controller in a processor chip. The memory controller is used to control the system memory, and the consistency controller is the next-level controller of the memory controller.

9. A processor chip, characterized in that, It includes a processor core and a data processing apparatus according to any one of claims 6-8.

10. A computer system, characterized in that, It includes system memory and a processor chip, the processor chip including a processor core and a data processing device according to any one of claims 6-8.

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