Data processing method and device, processor chip and computer system

Abstract

The invention relates to a data processing method and device, a processor chip and a computer system, and belongs to the technical field of computers. According to the method, a storage position of to-be-mirrored data in a memory and a storage position of mirrored data of the to-be-mirrored data in the memory are specified respectively through a mirrored address field and a mirrored address field in a preset address field, and due to the fact that the positions and sizes indicated by the mirrored address field and the mirrored address field are variable, the mirrored data of the to-be-mirrored data in the memory can be stored through a preset address pair. According to the method, the mirror image memory can be flexibly set for the to-be-mirrored data, so that the data with relatively low reliability requirements in the computer system can be ignored, only the data with relatively high reliability requirements in the computer system is taken as the to-be-mirrored data, and the mirror image memory is set for the to-be-mirrored data through the preset address pair; therefore, the memory space of the memory in the computer system can be utilized to the maximum extent, and the hardware cost of the memory in the computer system is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing method, apparatus, processor chip, and computer system. Background Technology

[0002] Current computer systems consist of a processor chip and multiple memory chips. Each processor chip includes multiple memory channels, and each memory channel connects to at least one memory chip. For data backup, currently, at the memory channel level, a portion of these memory chips are designated as the main memory of the computer system, while other memory chips are designated as mirror memory of the main memory. For example, a processor chip may include memory channel 1 and memory channel 2. The memory chips connected to memory channel 1 are designated as main memory, and the memory chips connected to memory channel 2 are designated as mirror memory of the main memory.

[0003] When a processor chip stores data in main memory, it also stores a mirror image of that data in mirror memory for backup. However, the data that needs to be backed up is generally data with high reliability requirements (i.e., data with high reliability requirements), while not all data in main memory has high reliability requirements. Typically, the proportion of data with high reliability requirements in main memory is relatively small, meaning that data with high reliability requirements in main memory occupies relatively little memory space in mirror memory. In the backup scheme described above, when setting up mirror memory at the memory channel level, the reliability requirements of the data are not considered. When storing data in main memory, the mirror image of that data is also stored in mirror memory. This results in some data in main memory with low reliability requirements being backed up in mirror memory, occupying memory space in mirror memory and thus wasting memory space. Summary of the Invention

[0004] This disclosure provides a data processing method, apparatus, processor chip, and computer system, which can reduce the waste of memory space in computer systems. The technical solution of this disclosure is as follows: According to a first aspect of the present disclosure, a data processing method is provided, applied to a first processor chip in a computer system, the method comprising: Obtain a first write request, the first write request indicating that first data be written to the memory space indicated by a first memory address segment in the computer system; Write the first data into the memory space indicated by the first memory address segment; Based on at least one preset address pair, it is determined whether the first memory address segment belongs to the mirrored address segment. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store the data to be mirrored in the computer system, and the mirrored address segment is used to store the mirrored data of the data. If the first memory address segment belongs to the mirrored address segment, write the mirrored data of the first data to the memory space indicated by the mirrored address segment of the first memory address segment, where the mirrored address segment of the first memory address segment belongs to the mirrored address segment of the mirrored address segment to which the first memory address segment belongs.

[0005] Optionally, the length of the mirrored address segment and the mirrored address segment of the mirrored address segment are the same.

[0006] Optionally, the mirrored address segment to which the first memory address segment belongs corresponds to the first memory channel in the first processor chip, and the mirrored address segment of the first memory address segment corresponds to the second memory channel in the first processor chip. Writing the first data to the memory space indicated by the first memory address segment includes: The first data is written into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment includes: If the first memory address segment belongs to the mirrored address segment, the mirrored data of the first data is written to the memory space indicated by the mirrored address segment of the first memory address segment through the second memory channel.

[0007] Optionally, the computer system includes a second processor chip, the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and the mirrored address segment of the first memory address segment corresponds to a memory channel in the second processor chip. Writing the first data to the memory space indicated by the first memory address segment includes: The first data is written into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment includes: If the first memory address segment belongs to the mirrored address segment, a second write request is sent to the second processor chip. The second write request indicates that mirrored data of the first data be written to the memory space indicated by the mirrored address segment of the first memory address segment.

[0008] Optionally, the at least one preset address is set based on the business's demand for mirrored data.

[0009] According to a second aspect of the present disclosure, a data processing method is provided, applied to a first processor chip in a computer system, the method comprising: Obtain a first read request, the first read request instructing the reading of second data from the memory space indicated by the second memory address segment in the computer system; Read the second data from the memory space indicated by the second memory address segment; If a data reading error occurs when reading the second data, it is determined whether the second memory address segment belongs to the mirrored address segment based on at least one preset address pair. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store the mirrored data in the computer system, and the mirrored address segment is used to store the mirrored data of the mirrored data. If the second memory address segment belongs to the mirrored address segment, read the mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment, where the mirror address segment of the second memory address segment belongs to the mirror address segment of the mirrored address segment to which the second memory address segment belongs; Send the mirror image data of the second data that has been read.

[0010] Optionally, the length of the mirrored address segment and the mirrored address segment of the mirrored address segment are the same.

[0011] Optionally, the mirrored address segment to which the second memory address segment belongs corresponds to the third memory channel in the first processor chip, and the mirrored address segment of the second memory address segment corresponds to the fourth memory channel in the first processor chip. Reading the second data from the memory space indicated by the second memory address segment includes: The second data is read from the memory space indicated by the second memory address segment through the third memory channel; If the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment includes: If the second memory address segment belongs to the mirrored address segment, the mirrored data of the second data is read from the memory space indicated by the mirrored address segment of the second memory address segment through the fourth memory channel.

[0012] Optionally, the computer system includes a third processor chip, the mirrored address segment to which the second memory address segment belongs corresponds to a first memory channel in the first processor chip, and the mirrored address segment of the second memory address segment corresponds to a memory channel in the third processor chip; Reading the second data from the memory space indicated by the second memory address segment includes: The second data is read from the memory space indicated by the second memory address segment through the third memory channel; If the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment includes: If the second memory address segment belongs to the mirrored address segment, a second read request is sent to the third processor chip. The second read / write request indicates that the mirrored data of the second data be read from the memory space indicated by the mirrored address segment of the second memory address segment.

[0013] Optionally, the at least one preset address is set based on the business's demand for mirrored data.

[0014] According to a third aspect of the present disclosure, a data processing apparatus is provided, including a cache and a control circuit, wherein the cache is used to store data, and the control circuit is configured to perform a data processing method provided in any of the possible embodiments of the first and second aspects described above.

[0015] Optionally, the data processing device is a consistency controller or a memory controller in a processor chip, wherein the memory controller is used to control the memory chip, and the consistency controller is a higher-level controller than the memory controller.

[0016] According to a fourth aspect of the present disclosure, a processor chip is provided, the processor chip including a processor core and the data processing apparatus provided in the third aspect above.

[0017] According to a fifth aspect of the present disclosure, a computer system is provided, the computer system including a memory chip and a processor chip provided in the fourth aspect above, the memory chip being used to store data written by the processor chip.

[0018] In the above data processing method, for the data to be mirrored, the memory storage location of the data is specified by the mirrored address segment within a preset address range, and the memory storage location of the mirrored data is specified by the mirrored address segment within the same preset address range. Thus, the preset address pairs allow for setting mirror memory for the data to be mirrored at the address range granularity. Since the location and size indicated by both the mirrored and mirrored address segments are variable, the preset address pairs enable flexible setting of mirror memory for the data to be mirrored at the address range granularity. This allows data with relatively low reliability requirements in the computer system to be ignored, and mirror memory not to be set for such data. Only data with relatively high reliability requirements in the computer system is used as the data to be mirrored. By setting mirror memory of appropriate size and location for the data to be mirrored using preset address pairs, the utilization of the computer system's memory space can be maximized, reducing the hardware cost of the computer system's memory.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0021] Figure 1 This is a schematic diagram of a computer system according to an exemplary embodiment; Figure 2 This is a schematic diagram illustrating a system address space according to an exemplary embodiment; Figure 3 This is a schematic diagram illustrating a method for setting up mirrored memory in the same processor chip according to an exemplary embodiment; Figure 4 This is a schematic diagram illustrating a cross-chip mirrored memory configuration according to an exemplary embodiment; Figure 5 This is a flowchart illustrating a data processing method according to an exemplary embodiment; Figure 6 This is a flowchart illustrating a data writing process according to an exemplary embodiment; Figure 7 This is a flowchart illustrating another data processing method according to an exemplary embodiment; Figure 8 This is a flowchart illustrating a data reading process according to an exemplary embodiment; Figure 9This is a structural block diagram of a data processing apparatus according to an exemplary embodiment. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0023] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0024] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the read / write requests or data involved in this application were obtained with full authorization.

[0025] In response, it is used to indicate the conditions or states on which the operation performed depends. When the conditions or states on which it depends are met, one or more operations performed can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0026] In some embodiments, the meaning of A and / or B includes three cases: A and B, and A and B.

[0027] First, the following is an introduction to some of the terms used in this disclosure.

[0028] Network on chip (NOC) is an on-chip interconnect architecture for complex Systems on a Chip (SoC) with multiple cores / processors. Borrowing from the layered design principles of computer networks, it abstracts various on-chip functional modules (processor cores, memory controllers, I / O devices, proxy devices, consistency controllers, etc.) as "nodes." Through predefined topologies and communication protocols, it enables efficient, scalable, and low-latency data interaction between nodes. In other words, NOC is a network-based communication subsystem within an integrated circuit chip used to transmit data, interrupts, and other information between multiple nodes.

[0029] Cache consistency is a set of technical principles and protocols in multi-core / multi-processor systems that ensure logical consistency of the same shared data across multiple cache copies (distributed across caches on different processor cores) and memory. Its core objective is to ensure that when any node (processor core or I / O device) performs a read or write operation on shared data, other nodes accessing that data can obtain the latest valid version, avoiding data races, logical errors, or distortion of calculation results caused by asynchronous cache copies.

[0030] The Home Node / Home Agent is an abstracted consistency controller, a core component for maintaining cache consistency across multi-core processors. It manages data ownership, coordinates inter-core communication, and resolves cache conflicts. It receives read and write requests from multiple processor cores, handles cache line permission allocation (e.g., exclusive, shared, invalid states), and prevents data conflicts caused by concurrent access from multiple processor cores. It implements consistency protocols (e.g., directory protocols, listener protocols) and maintains the global cache state through message broadcasting or directory tables.

[0031] This disclosure relates to processor chips, which can also be called processors, such as central processing units (CPUs). Processor chips include processor cores, caches, coherence controllers, memory controllers, and multiple memory channels.

[0032] The processor core is the computing core of a processor chip, responsible for executing instructions and processing data. A processor core, such as a CPU core, is a typical example. A processor chip typically contains at least one processor core.

[0033] The cache in a processor chip provides data caching services (i.e., for storing data) for the processor cores within the chip. This cache includes a Level 1 cache, a Level 2 cache, and a Level 3 cache. The Level 1 and Level 2 caches are private caches for the processor cores, while the Level 3 cache is a shared cache within the processor chip. Each processor core is connected to one Level 1 cache, each Level 1 cache is connected to at least one Level 2 cache, and the Level 3 cache is connected to each Level 2 cache.

[0034] Optionally, the processor chip also includes at least one accelerated computing core, which refers to a computing core heterogeneous with the processor core and used for accelerated computing. Optionally, the processor chip also includes a Direct Memory Access (DMA) device. Optionally, the processor chip also includes other components capable of accessing system memory besides the processor core, accelerated computing core, and DMA device; no limitation is made to these other components.

[0035] Processor chips are used in computer systems. A computer system includes at least one system memory, which is the memory within the computer system used to provide data storage services. System memory can also be called the computer system's RAM, and correspondingly, the memory controller can also be called a memory controller. A computer system has one system memory, and each system memory includes multiple memory chips, each of which provides data storage services.

[0036] The memory controller controls the system memory in a computer system and is responsible for data interaction between the system memory and the processor chip. The memory controller connects to multiple memory channels in the processor chip, and each memory channel connects to at least one memory chip in the memory system. For any memory channel in the processor chip, the memory controller can perform data read and write operations on the memory chip connected to that memory channel.

[0037] The consistency controller is the consistency master node. Any component in the processor chip that needs to read or write data to the system memory (such as the processing core, accelerated computing core, or DMA device) can initiate a read / write request to the consistency controller, which will then process the requests and complete the data read / write operations on the system memory. The consistency controller is the next-level controller above the memory controller, and it can perform data read operations on the system memory through the memory controller.

[0038] The aforementioned processor chip can be used in computer systems. Figure 1This is a schematic diagram of a computer system according to an exemplary embodiment. The computer system includes at least one processor chip and at least one system memory. The processor chip and system memory have been described above and will not be repeated here. When the computer system includes multiple processor chips, the multiple processor chips are each independent chips, or some or all of the multiple processor chips can be integrated into a single large chip.

[0039] Components in the processor chip and at least one component in the system memory (such as a memory chip) are interconnected via a transmission network to enable the components in the processor chip to communicate with the components in the system memory.

[0040] like Figure 1 As shown, the computer system includes at least one processor cluster 10, at least one processor agent device 11, at least one input / output (I / O) device 12, at least one I / O agent device 13, multiple coherence controllers 14, multiple directory snooping filters 15, memory chips 16, multiple memory controllers 17, at least one accelerated computing core 18, at least one accelerated computing core agent device 19, at least one DMA device 20, at least one DMA agent device 21, and a transport network 22.

[0041] For ease of description, the processor proxy device 11, IO proxy device 13, accelerated computing core proxy device 19, and DMA proxy device 21 in the computer system are referred to as proxy devices in the computer system. Each proxy device in the computer system and the consistency controller 14 are connected to the transmission network 22, so that these proxy devices and the consistency controller 14 can interact with each other through the transmission network 22.

[0042] The transport network 22 includes multiple interconnected transport nodes. Each agent device and the consensus controller 14 in the computer system are connected to the transport nodes in the transport network 22, thus interconnecting the agent devices, consensus controller 14, and transport nodes in the computer system to form a Network of Consensus (NOC). The NOC contains the agent devices, consensus controller 14, and transport nodes in the transport network 22. Each piece of hardware in the NOC (such as an agent device or consensus controller 14) is abstracted (or virtualized) as a node. Therefore, in some embodiments, the agent devices, consensus controller 14, and transport nodes in the transport network 22 are respectively referred to as agent nodes, consensus master nodes (or consensus nodes), and transport nodes. The nodes in the NOC are connected via a bus. To meet functional requirements such as cache consistency and memory consistency, as well as performance requirements such as bandwidth, latency, and power consumption, the nodes in the NOC interact with each other through a consensus on-chip network bus protocol for requests, responses, and data exchange.

[0043] The computer system includes at least one processor chip X, and each processor chip X includes at least one processor core, a processor agent device 11, a cache (such as a level 1 cache, a level 2 cache, and a level 3 cache), a coherence controller 14, a directory snooping filter 15, a memory controller 17, an accelerated computing core 18, an accelerated computing core agent device 19, a DMA device 20, and a DMA agent device 21.

[0044] Each processor cluster 10 includes multiple processor cores, and each processor cluster 10 is a logical unit composed of multiple processor cores. For example... Figure 1 As shown, processor cores in the same processor cluster 10 may come from the same processor chip. In other embodiments, processor cores in the same processor cluster 10 may also come from multiple processor chips.

[0045] Each processor cluster 10 has its own cache, which serves as an intermediate layer between the processor cluster 10 and the system memory, used to accelerate data access by the processor cores within the processor cluster 10. From a hierarchical perspective, the cache of any processor cluster 10 is divided into private caches and shared caches. Private caches are independent caches for each processor core within the processor cluster 10, belonging to a single processor core; examples include the Level 1 (L1) cache and Level 2 (L2) cache in processor chip X. Shared caches are caches shared by multiple processor cores within the processor cluster 10, belonging to the processor cluster 10, and used for sharing data among multiple processor cores; examples include the Last Level Cache (LLC) in a processor chip, such as the Level 3 cache in processor chip X.

[0046] Each processor cluster 10 corresponds to a processor proxy device 11. The processor proxy device 11 is a proxy node for the corresponding processor cluster 10 and is responsible for proxying the read and write transmissions generated by the corresponding processor cluster 10. The processor cluster 10 can interact with the consistency controller 14 through the corresponding processor proxy device 11. The processor proxy device 11 can be a hardware module independent of the processor cluster 10, or it can be a hardware module integrated into the processor core of the processor cluster 10.

[0047] The coherence controller 14 is the core component in processor chip X that implements the cache coherence protocol and is responsible for managing cache data coherence across processor clusters 10. For example, when a processor core in one processor cluster 10 requests to read data that is in the cache of another processor cluster 10, the coherence controller 14 can coordinate the data read and return the data in the cache of the other processor cluster 10 to the requesting processor core.

[0048] The consistency controller 14 is a hardware or logical component that coordinates cache data consistency operations in a multi-core / multi-processor (i.e., multi-processor cluster 10), and its form and implementation may vary depending on the computer system architecture.

[0049] The consistency controller 14 maintains cache consistency across multiple processor clusters 10 based on a cache consistency protocol, such as the MESI (Modified Exclusive Shared Invalid) protocol. Different consistency controllers 14 are responsible for maintaining cache consistency between their respective processor clusters 10.

[0050] Each consistency controller 14 corresponds to a directory listener filter 15, and the consistency controller 14 is connected to the corresponding directory listener filter 15. Each directory listener filter 15 is used to store a consistency directory, which records data caching information, including but not limited to: data owner information, data consistency status, etc. The data owner information indicates the storage location of the data, such as the processor core and / or processor cluster 10 to which the cache storing the data belongs. The data consistency status refers to the consistency status of the data among multiple processor clusters 10, such as modified state, exclusive state, shared state, invalid state, etc. The consistency controller 14 and the corresponding directory listener filter 15 work together. The consistency controller 14 obtains the data owner information and consistency status, etc., by querying the consistency directory in the directory listener filter 15.

[0051] For data access initiated by processor cores within the same processor cluster 10, if the data accessed by a processor core exists only in the cache of its own processor cluster 10 and not in the caches of other processor clusters 10, the data read and write operations can be performed directly in the cache of its own processor cluster 10 to complete the data access. If the data accessed by a processor core is not in the cache of its own processor cluster 10 but in the cache of another processor cluster 10, the consistency controller 14 needs to query the consistency directory to obtain the owner information and consistency status information of the data. Then, the consistency controller 14 transmits the data from the cache of the other processor cluster 10 to the requesting processor core through the transmission network 17 and the corresponding proxy node. Subsequently, the consistency controller 14 updates the cache information of the relevant data in the consistency directory to ensure cache consistency for subsequent accesses.

[0052] The state of data in the cache of processor cluster 10 is called the cache state of the data. The cache state of the data includes states such as the data having only a single copy in the caches of multiple processor clusters 10, the data having multiple copies in the caches of multiple processor clusters 10, or the data existing only in memory. Directory listener filter 15 can track the cache state of data and store the tracked cache state. When directory listener filter 15 discovers a consistent transaction through listening, it will query the cache state of the data it is tracking and issue corresponding probes to complete cache consistency maintenance.

[0053] It should be understood that the cache consistency maintenance performed by the consistency controller 14 for a certain data includes: maintaining the cache information of the data in the consistency directory, and / or, listening to the cache status of the data through the directory listening filter 15. Specifically, the cache consistency maintenance performed by the consistency controller 14 for a certain data also means performing cache consistency maintenance for the memory address corresponding to that data, where the memory address is the memory address in the memory space of the memory chip 16 used to store the data.

[0054] The memory chip 16 is located in the system memory, which includes at least one memory chip 16. The system memory is the memory in the computer system used to store data. Each memory controller 17 corresponds to multiple memory chips 16. The correspondence is as follows: the memory controller 17 is connected to multiple memory channels in the processor chip, and each memory channel corresponds to at least one memory chip 16, so that the memory controller 17 corresponds to the memory chip 16 of each connected memory channel.

[0055] The memory controller 17 is used to control the corresponding memory chip 16 through the memory channel, such as performing data read and write operations on the corresponding memory chip 16.

[0056] Each consistency controller 14 corresponds to a memory controller 17. Each consistency controller 14 is connected to the corresponding memory controller 17. The consistency controller 14 performs data read and write operations on the memory chip 16 corresponding to the memory controller 17 through the corresponding memory controller 17.

[0057] Each I / O device 12 corresponds to an I / O proxy device 13. The I / O proxy device 13 is a proxy node for the corresponding I / O device 12 and is responsible for proxying the read and write transmissions generated by the corresponding I / O device 12. The I / O proxy device 13 can be a hardware module independent of the I / O device 12, or it can be a hardware module integrated into the I / O device 12.

[0058] Each accelerated computing core 18 corresponds to an accelerated computing core proxy device 19. The accelerated computing core proxy device 19 is a proxy node for the corresponding accelerated computing core 18 and is responsible for proxying the read and write transmissions generated by the corresponding computing core 18. The accelerated computing core proxy device 19 can be a hardware module independent of the accelerated computing core 18, or it can be a hardware module integrated into the accelerated computing core 18. Figure 1 The processor chip X includes an accelerated computing core 18 and an accelerated computing core proxy device 19 as an example. In some embodiments, the processor chip X does not include the accelerated computing core 18 and the accelerated computing core proxy device 19, and the accelerated computing core 18 and the accelerated computing core proxy device 19 are located outside the processor chip X.

[0059] Each DMA device 20 corresponds to a DMA proxy device 21. The DMA proxy device 21 is a proxy node for the corresponding DMA device 20 and is responsible for proxying the read and write transfers generated by the corresponding DMA device 20. The DMA proxy device 21 can be a hardware module independent of the accelerated DMA device 20, or it can be a hardware module integrated into the DMA device 20. Figure 1 The processor chip X includes a DMA device 20 and a DMA proxy device 21 as an example. In some embodiments, the processor chip X does not include the DMA device 20 and the DMA proxy device 21, and the DMA device 20 and the DMA proxy device 21 are located outside the processor chip X.

[0060] For ease of description, the component in a computer system that can initiate read and write requests is called the source device. For example, the processor core, I / O device 12, accelerated computing core 18, or DMA device 20 in processor cluster 10 can all be used as source devices.

[0061] Any source device in the computer system can send read / write requests to its own proxy device (i.e., proxy node). The proxy device receives the read / write requests from the source device and forwards them to the consistency controller 14 via the transmission network 22. The consistency controller 14 receives the read / write requests from the source device, processes them, and returns the processing results to the proxy device of the source device. The proxy device then returns the processing results from the consistency controller 14 to the source device.

[0062] The I / O device 12, the accelerated computing core 18, the DMA device 20, and the directory listening filter 15 are all optional devices. In some embodiments, the computer system does not include at least one of the I / O device 12, the accelerated computing core 18, the DMA device 20, and the directory listening filter 15.

[0063] In some embodiments, the computer system described above is applied in an electronic device, and all components of the computer system reside in the same electronic device. In some embodiments, the computer system described above can span multiple electronic devices, and components in multiple electronic devices (such as system memory or processor chips) can be connected to the transmission network 22, so that the components in multiple electronic devices can be interconnected through the transmission network 22 to form a computer system that can communicate.

[0064] The aforementioned electronic devices can be terminals or servers. Terminals include, but are not limited to, mobile phones, computers, wearable devices, music players, smart home devices, and vehicles. Servers can be computing devices primarily used for performing computational tasks or storage devices primarily used for storing data. When the computer system described above spans multiple electronic devices located in racks, these multiple electronic devices can be located in the same rack or in different racks.

[0065] The memory spaces of all memory chips 16 within at least one system memory in the aforementioned computer system constitute the system memory space of the computer system. The system memory space includes the memory spaces of all memory chips 16 within the at least one system memory. The system memory space is uniformly addressed to obtain the system address space of the computer system. The system address space includes multiple memory addresses, each memory address indicating a memory space (or a block of memory space) within the system memory space.

[0066] The processor chip in a computer system can run a target application that sets up mirrored memory for the main memory of the computer system at the address segment granularity. For example, the target application divides the computer system's system memory space into a main memory space and multiple mirrored memory spaces. The main memory space serves as the main memory of the computer system, and the processor chip in the computer system can store data in the main memory.

[0067] The main memory space includes at least one mirrored memory space, which is a portion of the main memory space. Each mirrored memory space is used to store data to be mirrored in the computer system (i.e., data that needs to be mirrored). The mirrored data of any given data is exactly the same as the given data, and the mirrored data of any given data can be a copy of the given data.

[0068] Each mirrored memory space corresponds to at least one mirrored memory space, and different mirrored memory spaces correspond to different mirrored memory spaces. Each mirrored memory space is a mirror memory of the corresponding mirrored memory space, and each mirrored memory space is used to store mirror data of the data stored in the corresponding mirrored memory space.

[0069] The size of each mirrored memory space is the maximum amount of data that it can store. The size of each mirrored memory space is greater than or equal to the size of the corresponding mirrored memory space, ensuring that each mirrored memory space can store a mirror image of the data stored in the mirrored memory space. Optionally, the size of each mirrored memory space is equal to the size of the corresponding mirrored memory space, ensuring that each mirrored memory space can just hold a mirror image of the data stored in the mirrored memory space. This fully utilizes the mirrored memory space, avoids idle memory space in the mirrored memory space, prevents memory waste in the computer system, and allows more memory space in the system memory to be allocated to the main memory space for use by the processor chip.

[0070] In some embodiments, the target application divides at least one mirror memory space from the system memory space, with each mirrored memory space corresponding to one mirror memory space, and different mirrored memory spaces corresponding to different mirror memory spaces.

[0071] In summary, the system memory space includes at least one mirrored memory space and at least one mirrored memory space, and each mirrored memory space can correspond to one or more mirrored memory spaces.

[0072] When the system memory space includes multiple mirrored memory spaces, these multiple mirrored memory spaces can be distributed in the same system memory, or they can be distributed in different system memories, or they can be distributed in the same memory chip, or they can be distributed in different memory chips.

[0073] When the system memory space includes multiple mirrored memory spaces, the multiple mirrored memory spaces can be distributed in the same system memory, or they can be distributed in different system memories, or they can be distributed in the same memory chip, or they can be distributed in different memory chips.

[0074] The memory address segment used to indicate any address segment to be mirrored is called the mirrored address segment, and the memory address segment used to indicate any mirrored address segment is called the mirrored address segment. Therefore, the mirrored address segment is used to store data to be mirrored in the computer system, and the mirrored data is used to store the data to be mirrored. Any memory address segment includes multiple consecutive memory addresses in the computer system's system address space. For example... Figure 2 As shown, a certain address segment in the system address space is the mirrored address segment, and another address segment in the system address space is the mirrored address segment of the mirrored address segment. Both the mirrored address segment and the mirrored address segment include multiple memory addresses.

[0075] For any mirrored space, the target application can set at least one mirror space for that space. For example, a preset address pair can be established for the mirrored space. This preset address pair includes the mirrored address segment and at least one mirrored address segment of the mirrored address segment. The mirrored address segment is a memory address segment of the mirrored space, and each mirrored address segment is a memory address segment of one of the mirrored spaces of the mirrored space. It should be understood that, for the mirrored address segment and each mirrored address segment in the same preset address pair, the mirrored address segment stores the data to be mirrored in the computer system, and each mirrored address segment is used to store the mirrored data of that data.

[0076] For the mirrored address segment and each mirrored address segment in the same preset address pair, when the size of the mirrored memory space indicated by the mirrored address segment is smaller than the size of the mirrored memory space indicated by any other mirrored address segment, the length of the mirrored address segment is smaller than the length of the mirrored address segment. When the size of the mirrored memory space indicated by the mirrored address segment is equal to the size of the mirrored memory space indicated by any other mirrored address segment, the length of the mirrored address segment is the same as the length of the mirrored address segment.

[0077] For each mirrored space, the target application establishes a preset address pair for each mirrored space, thereby obtaining at least one preset address pair. Each preset address pair includes a mirrored address segment and at least one mirrored address segment of the mirrored address segment. Each mirrored address segment indicates a mirrored memory space in main memory, and each mirrored address segment of the mirrored address segment indicates a mirrored memory space corresponding to the mirrored memory space.

[0078] In some embodiments, the address space representing main memory in the system address space is called the main memory address space, which is a portion of the memory space within the system address space. Based on the business requirements for mirrored data, the target application determines at least one mirrored address segment from the main memory address space. For any mirrored address segment, at least one mirrored address segment is determined from the address space outside the main memory address space in the system address space. Based on the mirrored address segment and its at least one mirrored address segment, a preset address pair is generated. This preset address pair includes the mirrored address segment and its at least one mirrored address segment. A preset address pair can be generated for each mirrored address segment, thus enabling the generation of at least one preset address pair based on the business requirements for mirrored data.

[0079] This service refers to any service that the computer system supports processing. For example, it could be a service handled by the operating system kernel or a service handled by other components besides the kernel. This service requires mirrored data; for instance, when storing the service data in the computer system's memory, it also requires a backup of that data (i.e., storing mirrored data of the service data). This service data could be all the service data during its execution, or it could be a portion of the service data (such as critical data during the service's execution).

[0080] The number and length of the mirrored address segments determined from the main memory address space are related to the amount of mirrored data required by the service. The greater the amount of mirrored data required by the service, the more mirrored address segments there are and / or the longer the mirrored address segments are.

[0081] The target application can determine the number and length of mirrored address segments based on the business's demand for mirrored data. Then, it can configure mirrored address segments for each mirrored address segment, thereby enabling on-demand configuration of mirrored memory. This avoids a large amount of memory space in the system memory space being configured as mirrored memory space, allowing more memory space in the system memory space to be set as the main memory of the computer system for use by the processor chip. This further increases the memory space available to the processor chip in the computer system and further reduces the hardware cost of memory in the computer system.

[0082] Each memory address in the system address space can be mapped to a memory channel in a processor chip within a computer system. A single memory channel can be mapped to multiple memory addresses. For example, any memory channel can correspond to multiple memory addresses, including the memory addresses of various memory spaces within different memory chips on the same channel. The memory chips on the same channel are the memory chips connected to that channel. Multiple memory addresses corresponding to the same memory channel form at least one memory address segment, and this segment includes multiple consecutive memory addresses.

[0083] Memory addresses in the system address space can be mapped sequentially to multiple memory channels in the computer system, with each memory channel corresponding to a memory address segment. Alternatively, memory addresses in the system address space can be interleaved and mapped to multiple memory channels in the computer system according to a preset interleaving pattern. In this case, each memory channel corresponds to multiple memory address segments, and the multiple memory address segments corresponding to the same memory channel are not contiguous. The multiple memory channels in a computer system include the memory channels in each processor chip within the computer system.

[0084] For any given preset address pair, each address segment (including the mirrored address and the mirrored address segment) is mapped to a memory channel in the computer system (i.e., the address segment corresponds to a memory channel). The address segment can be a memory address segment corresponding to the memory channel, or it can be a part of a memory address segment corresponding to the memory channel.

[0085] Each address segment in any preset address pair is mapped to a different memory channel in the computer system (i.e., each address segment in any preset address pair corresponds to a different memory channel).

[0086] In some embodiments, each address segment in the preset address pair corresponds to a different memory channel in the same processor chip. Figure 3For example, a processor chip in a computer system includes memory channels 0-3. In the default address pair P1, the mirrored address segment P1_1 represents a portion of the memory addresses mapped onto memory channel 0. The mirrored address segment of P1_1 represents a portion of the memory addresses mapped onto memory channel 2. Therefore, the memory space indicated by the portion of memory addresses mapped onto memory channel 2 is a mirror image of the memory space indicated by the portion of memory addresses mapped onto memory channel 0, thus achieving memory mirroring of a portion of the memory addresses. Similarly, in the default address pair P2, the mirrored address segment P2_1 represents a portion of the memory addresses mapped onto memory channel 1. The mirrored address segment of P2_1 represents a portion of the memory addresses mapped onto memory channel 3. Therefore, the memory space indicated by the portion of memory addresses mapped onto memory channel 3 is a mirror image of the memory space indicated by the portion of memory addresses mapped onto memory channel 1, thus achieving memory mirroring of a portion of the memory addresses.

[0087] In a computer system where memory addresses are interleaved and mapped to multiple memory channels, address segments within different preset address pairs are interleaved and mapped to different memory channels. Address segments within the same preset address pair may or may not be adjacent. Figure 3 For example, each memory channel from 0 to 4 is mapped with multiple memory address segments. The multiple memory address segments mapped on the same memory channel are not adjacent. The mirrored address segment P1_1, the mirrored address segment of the mirrored address segment P1_1, the mirrored address segment P2_1, and the mirrored address segment of the mirrored address segment P2_1 are interleaved and mapped to different memory channels.

[0088] In some embodiments, each address segment in the same preset address pair corresponds to a memory channel in a different processor chip in a computer system, so as to realize the establishment of mirrored memory across processor chips. Figure 4For example, suppose a computer system includes processor chip 41 and processor chip 42, which are interconnected across chips via transmission network 22. Processor chip 41 includes memory channels 0-3, and processor chip 42 includes memory channels 4-7. The mirrored address segment P3_1 in the preset address pair P3 is a portion of the memory addresses mapped on memory channel 0. The mirrored address segment of mirrored address segment P3_1 is a portion of the memory addresses mapped on memory channel 4. Therefore, the memory space indicated by the portion of memory addresses mapped on memory channel 4 is a mirror of the memory space indicated by the portion of memory addresses mapped on memory channel 0, thus achieving memory mirroring of partial memory addresses. Processor chip 41 and processor chip 42 can be different processor chips packaged in the same chip, or different processor chips packaged in different chips, to achieve cross-package mirrored memory configuration. Alternatively, processor chip 41 and processor chip 42 can be located in different racks to achieve cross-rack mirrored memory configuration, or processor chip 41 and processor chip 42 can be located in different electronic devices to achieve cross-device mirrored memory configuration.

[0089] Figure 3 and Figure 4 The examples all use a processor chip with four memory channels as an example, but the number of memory channels in a processor chip is not limited to four. Figure 3 and Figure 4 These examples all illustrate the case of a single memory channel mapped to a single mirrored address segment. In some embodiments, a single memory channel may be mapped to multiple mirrored address segments, which belong to different preset address pairs. Figure 3 and Figure 4 These examples all use the example of a single memory channel mapped to a single mirror address segment. In some embodiments, a single memory channel can be mapped to multiple mirror address segments, which may belong to different preset address pairs or the same preset address pair.

[0090] When the address segments in any preset address pair are mapped to different memory channels, if the memory channel corresponding to any address segment (the mirrored address or the mirrored address segment) or the memory chip connected to the corresponding memory channel fails, data read and write operations can still be performed on the memory space indicated by other segments in the preset address pair (the mirrored memory space or the mirrored memory space) to ensure that the data read and write operations can be completed normally. Similarly, when the address segments in any preset address pair are mapped to memory channels of different processor chips, if the memory channel corresponding to any address segment (the mirrored address or the mirrored address segment) fails, the memory chip connected to the corresponding memory channel fails, or the processor chip corresponding to the corresponding memory channel fails, data read and write operations can still be performed on the memory space indicated by other segments in the preset address pair (the mirrored memory space or the mirrored memory space) to ensure that the data read and write operations can be completed normally.

[0091] It should be understood that for any data to be mirrored, the memory storage location of the data can be specified through the mirrored address segment within a preset address range, and the memory storage location of the mirrored data (i.e., the location of the mirrored memory) can be specified through the mirrored address segment within the same preset address range. Thus, the mirrored memory can be set at the address range granularity for the data to be mirrored using preset address pairs. The lengths of the mirrored address segment and the mirrored address segment vary with the length of the data (for example, the longer the data to be mirrored, the longer the mirrored address segment and the mirrored address segment). Therefore, the size of the mirrored memory set at the address range granularity can be flexible. The memory storage location of the data to be mirrored and the memory storage location of its mirrored data can be within the same processing chip, or they can span processing chips, packages, racks, or electronic devices. Therefore, the location of the mirrored memory set at the address range granularity for the data to be mirrored can also be flexible. In other words, using preset address pairs, the mirrored memory can be flexibly set at the address range granularity for the data to be mirrored. This allows the target application to ignore data with relatively low reliability requirements in the computer system, omitting the need to mirror such data. Instead, it can only mirror data with relatively high reliability requirements, allocating suitable memory space for this data in terms of size and location using preset address pairs. This maximizes the utilization of the computer system's memory space and reduces hardware costs. Specifically, data with relatively high reliability requirements is the data that needs to be mirrored (i.e., data that needs to be backed up), while data with relatively low reliability requirements is the data that does not need to be mirrored (i.e., data that does not need to be backed up).

[0092] This disclosure provides a data processing device applied to the processor chip described above. The target application can configure at least one preset address pair into the data processing device so that when the processor chip performs data read / write operations on the memory space indicated by a certain memory address, the data processing device queries whether the memory space is a mirrored memory space based on at least one preset address pair. If it is a mirrored memory space, it performs data read / write operations on the mirrored memory space of the memory space.

[0093] The timing of using preset address pairs differs between the data write operation and the data read operation. The following section will explain the timing of using preset address pairs in conjunction with the data write and read operation processes.

[0094] In the process of any processor chip performing a data write operation on the memory space indicated by a memory address segment in the system address space (i.e., the data write process), if the memory space is a mirrored memory space, then data write operations are performed on both the mirrored memory space and the memory space being mirrored. Next, combined with... Figure 5 This section introduces the data writing operation process.

[0095] Figure 5 This is a flowchart illustrating a data processing method according to an exemplary embodiment. The data processing method is applied to a first processor chip in any of the computer systems described above. The first processor chip can be any processor chip in the computer system, and the data processing method can be executed by a data processing device in the first processor chip. See also... Figure 5 The data processing method includes the following steps.

[0096] 501. The data processing device in the first processor chip obtains a first write request, the first write request instructing to write first data to the memory space indicated by the first memory address segment in the computer system.

[0097] In this context, the first memory address segment is the target memory address segment in the first write request, and the first data is the data requested to be written by the first write request, i.e., the data to be written to the memory space indicated by the first memory address segment. The first write request includes information about the first memory address segment and the first data. The information about any memory address segment indicates that memory address segment, and the information about any memory address segment includes the starting memory address and the length of the memory address segment. The length of the memory address segment is the offset between the starting memory address and the ending memory address of the memory address segment.

[0098] The first write request can be a write request from a source device, which can be any component in the computer system that initiates read or write requests (including read and write requests). Figure 1 Taking the computer system shown as an example, the source device is any processor core, accelerated computing core 18, DMA device 20 or I / O device 12 in a certain processor cluster 10. The source device may or may not be a component in the first processor chip.

[0099] Taking the data processing device as a consistency controller in the first processor chip as an example, the process of the data processing device obtaining the first write request can be as follows: the source device sends the first write request to the proxy device of the source device; the proxy device receives the first write request from the source device and sends the first write request to the consistency controller 14 corresponding to the memory chip 16 where the first memory address segment is located in the computer system through the transmission network 22 in the computer system; the consistency controller 14 receives the first write request. The processor chip in which the consistency controller 14 is located is the first processor chip. The proxy device of the source device is the proxy node of the source device in the computer system.

[0100] 502. The data processing device writes the first data to the memory space indicated by the first memory address segment.

[0101] Taking the data processing device as a consistency controller as an example, the data processing device can write the first data to the memory space indicated by the first memory address segment through the memory controller.

[0102] For ease of description, the consistency controller that receives read / write requests from the source device is referred to as the source consistency controller; that is, the data processing device is the source consistency controller. The memory controller corresponding to the source consistency controller (i.e., the memory controller in the first processor chip) is referred to as the source memory controller. For example... Figure 6 As shown, after the source consistency controller receives the first write request, it obtains the information of the first memory address segment and the first data from the first write request, generates a third write request based on the information of the first memory address segment and the first data, and sends the third write request to the source memory controller. The third write request includes the information of the first memory address segment and the first data, and the third write request instructs the memory space indicated by the first memory address segment to write the first data.

[0103] The source memory controller receives a third write request, parses the information of the first memory address segment and the first data from the third write request, and determines the memory channel (called the first memory channel) corresponding to the first memory address segment in the first processor chip based on the correspondence (i.e., mapping relationship) between memory addresses and memory channels in the computer system. Then, it writes the first data to the memory space indicated by the first memory address segment through the first memory channel.

[0104] 503. The data processing device determines whether a first memory address segment belongs to a mirrored address segment based on at least one preset address pair. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store data to be mirrored in the computer system, and the mirrored address segment is used to store mirrored data of the data.

[0105] The at least one preset address pair, as described above, will not be repeated here. The at least one preset address pair is configured in the data processing device by the target application. The at least one preset address pair can be generated by the target application based on the business's demand for mirrored data; therefore, the at least one preset address pair is set based on the business's demand for mirrored data.

[0106] The data processing device queries at least one preset address pair to determine whether the first memory address segment belongs to the mirrored address segment. If the mirrored address segment in any preset address pair includes the first memory address segment, the first memory address segment is determined to belong to the mirrored address segment. If the mirrored address segments in each preset address pair do not include the first memory address segment, the first memory address segment is determined not to belong to the mirrored address segment.

[0107] In this context, any mirrored address segment, including the first memory address segment, can be represented as follows: the first memory address segment is the same as the mirrored address segment, or the first memory address segment is a sub-address segment within the mirrored address segment. For example, if the mirrored address segment in a preset address pair is memory address 0001 to memory address 0100, and the first memory address segment is memory address 0002 to memory address 0005, then the first memory address segment is a sub-address segment of the mirrored address segment and belongs to the mirrored address segment. Further assuming the first memory address segment is memory address 0001 to memory address 0100, then the first memory address segment is the same as a sub-address segment of the mirrored address segment and belongs to the mirrored address segment. Finally, assuming the first memory address segment is memory address 0105 to memory address 0120, which is not located within the mirrored address segment, then the first memory address segment does not belong to the mirrored address segment.

[0108] If the first memory address segment belongs to the mirrored address segment, the data processing device performs step 504 below. If the first memory address segment does not belong to the mirrored address segment, the data processing device does not perform step 504 below.

[0109] 504. If the first memory address segment belongs to the mirrored address segment, the data processing device writes the mirror data of the first data to the memory space indicated by the mirrored address segment of the first memory address segment, where the mirrored address segment of the first memory address segment belongs to the mirrored address segment of the mirrored address segment to which the first memory address segment belongs.

[0110] The mirror data of the first data is a copy of the first data (i.e., a copy of the first data). The mirror address segment of the first memory address segment has the same length as the first memory address segment.

[0111] For a mirrored address segment to which the first memory address segment belongs, the preset address pair containing the mirrored address segment also includes at least one mirrored address segment of the mirrored address segment. For any mirrored address segment of the mirrored address segment, the data processing device determines the mirrored address segment of the first memory address segment from that mirrored address segment of the mirrored address segment. For example, if the mirrored address segment is the same as the first memory address segment, then that mirrored address segment of the mirrored address segment is determined as the mirrored address segment of the first memory address segment. If the first memory address segment is a sub-address segment of the mirrored address segment, then a free sub-address segment of the mirrored address segment of the mirrored address segment that has the same length as the first memory address segment is determined as the mirrored address segment of the first memory address segment.

[0112] The data processing device copies the first data to obtain mirror data of the first data. Based on the mirror data of the first data and the mirror address segment of the first memory address segment, a second write request is generated. The second write request includes the mirror data of the first data and the information of the mirror address segment of the first memory address segment. The second write request instructs to write the mirror data of the first data to the memory space indicated by the mirror address segment of the first memory address segment.

[0113] Taking the coherence controller in the first processor chip as an example, the data processing device determines the memory channel (called the second memory channel) corresponding to the mirror address segment of the first memory address segment in the computer system based on the correspondence (i.e., mapping relationship) between memory addresses and memory channels in the computer system. The data processing device then determines the processor chip to which the second memory channel belongs based on the relationship between each memory channel in the computer system and the processor chip.

[0114] The processor chip to which the second memory channel belongs may be the first processor chip, or any processor chip in the computer system other than the first processor chip. The second write request is processed by the coherence controller in the processor chip to which the second memory channel belongs, and executed by the memory controller in the processor chip to which the second memory channel belongs, so as to write mirrored data of the first data to the memory space indicated by the mirrored address segment of the first memory address segment if the first memory address segment belongs to the mirrored address segment.

[0115] Next, considering scenario 1 below, we will describe the processing and execution of the second write request when the second memory channel is located on the first processor chip. Considering scenario 2 below, we will describe the processing and execution of the second write request when the second memory channel is located on any processor chip in the computer system other than the first processor chip.

[0116] Case 1: The processor chip belonging to the second memory channel is the first processor chip.

[0117] When the processor chip to which the second memory channel belongs is the first processor chip, the mirror address segment of the first memory address segment corresponds to the second memory channel in the first processor chip.

[0118] The data processing unit in the first processor chip acts as a target consistency controller for processing the second write request. The data processing unit sends the second write request to the memory controller in the first processor chip. The memory controller receives the second write request, parses the information of the mirror address segment of the first memory address segment and the mirror data of the first data from the second write request, and, based on the correspondence (i.e., mapping relationship) between memory addresses and memory channels in the computer system, determines the memory channel (i.e., the second memory channel) corresponding to the mirror address segment of the first memory address segment in the first processor chip. Through the second memory channel, it writes the mirror data of the first data to the memory space indicated by the mirror address segment of the first memory address segment. This achieves the goal of writing the mirror data of the first data to the memory space indicated by the mirror address segment of the first memory address segment if the first memory address segment belongs to the mirrored address segment, through the second memory channel. After the mirror data of the first data is written, the memory controller sends a write response to the data processing unit for the second write request, indicating that the second write request has been completed. The data processing unit receives the write response to the second write request.

[0119] When the first memory channel and the second memory channel are different memory channels in the first processor chip, if either the first memory channel or the memory chip connected to it fails, the write operation of the first data can still be completed through the memory channel that is not faulty, ensuring that the write operation of the first data can be completed normally. For example, if the first memory channel or the memory chip connected to it fails, the mirrored data of the first data can be stored in the mirrored memory space (i.e., the memory space indicated by the mirrored address segment of the first memory address segment) through the second memory channel.

[0120] Case 2: The processor chip to which the second memory channel belongs is any processor chip in the computer system other than the first processor chip.

[0121] When the processor chip to which the second memory channel belongs is any processor chip in the computer system other than the first processor chip, the processor chip to which the second memory channel belongs is called the second processor chip. In this case, the mirror address segment of the first memory address segment corresponds to the memory channel in the second processor chip.

[0122] If the first memory address segment belongs to the mirrored address segment and the mirrored address segment of the first memory address segment corresponds to the memory channel in the second processor chip, the data processing device sends a second write request to the second processor chip, and the second processing chip writes the mirrored data of the first data to the memory space indicated by the mirrored address segment of the first memory address segment through the memory channel corresponding to the mirrored address segment of the first memory address segment in the second processor chip.

[0123] For example, the data processing device, targeting the consistency controller in the second processor chip, sends a second write request to the consistency controller in the second processor chip via the transmission network 22. The consistency controller in the second processor chip receives the second write request and sends it to the memory controller in the second processor chip. The memory controller receives the second write request, parses the information of the mirror address segment of the first memory address segment and the mirror data of the first data from the second write request, and, based on the correspondence between memory addresses and memory channels in the computer system, determines the memory channel (i.e., the second memory channel) corresponding to the mirror address segment of the first memory address segment in the second processor chip. Through the second memory channel, it writes the mirror data of the first data to the memory space indicated by the mirror address segment of the first memory address segment. After the mirror data is written, the memory controller in the second processor chip sends a write response to the consistency controller in the second processor chip for the second write request. The consistency controller in the second processor chip receives the write response to the second write request and sends a write response to the data processing device in the first data processor chip for the second write request. The data processing device receives the write response to the second write request.

[0124] In some embodiments, in response to the successful writing of first data to the memory space indicated by the first memory address segment, the data processing device sends a write response to the proxy device of the source device for the first write request. For example, the write response to the first write request is sent to the proxy device of the source device via the transmission network 22 in the computer system. The proxy device of the source device receives the write response to the first write request and sends a write response to the first write request to the source device, wherein the write response to the first write request indicates that the first write request has been completed.

[0125] When the first memory channel and the second memory channel are different memory channels in different processor chips, if either the first memory channel or the second memory channel fails or the memory chip connected to that memory channel fails, the first data can still be written through the memory channel that has not failed, so as to ensure that the writing operation of the first data can be completed normally.

[0126] In some embodiments, in response to the successful writing of first data to the memory space indicated by the first memory address segment and the successful writing of mirror data of the first data to the memory space indicated by the mirror address segment of the first memory address segment, the data processing device sends a write response to the proxy device of the source device for the first write request. Exemplarily, in response to the successful writing of first data to the memory space indicated by the first memory address segment and receiving a write response for the second write request, the data processing device sends a write response to the proxy device of the source device for the first write request.

[0127] In some embodiments, during the execution of step 502, the data processing device also executes steps 503 and 504. In some embodiments, assuming the data processing device is a consistency controller in a first processor chip, when the first memory address segment belongs to the mirrored address segment (i.e., the first memory address hits the mirrored address), the consistency controller takes the consistency controller in the processor chip where the memory channel to which the mirrored address segment of the first memory address segment belongs is located as the target consistency controller. For example, in case 1 above, the target consistency controller is the consistency processor in the first processor chip; and in case 2 above, the target consistency controller is the consistency processor in the second processor chip. The consistency controller in the first processor chip acts as the source node of the second write request and the target consistency controller as the destination node. The second write request carries the identifiers of both the source and destination nodes. The consistency controller in the first processor chip sends the second write request to the transmission network in the computer system. The transmission network, based on the destination node identifier in the second write request, transmits the second write request to the target consistency controller. The target consistency controller processes the second write request, writing the mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment. It then returns the processing result of the second write request (such as a write response to the second write request) back to the consistency controller in the first processor chip, enabling the consistency controller in the first processor chip to obtain the processing result of the second write request. The following will illustrate this further. Figure 6 For example, these two embodiments will be described by way of example.

[0128] like Figure 6As shown, assuming the data processing device is the consistency controller in the first processor chip (referred to as the source consistency controller), and the memory controller in the first processor chip is referred to as the source memory controller, the source consistency controller sends a third write request to the source memory controller, waits for the source memory controller to write the first data based on the third write request, and after the first data is written, the source consistency controller returns a write response to the first write request to the proxy device of the source device. Alternatively, it may not return a write response to the first write request to the proxy device of the source device immediately. While waiting for the first data to be written, the source consistency controller determines whether the accessed address segment (i.e., the first memory address segment) belongs to the mirrored address segment. If the accessed address segment does not belong to the mirrored address segment, it returns a write response to the first write request to the proxy device of the source device. If the accessed address segment belongs to a mirror address segment, the source consistency controller determines the memory channel (i.e., the target memory channel) mapped to the mirror address segment of the accessed address segment based on the interleaving pattern of memory address mapping to memory channels in the computer system (i.e., the mapping relationship between memory addresses and memory channels). The memory controller connected to the target memory channel is designated as the target memory controller, and the consistency controller corresponding to the target memory controller (i.e., the consistency controller in the processor chip where the target memory controller resides) is designated as the target consistency controller. This achieves the determination of the target consistency controller based on the mirror address segment of the accessed address segment and the interleaving pattern of memory address mapping to memory channels in the computer system, thus determining the location of the target memory controller in the computer system. The source consistency controller, using itself as the source node of the second write request and the target consistency controller as the destination node of the second write request, sends the second write request to the target consistency controller through the transmission network. The second write request includes the mirror data of the first data and the mirror address segment of the accessed address segment. The target consistency controller receives the second write request, generates a new write request (called the fourth write request) based on the second write request, and sends the fourth write request to the target memory controller. The fourth write request includes the mirror data of the first data and the mirror address segment of the accessed address segment. The target memory controller receives a fourth write request. Based on this request, it writes the mirror data of the first data into the mirror memory space (i.e., the memory space indicated by the mirror address segment of the accessed address segment). For example, the target memory controller determines the target memory channel based on the mirror address segment in the fourth write request and the interleaving pattern of memory addresses mapped to memory channels in the computer system. Then, it writes the mirror data of the first data into the mirror memory space through the target memory channel. After the mirror data of the first data is written, the target memory controller returns a write response to the target consistency controller in response to the fourth write request, indicating that the fourth write request has been completed (i.e., indicating that the mirror data of the first data has been written).Based on the received write response to the fourth write request, the target consistency controller generates a write response for the second write request. Using the target consistency controller as the source node and the source consistency controller as the destination node, the write response for the second write request is sent to the source consistency controller via the transmission network. After receiving the write response for the second write request and completing the first data write, the source consistency controller returns a write response for the first write request to the proxy device of the source device. The processing of the first write request is then complete, ending the processing of the first write request. Specifically, when the target memory channel is located on the processor chip where the source consistency controller resides (i.e., the first processor chip), the target consistency controller and the source consistency controller are the same consistency controller, and the target memory controller and the source memory controller are the same memory controller. When the target memory channel is located on a processing chip other than the first processor chip (i.e., the second processor chip), the target consistency controller and the source consistency controller are different consistency controllers, and the target memory controller and the source memory controller are different memory controllers.

[0129] It should be understood that if the first memory address segment belongs to a mirrored address segment, and the mirrored address segment to which the first memory address segment belongs has multiple mirrored address segments (for example, the preset address pair to which the mirrored address segment to which the first memory address segment belongs includes multiple mirrored address segments), then the data processing device determines a mirrored address segment for the first memory address segment from each mirrored address segment of the mirrored address segment to which the first memory address segment belongs, so that the first memory address segment has multiple mirrored address segments. The device then writes mirrored data of the first data to the memory space indicated by each mirrored address segment of the first memory address segment, thus creating multiple backups of the first data. The process of writing mirrored data of the first data to the memory space indicated by one mirrored address segment of the first memory address segment can be referred to the relevant description in step 504 above, and will not be repeated here.

[0130] The above embodiments are all described using the example of a write request including the data to be written. In some embodiments, the data to be written may not be included in the write request, and the write request and the data to be written may be sent separately.

[0131] In the method provided in this disclosure, the storage location of the data to be mirrored and the storage location of its mirror data in memory are specified respectively by the mirrored address segment and the mirrored address segment in the preset address pair. This achieves the setting of mirror memory at the granularity of address segments. When the memory address of the data to be written matches the mirrored address segment, the data is written to the storage location indicated by the memory address, and the mirrored data is written to the storage location indicated by the mirrored address segment to back up the data. Because the preset address pair allows for flexible setting of mirror memory for the data to be mirrored at the granularity of address segments, data with relatively low reliability requirements in the computer system can be ignored. Mirror memory is not set for data with relatively low reliability requirements, and only data with relatively high reliability requirements in the computer system is used as the data to be mirrored. By setting mirror memory of appropriate size and location for the data to be mirrored through the preset address pair, the memory space of the computer system can be maximized, and the hardware cost of the memory in the computer system can be reduced.

[0132] The mirrored address segment and the mirrored address segment in the preset address pair specify the memory storage location of the data to be mirrored and the memory storage location of its mirror data, respectively. Once any data to be mirrored and its mirror data are stored in the specified storage locations, the data to be mirrored in memory becomes the mirrored data (i.e., the data being mirrored). Therefore, the memory space indicated by the mirrored address segment in the preset address pair is also used to store the mirrored data in the computer system; in other words, the mirrored address segment is also used to store the mirrored data.

[0133] When a processor chip reads data from the computer system's memory, if the data being read is mirrored data and a data read error occurs, then the mirrored data of the mirrored data can be read from the mirrored memory of the mirrored data, and this read mirrored data can be used as the data read result. Next, combined with... Figure 7 This section introduces the data read operation process.

[0134] Figure 7 This is a flowchart illustrating another data processing method according to an exemplary embodiment. The data processing method is applied to a first processor chip in any of the computer systems described above. The first processor chip can be any processor chip in the computer system, and the data processing method can be executed by a data processing device in the first processor chip. See also... Figure 7 The data processing method includes the following steps.

[0135] 701. The data processing device in the first processor chip obtains a first read request, the first read request instructing to read second data from the memory space indicated by the second memory address segment in the computer system.

[0136] The second memory address segment is the target memory address segment in the first read request, and the second data is the data requested to be read by the first read request. The first read request includes information from the second memory address segment.

[0137] The first read request can be a read request from a source device, which is any component in the computer system that initiates a read request (including read requests and read requests). Figure 1 Taking the computer system shown as an example, the source device is any processor core, accelerated computing core 18, DMA device 20 or I / O device 12 in a certain processor cluster 10. The source device may or may not be a component in the first processor chip.

[0138] Taking the data processing device as the consistency controller in the first processor chip as an example, the process of the data processing device obtaining the first read request is the same as the process of the data processing device obtaining the first write request from the source device. The process of obtaining the first read request will not be described again here.

[0139] 702. The data processing device reads the second data from the memory space indicated by the second memory address segment.

[0140] Taking the data processing device as a consistency controller as an example, the data processing device can read the second data from the memory space indicated by the second memory address segment through the memory controller.

[0141] For ease of description, the consistency controller that receives read / write requests from the source device is referred to as the source consistency controller, i.e., the data processing device is the source consistency controller. The memory controller corresponding to the source consistency controller (i.e., the memory controller in the first processor chip) is referred to as the source memory controller (i.e., the memory controller in the first processor chip).

[0142] like Figure 8 As shown, after receiving the first read request, the source consistency controller obtains the information of the second memory address segment from the first read request, generates a third read request based on the information of the second memory address segment, and sends the third read request to the source memory controller. The third read request includes the information of the second memory address segment and indicates that the second data should be read from the memory space indicated by the second memory address segment.

[0143] The original memory controller receives the third read request, parses the information of the second memory address segment from the third read request, and determines the memory channel (called the third memory channel) corresponding to the second memory address segment in the first processor chip based on the correspondence (i.e., mapping relationship) between memory addresses and memory channels in the computer system. Through the third memory channel, it reads from the memory space indicated by the second memory address segment to obtain the read data.

[0144] When the source memory controller reads data from the memory space indicated by the second memory address segment, if the data read from that memory space is the same as the second data (i.e., the read data is the second data), then the second data reading is normal. The source memory controller then sends a read response to the data processing device for the third read request. This read response includes the read second data and indicates that the third read request has been completed and the data reading is normal. Upon receiving this read response, the data processing device, based on it, sends a read response to the proxy device of the source device for the first read request. The data processing device no longer executes steps 703 to 705 below, and the data processing device completes the first data reading process. The read response to the first read request includes the second data, and the read response to the first read request indicates that the first read request has been completed and the data reading is normal.

[0145] by Figure 8 For example, taking the data processing device as the source consistency controller, after the consistency controller in the first processor chip sends a third read request to the source memory controller, it waits for the source memory controller to return read data, which is the data read by the source memory controller based on the third read request. If the read data returned by the source memory controller is error-free (i.e., the read data is the same as the second read data), the source consistency controller returns a read response to the first read request to the proxy device of the source device. The read response to the first read request includes the read data.

[0146] If the data read from the memory space indicated by the second memory address segment by the memory controller is different from the second data, a data read error occurs when reading the second data. The memory controller sends a read response to the data processing device for the third read request. At this time, the read response to the third read request includes the data read from the memory space. The read response indicates that the third read request has been completed and a data read error has occurred. The data processing device receives the read response to the third read request. If the read response indicates a data read error, the data processing device executes steps 703 to 705 below.

[0147] 703. If a data reading error occurs when reading the second data, the data processing device determines whether the second memory address segment belongs to the mirrored address segment based on at least one preset address pair. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store the mirrored data in the computer system, and the mirrored address segment is used to store the mirrored data of the mirrored data.

[0148] For example, if the data processing device receives a read response to a third read request and the read response indicates a data read error, it determines whether the second memory address segment belongs to the mirrored address segment based on at least one preset address pair.

[0149] The process by which the data processing device determines whether the second memory address segment belongs to the mirrored address segment based on at least one preset address pair is the same as the process by which the first memory address segment belongs to the mirrored address segment in step 503 above. Therefore, the process of determining whether the second memory address segment belongs to the mirrored address segment will not be described again here.

[0150] If the second memory address segment does not belong to any of the mirrored address segments, the data processing device sends a read response to the source device proxy device in response to the first read request. This read response includes the data read from the first memory address space and indicates a data read error. Figure 8 For example, if the source memory controller returns a read data error to the source consistency controller (i.e., the read data is different from the second data), the source consistency controller queries whether the accessed address segment (i.e., the second memory address segment) belongs to the mirrored address segment. If the accessed address segment does not belong to the mirrored address segment, it sends a read response to the source device proxy device for the first read request.

[0151] If the second memory address segment does not belong to a mirrored address segment, the data processing device performs steps 704 and 705 as follows.

[0152] 704. If the second memory address segment belongs to the mirrored address segment, the data processing device reads the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment, where the mirrored address segment of the second memory address segment belongs to the mirrored address segment of the mirrored address segment to which the second memory address segment belongs.

[0153] For the mirrored address segment to which the second memory address segment belongs, the preset address pair containing the mirrored address segment also includes the mirrored address segment of the mirrored address segment. The data processing device determines the mirrored address segment of the second memory address segment from the mirrored address segment of the mirrored address segment. For example, if the mirrored address segment is the same as the second memory address segment, then the mirrored address segment of the mirrored address segment is determined as the mirrored address segment of the second memory address segment. If the second memory address segment is a sub-address segment within the mirrored address segment, then the sub-address segment at the target location within the mirrored address segment is determined as the mirrored address segment of the second memory address segment, where the target location is the position of the second memory address segment within its corresponding mirrored address segment.

[0154] The data processing device generates a second read request based on the mirror address segment of the second memory address segment. The second read request includes information about the mirror address segment of the second memory address segment and instructs to read mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment.

[0155] Taking the coherence controller in the first processor chip as an example, the data processing device determines the memory channel (referred to as the fourth memory channel) corresponding to the mirror address segment of the second memory address segment in the computer system based on the correspondence (i.e., mapping relationship) between memory addresses and memory channels in the computer system. The data processing device then determines the processor chip to which the fourth memory channel belongs based on the relationship between each memory channel in the computer system and the processor chip.

[0156] The processor chip to which the fourth memory channel belongs may be the first processor chip, or any processor chip in the computer system other than the first processor chip. The second read request can be processed by the coherence controller in the processor chip to which the fourth memory channel belongs, and executed by the memory controller in the processor chip to which the fourth memory channel belongs, so as to read the mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment through the fourth memory channel if the second memory address segment belongs to the mirrored address segment.

[0157] Next, based on scenario 1 below, we will describe the processing and execution of the second read request when the fourth memory channel is located on the first processor chip. Based on scenario 2 below, we will describe the processing and execution of the second read request when the fourth memory channel is located on any processor chip in the computer system other than the first processor chip.

[0158] Case 1: The processor chip belonging to the fourth memory channel is the first processor chip.

[0159] When the processor chip to which the fourth memory channel belongs is the first processor chip, the mirror address segment of the second memory address segment corresponds to the fourth memory channel in the first processor chip. In this case, the data processing unit in the first processor chip is a target consistency controller used to process the second read request.

[0160] If the second memory address segment belongs to the mirrored address segment, the data processing device sends a second read request to the memory controller in the first processor chip. The memory controller receives the second read request, parses the information of the mirrored address segment of the second memory address segment from the request, and, based on the correspondence (mapping relationship) between memory addresses and memory channels in the computer system, determines the memory channel (i.e., the fourth memory channel) corresponding to the mirrored address segment of the second memory address segment in the first processor chip. Through the fourth memory channel, it reads the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment. This achieves the goal of reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment through the fourth memory channel if the second memory address segment belongs to the mirrored address segment. After the mirrored data of the second data is read, the memory controller sends a read response to the data processing device for the second read request. This read response includes the read mirrored data of the second data and indicates that the second read request has been completed. The data processing device receives the read response to the second read request.

[0161] When the third memory channel and the fourth memory channel are different memory channels in the first processor chip, if the third memory channel or the memory chip connected to the third memory channel fails, or if a data reading error occurs when reading the second data, the mirror data of the second data can be read from the mirror memory space (i.e., the memory space indicated by the mirror address segment of the second memory address segment) through the fourth memory channel to realize the reading of the second data and ensure that the reading operation of the second data can be completed normally.

[0162] Case 2: The processor chip to which the fourth memory channel belongs is any processor chip in the computer system other than the first processor chip.

[0163] When the processor chip to which the fourth memory channel belongs is any processor chip in the computer system other than the first processor chip, the processor chip to which the fourth memory channel belongs is called the third processor chip. In this case, the mirror address segment of the second memory address segment corresponds to the memory channel in the third processor chip.

[0164] If the second memory address segment belongs to the mirrored address segment and the mirrored address segment of the second memory address segment corresponds to the memory channel in the third processor chip, the data processing device sends a second read request to the third processor chip, and the second processing chip reads the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment through the memory channel (i.e., the fourth memory channel) corresponding to the mirrored address segment of the second memory address segment in the third processor chip.

[0165] For example, the data processing device, targeting the consistency controller in the third processor chip, sends a second read request to the consistency controller in the third processor chip via transmission network 22. The consistency controller in the third processor chip receives the second read request and sends it to the memory controller in the third processor chip. The memory controller receives the second read request, parses the information of the mirror address segment of the second memory address segment from the second read request, and, based on the correspondence between memory addresses and memory channels in the computer system, determines the memory channel (i.e., the fourth memory channel) corresponding to the mirror address segment of the second memory address segment in the third processor chip. Through the fourth memory channel, it reads the mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment. After reading the mirror data of the second data, the system memory in the third processor chip sends a read response to the consistency controller in the third processor chip in response to the second read request. The consistency controller in the third processor chip receives the read response and sends it to the data processing device in the first data processor chip in response to the second read request. The data processing device receives the read response to the second read request, which includes the read mirror data of the second data.

[0166] 705. The data processing device sends the mirror data of the second data read.

[0167] Upon receiving a read response to the second read request, the data processing device obtains mirror data of the second data from the read response and generates a read response to the first read request based on the mirror data of the second data. At this time, the read response to the first read request includes the mirror data of the second data.

[0168] The data processing device sends a read response to the first read request to the proxy device of the source device. For example, it sends the read response to the first read request to the proxy device of the source device through the transmission network 22 in the computer system. The proxy device of the source device receives the read response to the first read request and sends a read response to the source device, at which point the read response to the first read request indicates that the first read request has been completed.

[0169] When the third memory channel and the fourth memory channel are different memory channels in different processor chips, if the third memory channel fails, the memory chip connected to the third memory channel fails, or a data reading error occurs when reading the second data, the mirror data of the second data can still be read from the mirror memory space through the fourth memory channel. The mirror data of the second data is used as the reading result of the second data to ensure that the reading operation of the second data can be completed normally.

[0170] Assuming the data processing device is the consistency controller in the first processor chip, for ease of description, the data processing device is referred to as the source consistency controller, and the memory controller in the first processor chip is referred to as the source memory controller. In some embodiments, when the first memory address segment belongs to the mirrored address segment (i.e., the first memory address hits the mirrored address), the source consistency controller takes the consistency controller in the processor chip where the memory channel (referred to as the target memory channel) to which the mirrored address segment of the first memory address segment belongs as the target consistency controller. The source consistency controller can route the second read request to the target consistency controller through the target network, and the target consistency controller processes the second read request.

[0171] Assuming the data processing device is the consistency controller in the first processor chip, for ease of description, the data processing device is referred to as the source consistency controller, and the memory controller in the first processor chip is referred to as the source memory controller. In some embodiments, when the first memory address segment belongs to the mirrored address segment (i.e., the first memory address hits the mirrored address), the source consistency controller takes the consistency controller in the processor chip where the memory channel (referred to as the target memory channel) to which the mirrored address segment of the first memory address segment belongs as the target consistency controller. The source consistency controller can route the second read request to the target consistency controller through the target network, and the target consistency controller processes the second read request.

[0172] by Figure 8For example, if the accessed address segment belongs to a mirror address segment, the source consistency controller, based on the interleaving pattern of memory address mapping to memory channel in the computer system (i.e., the mapping relationship between memory address and memory channel), determines the memory channel mapped to the mirror address segment of the accessed address segment (i.e., the target memory channel). It then designates the memory controller connected to the target memory channel as the target memory controller and the consistency controller corresponding to the target memory controller (i.e., the consistency controller in the processor chip where the target memory controller resides) as the target consistency controller. This achieves the determination of the target consistency controller based on the mirror address segment of the accessed address segment and the interleaving pattern of memory address mapping to memory channel in the computer system, thus determining the location of the target memory controller in the computer system. The source consistency controller, using itself as the source node of the second read request and the target consistency controller as the destination node, sends the second read request to the target consistency controller through the transmission network. The second read request includes the mirror address segment of the accessed address segment. The target consistency controller receives the second read request, generates a new read request (called the fourth read request) based on it, and sends the fourth read request to the target memory controller. The fourth read request includes the mirror address segment of the accessed address segment. Based on the fourth read request, the target memory controller reads the mirror data of the second data from the mirror memory space (i.e., the memory space indicated by the mirror address segment of the accessed address segment). For example, the target memory controller determines the target memory channel based on the mirror address segment in the fourth read request and the interleaving pattern of memory address mapping to memory channels in the computer system, and reads the mirror data of the second data from the mirror memory space through the target memory channel. After reading the mirror data of the second data, the target memory controller returns the mirror data of the second data to the target consistency controller, which receives the mirror data, thus enabling the target consistency controller to read the mirror data of the second data through the target memory controller. Based on the mirror data of the second data, the target consistency controller generates a read response for the second read request, which includes the mirror data of the second data. The target consistency controller, with itself as the source node of the read response and the source consistency controller as the destination node, sends the read response for the second read request to the source consistency controller through the transmission network, in order to return the mirror data of the second data to the source consistency controller. The source consistency controller receives the read response to the second read request, replaces the erroneous read data with the mirrored data of the second data, and returns the read response to the agent device of the source device for the first read request. The read response includes the mirrored data of the second data. When the target memory channel is located on the processor chip where the source consistency controller resides (i.e., the first processor chip), the target consistency controller and the source consistency controller are the same consistency controller, and the target memory controller and the source memory controller are the same memory controller.When the target memory channel is located on a processing chip (i.e., the third processor chip) outside the first processor chip, the target consistency controller and the source consistency controller are different consistency controllers, and the target memory controller and the source memory controller are different memory controllers.

[0173] It should be understood that if the second memory address segment belongs to the mirrored address segment, and the mirrored address segment to which the second memory address segment belongs has multiple mirrored address segments (for example, the preset address pair to which the mirrored address segment to which the second memory address segment belongs includes multiple mirrored address segments), then the data processing device can randomly select a mirrored address segment from the multiple mirrored address segments of the mirrored address segment, determine the mirrored address segment of the second memory address segment from the randomly selected mirrored address segment, and read the mirrored data of the second data from the mirrored address segment of the second memory address segment.

[0174] The above embodiments are all described using the example of a read response including the read data. In some embodiments, the read data may not be included in the read response, and the read response and the read data may be sent separately.

[0175] In the method provided in this disclosure, the storage locations of the mirrored data and the mirrored data in memory are specified respectively through the mirrored address segment and the mirrored address segment in the preset address pair, thereby setting the mirrored memory at the granularity of address segments. When the memory address of the data to be read matches the mirrored address segment, it indicates that the data is the mirrored data. If a data read error occurs when reading data from the storage location indicated by the memory address, the mirrored data of the data can be read from the storage location indicated by the corresponding mirrored address segment to ensure that the data is read. Since the preset address pair allows for flexible setting of the mirrored memory for the mirrored data at the granularity of address segments, data with relatively low reliability requirements in the computer system can be ignored, and mirrored memory can be not set for data with relatively low reliability requirements. Only data with relatively high reliability requirements in the computer system can be used as the mirrored data. By setting the mirrored data in mirrored memory that is suitable in terms of size and location through the preset address pair, the memory space of the computer system can be maximized, and the hardware cost of the memory in the computer system can be reduced.

[0176] The above description uses the data processing device as the consistency controller as an example. In some embodiments, the data processing device is the memory controller in the first processor chip. The memory controller can execute the method steps executed by the consistency controller. The difference is that the first write request obtained by the memory controller in the first processor chip is a third write request sent by the consistency controller to the memory controller. When the mirror address segment of the first memory address segment corresponds to the memory channel in the second processor chip, the memory controller in the first processor chip interacts with the consistency controller in the second processor chip through the transmission network to write the mirror data of the first data into the memory space indicated by the mirror address segment of the first memory address segment. The first read request obtained by the memory controller in the first processor chip is a third read request sent by the consistency controller to the memory controller. When the mirror address segment of the second memory address segment corresponds to the memory channel in the third processor chip, the memory controller in the first processor chip interacts with the consistency controller in the third processor chip through the transmission network to read the mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment.

[0177] In an exemplary embodiment, a processor chip is also provided, the processor chip including a processor core and a data processing device, the cache being used to store data, and the data processing device being configured to execute the respective method steps performed by the data processing device in the various data processing methods described above. The data processing device can be a consistency controller or a memory controller.

[0178] In an exemplary embodiment, a data processing apparatus is also provided, including a control circuit and a buffer. The buffer stores data, and the control circuit is configured to execute the method steps performed by the data processing apparatus in the various data processing methods described above. The control circuit may be implemented in at least one hardware form selected from Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), and Application Specific Integrated Circuit (ASIC). The implementation method of the control circuit is not limited herein.

[0179] by Figure 9 Taking the data processing device 900 shown as an example, as Figure 9As shown, the data processing device 900 includes a control circuit 901, a cache 902, and a control circuit 903. The control circuit 901 is the overall controller of the data processing device 900, used to implement the main business control logic of the data processing device 900. For example, when the data processing device 100 is a consistency controller, the control circuit 901 is used to control and coordinate data read / write, request, response, and frame listening behaviors in the computer system. When the data processing device 100 is a memory controller, the control circuit 901 is used to manage and control the memory chip, and to execute read / write request control from the corresponding consistency controller.

[0180] Cache 902 is used to cache data and can provide data caching services for control circuit 901 and control circuit 903.

[0181] The control circuit 903 is used to execute various method steps related to the mirrored address segment in the above method embodiments. For example, it is used to receive a preset address pair configured by the target application, determine whether the address segment (such as the first memory address segment or the second memory address segment) requested by the read / write request of the source device belongs to the mirrored address segment based on the preset address pair, and if the accessed address segment belongs to the mirrored address segment, determine the mirrored address segment of the accessed address segment, and perform data read / write operations on the memory space indicated by the mirrored address segment of the accessed address segment, etc.

[0182] Figure 9 The example illustrates two different control circuits, 901 and 903. In some embodiments, control circuit 903 may also be integrated into control circuit 901 as a circuit module within control circuit 901.

[0183] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0185] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data processing method, characterized in that, The method, applied to a first processor chip in a computer system, includes: Obtain a first write request, the first write request indicating that first data be written to the memory space indicated by a first memory address segment in the computer system; Write the first data into the memory space indicated by the first memory address segment; Based on at least one preset address pair, it is determined whether the first memory address segment belongs to the mirrored address segment. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store the data to be mirrored in the computer system, and the mirrored address segment is used to store the mirrored data of the data. If the first memory address segment belongs to the mirrored address segment, write the mirrored data of the first data to the memory space indicated by the mirrored address segment of the first memory address segment, where the mirrored address segment of the first memory address segment belongs to the mirrored address segment of the mirrored address segment to which the first memory address segment belongs.

2. The method according to claim 1, characterized in that, The length of the mirrored address segment and the mirrored address segment of the mirrored address segment are the same.

3. The method according to claim 1, characterized in that, The mirrored address segment to which the first memory address segment belongs corresponds to the first memory channel in the first processor chip, and the mirrored address segment of the first memory address segment corresponds to the second memory channel in the first processor chip. Writing the first data to the memory space indicated by the first memory address segment includes: The first data is written into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment includes: If the first memory address segment belongs to the mirrored address segment, the mirrored data of the first data is written to the memory space indicated by the mirrored address segment of the first memory address segment through the second memory channel.

4. The method according to claim 1, characterized in that, The computer system includes a second processor chip, the mirrored address segment to which the first memory address segment belongs corresponds to a first memory channel in the first processor chip, and the mirrored address segment of the first memory address segment corresponds to a memory channel in the second processor chip. Writing the first data to the memory space indicated by the first memory address segment includes: The first data is written into the memory space indicated by the first memory address segment through the first memory channel; If the first memory address segment belongs to the mirrored address segment, writing mirrored data of the first data into the memory space indicated by the mirrored address segment of the first memory address segment includes: If the first memory address segment belongs to the mirrored address segment, a second write request is sent to the second processor chip. The second write request indicates that mirrored data of the first data be written to the memory space indicated by the mirrored address segment of the first memory address segment.

5. The method according to any one of claims 1-4, characterized in that, The at least one preset address is set based on the business's demand for mirrored data.

6. A data processing method, characterized in that, The method, applied to a first processor chip in a computer system, includes: Obtain a first read request, the first read request instructing the reading of second data from the memory space indicated by the second memory address segment in the computer system; Read the second data from the memory space indicated by the second memory address segment; If a data reading error occurs when reading the second data, it is determined whether the second memory address segment belongs to the mirrored address segment based on at least one preset address pair. The preset address pair includes the mirrored address segment and the mirrored address segment of the mirrored address segment. The mirrored address segment is used to store the mirrored data in the computer system, and the mirrored address segment is used to store the mirrored data of the mirrored data. If the second memory address segment belongs to the mirrored address segment, read the mirror data of the second data from the memory space indicated by the mirror address segment of the second memory address segment, where the mirror address segment of the second memory address segment belongs to the mirror address segment of the mirrored address segment to which the second memory address segment belongs; Send the mirror image data of the second data that has been read.

7. The method according to claim 6, characterized in that, The length of the mirrored address segment and the mirrored address segment of the mirrored address segment are the same.

8. The method according to claim 6, characterized in that, The mirrored address segment to which the second memory address segment belongs corresponds to the third memory channel in the first processor chip, and the mirrored address segment of the second memory address segment corresponds to the fourth memory channel in the first processor chip. Reading the second data from the memory space indicated by the second memory address segment includes: The second data is read from the memory space indicated by the second memory address segment through the third memory channel; If the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment includes: If the second memory address segment belongs to the mirrored address segment, the mirrored data of the second data is read from the memory space indicated by the mirrored address segment of the second memory address segment through the fourth memory channel.

9. The method according to claim 6, characterized in that, The computer system includes a third processor chip, the mirrored address segment to which the second memory address segment belongs corresponds to the first memory channel in the first processor chip, and the mirrored address segment of the second memory address segment corresponds to the memory channel in the third processor chip. Reading the second data from the memory space indicated by the second memory address segment includes: The second data is read from the memory space indicated by the second memory address segment through the third memory channel; If the second memory address segment belongs to the mirrored address segment, reading the mirrored data of the second data from the memory space indicated by the mirrored address segment of the second memory address segment includes: If the second memory address segment belongs to the mirrored address segment, a second read request is sent to the third processor chip. The second read / write request indicates that the mirrored data of the second data be read from the memory space indicated by the mirrored address segment of the second memory address segment.

10. The method according to any one of claims 6-9, characterized in that, The at least one preset address is set based on the business's demand for mirrored data.

11. A data processing apparatus, characterized in that, It includes a cache and a control circuit, the cache being used to store data, and the control circuit being configured to perform the data processing method according to any one of claims 1 to 10.

12. The data processing apparatus according to claim 11, characterized in that, The data processing device is a consistency controller or a memory controller in a processor chip. The memory controller is used to control the memory chip, and the consistency controller is the next-level controller of the memory controller.

13. A processor chip, characterized in that, It includes a processor core and the data processing apparatus as described in claim 11 or 12.

14. A computer system, characterized in that, It includes a memory chip and the processor chip of claim 13, wherein the memory chip is used to store data written by the processor chip.

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