Data interaction method and device for multi-core heterogeneous chip, equipment and medium

Abstract

The invention provides a data interaction method, device and equipment for a multi-core heterogeneous chip and a medium, and the method comprises the steps: transmitting a control command to a small core through a large core, so as to enable the small core to carry out initialization configuration; peripheral data and / or inter-core data are / is obtained through the initialized small core; and processing the peripheral data and / or the inter-core data through the small core to obtain target data, and transmitting the target data to the large core or the small core. Peripheral data and / or inter-core data are / is obtained through a small core, so that the multi-core heterogeneous chip can adapt to different application scenes, and the universality is good; data are processed in a serial or parallel manner through a plurality of small cores, data interaction among the cores is diversified, various scenes of data interaction are compatible, the flexibility is high, the expansibility is good, data interaction is directly carried out between a large core and the small cores, and the communication efficiency is high.

Description

Technical Field

[0001] This invention relates to, but is not limited to, the field of communication technology, and particularly to data interaction methods, apparatuses, devices, and media for multi-core heterogeneous chips. Background Technology

[0002] With the rapid development of integrated circuit technology, chip design schemes are trending towards multi-core heterogeneity, often consisting of multiple large cores and multiple small cores. In a multi-core heterogeneous platform, different cores define different responsibilities and run their own independent operating systems (OS).

[0003] Currently, inter-core communication in multi-core heterogeneous chips on the market is accomplished through specific hardware or shared memory and interrupts. Due to the limitations of the hardware itself, the number of communications is limited and the scalability is poor. Shared memory and interrupts require two memory blocks to communicate, and only support large cores copying data to shared memory. Small cores read the data, process it, and then copy it to shared memory, resulting in low communication efficiency. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The main objective of this invention is to propose a data interaction method, apparatus, device, and medium for multi-core heterogeneous chips, which can improve the communication efficiency and scalability of multi-core heterogeneous chips.

[0006] In a first aspect, embodiments of the present invention provide a data interaction method for a multi-core heterogeneous chip, applied to a multi-core heterogeneous chip system, wherein the multi-core heterogeneous chip system includes a large core and multiple small cores, the large core and the multiple small cores being connected via a bus, and the data interaction method for the multi-core heterogeneous chip includes: The large core sends control commands to the small core to enable the small core to perform initialization configuration. Peripheral data and / or inter-core data are acquired through the initialized small core, wherein the inter-core data represents data generated by the large core or the small core; The target data is obtained by processing the peripheral data and / or the inter-core data through the small core, and then the target data is sent to the large core or the small core; wherein, the target data is obtained by serial processing of the data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of the data generated by the large core through multiple small cores.

[0007] The data interaction method for multi-core heterogeneous chips according to embodiments of the present invention has at least the following beneficial effects: peripheral data and / or inter-core data are acquired through small cores, thereby enabling multi-core heterogeneous chips to adapt to different application scenarios and have good versatility; data is processed serially or in parallel by multiple small cores, resulting in diverse inter-core data interaction, compatibility with various data interaction scenarios, high flexibility, good scalability, and direct data interaction between large cores and small cores, resulting in high communication efficiency.

[0008] In some optional embodiments, sending control commands from the large core to the small core to cause the small core to perform initialization configuration includes: The initialization thread is created when the small core starts up, and the number of initialization threads is configured according to the number of processes on the large core. The large core calls the cross-core control interface to establish control channels with the multiple small cores respectively; The large core calls the initialization configuration, and the large core sends an initialization control command to the small core through the control channel, while simultaneously calling the cross-core data transmission interface to establish the data transmission channel. The initialization control command is sent to multiple small cores through the control channel via the multi-process call of the large core, so that the multiple small cores can perform initialization configuration; The initialization thread creates a command processing thread between the small core and the large core. The control command is sent to the small core via the command processing thread to enable the small core to perform initialization configuration. Data transmission is initiated by the large core, and after the small core receives the command to initiate transmission through the command processing thread, it creates a data processing thread and a data transmission thread. In some optional embodiments, the step of creating a command processing thread between the small core and the large core through the initialization thread includes: The initialization thread creates the first cross-core control interface for the small core and waits for the large core to call the second cross-core control interface to create a control channel. The large core calls a second cross-core control interface that is the same as the first cross-core control interface, and the second cross-core control interface is located at the large core end; After the first cross-core control interface and the second cross-core control interface are successfully invoked, the initialization thread will create a command processing thread and then clear the initialization thread itself.

[0009] In some optional embodiments, establishing the data transmission channel between the large core and the small core includes: After the small core receives the initialization command through the command processing thread, it calls the first cross-core data interface of the small core and waits for the large core to call the second cross-core data interface to create a data transmission channel. The large core calls a second cross-core data interface that is the same as the first cross-core data interface, and the second cross-core data interface is located at the large core. After the first cross-core data interface and the second cross-core data interface are successfully invoked, the large core starts cross-core data transmission; The data transmission channels are divided into two types according to requirements: big core to small core data transmission or small core to big core data transmission. The number of data transmission channels is configured by the number of large core multiprocesses, and the data transmission channels can independently and in parallel transmit different types of data.

[0010] In some optional embodiments, after receiving the start transmission command through the command processing thread, the small core creates the data processing thread and the data transmission thread, including: The data processing thread processes peripheral data and / or inter-core data in real time. The data transmission thread transmits the data processed by the data processing thread to the small core or the large core. After receiving the start transmission command through the command processing thread, the small core, after creating the data transmission thread and the data transmission thread, sends a feedback command to the large core through the cross-core command interface to indicate that the small core is ready and the data transmission function of the large core is enabled.

[0011] In some optional embodiments, after initializing and configuring the small core, the method further includes: Establish a cross-core transport component among the multiple small cores; Data is transmitted sequentially between the multiple small cores via the cross-core transmission component, so that the multiple small cores process the data serially.

[0012] In some optional embodiments, the step of acquiring peripheral data and / or inter-core data through the initialized small core includes: The peripheral data is obtained through the first sub-core; The first data of the first sub-core is obtained through the second sub-core. The first data belongs to the inter-core data. The first data is obtained by processing the peripheral data through the first sub-core. The second data is obtained by processing the first data of the first sub-core through the second sub-core, and the second data belongs to the inter-core data; The third data of the large core is obtained through the third sub-core. The third data belongs to the inter-core data. The first sub-core, the second sub-core, and the third sub-core represent different types of small cores.

[0013] In some optional embodiments, when the multi-core heterogeneous chip is in sleep mode, the method further includes: The large core sends a low-power command to the fourth sub-core to cause the fourth sub-core to enter a low-power mode. The fourth sub-core represents the small core used to acquire peripheral data during the hibernation period of the multi-core heterogeneous chip. The large core sends a hibernation command or a shutdown command to the fifth sub-core, causing the fifth sub-core to enter hibernation or shutdown. The fifth sub-core represents the small core that has entered hibernation or shutdown. After the fifth sub-core enters hibernation or is shut down, the large core enters low-power mode or hibernation.

[0014] In some optional embodiments, when the multi-core heterogeneous chip is woken up, the method further includes: When the peripheral data received by the fourth sub-core is wake-up data, the fourth sub-core wakes up the large core to exit sleep or exit low-power mode, and the large core wakes up the fourth sub-core to exit low-power mode. In the case where the wake-up data represents a first-level wake-up, the large core wakes up the hardware resources, saves the data generated by the fourth sub-core to the hardware resources, controls the fourth sub-core to continue receiving and processing the wake-up data, and determines whether to enter a second-level wake-up by processing the wake-up data through the fourth sub-core. After successful judgment, in the case of entering the second-level wake-up, the large core sends a command to the fourth sub-core to enter normal mode, and at the same time wakes up or starts the fifth sub-core to enter normal mode, and then the large core enters normal mode.

[0015] Secondly, embodiments of the present invention provide a data interaction device for a multi-core heterogeneous chip, comprising: a first module, configured to send control commands to the small core through the large core, so that the small core performs initialization configuration; The second module is used to acquire peripheral data and / or inter-core data through the initialized small core, wherein the inter-core data represents data generated by the large core or the small core; The third module is used to process the peripheral data and / or the inter-core data through the small core to obtain target data, and to send the target data to the large core or the small core; wherein the target data is obtained by serial processing of data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of data generated by the large core through multiple small cores.

[0016] Thirdly, embodiments of the present invention provide an electronic device, including: at least one processor; at least one memory for storing at least one program; when the at least one program is executed by the at least one processor, the at least one processor implements the above-described data interaction method for multi-core heterogeneous chips.

[0017] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing program instructions, which, when executed by a processor, implement the aforementioned data interaction method for multi-core heterogeneous chips.

[0018] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0019] Figure 1 This is an example diagram illustrating the implementation environment of the data interaction method for multi-core heterogeneous chips provided in this embodiment; Figure 2 This is a schematic diagram illustrating the steps of the data interaction method for multi-core heterogeneous chips provided in this embodiment; Figure 3 This is a framework diagram of the multi-core heterogeneous data interaction software provided in this embodiment; Figure 4 This is the multi-core heterogeneous data stream provided in this embodiment; Figure 5 This is the big core control flowchart provided in this embodiment; Figure 6 This is the small core control flowchart provided in this embodiment; Figure 7 This is a schematic diagram of the multi-core heterogeneous software solution provided in this embodiment; Figure 8 This is a schematic diagram of the multi-core heterogeneous low-power software solution provided in this embodiment; Figure 9 This is a schematic diagram of the internal modules of the data interaction device for multi-core heterogeneous chips provided in this embodiment; Figure 10 This is a schematic diagram of the device provided in this embodiment; Figure 11 This is a schematic diagram of the storage medium provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0022] This application provides a data interaction method, apparatus, device, and medium for multi-core heterogeneous chips, which will be described in detail in the following embodiments.

[0023] like Figure 1 The diagram shown is a structural schematic of an implementation environment provided by this invention. In this implementation environment, the multi-core heterogeneous chip system includes a large core and multiple small cores, which are connected via a bus. Through this bus connection, the large and small cores share hardware resources, and some peripheral resources can be shared with the small cores. Hardware resources can be configured for either the large or small cores based on specific usage scenarios, thus avoiding the drawbacks of separating the large and small cores and limiting the small cores to specific functions. Each processor (large and small cores) has a hardware transmission channel that supports pairwise communication between processors. For example, in a four-CPU communication scenario, CPU0 has the first transmission channel, and CPU0 communicates with CPU1, CPU2, and CPU3 through this first channel, and so on. Each CPU is allocated four channels to complete pairwise communication. Message transmission between processors can be implemented using interrupts.

[0024] It should be understood that the embodiments of the present invention are only by way of Figure 1 An example of an implementation environment that can be implemented is provided.

[0025] Reference Figure 2 This embodiment discloses a data interaction method for multi-core heterogeneous chips, including but not limited to steps S100-S300.

[0026] Step S100: The large core sends a control command to the small core to enable the small core to perform initialization configuration.

[0027] Specifically, refer to Figure 3 The software architecture of the multi-core heterogeneous chip in this application is divided into three layers: the application layer, the adaptation layer, and the driver layer. The main logic of the data interaction software solution is implemented in the adaptation layer.

[0028] The main functions of the application layer are to control the small core, configure algorithm parameters, send data to be processed, receive processed data or data processed by the small core, and provide reference examples to facilitate adaptation to user applications.

[0029] The adaptation layer shields the differences in underlying drivers, simplifying the interface for application layer use. It supports communication between multiple cores, serial or parallel processing algorithms with multiple small cores, and switching between low-power and normal modes.

[0030] The driver layer primarily implements multi-core communication drivers and also includes drivers configured for peripherals on large or small cores. Different systems have different drivers and communication methods. The adaptation layer provides a unified interface for applications, eliminating the need for them to concern themselves with the underlying drivers and communication methods.

[0031] The adaptation layer provides control and data transmission interfaces. The application layer calls the control interface to control the small cores to initialize resources, configure parameters (including algorithm parameters), start data processing, pause data processing, resume data processing, end data processing, release resources, and configure the creation of cross-core transmission components between small cores.

[0032] The application layer controls the initialization of resources by the small core. The small core first calls the cross-core data transfer interface and configures the parameters. Simultaneously, the large core calls the same cross-core data transfer interface to establish a data transfer channel. After the large core starts data transfer, the small core, upon receiving the command to start transfer, then creates the aforementioned data transfer thread and data transfer interface. It then sends a feedback command to the large core through the cross-core command interface. The large core can then call the data transfer interface to transfer data to the small core and receive the processed data from the small core, or the application layer can directly obtain the processed data from the small core.

[0033] The application layer calls the control interface to configure multiple small cores (cores 0-X) to initialize resources (i.e., initialize configuration). Each of these small cores calls the data transmission interface. After the application layer establishes a data transmission channel with multiple small cores through multiple processes calling the data transmission interface, it can send data to multiple small cores (cores 0-X) to achieve parallel processing. Depending on the application scenario, the data ultimately flows to either the large core or the small core. This design is suitable for algorithms used independently by multiple processes.

[0034] Reference Figure 3 The software architecture of this application is described below: I. Application Layer (App) Component: Contains multiple processes (Process0 - ProcessX). These processes interact with the adaptation layer through two APIs: Control API (Ctrl API0 - Ctrl APIX): This is part of the Cross-Core API and is used to send control commands to the adaptation layer, such as initializing small cores, configuring parameters, and controlling the start / pause / resumption / end of small core processing.

[0035] Data API (Data API0 - Data APIX): Also a cross-core API, used to transmit data to be processed to the adaptation layer and to receive data processed by the small core.

[0036] II. Adapter Layer Core components: Cross-Core API: Receives control and data API requests from the application layer and passes them to the lower layers. It serves to shield the underlying driver differences, simplify the interface, and facilitate application-layer calls.

[0037] Cross-core Framework: Responsible for managing and coordinating the work between multiple small cores (Small Core0 - Small CoreX). It enables communication between multiple cores, supports serial or parallel processing algorithms for small cores, and can handle switching between low-power mode and normal mode.

[0038] Interacting with small cores: Communicate with each small core through control (Ctrl) and data (Data) channels. Each small core contains a control processing (Ctrl Process (0 - X)) and a data processing (data Process (0 - X)) module, which respectively process control commands from the large core and data to be processed by the large or small core.

[0039] III. Driver Layer Framework: The framework adopted is AMP (Asymmetric Multi-Processing).

[0040] Communication components: Mailbox: A mechanism for inter-core communication that uses message queues and interrupt-driven signals to handle communication between multiple processors.

[0041] Msgbox: A message interruption mechanism adapted through the Mailbox framework.

[0042] VirtIo: A shared memory management framework.

[0043] RPMsg: A framework for inter-core data transfer based on VirtIo, enabling asynchronous message transfer between different cores.

[0044] IV. Overall Interaction Flow Application layer initiates requests: The application layer process sends control commands through the control API or sends data to be processed to the adaptation layer through the data API.

[0045] Adaptor layer processing and forwarding: After receiving a request, the cross-core API of the adaptation layer forwards the control instructions or data to the corresponding small core through the cross-core framework. The cross-core framework coordinates the working mode (serial or parallel) and power consumption mode of the small core according to the configuration and task requirements.

[0046] The small core performs tasks: After receiving control commands and data, the internal control processing module and data processing module process them separately. For example, the control processing module initializes resources and configures parameters according to the commands, while the data processing module performs algorithmic processing on the incoming data.

[0047] Result Return: After processing, the small core returns the result to the application layer through the adaptation layer. If it is a data processing result, it is returned through the data channel; if it is control-related feedback (such as small core resources being ready), it is returned through the control channel.

[0048] Driver layer support: The AMP framework and related communication components in the driver layer provide underlying support for communication between multiple cores, ensuring that control commands and data can be transmitted accurately and efficiently between different cores.

[0049] Step S200: Obtain peripheral data and / or inter-core data through the initialized small core, wherein the inter-core data represents the data generated by the large core or the small core.

[0050] Specifically, inter-core data can be generated by any core (either a large core or a small core). The small core connects to peripherals through specific hardware interfaces (such as SPI, I2C, UART, GPIO, etc.). Taking the SPI interface as an example, the small core acts as the master device, sending clock signals and control commands to the peripheral device (slave device). The peripheral device then transmits data back to the small core via data lines according to the commands. The small core temporarily stores the received data using internal registers.

[0051] Communication mechanisms: Inter-core communication relies on specific hardware communication mechanisms, such as shared memory, message passing (e.g., Mailbox mechanism, RPMsg exception transmission mechanism), and high-speed buses (e.g., PCIe, AXI). For example, when using shared memory, both large and small cores can access the same memory region.

[0052] Data reading: The small core locates the location of inter-core data in shared memory through address mapping, and then reads the data according to a predefined data format (such as a structure or array). If a message passing mechanism is used, the small core retrieves message data sent by the large core or other small cores from the corresponding message queue or mailbox.

[0053] Step S300: After processing the peripheral data and / or the inter-core data by the small core, the target data is obtained, and the target data is sent to the large core or the small core; wherein, the target data is obtained by serial processing of the data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of the data generated by the large core through multiple small cores.

[0054] Specifically, refer to Figure 4 Data transmission and processing scenarios include: Data streams produced by small cores (data produced by small cores includes data processed by small cores based on acquired peripheral data or data produced by the small cores themselves), processed serially by multiple small cores, and finally transmitted to or returned to the large core. Alternatively, data streams produced by the large core, processed serially by multiple small cores, and finally transmitted to or returned to the large core. Finally, data streams produced by the large core, processed in parallel by multiple small cores, and finally transmitted to or returned to the large core.

[0055] Data streams can be generated simultaneously by both small and large cores, and the direction of the data flow can be combined according to various transmission and processing scenarios. Data generated by small cores is processed serially by multiple small cores before being transmitted back to a small core or returned to a large core. Data generated by large cores is processed serially or in parallel by multiple small cores before being transmitted back to a small core or returned to a large core. The diverse scenarios of data streams allow for adaptation to different application scenarios, meaning different data interaction methods can be switched according to different application scenarios, thereby greatly improving the efficiency and applicability of data interaction.

[0056] In some optional embodiments, the step of sending control commands to the small cores via the large core to enable the small cores to perform initialization configuration includes: establishing control channels with multiple small cores respectively through the large core calling a cross-core control interface; the large core calling initialization configuration, sending initialization control commands to the small cores through the control channels, and simultaneously calling a cross-core data transmission interface to establish the data transmission channel; the large core sending the control commands to multiple small cores through multi-process calls to the control channels to enable the multiple small cores to perform initialization configuration; creating an initialization thread when the small core starts; creating a command processing thread between the small core and the large core through the initialization thread; and sending the control commands to the small cores through the command processing thread to enable the small cores to perform initialization configuration. When the large core initiates data transmission, the small cores, after receiving the start transmission command through the command processing thread, create the data processing thread and the data transmission thread. In some optional embodiments, the step of creating a command processing thread between the small core and the large core through the initialization thread includes: creating a first cross-core control interface on the small core through the initialization thread; creating a second cross-core control interface on the large core that is the same as the first cross-core control interface, the second cross-core control interface being located on the large core; creating the command processing thread between the first cross-core control interface and the second cross-core control interface, and then clearing the initialization thread itself.

[0057] In some optional embodiments, establishing the data transmission channel between the large core and the small core includes: the large core calling an initialization configuration; after receiving the initialization command through the command processing thread, the small core calls the first cross-core data interface and waits for the large core to call the second cross-core data interface to create the data transmission channel; the large core calls the second cross-core data interface, which is the same as the first cross-core data interface, located on the large core; after the first and second cross-core data interfaces are successfully called, the large core starts cross-core data transmission; the data transmission channel is divided into large core to small core data transmission or small core to large core data transmission type according to requirements; the number of data transmission channels is configured by the number of processes on the large core, and the data transmission channels can independently and in parallel transmit different types of data.

[0058] In some optional embodiments, after receiving the start transmission command through the command processing thread, the small core creates the data processing thread and the data transmission thread, including: processing peripheral data and / or inter-core data in real time through the data processing thread; transmitting the data processed by the data processing thread to the small core or the large core through the data transmission thread; after receiving the start transmission command through the command processing thread, the small core, after completing the creation of the data transmission thread and the data transmission thread, sends a feedback command to the large core through the cross-core command interface to indicate that the small core is ready and the data transmission function of the large core is enabled.

[0059] In some optional embodiments, after initializing and configuring the small cores, the method further includes: establishing a cross-core transmission component among the multiple small cores; and sequentially transmitting data among the multiple small cores through the cross-core transmission component, so that the multiple small cores process data serially.

[0060] Specifically, the control in this application is all performed on the large core, meaning it is controlled by the application. The control flow in this application is divided into two parts: one part is implemented on the large core, and the other part is implemented on the small core. (See reference...) Figure 5 The control flow implemented through the large core is as follows: The large core calls the cross-core control interface to establish control channels with all small cores. The large core sends commands through multiple processes calling the control channels to control multiple small cores to initialize resources and configure parameters (initialization configuration). Based on requirements, it configures cross-core transmission components between small cores and prepares to control the small cores to begin processing data. Each process of the application waits for each small core's resources to be created before notifying the small core to process the data. After processing is complete, the large core controls multiple small cores to stop processing data and release resources.

[0061] The aforementioned cross-core transfer component is used for sequential serial data processing between smaller cores. A smaller core that hasn't acquired data will wait for the data to arrive before starting its processing. The larger core stops the first smaller core, and then sequentially stops each of the serially processing smaller cores. Finally, the larger core controls the serially processing smaller cores to release their resources. Whether the larger core is configured to process data in parallel or serially depends on the application scenario.

[0062] Reference Figure 6The control flow implemented through the small cores is as follows: After the small cores start, they create a corresponding number of initialization threads based on the configured number (i.e., each small core creates an initial thread to communicate with the large core). These initialization threads are used to create control channels for communication with the large core, and each small core supports multiple channels to process data independently at the same time. After creating the cross-core control interface (i.e., the first cross-core control interface) on the small core through the initialization threads, it waits for the large core to create the same cross-core control interface (i.e., the second cross-core control interface). Once the large core is created, a corresponding command processing thread is created, and the initialization threads are destroyed. This command processing thread can then receive commands from the remote end and perform a series of operations on the small core, namely, initializing resources, configuring parameters, starting data processing, ending data processing, and releasing resources. Cross-core transmission components can also be created between small cores according to data transmission and processing requirements, enabling data to be processed serially between small cores. The specific data flow direction is determined by the commands from the large core. The serial execution order of the small cores is also controlled by the large core, and serial data transmission is completed by configuring the cross-core transmission components.

[0063] In some optional embodiments, the step of acquiring peripheral data and / or inter-core data through the initialized small core includes: acquiring the peripheral data through a first sub-core; acquiring first data of the first sub-core through a second sub-core, wherein the first data belongs to the inter-core data, and the first data is obtained by processing the peripheral data through the first sub-core; obtaining second data by processing the first data of the first sub-core through the second sub-core, wherein the second data belongs to the inter-core data; and acquiring third data of the large core through a third sub-core, wherein the third data belongs to the inter-core data, wherein the first sub-core, the second sub-core, and the third sub-core represent different types of small cores.

[0064] Specifically, refer to Figure 7 This application allows configuring one or more small cores (small core 0 and small core 2) to acquire data from peripherals. The application layer calls the control interface to configure multiple small cores to initialize resources. The small core with configured hardware resources (i.e., the first sub-core) acquires and processes data, and a certain number of small cores (small core 1, i.e., the second sub-core) are allocated to acquire and process data sequentially. The remaining small cores (small cores 3-X, i.e., the third sub-core) receive data processing from the large core. This is suitable for scenarios where multiple small cores (small core 0 and small core 1) process data serially, while the remaining small cores process data in parallel.

[0065] There are also the following two possibilities: 1. All other small cores participate in the serial data processing of the small cores that configure hardware resources. This is called serial processing of all small cores (that is, all small cores except the first sub-core are configured as the second sub-core).

[0066] 2. Other small cores do not participate in the data processing of the small cores configured with hardware resources, and all receive data processing from the large cores. In this case, the small cores configured with hardware resources process data separately, while the other small cores process data in parallel (that is, all small cores except the first sub-core are configured as the third sub-core).

[0067] Depending on the application scenario, the data is determined to come from either the small core (small core 0 and small core 2) or the large core (small core 3-X). Data generated by the small core is generally used directly for algorithm processing, while data generated by the large core is generally used as a module for the small core.

[0068] Depending on the application scenario, the final data flow is determined to either the large core or the small core. Generally, the large core receives the data for final processing. When multiple small cores process data serially, the data may also flow to the small cores; the specific data flow is not specified here.

[0069] In some optional embodiments, when the multi-core heterogeneous chip is in sleep mode, the method further includes: sending a low-power command to a fourth sub-core via the large core to cause the fourth sub-core to enter a low-power mode, the fourth sub-core representing the small core used to acquire peripheral data during the multi-core heterogeneous chip sleep period; sending a sleep command or a shutdown command to a fifth sub-core via the large core to cause the fifth sub-core to enter sleep mode or shut down, the fifth sub-core representing the small core that has entered sleep mode or shut down; and after the fifth sub-core enters sleep mode or shuts down, the large core enters a low-power mode or sleep mode.

[0070] Specifically, the sleep mode trigger condition in this application is prolonged inactivity or external button press. After sleep mode is triggered, it enters a low-power mode. At this time, the single production data small core (i.e., the fourth sub-core) enters the low-power mode (or sleeps), the large core enters the low-power mode (or sleeps), and the other small cores (i.e., the fifth sub-core) sleep (or are turned off). The specific control flow for the multi-core heterogeneous chip to enter the low-power mode is as follows: 1. The large core first sends a low-power command to the small core (fourth sub-core) that generates data, and the small core enters low-power mode. Depending on the application scenario, at most only one small core that generates data will remain in low-power mode.

[0071] 2. The large core then sends a hibernation command (or a shutdown command) to the other small cores (i.e., the fifth sub-core), waiting for the other small cores to successfully enter hibernation (or shutdown).

[0072] 3. After all other small cores have entered sleep mode (or been turned off), the large core can be configured to enter low-power mode (only retaining relevant hardware operations) or directly enter sleep mode, depending on the application scenario.

[0073] By retaining one small core for production data, putting other small cores to sleep or shutting them down, and configuring the large cores to low-power mode or putting them to sleep, the power consumption of multi-core heterogeneous chips is greatly reduced when they are in sleep mode, thus extending the battery life of multi-core heterogeneous chips.

[0074] In some optional embodiments, when the multi-core heterogeneous chip is woken up, the method further includes: if the peripheral data received by the fourth sub-core is wake-up data, waking up the large core from sleep or low-power mode via the fourth sub-core, and waking up the fourth sub-core from low-power mode via the large core; if the wake-up data indicates a first-level wake-up, waking up hardware resources via the large core, saving the data generated by the fourth sub-core to the hardware resources, controlling the fourth sub-core to continue receiving and processing the wake-up data, and determining whether to enter a second-level wake-up via the fourth sub-core processing the wake-up data; if the determination is successful and a second-level wake-up is entered, sending a command to enter normal mode to the fourth sub-core via the large core, simultaneously waking up or starting the fifth sub-core to enter normal mode, and then the large core enters normal mode.

[0075] Specifically, once certain conditions are met (voice recognition, image recognition, fingerprint recognition, external button wake-up, etc., meaning the peripheral data received by the fourth sub-core is wake-up data, which can be voice data, image data, fingerprint data, button data, etc.), a single production data small core will wake up the large core, the large core will then wake up the production data small core, and finally the large core will wake up (start) the other small cores into normal mode. After starting, in normal mode, at least one small core is configured to acquire data, and this small core supports low-power mode. The other small cores can be configured to acquire data, or they can acquire data from other small cores for serial processing, or they can independently process data from the large core in parallel. The large core also enters normal mode. The specific control flow for multi-core heterogeneous chip wake-up is as follows: 1. After the wake-up conditions are met, the small core (fourth sub-core) that produces data first notifies the large core, and the large core will exit the low-power mode and control the small core that produces data to exit the low-power mode.

[0076] 2. Entering Level 1 Wake-up. Depending on the application scenario, the main core will wake up certain hardware resources, such as storage-related resources, to obtain data produced by the fourth sub-core and save it to the storage medium. Then, it will control the fourth sub-core to continue processing peripheral data. After processing peripheral data (voice data, image data, index data, key press data, etc.), the fourth sub-core will determine whether to enter Level 2 wake-up.

[0077] 3. If the judgment is successful, it will enter the second-level wake-up. The large core will first send a command to enter normal mode to the fourth sub-core, and at the same time wake up (or start) other small cores (the fifth sub-core) to enter normal mode. Finally, the large core enters normal mode. By waking up in stages, the full wake-up of the multi-core heterogeneous chip is avoided when it is not necessary, which would cause unnecessary power consumption and thus extend the battery life of the multi-core heterogeneous chip.

[0078] The data flow is explained in two scenarios.

[0079] 1. In normal mode and Figure 4 The same applies, so I won't go into details.

[0080] 2. In low-power mode, refer to Figure 8 Only one small core continues to generate data, which is stored in SRAM and not transferred to other cores. When external conditions are met, a first-level wake-up occurs, where the large core retrieves the data generated by the small core and saves it to the storage medium. If a second-level wake-up does not occur, the large core will enter low-power mode or hibernate. In this mode, data is transferred from the small core's SRAM to the storage medium.

[0081] Another scenario involves the small core generating data without saving it, and then directly processing the data to determine wake-up. This is suitable for scenarios that require processing large amounts of data, such as facial recognition, where image data is large and takes up considerable space.

[0082] On the other hand, refer to Figure 9 This embodiment discloses a data interaction device for a multi-core heterogeneous chip, including a first module, a second module and a third module.

[0083] The first module is used to send control commands to the small core through the large core, so that the small core can perform initialization configuration; The second module is used to acquire peripheral data and / or inter-core data through the initialized small core, wherein the inter-core data represents data generated by the large core or the small core; The third module is used to process the peripheral data and / or the inter-core data through the small core to obtain target data, and to send the target data to the large core or the small core; wherein the target data is obtained by serial processing of data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of data generated by the large core through multiple small cores.

[0084] For example, with the cooperation of the first module, the second module and the third module in the device, the device of the embodiment can implement any of the aforementioned data interaction methods for multi-core heterogeneous chips.

[0085] On the other hand, refer to Figure 10 This embodiment provides an electronic device, including: at least one processor 810; at least one memory 820 for storing at least one program; when the at least one program is executed by the at least one processor 810, the at least one processor implements the above-described data interaction method for multi-core heterogeneous chips. The processor 810 may also be referred to as a CPU (Central Processing Unit). The processor 810 may be an integrated circuit chip with signal processing capabilities. The processor 810 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor may be a microprocessor, or it may be any conventional processor. The memory 820 may include various components (e.g., machine-readable media), including but not limited to random access memory components, read-only components, and any combination thereof. The memory 820 may also include (e.g., instructions (e.g., software) stored in one or more machine-readable media); these instructions implement the method of this embodiment of the invention.

[0086] The electronic device has the function of carrying and running the business data processing software system provided in the embodiments of the present invention, such as a personal computer (PC), mobile phone, smartphone, personal digital assistant (PDA), wearable device, handheld computer (PPC), tablet computer, etc.

[0087] On the other hand, refer to Figure 11 This embodiment provides a storage medium storing program instructions 910. When the program instructions 910 are executed by the processor, they implement the data interaction method of the multi-core heterogeneous chip described above.

[0088] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the device, can be implemented as software, firmware, hardware, and suitable combinations thereof.

[0089] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as processors, such as software executed by a central processing unit, digital signal processor, or microprocessor, or as hardware, or as integrated circuits, such as application-specific integrated circuits. Such software may be distributed on a computer-readable medium (hereinafter referred to as storage medium), which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer-readable medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0090] The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but this does not limit the scope of the invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of the present invention should be within the scope of the present invention.

Claims

1. A data interaction method for multi-core heterogeneous chips, characterized in that, An application is made in a multi-core heterogeneous chip system, wherein the multi-core heterogeneous chip system includes a large core and multiple small cores, the large core and the multiple small cores are connected via a bus, and the data interaction method of the multi-core heterogeneous chip includes: The large core sends control commands to the small core to enable the small core to perform initialization configuration. Peripheral data and / or inter-core data are acquired through the initialized small core, wherein the inter-core data represents data generated by the large core or the small core; The target data is obtained by processing the peripheral data and / or the inter-core data through the small core, and then the target data is sent to the large core or the small core; wherein, the target data is obtained by serial processing of the data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of the data generated by the large core through multiple small cores.

2. The data interaction method for multi-core heterogeneous chips according to claim 1, characterized in that, The step of sending control commands from the large core to the small core to enable the small core to perform initialization configuration includes: An initialization thread is created during startup of the small core, and the number of initialization threads is configured according to the number of processes on the large core. The large core calls the cross-core control interface to establish control channels with the multiple small cores respectively; The large core calls the initialization configuration, and the large core sends an initialization control command to the small core through the control channel, while calling the cross-core data transmission interface to establish a data transmission channel. The initialization control command is sent to multiple small cores through the control channel via the multi-process call of the large core, so that the multiple small cores can perform initialization configuration; The initialization thread creates a command processing thread between the small core and the large core. The control command is sent to the small core via the command processing thread to enable the small core to perform initialization configuration. Data transmission is initiated by the large core. After receiving the start transmission command through the command processing thread, the small core creates a data processing thread and a data transmission thread.

3. The data interaction method for multi-core heterogeneous chips according to claim 2, characterized in that, The step of creating a command processing thread between the small core and the large core through the initialization thread includes: The initialization thread calls the first cross-core control interface of the small core and waits for the large core to call the second cross-core control interface to create a control channel. The large core calls a second cross-core control interface that is the same as the first cross-core control interface, and the second cross-core control interface is located at the large core end; After the first cross-core control interface and the second cross-core control interface are successfully invoked, the initialization thread will create the command processing thread and then clear the initialization thread itself.

4. The data interaction method for multi-core heterogeneous chips according to claim 2, characterized in that, Establishing the data transmission channel between the large core and the small core includes: After the small core receives the initialization command through the command processing thread, it calls the first cross-core data interface of the small core and waits for the large core to call the second cross-core data interface to create a data transmission channel. The large core calls a second cross-core data interface that is the same as the first cross-core data interface, and the second cross-core data interface is located at the large core. After the first cross-core data interface and the second cross-core data interface are successfully invoked, the large core starts cross-core data transmission; The data transmission channels are divided into two types according to requirements: big core to small core data transmission or small core to big core data transmission. The number of data transmission channels is configured by the number of large core multiprocesses, and the data transmission channels can independently and in parallel transmit different types of data.

5. The data interaction method for multi-core heterogeneous chips according to claim 2, characterized in that, After receiving the start transmission command through the command processing thread, the small core creates the data processing thread and the data transmission thread, including: The data processing thread processes the peripheral data and / or the inter-core data in real time. The data transmission thread transmits the data processed by the data processing thread to the small core or the large core. After receiving the start transmission command through the command processing thread, the small core, after creating the data transmission thread and the data transmission thread, sends a feedback command to the large core through the cross-core command interface to indicate that the small core is ready and the data transmission function of the large core is enabled.

6. The data interaction method for multi-core heterogeneous chips according to claim 2, characterized in that, After initializing and configuring the small core, the method further includes: Establish a cross-core transport component among the multiple small cores; Data is transmitted sequentially between the multiple small cores via the cross-core transmission component, so that the multiple small cores process the data serially.

7. The data interaction method for multi-core heterogeneous chips according to claim 1, characterized in that, The step of acquiring peripheral data and / or inter-core data through the initialized small core includes: The peripheral data is obtained through the first sub-core; The first data of the first sub-core is obtained through the second sub-core. The first data belongs to the inter-core data. The first data is obtained by processing the peripheral data through the first sub-core. The second data is obtained by processing the first data of the first sub-core through the second sub-core, and the second data belongs to the inter-core data; The third data of the large core is obtained through the third sub-core. The third data belongs to the inter-core data. The first sub-core, the second sub-core, and the third sub-core represent different types of small cores.

8. The data interaction method for multi-core heterogeneous chips according to claim 1, characterized in that, When the multi-core heterogeneous chip is in sleep mode, the method further includes: The large core sends a low-power command to the fourth sub-core to cause the fourth sub-core to enter a low-power mode. The fourth sub-core represents the small core used to acquire peripheral data during the hibernation period of the multi-core heterogeneous chip. The large core sends a hibernation command or a shutdown command to the fifth sub-core, causing the fifth sub-core to enter hibernation or shutdown. The fifth sub-core represents the small core that has entered hibernation or shutdown. After the fifth sub-core enters hibernation or is shut down, the large core enters low-power mode or hibernation.

9. The data interaction method for multi-core heterogeneous chips according to claim 8, characterized in that, In the case of waking up the multi-core heterogeneous chip, the method further includes: When the peripheral data received by the fourth sub-core is wake-up data, the fourth sub-core wakes up the large core to exit sleep or exit low-power mode, and the large core wakes up the fourth sub-core to exit low-power mode. In the case where the wake-up data represents a first-level wake-up, the large core wakes up the hardware resources, saves the data generated by the fourth sub-core to the hardware resources, controls the fourth sub-core to continue receiving and processing the wake-up data, and determines whether to enter a second-level wake-up by processing the wake-up data through the fourth sub-core. After successful judgment, in the case of entering the second-level wake-up, the large core sends a command to the fourth sub-core to enter normal mode, and at the same time wakes up or starts the fifth sub-core to enter normal mode, and then the large core enters normal mode.

10. A data interaction device for a multi-core heterogeneous chip, characterized in that, The data interaction method for multi-core heterogeneous chips according to any one of claims 1 to 9, wherein the data interaction device for multi-core heterogeneous chips comprises: The first module is used to send control commands to the small core through the large core, so that the small core can perform initialization configuration; The second module is used to acquire peripheral data and / or inter-core data through the initialized small core, wherein the inter-core data represents data generated by the large core or the small core; The third module is used to process the peripheral data and / or the inter-core data through the small core to obtain target data, and to send the target data to the large core or the small core; wherein the target data is obtained by serial processing of data generated by the small core through multiple small cores, and the target data is obtained by serial or parallel processing of data generated by the large core through multiple small cores.

11. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the data interaction method for multi-core heterogeneous chips as described in any one of claims 1 to 9.

12. A computer-readable storage medium storing program instructions that, when executed by a processor, implement the data interaction method for a multi-core heterogeneous chip as described in any one of claims 1 to 9.

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