Data processing device and data processing method for rocket measurement
The data processing device, designed through a master-slave control unit architecture and processor logic circuit collaboration, solves the development difficulty and maintenance flexibility issues of FPGA solutions, achieving high performance and flexible expansion of the rocket measurement system to adapt to diverse mission requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING LANDSPACETECH CO LTD
- Filing Date
- 2026-04-03
- Publication Date
- 2026-06-30
Smart Images
Figure CN121979835B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of rocket measurement technology, and in particular relates to a data processing device and data processing method for rocket measurement. Background Technology
[0002] In rocket measurement systems, the data synthesizer is the core unit and also the rocket's data center, enabling real-time reception, synthesis, and transmission of various types of data, including rocket measurement data and bus data. Due to its high real-time and strong parallel requirements, customized data synthesis solutions based on FPGA (programmable logic device) devices have long been widely adopted.
[0003] As rockets continue to evolve towards greater carrying capacity, higher performance, and reusability, the number of measurement devices in measurement systems has increased significantly, the demand for telemetry data bandwidth has surged, online upgrade capabilities have become a necessity, and new high-speed communication technologies are gradually being introduced. Against this backdrop, existing FPGA-based customized hardware solutions, due to their high development difficulty, long development cycles, and insufficient flexibility in later maintenance and upgrades, are increasingly unable to meet the future development requirements of measurement systems for high performance, high flexibility, and reusability. Summary of the Invention
[0004] To address the problems existing in the prior art, the present invention provides a data processing device and data processing method for rocket measurement.
[0005] In a first aspect, the present disclosure provides a data processing device for rocket measurement, including a main control unit and a slave control unit that can operate independently and have the same structure, and the main control unit and the slave control unit are connected through an internal bus.
[0006] The main control unit is used to receive data from the first part of external devices and perform data processing, transmission and task scheduling.
[0007] The slave control unit is used to receive data from the second part of external devices, parse it, and then send it to the master control unit through the internal bus.
[0008] Both the main control unit and the slave control unit include a data processing circuit, an external interface circuit, a power supply circuit, a debugging circuit, and a storage circuit; wherein, the data processing circuit includes a logic chip integrating a processor system and programmable logic circuits, as well as a memory;
[0009] The data processing circuit further includes a data processing unit, which includes a data parsing and caching module and a framing module. The data parsing and caching module is used to parse the received data and store the parsed data in the data buffer area to be framed.
[0010] The framing module, which operates on a programmable logic circuit, is used to extract data from the data buffer to be framed according to a preset waveguide table and frame it to form a PCM data stream.
[0011] Optionally, the external interface circuit is used to realize electrical signal conversion between external devices; the external interface circuit includes at least one of Powerlink interface circuit, synchronous / asynchronous serial port interface circuit, and discrete quantity acquisition circuit.
[0012] Optionally, the power supply circuit is a tertiary power supply circuit; the debugging circuit includes a gigabit Ethernet interface circuit; and the storage circuit includes a FLASH circuit and an eMMC FLASH circuit.
[0013] Optionally, the data processing unit further includes:
[0014] The data receiving module, which operates on a programmable logic circuit, is used to receive external data converted by the external interface circuit in parallel.
[0015] The data transmission module is used to send or store the framed PCM data stream.
[0016] Optionally, the data parsing and caching module is configured as follows:
[0017] For discrete data or communication data with protocol complexity lower than the set value, the data is parsed by the programmable logic circuit and stored in the frame buffer area of the programmable logic circuit.
[0018] For communication data with a protocol complexity of not less than a set value, the processor system reads the data received by the programmable logic circuit and parses it. The parsed data is stored in the data buffer area of the memory, and then read by the programmable logic circuit and stored in the frame-to-be-framed data buffer area of the programmable logic circuit.
[0019] Optionally, the data processing device supports online program upgrades. When the main control unit receives a program update instruction and a new program data packet, it performs the following operations:
[0020] If the update target is the main control unit, the received update data is written into the FLASH circuit of the main control unit to complete the hardening;
[0021] If the update target is the slave control unit, the update data is forwarded to the slave control unit through the internal bus, and the update data is written into the FLASH circuit of the slave control unit to complete the hardening.
[0022] Optionally, the online program upgrade includes:
[0023] After power-on, the main control unit and the slave control unit run the processor system monitoring program and the logic program of the programmable logic circuit, and wait for the handshake command from the ground equipment.
[0024] If the main control unit does not receive an update handshake command within the set time, it will load and execute the data integration program normally; if it receives an update handshake command and target unit information, the main control unit will receive the new data in packets and cache it.
[0025] Secondly, embodiments of this disclosure also provide a data processing method based on the data processing apparatus for rocket measurement described in any one of the first aspects, comprising:
[0026] It receives data from multiple external devices through an external interface circuit;
[0027] In the data processing circuits of the main control unit and the slave control unit, the received data is parsed and buffered in parallel;
[0028] The parsed data is sent from the control unit to the main control unit via the internal bus;
[0029] In the main control unit, all data to be framed are processed to form a PCM data stream;
[0030] Send or store the framed PCM data stream.
[0031] Optionally, the step of performing frame encoding processing on all data to be framed to form a PCM data stream includes:
[0032] According to the pre-loaded waveguide table, the data of each data buffer to be framed is extracted and framed to form the required PCM data streams.
[0033] Optionally, sending or storing the framed PCM data stream includes:
[0034] For PCM data streams that need to be stored, the programmable logic circuit reads the corresponding PCM data stream from the buffer and writes it into the EMMC FLASH chip for persistent storage.
[0035] This invention provides a data processing device and method for rocket measurement. The data processing device for rocket measurement has a hardware architecture consisting of a unified, independently operating main control unit and slave control units interconnected via an internal bus. This data processing device can flexibly configure the number of control units according to the actual task's data processing volume, interface types, and quantity requirements, achieving smooth expansion of processing performance and interface capabilities to respond to diverse task demands. Each control unit is based on a logic chip integrating a processor system and programmable logic circuits. Through deep hardware and software collaboration, the processor system and programmable logic circuits significantly reduce the development difficulty and cycle time of traditional FPGA solutions while ensuring high system performance. This achieves the goal of flexibly responding to task requirements and reducing development difficulty and cycle time.
[0036] The data processing device of this application can upgrade the program of the control unit online via an internal bus. The main control unit can receive and manage the firmware update process of itself or from the control unit, realizing remote secure hardening of the program. This ensures that the system has the ability to quickly iterate functions and repair faults in scenarios such as rocket reuse, greatly improving the maintainability and mission adaptability of the system. Attached Figure Description
[0037] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.
[0038] Figure 1a A schematic block diagram of a data processing apparatus for rocket measurement provided in an embodiment of this disclosure;
[0039] Figure 1b A schematic block diagram of the control unit provided for embodiments of this disclosure;
[0040] Figure 1c A schematic block diagram of the main control unit provided in the embodiments of this disclosure;
[0041] Figure 1d A schematic diagram illustrating the data input and output principles provided in the embodiments of this disclosure;
[0042] Figure 2a A block diagram illustrating the principle of master-slave data processing provided in this embodiment of the disclosure;
[0043] Figure 2b A schematic block diagram of the data processing unit provided in the embodiments of this disclosure;
[0044] Figure 2c A schematic block diagram of a data processing unit provided for embodiments of this disclosure;
[0045] Figure 3 A flowchart for program upgrade provided in this embodiment of the disclosure;
[0046] Figure 4 A flowchart illustrating the program upgrade process provided in this embodiment of the disclosure. Detailed Implementation
[0047] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0048] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0049] It should be noted that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice method. Furthermore, this device and / or practice method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.
[0050] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0051] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0052] This embodiment discloses a data processing device for rocket measurement, including a main control unit and a slave control unit that can operate independently and have the same structure. The main control unit and the slave control unit are connected through an internal bus.
[0053] The main control unit is used to receive data from the first part of external devices and perform data processing, transmission and task scheduling.
[0054] The slave control unit is used to receive data from the second part of external devices, parse it, and then send it to the master control unit through the internal bus.
[0055] Both the main control unit and the slave control unit include a data processing circuit, an external interface circuit, a power supply circuit, a debugging circuit, and a storage circuit; wherein, the data processing circuit includes a logic chip integrating a processor system and programmable logic circuits, as well as a memory;
[0056] The data processing circuit further includes a data processing unit, which includes a data parsing and caching module and a framing module. The data parsing and caching module is used to parse the received data and store the parsed data in the data buffer area to be framed.
[0057] The framing module, which operates on a programmable logic circuit, is used to extract data from the data buffer to be framed according to a preset waveguide table and frame it to form a PCM data stream.
[0058] The device in this embodiment has complete real-time data reception, integration, and transmission functions: it receives data from external devices such as camera devices, acquisition and editing equipment, and flight controllers in real time, performs integrated processing, and sends the processed data to terminal devices such as memory, telemetry equipment, and ground control units. Figures 1a to 1d As shown.
[0059] This device has significant advantages in both hardware scalability and data processing flexibility.
[0060] (1) Hardware level:
[0061] The hardware consists of several independently operable control units, and the number of control units can be flexibly configured according to the data volume and processing performance requirements of the specific task.
[0062] When multiple control units are configured, the units interact with each other through an internal bus and adopt a master-slave collaborative working mode: one unit acts as the master control unit, which is responsible for receiving, integrating, sending and scheduling data; the other units act as slave control units, which receive some data from external input devices, parse it and send it to the master control unit in real time for data framing processing.
[0063] Each control unit adopts a unified hardware composition, including power supply circuits, debugging circuits, storage circuits, data processing circuits, and external interface circuits. The power supply, debugging, storage, and data processing circuits of each control unit are designed identically; only the external interface circuits are configured and expanded in terms of type and quantity depending on the external devices to be connected. This design ensures standardization of the core hardware while also taking into account the flexible adaptability of the external interfaces.
[0064] External interface circuits include PowerLink interface circuits, synchronous / asynchronous serial port interface circuits, and discrete quantity acquisition circuits, which serve as electrical conversion interfaces for information exchange with external devices. These external interface circuits can convert signals from external data sources such as cameras, acquisition and editing equipment, and flight controllers into internally recognizable and processable digital signals; and convert data synthesized by data processing circuits into electrical forms that meet the requirements of terminal equipment such as memory, telemetry equipment, and ground units.
[0065] Power supply circuit: A three-stage power supply circuit can be used to provide power to the control unit;
[0066] Debugging circuit: A gigabit Ethernet interface circuit can be used to send the operating status of the control unit to the ground unit in real time, monitor the operating status of the control unit, and improve efficiency, especially during debugging and troubleshooting.
[0067] Storage circuitry: including FLASH circuitry and EMMC FLASH circuitry, used to store software programs, FPGA programs, Bode tables, and on-board data, etc.
[0068] Data processing circuitry includes logic chips and DDR circuitry. The logic chips can utilize ZYNQ circuits. The data processing circuitry is used for data reception, processing, and transmission. The ZYNQ circuit is based on the ZYNQ chip, which integrates a processor system (PS) and programmable logic (PL) into a single-chip system. The ZYNQ PL portion utilizes FPGA (programmable logic array) resources, with each function implemented using VHDL (hardware description language), providing parallel processing capabilities. The ZYNQ PS portion is based on a dual-core ARM Cortex-A9, providing a complete computing platform for software operation. Based on this platform, users can develop applications using C / C++ and leverage mature operating systems and software stacks to quickly implement complex control, computation, and communication tasks.
[0069] (2) Data processing level:
[0070] The device's data processing is achieved collaboratively by multiple data processing units, operating in a master-slave collaborative mode. This allows for flexible adjustment of the data processing scale simply by increasing or decreasing the number of nodes (i.e., control units) on the internal bus, without altering the core processing framework. Each data processing unit is implemented using a single control unit hardware.
[0071] The master-slave data processing block diagram of this embodiment is as follows: Figures 2a to 2c As shown, each data processing unit includes a data buffer running in DDR, data reception and parsing running on the ZYNQ PS end, reception logic running on the ZYNQ PL end, a data buffer to be framed, internal bus transceiver logic, and parsing logic. The main data processing unit also includes software programs for controlling transmission on the ZYNQ PS end, transmission logic running on the ZYNQ PL end, an output data buffer, a waveguide table, framing logic, and a waveguide table.
[0072] Data cache in DDR: This data cache is a shared cache area between the ZYNQ PS end and the ZYNQ PL end, providing a low-latency, high-bandwidth data path for collaboration between the ZYNQ PS end and the ZYNQ PL end;
[0073] Data reception: Implemented at the ZYNQ PL terminal. All external input data are converted by their respective interface circuits and then simultaneously input to the PL terminal, where they are received in parallel by the corresponding data receiving logic.
[0074] Data parsing and caching: After receiving common communication data and discrete quantities, the PL end parses the data and stores it in the data buffer area to be framed. After receiving complex and new communication data, the PL end writes the data to the DDR data buffer area via the high-speed bus AXI_HP. The PS end directly reads the data and parses it. The parsed data is stored in the DDR data buffer area. The PL end reads the data via the high-speed bus AXI_HP and places it in the data buffer area to be framed.
[0075] Framing and buffering: Implemented on the ZYNQ PL end. Based on the waveguide table, the data of each data buffer to be framed is extracted and framed to form the required multiple PCM data streams, which are stored in their respective data buffers.
[0076] Packetized Sending: For common and simple communications, the ZYNQ PL end implements the packetized sending logic according to the communication protocol requirements; for complex and new communications, the PS end and PL end cooperate, with the PS end packaging the data and the PL end sending the packaged data.
[0077] By leveraging the collaborative design of FPGA (running on the PL side of ZYNQ) and software (running on the PS side of ZYNQ), the system's development flexibility and maintainability are significantly improved while maintaining high-speed parallel processing capabilities. This effectively reduces the overall design complexity and development cycle, supporting rapid adaptation and continuous iteration of system functions. Flexible expansion is achieved through a master-slave architecture, and the efficient collaboration between FPGA hardware logic and processor software enables comprehensive processing and scheduling of multi-channel data.
[0078] This device supports online product upgrades, allowing for program upgrades without removing the product from the rocket when it is reused. For example... Figure 3 As shown, when a product requires a program upgrade, the ground equipment sends multiple packets of the new program to the data integration product via the on-board bus. The master control unit first receives all packets and caches them in the master DDR. After all packets are received, if the target is the master control unit itself, it immediately reads the new program from the DDR and writes it to the master FLASH, completing the self-hardening process. If the target is a slave control unit, the master control unit forwards the program in the DDR to the corresponding slave control DDR via the internal bus. After the transmission is complete, the program is written from the DDR to the slave FLASH, thus hardening the slave control program and ending the upgrade process.
[0079] In a specific application scenario
[0080] The data processing flow is as follows:
[0081] (1) Product power-on and initialization:
[0082] After the product is powered on, the system starts running. First, the PS-side software program and PL-side logic program are loaded. Then, the PS-side software program starts executing, reading the waveguide table from the FLASH memory and writing it into the fixed address space of the PL-side. Finally, the PL-side program starts running and completes the initialization.
[0083] (2) Data reception:
[0084] Data reception is handled by a hardware interface circuit. Data from external devices is converted by the interface circuit and then transmitted to the PL terminal for reception. When there are many external devices, the product can expand its interface capabilities and data processing capabilities by adding multiple control units.
[0085] (3) Data analysis:
[0086] Data parsing employs a categorized processing approach based on data source and protocol complexity. For discrete data, the PL end performs only simple processing such as filtering upon receipt, then directly stores it in the data buffer to be framed, awaiting framing. For common communications with simple protocols, protocol parsing is performed directly at the PL end, extracting useful data and placing it in the PL end's data buffer. For newer or more complex communications, the PS end reads the received data via the AXI_GP bus, performs protocol parsing at the PS end, extracts useful data, and places it in the DDR data buffer. Subsequently, the PL end reads the data from the DDR data buffer via the AXI_HP bus and places it in the PL end's data buffer to be framed, awaiting framing. If the product has multiple control units, after data parsing is completed at the control unit, the parsed data is sent via the internal bus to the PL end's data buffer to be framed at the main control unit, also awaiting framing.
[0087] (4) Data framing:
[0088] The product extracts data from each framed data buffer according to a pre-loaded waveguide table and performs frame processing to form the required PCM data streams. These data streams are usually stored in the data buffer at the PL end, but for data that needs to be sent to the EMMCFLASH chip for storage, its corresponding PCM data stream is written to the DDR data buffer address via the AXI_HP bus to prepare for subsequent storage.
[0089] (5) Data Packaging:
[0090] Besides the PCM data stream sent to the EMMC FLASH chip, the remaining framed data needs to be packaged according to their respective communication protocols. The product encapsulates the PCM data stream in the framed data buffer according to the protocol, completing the data packaging process.
[0091] (6) Data transmission:
[0092] Data transmission is divided into two flow directions: For PCM data streams that need to be stored, the PS end reads them from the DDR data cache and writes them into the EMMC FLASH chip for persistent storage; for data that needs to be sent to external devices, the packaged PCM data stream is sent to the corresponding external device through the corresponding interface circuit to complete the entire data processing flow.
[0093] Program updates such as Figure 4 As shown:
[0094] (1) Power-on start:
[0095] After the product is powered on, all control modules run the PS-side monitoring program and PL-side logic program, waiting for the handshake command from the ground equipment.
[0096] (2) Update judgment and reception:
[0097] If the main control unit does not receive an update handshake instruction within 1 second, it will load and execute the data synthesis program normally; if it receives an update instruction and target unit information, the main control unit will receive the new program in packets and cache it in DDR.
[0098] (3) Program solidification:
[0099] If the main control unit is updated: the new program in DDR is written into FLASH to complete the hardening process;
[0100] If updating the slave control unit: the master control unit forwards the new program to the target slave control unit through the internal bus and caches it in its DDR. After all forwarding is completed, it is written to the slave control unit's FLASH.
[0101] (4) Power off:
[0102] The product is powered off, and the update process is complete.
[0103] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0104] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.
[0105] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.
[0106] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.
[0107] Various changes, substitutions, and modifications can be made to the techniques described herein without departing from the teachings defined in this embodiment. Furthermore, the scope of this embodiment is not limited to the specific aspects of the processes, machines, manufacturing processes, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufacturing processes, events, means, methods, or actions that perform substantially the same functions or achieve substantially the same results as the corresponding aspects described herein can be utilized. Therefore, this embodiment includes such processes, machines, manufacturing processes, events, means, methods, or actions within its scope.
[0108] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.
[0109] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.
Claims
1. A data processing device for rocket measurement, characterized in that, It includes a main control unit and a slave control unit that can operate independently and have the same structure, and the main control unit and the slave control unit are connected through an internal bus; The main control unit is used to receive data from the first part of external devices and perform data processing, transmission and task scheduling. The slave control unit is used to receive data from the second part of external devices, parse it, and then send it to the main control unit through the internal bus. Both the main control unit and the slave control unit include a data processing circuit, an external interface circuit, a power supply circuit, a debugging circuit, and a storage circuit. The data processing circuit includes a logic chip integrating a processor system and a programmable logic circuit, as well as a memory. The data cache area of the memory is a shared cache area for the logic chip of the processor system and the programmable logic circuit, providing a low-latency, high-bandwidth data path for the collaboration between the logic chip of the processor system and the programmable logic circuit. The data processing circuit further includes a data processing unit, which includes a data parsing and caching module and a framing module. The data parsing and caching module is used to parse the received data and store the parsed data in the data buffer area to be framed. The framing module, which runs on a programmable logic circuit, is used to extract data from the data buffer to be framed according to a preset waveguide table and frame it to form a PCM data stream. The data parsing and caching module is configured as follows: For discrete data or communication data with protocol complexity lower than the set value, the data is parsed by the programmable logic circuit and stored in the frame buffer area of the programmable logic circuit. For communication data with a protocol complexity of not less than a set value, the processor system reads the data received by the programmable logic circuit and parses it. The parsed data is stored in the data buffer area of the memory, and then read by the programmable logic circuit and stored in the frame-to-be-framed data buffer area of the programmable logic circuit.
2. The data processing device for rocket measurement according to claim 1, characterized in that, The external interface circuit is used to realize the electrical signal conversion between external devices; the external interface circuit includes at least one of the following: Powerlink interface circuit, synchronous / asynchronous serial port interface circuit, and discrete quantity acquisition circuit.
3. The data processing device for rocket measurement according to claim 1, characterized in that, The power supply circuit is a tertiary power supply circuit; the debugging circuit includes a gigabit Ethernet interface circuit; the storage circuit includes a FLASH circuit and an EMMC FLASH circuit.
4. The data processing device for rocket measurement according to claim 1, characterized in that, The data processing unit further includes: The data receiving module, which operates on a programmable logic circuit, is used to receive external data converted by the external interface circuit in parallel. The data transmission module is used to send or store the framed PCM data stream.
5. The data processing device for rocket measurement according to claim 4, characterized in that, The data processing device supports online program upgrades. When the main control unit receives a program update instruction and a new program data packet, it performs the following operations: If the update target is the main control unit, the received update data is written into the FLASH circuit of the main control unit to complete the hardening; If the update target is the slave control unit, the update data is forwarded to the slave control unit through the internal bus, and the update data is written into the FLASH circuit of the slave control unit to complete the hardening.
6. The data processing apparatus for rocket measurement according to claim 5, characterized in that, The online program upgrade includes: After power-on, the main control unit and the slave control unit run the processor system monitoring program and the logic program of the programmable logic circuit, and wait for the handshake command from the ground equipment. If the main control unit does not receive an update handshake command within the set time, it will load and execute the data integration program normally; if it receives an update handshake command and target unit information, the main control unit will receive the new data in packets and cache it.
7. A data processing method based on the data processing apparatus for rocket measurement according to any one of claims 1 to 6, characterized in that, include: It receives data from multiple external devices through an external interface circuit; In the data processing circuits of the main control unit and the slave control unit, the received data is parsed and buffered in parallel; The parsed data is sent from the control unit to the main control unit via the internal bus; In the main control unit, all data to be framed are processed to form a PCM data stream; Send or store the framed PCM data stream.
8. The data processing method according to claim 7, characterized in that, The step of performing frame encoding processing on all data to be encoded to form a PCM data stream includes: According to the pre-loaded waveguide table, the data of each data buffer to be framed is extracted and framed to form the required PCM data streams.
9. The data processing method according to claim 7, characterized in that, The step of sending or storing the framed PCM data stream includes: For PCM data streams that need to be stored, the programmable logic circuit reads the corresponding PCM data stream from the buffer and writes it into the EMMC FLASH chip for persistent storage.