Production work order generation method and device, computer equipment and storage medium

Abstract

The invention provides a production work order generation method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining the design data of a to-be-manufactured chip, carrying out the semantic analysis of a design file and technological parameters through a pre-constructed semiconductor manufacturing knowledge graph, and obtaining the design data of the to-be-manufactured chip; the method comprises the following steps: obtaining attribute values of a plurality of chip entities of a to-be-manufactured chip and an association relationship among the plurality of chip entities, performing compatibility verification on the attribute values of the plurality of chip entities of the to-be-manufactured chip according to equipment information of chip process equipment, and if the compatibility verification is passed, sending the to-be-manufactured chip to the chip processing equipment; and if yes, generating a chip manufacturing file of the to-be-manufactured chip according to the attribute values of the plurality of chip entities and the association relationship of the plurality of chip entities, and generating a production work order of the to-be-manufactured chip according to the chip manufacturing file and the order type. According to the scheme, manual work is liberated from repeated and high-risk labor through semantic analysis and intelligent verification, automation and intelligence of the business process are achieved, and tape-out failure is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically, to a method, apparatus, computer equipment, and storage medium for generating production work orders. Background Technology

[0002] With the continuous development of semiconductor manufacturing technology, chip manufacturing has formed a specialized division of labor between chip designers and wafer foundries. In this model, chip designers are responsible for chip architecture and circuit design, while wafer foundries undertake the actual manufacturing tasks.

[0003] In related technologies, before chip manufacturing begins, wafer manufacturers typically receive data such as orders and process documents from chip designers, and generate production work orders by manually analyzing, verifying, and entering them into the manufacturing execution system.

[0004] However, the above methods are inefficient and error-prone, resulting in low levels of automation in business processes and a high risk of chip fabrication failure. Summary of the Invention

[0005] In view of this, embodiments of this application provide a production work order generation method, apparatus, computer equipment, and storage medium to solve the problems of low efficiency and error-proneness in existing systems, resulting in low automation of business processes and easy chip tape-out failures.

[0006] In a first aspect, embodiments of this application provide a method for generating production work orders, including: Obtain the design data of the chip to be manufactured, including: design files, process parameters, and the order type corresponding to the chip to be manufactured; A pre-constructed semiconductor manufacturing knowledge graph is used to perform semantic parsing on the design documents and process parameters to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the association relationships between the multiple chip entities. The semiconductor manufacturing knowledge graph includes: multiple chip entities and the association relationships between the multiple chip entities. Based on the equipment information of the chip manufacturing equipment, the attribute values ​​of multiple chip entities of the chip to be manufactured are verified for compatibility. If the compatibility check passes, a chip manufacturing file for the chip to be manufactured is generated based on the attribute values ​​of the multiple chip entities and the association between the multiple chip entities. Based on the chip manufacturing documents and the order type, a production work order for the chip to be manufactured is generated, so as to manufacture the chip to be manufactured using the chip process equipment.

[0007] In an optional implementation, the plurality of chip entities include: a process node entity, an order quantity entity, an equipment requirement entity, and a process requirement entity; the step of performing compatibility verification on the attribute values ​​of the plurality of chip entities of the chip to be manufactured based on the equipment information of the chip process equipment includes: Based on the process baseline information, capacity information, equipment type, and process configuration information of the chip manufacturing equipment, compatibility checks are performed on the attribute values ​​of the process node entity, the order quantity entity, the equipment demand entity, and the process demand entity, respectively.

[0008] In an optional implementation, the plurality of chip entities further include: a process path state entity of the chip to be manufactured; the method further includes: Based on the attribute values ​​of the process path state entity, the process path state of the chip to be manufactured is verified. If the attribute value of the process path status entity indicates that the process path status of the chip to be manufactured is a preset authorized status, then the status verification is determined to be successful. If the compatibility verification passes, then based on the attribute values ​​of the multiple chip entities and their associations, a chip manufacturing file for the chip to be manufactured is generated, including: If the compatibility check and the status check pass, the chip manufacturing file is generated based on the attribute values ​​of the multiple chip entities and the association relationship between the multiple chip entities.

[0009] In an optional implementation, generating the chip manufacturing file based on the attribute values ​​of the plurality of chip entities and the association relationships among the plurality of chip entities includes: The attribute values ​​of the multiple chip entities are routed to each chip manufacturing review node to perform secondary verification of the attribute values ​​of the multiple chip entities based on the chip process equipment. If a review pass message is received from each of the chip manufacturing review nodes, the chip manufacturing file is generated based on the attribute values ​​of the multiple chip entities and the association relationships between the multiple chip entities.

[0010] In an optional implementation, generating a production work order for the chip to be manufactured based on the chip manufacturing file and the order type includes: Entity name recognition is performed on the chip manufacturing file to obtain preset sensitive entities and attribute values ​​of the preset sensitive entities in the chip manufacturing file; The attribute values ​​of the preset sensitive entities are desensitized to obtain the desensitization parameter range of the preset sensitive entities; The chip manufacturing file is updated according to the preset sensitive entity desensitization parameter range, and the production work order is generated according to the updated chip manufacturing file and the order type.

[0011] In an optional implementation, the method further includes: The design data is hashed to obtain the target digital fingerprint; Using a pre-set smart contract, verification data corresponding to the design data is obtained from a pre-set consortium blockchain network. The verification data is written by the chip designer to the pre-set consortium blockchain network and includes verification digital fingerprints, timestamps, information of the chip designer, and information of the chip manufacturer. Based on the verification data and the target digital fingerprint, the design data is subjected to consistency verification.

[0012] In an optional implementation, generating a production work order for the chip to be manufactured based on the chip manufacturing file and the order type includes: If the order type is a new customer import order type, the chip manufacturing file is imported into the tape-out management system, and the first tape-out work order is generated after the chip manufacturing file passes verification. If the order type is a mass production order type, the chip manufacturing file is imported into the chip manufacturing execution system, and a mass production work order is generated after the chip manufacturing file passes verification.

[0013] Secondly, embodiments of this application also provide a production work order generation device, comprising: The acquisition module is used to acquire the design data of the chip to be manufactured, the design data including: design files, process parameters and the order type corresponding to the chip to be manufactured; The processing module is used to perform semantic parsing on the design file and the process parameters using a pre-built semiconductor manufacturing knowledge graph to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the association relationships between the multiple chip entities. The semiconductor manufacturing knowledge graph includes: the multiple chip entities and the association relationships between the multiple chip entities. The processing module is further configured to perform compatibility verification on the attribute values ​​of multiple chip entities of the chip to be manufactured based on the equipment information of the chip process equipment. The generation module is used to generate a chip manufacturing file for the chip to be manufactured based on the attribute values ​​of the multiple chip entities and the association relationship between the multiple chip entities if the compatibility verification passes. The generation module is further configured to generate a production work order for the chip to be manufactured based on the chip manufacturing file and the order type, so as to manufacture the chip to be manufactured through the chip process equipment.

[0014] Thirdly, embodiments of this application also provide a computer device, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method described in any of the first aspects.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method described in any of the first aspects.

[0016] This application provides a method, apparatus, computer equipment, and storage medium for generating production work orders. The method includes: acquiring design data of a chip to be manufactured; using a pre-constructed semiconductor manufacturing knowledge graph, performing semantic parsing on the design documents and process parameters to obtain attribute values ​​of multiple chip entities and the relationships between these entities; performing compatibility verification on the attribute values ​​of the multiple chip entities based on the equipment information of the chip process equipment; if the compatibility verification passes, generating a chip manufacturing file for the chip to be manufactured based on the attribute values ​​and relationships between the multiple chip entities; and generating a production work order for the chip to be manufactured based on the chip manufacturing file and the order type. This solution, through semantic parsing and intelligent verification, frees manual labor from repetitive and high-risk tasks, automating and intelligentizing the business process and avoiding tape-out failures. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 1 ; Figure 2 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 2 ; Figure 3 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 3 ; Figure 4 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 4 ; Figure 5 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 5 ; Figure 6 A schematic diagram illustrating a specific chip work order generation process provided in this application embodiment; Figure 7 This is a schematic diagram of the structure of the production work order generation device provided in the embodiments of this application; Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] To address the issues of low efficiency and error-proneness in existing chip work order generation, especially during the new product introduction phase where chaotic version management can easily lead to tape-out failures, this application uses semantic parsing and intelligent verification to free manual labor from repetitive and high-risk tasks, thereby automating and intelligentizing business processes and preventing tape-out failures.

[0021] Figure 1 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 1 In this embodiment, the execution subject is the computer equipment of the chip manufacturer.

[0022] like Figure 1 As shown, the method may include: S101. Obtain the design data of the chip to be manufactured.

[0023] Design data includes: design documents, process parameters, and the order type corresponding to the chip to be manufactured.

[0024] Among them, design documents refer to technical documents provided by the chip designer to describe the physical structure and circuit connection relationship of the chip. The design document format can be, for example, GDSII (Graphic Data System II) or OASIS (Open Artwork System Interchange Standard). The design document can include the hierarchical layout information of the chip to be manufactured, metal traces, via configuration, device dimensions, etc.

[0025] Process parameters can include process nodes (such as 7nm, 5nm), the number of lithography layers required, minimum linewidth / spacing, dielectric layer thickness, and doping concentration range. Among these, process nodes (such as 7nm, 5nm, 3nm) are the core indicator for measuring the advancement of chip manufacturing; the smaller the value, the more advanced the manufacturing process.

[0026] The order type corresponding to the chip to be manufactured refers to the type of order to which the chip to be manufactured belongs, such as new product introduction order and mass production order. New product introduction order refers to prototyping and debugging order or order to provide manufacturing services to the chip designer for the first time. Mass production order refers to formal production and sales order.

[0027] In some embodiments, the chip designer's computer device encrypts and digitally signs the chip data to obtain encrypted data and signed data, and sends them to the chip manufacturer's computer device. The chip manufacturer's computer device decrypts the encrypted data to obtain decrypted data, calculates the digital signature of the decrypted data, and then performs a consistency check with the received signature data. If the digital signature of the decrypted data matches the received signature data, it indicates that the data has not been tampered with during transmission. If the digital signature of the decrypted data does not match the received signature data, it indicates that the data has been tampered with during transmission. This ensures transmission security, provides trusted audit traces, and improves the reliability of data transmission.

[0028] It should be noted that the encryption / decryption algorithm and digital signature algorithm can be selected according to the actual situation, and this embodiment does not impose any special limitations on them.

[0029] S102. Using a pre-built semiconductor manufacturing knowledge graph, semantic parsing is performed on the design documents and process parameters to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the relationships between the multiple chip entities.

[0030] The semiconductor manufacturing knowledge graph includes multiple chip entities and the relationships between them.

[0031] The semiconductor manufacturing knowledge graph is a specialized knowledge graph for the chip manufacturing field. A chip entity in the knowledge graph is a node, and the edges in the knowledge graph represent the relationships between entities. These relationships can include belonging, dependency, precedence, and use relationships, and are used to characterize the technical constraints and process logic in the manufacturing process.

[0032] Multiple chip entities may include, for example, process node entities, order quantity entities, equipment requirement entities, and process requirement entities. The process node entity is used to indicate the process of the chip to be manufactured. The smaller the attribute value, the more advanced it is. For example, 7nm, 5nm, and 3nm represent more advanced manufacturing processes. It is used to indicate and determine the basic process framework required for chip manufacturing. The process node entity determines the process requirement entity and the process requirement entity. Therefore, there is a dependency relationship between the process node entity and the equipment requirement entity and the process requirement entity.

[0033] The order quantity entity has the attribute value of the number of chips to be manufactured. The equipment requirement entity has the attribute value of the type of equipment required to manufacture the chips. The process requirement entities include the photomask requirement entity, gate width entity, etching time entity, polishing pressure entity, and doping concentration entity. Among them, the photomask requirement entity has the attribute value of the number of photomask layers required by the lithography machine, the gate width entity has the attribute value of the gate width, the etching time entity has the attribute value of the etching time of the etching machine, the polishing pressure entity has the attribute value of the polishing pressure of the polishing equipment, and the doping concentration entity has the attribute value of the doping concentration of the ion implanter.

[0034] The semiconductor manufacturing knowledge graph also includes order entity nodes, process node entities and order quantity nodes belong to order entity nodes, and process entity nodes have dependencies on process demand entities.

[0035] By employing a semiconductor manufacturing knowledge graph, semantic parsing is performed on design documents and process parameters to extract attribute values ​​of multiple chip entities from the design documents and process parameters, and the relationships between multiple chip entities are extracted from the semiconductor manufacturing knowledge graph.

[0036] Among them, the attribute value of the chip entity is the entity value of the chip entity. For example, the attribute value of the process node entity is 7nm, the attribute value of the order quantity entity is 100, the attribute value of the equipment requirement entity is the information of the production equipment required to manufacture the chip, such as lithography machine, etching machine, etc., and the attribute value of the process requirement entity is the number of photomask layers, etc.

[0037] It should be noted that, due to inconsistencies in terminology naming, file formats, and data organization structures in the chip data provided by different chip designers, a semiconductor manufacturing knowledge graph is introduced as an intermediate layer to perform semantic parsing and unified mapping. This yields the attribute values ​​and relationships of multiple common chip entities, thereby generating a universal representation that is easy for chip manufacturers to understand and use to generate work orders.

[0038] S103. Based on the equipment information of the chip manufacturing equipment, perform compatibility verification on the attribute values ​​of multiple chip entities to be manufactured.

[0039] Chip manufacturing equipment refers to the equipment used by chip manufacturers to produce chips, such as lithography machines, etching machines, and thin-film deposition equipment. Based on the equipment information of the chip manufacturing equipment, compatibility checks are performed on the attribute values ​​of multiple chip entities to be manufactured, in order to verify whether the chip manufacturing equipment meets the manufacturing requirements of the chip to be manufactured.

[0040] In an optional implementation, the multiple chip entities may include: a process node entity, an order quantity entity, an equipment requirement entity, and a process requirement entity; step S103 above, which performs compatibility verification on the attribute values ​​of the multiple chip entities to be manufactured based on the equipment information of the chip process equipment, may include: performing compatibility verification on the attribute values ​​of the process node entity, the order quantity entity, the equipment requirement entity, and the process requirement entity respectively based on the process baseline information, capacity information, equipment type, and process configuration information of the chip process equipment.

[0041] Among them, the process baseline information of the chip process equipment refers to the chip manufacturing node supported by the chip process equipment, such as 5nm and 7nm. The capacity limit refers to the maximum number of chips that the chip process equipment can produce per unit time. The equipment type can include, for example, lithography machines, etching machines, thin film deposition equipment, ion implanters, chemical mechanical polishing machines, metrology and testing equipment, etc. The process configuration information includes mask configuration information, gate configuration width, etching configuration time, and polishing configuration pressure. The mask configuration information includes the number of mask layers supported by the lithography machine, such as 40 layers. The gate configuration width is the etching width supported by the lithography machine and the etching machine. The etching configuration time is the etching time supported by the etching machine. The polishing configuration pressure is the polishing pressure supported by the polishing equipment. The doping configuration concentration is the doping concentration supported by the ion implanter.

[0042] Based on the process baseline information of the chip manufacturing equipment, compatibility checks are performed on the attribute values ​​of the process node entity to verify whether the process baseline of the chip manufacturing equipment meets the requirements of the process node of the chip to be manufactured. Based on the capacity limit, compatibility checks are performed on the attribute values ​​of the order quantity entity to verify whether the capacity of the chip manufacturing equipment meets the quantity requirements of the chip to be manufactured. Based on the equipment type, compatibility checks are performed on the attribute values ​​of the equipment requirement entity to verify whether the chip manufacturing equipment meets the requirements of the chip to be manufactured for the manufacturing equipment. Finally, based on the process configuration information, compatibility checks are performed on the attribute values ​​of the process requirement entity to verify whether the process configuration information of the chip manufacturing equipment meets the process requirements of the chip to be manufactured.

[0043] S104. If the compatibility verification passes, then generate the chip manufacturing file for the chip to be manufactured based on the attribute values ​​of multiple chip entities and the association between the multiple chip entities.

[0044] If the compatibility verification passes, it means that the chip manufacturer's chip process equipment meets the manufacturing requirements of the chip to be manufactured. Then, based on the attribute values ​​of multiple chip entities and the relationships between multiple chip entities, a chip manufacturing file is generated. The chip manufacturing file includes the attribute values ​​of multiple chip entities and the relationships between multiple chip entities. The chip manufacturing file is a manufacturing data package packaged in a standardized format.

[0045] S105. Based on the chip manufacturing documents and order type, generate a production work order for the chip to be manufactured, so as to manufacture the chip to be manufactured using chip process equipment.

[0046] Specifically, based on the order type, the corresponding work order template is selected, and a production work order corresponding to the order type is generated based on the chip manufacturing file, so that the chip to be manufactured can be manufactured through chip process equipment based on the production work order.

[0047] In an optional implementation, step S105 above, which generates a production work order for the chip to be manufactured based on the chip manufacturing documents and the order type, may include: If the order type is a new customer import order type, the chip manufacturing files will be imported into the tape-out management system, and the first tape-out work order will be generated after the chip manufacturing files are verified.

[0048] If the order type is a mass production order, the chip manufacturing file will be imported into the chip manufacturing execution system, and a mass production work order will be generated after the chip manufacturing file is verified.

[0049] The tape-out management system is an engineering collaboration platform specifically designed for the New Product Introduction (NPI) phase. It features version control, multi-department review, issue tracking, and change management. If the order type is a new customer import order, the chip manufacturing files can be imported into the tape-out management system through system integration interfaces (such as RESTful APIs). The tape-out management system then performs process verification to ensure that the chip design itself is logically correct, physically manufacturable, and conforms to standardized process design rules.

[0050] After the chip manufacturing documents are verified, a first tape-out order (NTO) is generated based on the chip manufacturing documents to convert the chip manufacturing documents into detailed instructions that the chip manufacturer can execute, thereby generating the first tape-out order (NTO).

[0051] If the order type is a mass production order, the chip manufacturing file is imported into the Manufacturing Execution System (MES). The MES system is the core hub for daily production scheduling in the factory, responsible for work order issuance, equipment linkage, material tracking, and real-time data collection. The MES system performs process verification to ensure that the chip manufacturing file and the status of the chip process equipment are completely matched, so that the chip process equipment can be driven to manufacture chips safely and without errors. If the verification is successful, the chip manufacturing file is converted into detailed instructions that can be executed by chip manufacturers, and then a mass production work order is generated.

[0052] In this embodiment, semantic parsing and intelligent verification free manual labor from repetitive and high-risk tasks, eliminating manual data verification, preventing human error, and automating business processes. This achieves automation and intelligence of business processes, avoiding tape-out failures. Furthermore, since general data exchange platforms cannot understand the specialized semantics of the semiconductor field, they cannot achieve automatic verification and process triggering based on business logic, making it difficult to support the needs of rapid iteration and efficient production, resulting in low collaborative efficiency. Based on this, this application uses knowledge graphs to automatically identify chip entities and their relationships, preventing tape-out failures caused by design rule version mismatches. This eliminates production accidents caused by data inconsistency from the source, ensuring that mass production orders use the correct process route.

[0053] Figure 2 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 2 ,like Figure 2 As shown, in an optional embodiment, the plurality of chip entities may further include: a process path state entity of the chip to be manufactured; the method may further include: S201. Based on the attribute values ​​of the process path status entity, perform status verification on the process path status of the chip to be manufactured.

[0054] Language understanding is used to extract attribute values ​​of process path status entities from design documents. The attribute values ​​of process path status can include "released" and "not released". "Released" indicates that the process path status of the chip to be manufactured is a preset authorized status, that is, an order that has been approved and can be manufactured. "Not released" indicates that the process path status of the chip to be manufactured is an unauthorized status, that is, an order that has not been approved and can be manufactured.

[0055] S202. If the attribute value of the process path status entity indicates that the process path status of the chip to be manufactured is the preset authorized status, then the status verification is confirmed to be successful.

[0056] If the compatibility verification passes in step S104 above, a chip manufacturing file for the chip to be manufactured is generated based on the attribute values ​​of multiple chip entities and the association relationships between the multiple chip entities. This file may include: S203. If the compatibility check and the status check pass, then generate the chip manufacturing file based on the attribute values ​​of multiple chip entities and the association between the multiple chip entities.

[0057] If the attribute value of the process path status entity indicates that the process path status of the chip to be manufactured is the preset authorized status, it means that the status verification has passed. Then, when both the compatibility verification and the status verification have passed, the chip manufacturing file is generated based on the attribute values ​​of multiple chip entities and the association between multiple chip entities.

[0058] In this embodiment, status verification is used to prevent the erroneous manufacturing of chips that have not been approved for mass production, thereby avoiding quality accidents and further ensuring the standardization of chip manufacturing.

[0059] Figure 3 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 3 ,like Figure 3 As shown, in an optional implementation, step S203 above, generating a chip manufacturing file based on the attribute values ​​of multiple chip entities and the association relationships between the multiple chip entities, may include: S301. The attribute values ​​of multiple chip entities are routed to each chip manufacturing review node to perform secondary verification of the attribute values ​​of multiple chip entities based on the chip process equipment.

[0060] S302. If the review pass message of each chip manufacturing review node is received, then generate chip manufacturing documents based on the attribute values ​​of multiple chip entities and the association relationship of multiple chip entities.

[0061] To ensure that the chip undergoes full evaluation and confirmation at each chip manufacturing review node before formal manufacturing, the attribute values ​​of multiple chip entities can be routed to each chip manufacturing review node. Each chip manufacturing review node is used to perform secondary verification on the attribute values ​​of the corresponding chip entities based on the chip process equipment, so as to determine again whether the chip process equipment meets the manufacturing requirements of the chip to be manufactured.

[0062] Chip manufacturing review nodes may include, for example, process feasibility review nodes, equipment resource review nodes, and photomask review nodes. Among them, the process feasibility review node is used to evaluate whether the chip process equipment meets the process feasibility requirements of the chip to be manufactured based on the process node entity. The equipment resource review node is used to evaluate whether the chip process equipment meets the quantity and equipment requirements of the chip to be manufactured based on the attribute values ​​of the order quantity entity and the equipment requirement entity. The photomask review node is used to evaluate whether the etching machine can meet the photomask requirements of the chip to be manufactured based on the attribute values ​​of the process requirement entity.

[0063] By routing the attribute values ​​of multiple chip entities to each chip manufacturing review node, if a review pass message is received from each chip review node, it indicates that the chip to be manufactured has undergone sufficient evaluation and confirmation by each chip review node. Then, chip manufacturing documents can be generated based on the attribute values ​​of multiple chip entities and the relationships between multiple chip entities.

[0064] In this embodiment, a multi-review node collaboration mechanism is introduced to intelligently distribute the attribute values ​​of the chip entity to the chip manufacturing review nodes. The final generation of the chip manufacturing file is only triggered after all review nodes have passed the review. This automates and ensures the traceability of the review process while preventing the mismanufacturing of chips.

[0065] Figure 4 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 4 ,like Figure 4 As shown, in an optional implementation, step S105 above, which generates a production work order for the chip to be manufactured based on the chip manufacturing documents and the order type, may include: S401. Perform entity name recognition on the chip manufacturing file to obtain the preset sensitive entities and their attribute values ​​in the chip manufacturing file.

[0066] The chip entities may also include preset sensitive entities, such as gate width entities, etching time entities, and doping concentration entities. By using entity name recognition algorithms in natural language processing, regular expressions are used to identify entity names in the chip manufacturing documents to obtain the preset sensitive entities and their attribute values.

[0067] It should be noted that preset sensitive parameters refer to a type of chip entity that is pre-marked as having a high level of confidentiality in the semiconductor manufacturing knowledge graph. Its attribute values ​​directly reflect specific design intentions, process optimization results, or equipment calibration experience. Once leaked, it may lead to the risk of technology imitation or competition.

[0068] S402. Desensitize the attribute values ​​of the preset sensitive entities to obtain the desensitization parameter range of the preset sensitive entities.

[0069] The attribute values ​​of the preset sensitive entities are desensitized. The preset desensitization logic is used to generate a desensitization parameter range based on the attribute values ​​of the preset sensitive entities, thus obtaining the desensitization parameter range of the preset sensitive entities.

[0070] For example, by replacing the gate width physical property value from 5.1nm to 5.0-5.2nm and the polishing pressure from 2.85psi to 2.80-2.90psi, the data security of the core manufacturing process is protected, which is a differentiated two-way protection mechanism.

[0071] Step S105 above, which generates a production work order for the chip to be manufactured based on the chip manufacturing documents and order type, may include: S403. Update the chip manufacturing file according to the preset desensitization parameter range of sensitive entities, and generate a production work order according to the updated chip manufacturing file and order type.

[0072] Replace the attribute values ​​of preset sensitive entities in the chip manufacturing file with the desensitization parameter range of the preset sensitive entities, and generate a production work order based on the updated chip manufacturing file and order type. The updated chip manufacturing file can be imported into the tape-out management system or chip manufacturing execution system so that the first tape-out work order or mass production work order can be generated after verification.

[0073] It should be noted that when generating production work orders, chip manufacturers can adjust parameters based on the desensitized parameter range in the updated chip manufacturing files to select a parameter value from the desensitized parameter range as a new attribute value for the preset sensitive parameter, and generate production work orders in combination with the order type.

[0074] In this embodiment, entity name recognition technology is used to locate sensitive parameters, and the attribute values ​​of the sensitive parameters are replaced with numerical ranges to achieve dynamic desensitization of chip manufacturing files, protecting the design parameters of both the chip designer and the chip manufacturer. This achieves a collaborative mode where data is available but not visible, ensuring end-to-end data transmission security and providing tamper-proof transaction evidence and fine-grained data desensitization protection.

[0075] Figure 5 A flowchart illustrating the production work order generation method provided in this application embodiment. Figure 5 ,like Figure 5 As shown, in an optional implementation, the method may further include: S501. Perform hash processing on the design data to obtain the target digital fingerprint.

[0076] When chip manufacturers receive design data, they use a hash algorithm (such as SHA-256) to hash the design data and generate a unique target digital fingerprint.

[0077] S502. Use a pre-set smart contract to obtain verification data corresponding to the design data from a pre-set consortium blockchain network.

[0078] The verification data is written into a pre-defined consortium blockchain by the chip designer. The verification data includes verification digital fingerprints, timestamps, information about the chip designer, and information about the chip manufacturer.

[0079] In some embodiments, the information of the chip designer is the chip designer's identity identifier, the information of the chip manufacturer is the chip manufacturer's identity identifier, and the timestamp refers to the time when the data is written into the preset consortium blockchain, which is used to identify the data storage time and ensure the authenticity and anti-counterfeiting of the data submission behavior.

[0080] Chip designers use pre-defined smart contracts and hash algorithms (such as SHA-256) to process the design data, generating a verification digital fingerprint. This verification digital fingerprint, along with a timestamp, chip designer information, and chip manufacturer information, is then written into a pre-defined consortium blockchain network—for example, into the network's distributed ledger. Because consortium blockchains are decentralized, immutable, and traceable, data uploaded to the chain becomes an undeniable electronic certificate.

[0081] S503. Based on the verification data and the target digital fingerprint, perform consistency verification on the design data.

[0082] When the chip manufacturer receives the design data, it uses a pre-set smart contract to retrieve the verification data from the pre-set consortium blockchain based on the information of the chip designer and the chip manufacturer, and compares the target digital fingerprint and the verification digital fingerprint to verify the consistency of the design data.

[0083] If the target digital fingerprint and the verification digital fingerprint are consistent, it means that the design data received by the chip manufacturer is consistent with the design data sent by the chip designer, and the design data received by the chip manufacturer is not leaked or tampered with. If the target digital fingerprint and the verification digital fingerprint are inconsistent, it means that the design data received by the chip manufacturer is consistent with the design data sent by the chip designer, and the design data received by the chip manufacturer may have been leaked or tampered with.

[0084] In some embodiments, the time when data is uploaded to the blockchain can be located based on the timestamp. In this way, when there are multiple versions of design data, the multiple iterations of the design data can be traced based on the timestamps corresponding to the digital fingerprints of each version of the design data in the preset consortium blockchain network.

[0085] In this embodiment, the pre-defined consortium blockchain network is jointly maintained by the chip designer and the chip manufacturer. Leveraging the decentralized trust characteristics of blockchain, an immutable electronic stamp is created for each data exchange, ensuring the non-repudiation and traceability of data exchange activities and providing credible electronic evidence for dispute resolution. Furthermore, it enables fully automated, error-free workflow from chip designer to chip manufacturer, constructing a trusted data exchange environment and providing immutable electronic evidence for business disputes.

[0086] In summary, this application liberates manual labor from repetitive and high-risk tasks through semantic parsing and intelligent verification, significantly shortening the new product introduction cycle and achieving automated and error-free mass production order processing. It also automates and intelligentizes business processes. Furthermore, by using blockchain for notarization and dynamic anonymization, it constructs a security system integrating transmission security, data security, and trust foundation, resolving the core contradiction between data protection and data sharing, and enhancing the security and trustworthiness of industry collaboration. In addition, by providing new production relationships and collaboration standards, it effectively reduces operating costs and improves yield and production efficiency, demonstrating extremely high industrial application value.

[0087] Figure 6 This application provides a schematic diagram illustrating a specific chip work order generation process, as shown in the embodiment. Figure 6 As shown, it includes a customer layer, an intelligent secure exchange layer, and a contract manufacturer layer. The customer layer deploys systems such as customer MES and Enterprise Resource Planning (ERP), while the intelligent secure exchange layer deploys a secure transmission gateway, a semantic parsing and intelligent routing module, a dynamic de-identification control module, and a blockchain decentralized evidence storage module.

[0088] The customer layer is integrated into the computer equipment of the chip designer, while the smart secure switching layer and the foundry layer are integrated into the computer equipment of the chip manufacturer.

[0089] The customer layer transmits design data to the semantic parsing and intelligent routing module through a secure transmission gateway via systems such as MES and ERP. The semantic parsing module is used to perform semantic parsing to obtain the attribute values ​​of each chip entity. The intelligent routing module is used to route the attribute values ​​of each chip entity to each chip manufacturing review node. The semantic parsing module integrates a knowledge graph and a business rule engine to provide semantic parsing and verification logic.

[0090] The blockchain decentralized evidence storage module is used to calculate the target digital fingerprint of the design data, obtain verification data from the preset consortium blockchain network, and perform consistency verification on the design data based on the verification data and the target digital fingerprint.

[0091] The dynamic desensitization module is used to pre-decode the attribute values ​​of sensitive entities. It integrates a dynamic desensitization console and a Named Entity Recognition (NLP) module, which are used to distribute desensitization logic and provide entity recognition functionality.

[0092] The foundry layer is used to generate corresponding production work orders based on order type. For new customer orders, it verifies the anonymized data (chip manufacturing files) and then creates an NTO work order. For mass production orders, it verifies the anonymized data (chip manufacturing files) and then creates a mass production work order.

[0093] In this embodiment, the three modules are connected in series to form an automated pipeline. The secure transmission and evidence storage module is responsible for secure access and trusted evidence storage, laying the foundation for subsequent processes. The semantic parsing and intelligent routing module serves as the control center, making intelligent decisions and distributing tasks. The dynamic identification and desensitization control module performs refined data security processing according to instructions. Finally, the processed secure data is automatically synchronized to the foundry's internal system through a system integration interface (such as a RESTful API), forming a complete, secure, and intelligent closed loop from customer order placement to factory order acceptance. This constructs a complete secure data exchange system, effectively solving the security, efficiency, and reliability issues in semiconductor manufacturing collaboration.

[0094] Figure 7 This is a schematic diagram of the production work order generation device provided in an embodiment of this application. The device can be integrated into the computer equipment of the chip manufacturer.

[0095] like Figure 7 As shown, the device may include: The acquisition module 601 is used to acquire the design data of the chip to be manufactured. The design data includes: design files, process parameters and the order type corresponding to the chip to be manufactured. The processing module 602 is used to perform semantic parsing on the design documents and process parameters using a pre-built semiconductor manufacturing knowledge graph to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the relationship between the multiple chip entities. The semiconductor manufacturing knowledge graph includes: multiple chip entities and the relationship between the multiple chip entities. The processing module 602 is also used to perform compatibility verification on the attribute values ​​of multiple chip entities to be manufactured based on the equipment information of the chip process equipment. The generation module 603 is used to generate a chip manufacturing file for the chip to be manufactured based on the attribute values ​​of multiple chip entities and the association relationship between the multiple chip entities, if the compatibility verification passes. The generation module 603 is also used to generate a production work order for the chip to be manufactured based on the chip manufacturing documents and the order type, so as to manufacture the chip to be manufactured through chip process equipment.

[0096] In an optional implementation, the processing module 602 is specifically used for: Based on the process baseline information, capacity information, equipment type, and process configuration information of the chip manufacturing equipment, compatibility checks are performed on the attribute values ​​of the process node entity, the order quantity entity, the equipment requirement entity, and the process requirement entity.

[0097] In an optional implementation, the processing module 602 is further configured to: Based on the attribute values ​​of the process path state entity, the process path state of the chip to be manufactured is verified. If the attribute value of the process path status entity indicates that the process path status of the chip to be manufactured is the preset authorized status, then the status verification is confirmed to be successful. Processing module 602 is specifically used for: If the compatibility check and the status check pass, then the chip manufacturing file is generated based on the attribute values ​​of multiple chip entities and the relationships between the multiple chip entities.

[0098] In an optional implementation, the generation module 603 is specifically used for: The attribute values ​​of multiple chip entities are routed to each chip manufacturing review node to perform secondary verification of the attribute values ​​of multiple chip entities based on the chip process equipment. If a review pass message is received from each chip manufacturing review node, a chip manufacturing file is generated based on the attribute values ​​of multiple chip entities and the relationships between them.

[0099] In an optional implementation, the generation module 603 is specifically used for: Entity name recognition is performed on the chip manufacturing documents to obtain the preset sensitive entities and their attribute values. The attribute values ​​of the preset sensitive entities are desensitized to obtain the desensitization parameter range of the preset sensitive entities; Based on the preset desensitization parameter range for sensitive entities, update the chip manufacturing file, and generate a production work order based on the updated chip manufacturing file and order type.

[0100] In an optional implementation, the processing module 602 is further configured to: The design data is hashed to obtain the target digital fingerprint; Using a pre-set smart contract, verification data corresponding to the design data is obtained from a pre-set consortium blockchain network. The verification data is written by the chip designer to the pre-set consortium blockchain network. The verification data includes verification digital fingerprints, timestamps, information of the chip designer, and information of the chip manufacturer. Based on the verification data and the target digital fingerprint, the design data is validated for consistency.

[0101] In an optional implementation, the generation module 603 is specifically used for: If the order type is a new customer import order type, the chip manufacturing files will be imported into the tape-out management system, and the first tape-out work order will be generated after the chip manufacturing files pass the verification. If the order type is a mass production order, the chip manufacturing file will be imported into the chip manufacturing execution system, and a mass production work order will be generated after the chip manufacturing file is verified.

[0102] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0103] Figure 8 A schematic diagram of the structure of the computer device provided in the embodiments of this application, such as... Figure 8 As shown, the device may include a processor 701, a memory 702, and a bus 703. The memory 702 stores machine-readable instructions that can be executed by the processor 701. When the computer device is running, the processor 701 communicates with the memory 702 through the bus 703, and the processor 701 executes the machine-readable instructions to perform the above-described method.

[0104] This application also provides a computer-readable storage medium storing a computer program, which is executed by a processor to perform the above-described method.

[0105] In this embodiment, the computer program, when run by the processor, can also execute other machine-readable instructions to perform other methods as described in the embodiments. For details on the specific execution steps and principles, please refer to the description of the embodiments, which will not be repeated here.

[0106] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0107] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0108] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0109] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0111] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for generating production work orders, characterized in that, The method includes: Obtain the design data of the chip to be manufactured, including: design files, process parameters, and the order type corresponding to the chip to be manufactured; A pre-constructed semiconductor manufacturing knowledge graph is used to perform semantic parsing on the design documents and process parameters to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the association relationships between the multiple chip entities. The semiconductor manufacturing knowledge graph includes: multiple chip entities and the association relationships between the multiple chip entities. Based on the equipment information of the chip manufacturing equipment, the attribute values ​​of multiple chip entities of the chip to be manufactured are verified for compatibility. If the compatibility check passes, a chip manufacturing file for the chip to be manufactured is generated based on the attribute values ​​of the multiple chip entities and the association between the multiple chip entities. Based on the chip manufacturing documents and the order type, a production work order for the chip to be manufactured is generated, so as to manufacture the chip to be manufactured using the chip process equipment.

2. The method according to claim 1, characterized in that, The multiple chip entities include: process node entity, order quantity entity, equipment requirement entity, and process requirement entity; The step of performing compatibility verification on the attribute values ​​of multiple chip entities of the chip to be manufactured based on the equipment information of the chip manufacturing equipment includes: Based on the process baseline information, capacity information, equipment type, and process configuration information of the chip manufacturing equipment, compatibility checks are performed on the attribute values ​​of the process node entity, the order quantity entity, the equipment demand entity, and the process demand entity, respectively.

3. The method according to claim 2, characterized in that, The plurality of chip entities further include: a process path state entity of the chip to be manufactured; the method further includes: Based on the attribute values ​​of the process path state entity, the process path state of the chip to be manufactured is verified. If the attribute value of the process path status entity indicates that the process path status of the chip to be manufactured is a preset authorized status, then the status verification is determined to be successful. If the compatibility verification passes, then based on the attribute values ​​of the multiple chip entities and their associations, a chip manufacturing file for the chip to be manufactured is generated, including: If the compatibility check and the status check pass, the chip manufacturing file is generated based on the attribute values ​​of the multiple chip entities and the association relationship between the multiple chip entities.

4. The method according to claim 1, characterized in that, The step of generating the chip manufacturing file based on the attribute values ​​of multiple chip entities and the association relationships among the multiple chip entities includes: The attribute values ​​of the multiple chip entities are routed to each chip manufacturing review node to perform secondary verification of the attribute values ​​of the multiple chip entities based on the chip process equipment. If a review pass message is received from each of the chip manufacturing review nodes, the chip manufacturing file is generated based on the attribute values ​​of the multiple chip entities and the association relationships between the multiple chip entities.

5. The method according to claim 1, characterized in that, The step of generating a production work order for the chip to be manufactured based on the chip manufacturing documents and the order type includes: Entity name recognition is performed on the chip manufacturing file to obtain preset sensitive entities and attribute values ​​of the preset sensitive entities in the chip manufacturing file; The attribute values ​​of the preset sensitive entities are desensitized to obtain the desensitization parameter range of the preset sensitive entities; The chip manufacturing file is updated according to the preset sensitive entity desensitization parameter range, and the production work order is generated according to the updated chip manufacturing file and the order type.

6. The method according to claim 1, characterized in that, The method further includes: The design data is hashed to obtain the target digital fingerprint; Using a pre-set smart contract, verification data corresponding to the design data is obtained from a pre-set consortium blockchain network. The verification data is written by the chip designer to the pre-set consortium blockchain network and includes verification digital fingerprints, timestamps, information of the chip designer, and information of the chip manufacturer. Based on the verification data and the target digital fingerprint, the design data is subjected to consistency verification.

7. The method according to claim 1, characterized in that, The step of generating a production work order for the chip to be manufactured based on the chip manufacturing documents and the order type includes: If the order type is a new customer import order type, the chip manufacturing file is imported into the tape-out management system, and the first tape-out work order is generated after the chip manufacturing file passes verification. If the order type is a mass production order type, the chip manufacturing file is imported into the chip manufacturing execution system, and a mass production work order is generated after the chip manufacturing file passes verification.

8. A production work order generation device, characterized in that, include: The acquisition module is used to acquire the design data of the chip to be manufactured, the design data including: design files, process parameters and the order type corresponding to the chip to be manufactured; The processing module is used to perform semantic parsing on the design file and the process parameters using a pre-built semiconductor manufacturing knowledge graph to obtain the attribute values ​​of multiple chip entities of the chip to be manufactured and the association relationships between the multiple chip entities. The semiconductor manufacturing knowledge graph includes: the multiple chip entities and the association relationships between the multiple chip entities. The processing module is further configured to perform compatibility verification on the attribute values ​​of multiple chip entities of the chip to be manufactured based on the equipment information of the chip process equipment. The generation module is used to generate a chip manufacturing file for the chip to be manufactured based on the attribute values ​​of the multiple chip entities and the association relationship between the multiple chip entities if the compatibility verification passes. The generation module is further configured to generate a production work order for the chip to be manufactured based on the chip manufacturing file and the order type, so as to manufacture the chip to be manufactured through the chip process equipment.

9. A computer device, characterized in that, include: The computer device includes a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method according to any one of claims 1 to 7.

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