Multi-screen compatible embedded mainboard circuit system and display self-adaption method thereof

Abstract

The invention relates to the technical field of electronics associated with display driving printed circuits, in particular to a multi-screen compatible embedded mainboard circuit system and a display self-adaption method thereof, and the system comprises a main control chip, a display interface module comprising a first display interface and a second display interface, and a configurable screen power supply module. Wherein a group of reusable signal pins of the main control chip are electrically and simultaneously connected to the first display interface and the second display interface, and respond to software configuration to directly drive one of the first display interface and the second display interface. The configurable screen power supply module provides various selectable working voltages for the second display interface through selection of physical devices. The method comprises the steps of physically configuring screen power supply voltage, configuring pin working modes through software and the like. Under the condition that an external protocol conversion chip is not added, a pin multiplexing function built in the main control chip is utilized and a configurable power supply scheme of hardware is combined, so that a single mainboard hardware platform is compatible with various display screens with different interface standards and power supply specifications.

Description

Technical Field

[0001] This invention relates to the field of electronic technology related to display driver printed circuits, and more particularly to a multi-screen compatible embedded motherboard circuit system and its display self-adaptation method. Background Technology

[0002] Embedded motherboards are core components in industrial control, commercial display terminals, and IoT devices. One of their functions is to drive displays to enable human-machine interaction. In practical applications, there are many types of displays, and their physical interfaces and electrical standards vary. Mainstream interface standards include High Definition Multimedia Interface (HDMI), Mobile Industry Processor Interface (MIPI-DSI), and Low Voltage Differential Signaling Interface (LVDS). Furthermore, even with the same interface standard (such as LVDS), different sizes or different suppliers of screen modules may require different operating voltages, commonly 3.3V, 5V, and 12V.

[0003] Currently, to enable a single embedded motherboard model to adapt to different display specifications, those skilled in the art typically employ the following techniques. The first approach is to use an external protocol conversion chip. For example, when the main control chip only provides MIPI-DSI output, but the application needs to connect to an LVDS screen, a MIPI-to-LVDS bridge chip is integrated on the motherboard. While this method solves the interface incompatibility problem, it significantly increases hardware costs and PCB design complexity, while also introducing additional power consumption and potential signal integrity risks. The second approach is to design dedicated motherboard models for different interfaces. For example, designing motherboard A for the MIPI screen market and motherboard B for the LVDS screen market. This approach leads to a bloated product line, significantly increasing R&D, production, material management, and inventory costs, hindering large-scale production and rapid response to market changes.

[0004] Furthermore, in terms of screen power supply, traditional motherboards typically only provide a fixed operating voltage for the display interface. When it is necessary to replace the screen with one that has a different power supply specification, it is often necessary to modify the motherboard hardware, such as by adjusting the voltage through "flying wires" or by replacing components. This operation is not only inefficient, but also seriously affects the reliability and consistency of the product.

[0005] Therefore, how to achieve broad compatibility of a single hardware platform with multiple mainstream display interfaces and power supply specifications in a low-cost, highly integrated and highly reliable manner with limited main control chip pin resources and PCB area is a technical problem that urgently needs to be solved in the field of embedded motherboard circuit system design. Summary of the Invention

[0006] To help solve the technical problems existing in the prior art, the present invention provides a multi-screen compatible embedded motherboard circuit system and its display self-adaptation method, which can enable a single motherboard hardware platform to be compatible with multiple displays with different interface standards and power supply specifications without adding an external protocol conversion chip, by utilizing the pin multiplexing function built into the main control chip and combining it with a hardware configurable power supply scheme.

[0007] This invention discloses a multi-screen compatible embedded motherboard circuit system, comprising: One main control chip; A display interface module, the display interface module including at least one first display interface and at least one second display interface, the first display interface and the second display interface being used to connect to a display screen conforming to a first display standard and a second display standard, respectively; Among them, a set of reusable signal pins of the main control chip are electrically connected to the signal terminals of the first display interface and the second display interface simultaneously. The set of reusable signal pins is configured to selectively operate in a first working mode or a second working mode in response to software configuration, so as to output display signals that conform to the first display standard or the second display standard respectively, thereby directly driving the first display interface or the second display interface. It also includes a configurable screen power supply module, which includes: At least two power rails, each carrying a different voltage value; A power selection interface, wherein multiple input terminals of the power selection interface are electrically connected to the at least two power rails respectively, and its output terminal is electrically connected to a power pin of the second display interface; The power selection interface is used to select one of the plurality of input terminals to be connected to the output terminal by plugging or shorting physical devices, so as to provide the required operating voltage to the display screen connected to the second display interface.

[0008] It is understood that the embedded motherboard circuit system disclosed in this invention aims to construct an efficient display interface multiplexing architecture by combining physical sharing at the hardware level with logical switching at the software level. Specifically, the main control chip in this system provides a set of signal pins with multi-functional multiplexing capabilities. In terms of circuitry, the wiring of this set of multiplexed signal pins is not dedicated to a specific interface, but is designed to electrically establish connections with the corresponding signal terminals of the first display interface (e.g., MIPI-DSI interface) and the second display interface (e.g., LVDS interface) simultaneously. This parallel or common-path design at the hardware level provides the foundation for subsequent function switching.

[0009] In conjunction with the aforementioned hardware structure, the operating mode of this set of multiplexed signal pins is not fixed but can be dynamically configured by software. When the system needs to drive the first display interface, the operating system or low-level driver sends an instruction to the main control chip to configure this set of pins into the first operating mode. In this mode, the electrical signals output by the pins conform to the first display standard in terms of protocol, timing, and level characteristics, thereby directly driving the first display interface physically connected to it. Similarly, when the second display interface needs to be driven, the software instructs the main control chip to switch the same set of pins to the second operating mode, outputting signals conforming to the second display standard, thereby activating the second display interface. At any given time, only one interface is active, ensuring the uniqueness and validity of the signal. This design, without adding any external protocol conversion chips, utilizes the inherent capabilities of the main control chip to support multiple display standards with limited pin resources.

[0010] Furthermore, to enhance compatibility with different displays, the system integrates a physical selection-based screen power supply module independent of software control. This module converges multiple existing power rails with different voltage values ​​(e.g., 3.3V, 5V, and 12V) on the motherboard to the input of a power selection interface. The output of this interface is then fixedly connected to the power pin of the second display interface. The operator can establish a defined physical conduction path on the power selection interface using jumper caps or other physical devices, shorting the required voltage power rail to the output. This purely hardware-based configuration provides a clear and stable operating voltage for the second display interface, unaffected by system software status, thus creating a highly reliable power supply adaptation solution.

[0011] In summary, this invention fully realizes a multi-screen compatible embedded motherboard circuit system through the coordinated operation of three major technical features: physical multiplexing of signal paths in hardware, logical switching of pin functions in software, and manual configuration of screen power supply at the physical level.

[0012] Based on the aforementioned embedded motherboard circuit system, this invention also discloses a display self-adaptation method for a multi-screen compatible embedded motherboard circuit system, applied to the aforementioned embedded motherboard circuit system of this invention, comprising the following steps: according to the specifications of the display screen to be connected and conforming to the second display standard, by plugging or shorting physical components on the power selection interface to select a matching operating voltage for the power pins of the second display interface; by modifying the device tree file in the operating system, setting the state of the controller node corresponding to the second display interface to enabled, and simultaneously setting the state of the controller node corresponding to the first display interface to disabled; powering on and starting the embedded motherboard circuit system, so that the system kernel, according to the configuration of the device tree file, configures the set of multiplexable signal pins of the main control chip to the second operating mode, and loads the corresponding driver to light up the display screen. It is understood that the display self-adaptation method provided by this invention aims to ensure that the motherboard can correctly identify and drive displays of different specifications through an orderly combination of physical layer pre-configuration and logical layer dynamic adaptation. Specifically, the first step of this method is to perform hardware adaptation at the physical layer, the core of which is the pre-setting of the screen's operating voltage. Before powering on the system, the operator first determines the exact operating voltage value required by the second standard display to be connected (e.g., an LVDS screen) according to its product specifications. Subsequently, the operator uses jumpers or other physical devices on the motherboard's power selection interface to physically short-circuit the power rail input terminal carrying the corresponding voltage value to the output terminal of the interface. This step establishes a definite and unchangeable power supply path at the hardware level. The essence of this operation is to create a safe and correct electrical environment for subsequent software initialization and signal output, ensuring that the display is not damaged due to incorrect power supply voltage. This pre-configuration step is independent of any software process, providing a fundamental reliability guarantee for the entire self-adaptation process.

[0013] The second step of this method is to perform software adaptation at the logic layer, the core of which is the declaration and configuration of the main control chip's pin functions. This step is accomplished by modifying the device tree file of the embedded operating system (such as Linux or Android). The device tree is a data structure that describes hardware device information, and the operating system kernel uses this file to initialize the hardware during startup. The operator locates the hardware controller nodes corresponding to the first and second display interfaces in the device tree file. Based on the actual physical connection, the operator sets the status attribute of the controller node corresponding to the second display interface to "enabled," while simultaneously setting the status attribute of the controller nodes corresponding to the first display interface (and all other interfaces sharing signal pins with the second display interface) to "disabled." The fundamental purpose of this modification is to provide explicit instructions to the operating system kernel, telling it which functional mode to configure for which physically shared, reusable signal pins in the subsequent startup process.

[0014] The third step of this method is system startup and automated adaptation execution. After completing the configuration in the first two steps, the operator powers on the system. During system startup, the bootloader loads the operating system kernel and the modified device tree file. During kernel initialization, its pin control subsystem parses the configuration information in the device tree. Based on the "enable" and "disable" states set in the second step, this subsystem automatically sends instructions to the pin multiplexing controller of the main control chip to precisely configure the multiplexed signal pin group to the second operating mode (e.g., LVDS output mode). Next, the operating system loads the device driver that matches the second display interface. This driver further reads detailed parameters from the device tree, such as screen resolution and timing, and initializes the display controller inside the main control chip accordingly. Finally, the display controller begins to output video signals conforming to the second display standard through the correctly configured signal pins and physical interfaces, thus successfully lighting up and driving the display screen to work normally.

[0015] In summary, the method of this invention separates and executes physical security configuration and software logic configuration in an orderly manner through a process of first determining the power supply in hardware and then determining the signal in software. Finally, the system kernel automatically completes the precise scheduling of hardware resources at startup, thereby fully realizing an efficient and reliable display self-adaptation process.

[0016] Furthermore, the first display interface is a MIPI-DSI interface, and the second display interface is an LVDS interface; the power selection interface is a multi-pin jumper header, and the physical device is a jumper cap; the at least two power rails include at least two of 3.3V, 5V, and 12V power rails. It can be understood that this scheme aims to explicitly define the first display interface as a MIPI-DSI interface and the second display interface as an LVDS interface. These two interfaces are currently the two most widely used high-speed serial display interfaces in the embedded field, thus clarifying the two mainstream technical standards that this invention aims to be compatible with. Simultaneously, limiting the power selection interface to a multi-pin jumper header and using jumper caps for physical shorting achieves both low cost and high reliability in engineering practice. Specifically limiting the selectable voltage rails to 3.3V, 5V, and 12V covers the logic operating voltage specifications of most LVDS displays on the market, thus giving the configurable power supply module of this invention broad applicability.

[0017] Furthermore, the motherboard circuit system of the present invention also includes a touch screen interface, which includes: a touch screen connector; and a power supply noise isolation circuit, the power supply noise isolation circuit including a π-type filter network. This π-type filter network consists of a ferrite bead connected in series between a system power supply and the power supply pin of the touch screen connector, and two capacitors located between the two ends of the ferrite bead and ground, respectively, to suppress the conduction of power supply noise generated by the high-speed digital signals of the display interface module to the touch screen connector. It can be understood that this solution aims to provide a highly clean operating power supply for the touch screen controller to avoid interference from high-speed digital signals on touch detection accuracy. The analog front-end inside the touch controller is extremely sensitive to power supply noise, and high-speed display interfaces such as MIPI-DSI inject a large amount of high-frequency noise into the system power bus during operation. This solution achieves effective isolation of the touch controller power supply at the radio frequency layer by setting a π-type filter network composed of a ferrite bead and capacitors. The high-frequency impedance characteristics of the ferrite bead can block the conduction path of digital noise, while the capacitors at its two ends provide stable energy storage and high-frequency bypass for the local circuit. This dedicated power supply noise isolation design improves the signal-to-noise ratio of the touch controller's power supply, directly enhancing the accuracy of touch positioning and the stability of response, thereby ensuring the reliability of the entire human-computer interaction system.

[0018] Furthermore, the motherboard circuit system of the present invention also includes a main logic power control circuit for the second display interface. The main logic power control circuit includes: a power switch transistor connected in series between a system power supply and a logic power output terminal for powering the display screen connected to the second display interface; a control transistor whose conduction and cutoff are controlled by an enable signal from the main control chip, the output terminal of the control transistor being connected to the control electrode of the power switch transistor; wherein, a pull-down resistor is also connected between the base of the control transistor and ground to provide a default low-level bias, so as to ensure that the control transistor remains in the cutoff state when the enable signal is in a high-impedance state, thereby keeping the power switch transistor in the off state.

[0019] This solution aims to ensure the main logic power supply of the LVDS screen is reliably off when the system is not fully ready, preventing damage to the screen from abnormal power-on. This is achieved through a fail-safe circuit consisting of pull-down resistors. When the enable signal of the main control chip is in a high-impedance state (e.g., during system power-on initialization or software malfunction), the pull-down resistor provides a defined low level to the base of the control transistor, forcibly keeping the main power switch off. This design provides a clear "default off" state for the power control logic, effectively avoiding unexpected power-on problems caused by floating or undefined control signals, thus significantly enhancing the system's robustness and the determinism of the power-on sequence.

[0020] Furthermore, a capacitor is connected in parallel between the control electrode and the source of the power switch transistor. This capacitor, together with the pull-up resistor connected to the control electrode, forms an RC network to smooth the turn-on speed of the power switch transistor, thereby suppressing the inrush current generated when the display screen connected to the second display interface is powered on. It can be understood that this solution aims to smooth the turn-on process of the power switch transistor, avoiding a drop in the main power supply voltage or damage to components due to a sudden surge in current. The LVDS display screen and its onboard filter capacitor act as a large capacitive load at the moment of power-on. If the power switch transistor is turned on instantaneously, a very large charging current peak will be generated. This solution constructs an RC network between the control electrode and the source of the power switch transistor, utilizing the physical characteristic that capacitor voltage cannot change abruptly, to make the control electrode voltage of the switch transistor change slowly, thus changing its conduction process from "instantaneous" to "gradual." This soft-start design significantly reduces the peak value of the inrush current and broadens its duration, effectively protecting the stability of the main system power supply and the reliability of the power switch transistor itself, improving the overall electrical performance and service life of the device.

[0021] Furthermore, the motherboard circuit system of the present invention also includes a TFT bias power supply generation circuit, which includes: a single-inductor boost converter for generating a first positive bias voltage; a first charge pump circuit and a second charge pump circuit, wherein the first and second charge pump circuits both reuse a high-frequency switching node inside the boost converter for operation, and are respectively used to generate a second positive bias voltage higher than the first positive bias voltage and a negative bias voltage; wherein a current-limiting resistor for achieving soft start is connected in series on the output path of the second positive bias voltage; and Zener diodes for achieving overvoltage or undervoltage clamping protection are respectively connected in parallel at the respective output terminals of the second positive bias voltage and the negative bias voltage.

[0022] This solution aims to generate multiple critical bias voltages with specific timing and voltage ranges required for TFT-LCD panel operation with minimal components and PCB area. It utilizes a single-core, dual-pump topology, employing a single-inductor boost converter to generate the main analog voltage and multiplexing its internal switching nodes to drive two sets of passive charge pumps to generate the gate-on positive voltage and gate-off negative voltage respectively, achieving higher integration. This structure inherently ensures that the main analog voltage takes precedence over the gate voltage during power-on, meeting the panel's reliability requirements. Furthermore, the solution employs a series current-limiting resistor to achieve soft-start of the gate voltage, preventing power-on overshoot; and a parallel Zener diode provides final hardware overvoltage / undervoltage clamping protection for the gate positive and negative bias voltages, ensuring that the expensive display panel will not be damaged by abnormal bias voltages under most operating conditions.

[0023] Furthermore, the motherboard circuit system of the present invention also includes an LED backlight driving circuit, which includes: a constant current driving chip for driving the LED backlight; and a current sampling network connected to the feedback pin of the constant current driving chip. The current sampling network is composed of at least two precision resistors connected in parallel to distribute the total current flowing through the network, thereby reducing the power stress of a single resistor and achieving a balanced heat distribution.

[0024] Understandably, this solution aims to address the potential overheating and reliability issues of a single current sampling resistor in high-power backlight drivers. In constant-current drive circuits, the current sampling resistor is a core feedback component, and its heat generation and stability directly affect the accuracy and lifespan of the backlight brightness. This solution uses at least two precision resistors connected in parallel to form the overall sampling network. This design is not simply a combination of resistance values; its innovation lies in: 1. Dividing the total sampling current, significantly reducing the actual power borne by each resistor, achieving a power level far below its rated power, thereby greatly improving power margin and long-term operational reliability. 2. Distributing the heat source from a concentrated point to multiple physical locations, achieving a balanced heat distribution on the PCB board, avoiding the formation of localized hotspots, and improving the overall heat dissipation performance.

[0025] Furthermore, the LED backlight driving circuit also includes an analog dimming conversion circuit, which includes an RC low-pass filter composed of resistors and capacitors, used to convert the PWM dimming signal from the main control chip into a stable DC voltage; wherein the stable DC voltage is injected into the feedback pin of the constant current driving chip, and the constant DC current flowing through the LED backlight is smoothly changed by adjusting the feedback reference to achieve noiseless analog dimming.

[0026] Understandably, this solution aims to eliminate the audible noise and color shift issues that can arise from traditional PWM direct dimming. Traditional digital dimming methods use high-frequency switching of LED strings to adjust brightness. This rapid current switching causes mechanical vibration in the inductors and ceramic capacitors, producing an audible whistling sound. This solution uses an RC low-pass filter to smoothly convert the input PWM signal into a stable DC voltage. This DC voltage is then used to adjust the feedback reference of the constant current driver chip, thereby achieving linear, analog adjustment of the LED drive current. Under this solution, the LED always operates in a constant DC state, with only the current magnitude changing, thus physically eliminating switching noise. Simultaneously, the stable DC drive ensures the consistency of the LED's spectral characteristics at different brightness levels, resulting in better color fidelity.

[0027] Furthermore, the motherboard circuit system of the present invention also includes an adaptive level-shifting backlight control interface, which includes: a level-shifting chip, whose input terminal receives a backlight control signal operating in a first voltage domain from the main control chip, and whose output terminal outputs a backlight control signal operating in a second voltage domain; and an output enable control circuit, which includes a pull-up resistor connected between the power supply in the first voltage domain and the output enable pin of the level-shifting chip. The pull-up resistor provides a hardware default high level for the output enable pin, while allowing the main control chip to actively pull the output enable pin low to achieve software gating.

[0028] This solution aims to address potential logic level mismatches between the main control chip and the backlight driver board, providing a gating mechanism that combines a hardware default safety state with fine-grained software control. First, a dedicated level conversion chip reliably converts signals between different voltage domains. Its core innovation lies in controlling the chip's output enable (OE) pin: a pull-up resistor provides a hardware "default enable" state for the OE pin, ensuring the backlight control channel is in a known ready state during uncertain phases such as system initialization, preventing abnormal output. Simultaneously, this pull-up resistor design allows the main control chip's GPIO to actively pull it low with extremely low drive capability, giving the software the ability to precisely turn the backlight control signal on or off at any time, or instantly cut it off in emergencies. This combined hardware and software design significantly improves the system's power-on / off experience and operational reliability.

[0029] The technical effects of the multi-screen compatible embedded motherboard circuit system and its display self-adaptation method of the present invention include: First, by connecting multiple display interface signal paths of different standards to the same set of multiplexed signal pins of the main control chip, and selectively activating one of the interface functions through software configuration, the motherboard's display interface capabilities are expanded at zero additional hardware cost. This design directly eliminates the need for external protocol conversion chips such as MIPI-to-LVDS commonly used in existing technologies, which not only significantly reduces bill of materials (BOM) costs, but also simplifies PCB design complexity, reduces system power consumption, and improves signal transmission reliability by reducing the number of components and high-speed signal conversion steps.

[0030] Secondly, the configurable screen power supply module of this invention provides multiple existing voltage rails on the motherboard for the display interface to choose from through a simple physical jumper interface. The operator can manually configure the operating voltage according to the actual needs of the display screen. This purely hardware-based configuration method is intuitive and reliable, avoiding the risk of damage to the display screen due to incorrect output voltage caused by software errors or system anomalies. This design decouples the motherboard hardware from the display screen's power supply specifications, enabling a single hardware platform to safely and conveniently adapt to peripheral devices requiring different operating voltages, significantly enhancing the product's versatility and adaptability to supply chain changes.

[0031] The combination of these two technical features provides embedded product developers with a versatile electronic circuit hardware platform. Manufacturers no longer need to design, manufacture, and stock multiple motherboard models for screens with different interfaces or power supply specifications, thereby significantly simplifying product line management (SKU), reducing R&D, production, and inventory costs, and accelerating product integration and time-to-market.

[0032] Furthermore, the display self-adaptation method proposed in this invention places the selection of the power supply voltage, which is crucial for electrical safety, in the pure hardware configuration stage before the system is powered on. It utilizes the connection of physical components to ensure the absolute correctness of the power supply, eliminating the possibility of hardware damage due to software errors from the operational process, effectively improving the safety and reliability of system integration. Simultaneously, it reduces the complex pin function switching and screen parameter configuration to standardized modifications of the device tree file, making the adaptation of different screens streamlined, repeatable, and easy to manage. This hardware-first, software-later, step-by-step adaptation process not only clearly defines the hardware safety boundaries and software functional boundaries but also makes the entire adaptation process efficient and controllable, significantly reducing the debugging difficulty and time cost for developers when replacing displays. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This is a circuit schematic of the HDMI output interface in the embodiment; Figure 2 This is a circuit schematic diagram of the MIPI display interface and touch screen interface in an embodiment of the present invention; Figure 3 This is a circuit diagram of a single-channel LVDS display interface and backlight driving circuit in an embodiment of the present invention; Figure 4 yes Figure 3 The circuit diagram of the sub-module related to the J34 connector and its peripheral circuitry; Figure 5 yes Figure 3 The circuit diagram of the sub-module for electrostatic discharge (ESD) protection circuit of LVDS high-speed signal; Figure 6 yes Figure 3 The circuit diagram of the sub-module related to the backlight driving circuit; Figure 7 yes Figure 3 The circuit diagram shows the power supply circuit for providing TFT bias voltage to the LCD panel. Figure 8 yes Figure 3 The circuit diagram of the sub-module related to the main logic power control circuit of the screen; Figure 9 yes Figure 3 A partial diagram of the peripheral auxiliary circuit structure; Figure 10 yes Figure 3 The circuit diagram of the sub-module related to the backup touch panel interface; Figure 11 This is a circuit schematic diagram of the signal multiplexing LVDS interface and configurable power supply module in an embodiment of the present invention; Figure 12 yes Figure 11 The pin definitions and layout circuit diagram for the J17 connector are included. Figure 13 yes Figure 11 The circuit diagram for the adaptive level conversion backlight control interface is included. Figure 14 This is a flowchart of step one of the display self-adaptation method steps for the circuit system of the embodiment to switch from MIPI-DSI to LVDS; Figure 15 This is a flowchart of step two of the display self-adaptation method for switching the circuit system from MIPI-DSI to LVDS in the embodiment. Figure 16 This is a flowchart of step three of the display self-adaptation method for switching the circuit system from MIPI-DSI to LVDS in the embodiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0036] like Figures 1 to 13As shown, this embodiment provides a multi-screen compatible embedded motherboard circuit system. This system is integrated onto a single printed circuit board (PCB), and its core components include a main control chip, a display interface module, and a configurable screen power supply module. In this embodiment, the main control chip can be the Rockchip RK3568 processor. This processor integrates a display controller supporting multiple display standards (including MIPI-DSI and LVDS) and provides general-purpose input / output ports (GPIO) with pin multiplexing capabilities.

[0037] To achieve broad physical compatibility, the display interface module of this system also includes an HDMI display interface directly driven by a dedicated HDMI controller from the main control chip. Please refer to [link / reference]. Figure 1 The physical carrier of this HDMI display interface is a standard HDMI Type A connector J12, which is used to connect external high-definition display devices.

[0038] Please see Figure 2 , Figure 3 and Figure 11 The display interface module in this system includes at least one first display interface and one second display interface. In this embodiment, the first display interface is a MIPI-DSI interface, and its physical carrier is... Figure 2 The 40-pin FPC connector J13 shown is used to connect a display screen that conforms to the MIPI-DSI display standard. The second display interface is an LVDS interface, and its physical carrier can be... Figure 3 The 40-pin FPC connector J34 shown is for single-channel LVDS or Figure 11 The 30-pin dual-row connector J17 shown is for single / dual-channel LVDS. Both interfaces are used to connect displays that conform to the LVDS display standard.

[0039] One of the core design features of this embodiment lies in the physical multiplexing of signals. For example... Figure 2 and Figure 11 As shown, a set of multiplexed signal pins of the main control chip are designed, at the PCB routing level, to be electrically connected simultaneously to the signal terminals of the first display interface (connector J13) and the second display interface (connector J17). Specifically, the MIPI-DSI1-DOP / N differential signal lines originating from the main control chip are not only routed to pins 8 and 9 of connector J13, but also physically connected to pins 8 and 10 of connector J17. Similarly, other MIPI-DSI data and clock signal lines also share a common path with the corresponding pins of connector J17.

[0040] This physical common-path design allows the multiplexed signal pins to be switched via software. Specifically, this is achieved by modifying the Device Tree configuration file of the embedded operating system (such as Linux). The Device Tree is a data structure describing hardware topology and configuration information; the operating system kernel parses this file during startup to initialize the hardware. Developers can edit the Device Tree file, setting the status attribute of the hardware node corresponding to the MIPI-DSI controller to "enabled" and the status attribute of the hardware node corresponding to the LVDS controller to "disabled". When the system starts according to this configuration, the kernel's pin control subsystem instructs the main control chip to configure the multiplexed signal pins to the first operating mode, i.e., MIPI-DSI mode. In this mode, the electrical signals output by the pins conform to the MIPI-DSI standard in terms of protocol, timing, and level characteristics, thereby directly driving the first display interface J13, which is physically connected to it. Conversely, if the LVDS controller node is enabled and the MIPI-DSI controller node is disabled in the device tree, the same set of pins will be configured to the second operating mode, i.e., LVDS mode, upon system startup. This outputs signals conforming to the LVDS standard, directly driving the second display interface J17 or J34. At any given time, only one display controller and its corresponding physical interface are active, avoiding signal conflicts. This design achieves native hardware support for two different display standards by utilizing the built-in functions of the main control chip without adding any external protocol conversion chips.

[0041] Please see Figure 11 To address the issue of varying power supply voltages for different LVDS displays, this system also includes a configurable screen power supply module. The core of this module is a power selection interface, specifically a 5-pin single-row connector J15 in this embodiment. This module utilizes multiple existing power rails on the motherboard. Specifically, pins 2, 4, and 5 of connector J15 serve as input terminals, electrically connected to the 3.3V power rail (VCC3V3_LCD0), 5V power rail (VCC5V0_SYS), and 12V power rail (VCC12V_DCIN) on the motherboard, respectively. Pins 1 and 3 of connector J15 serve as output terminals, both connected to a power network named VCC_LVDS. This VCC_LVDS power network is directly connected to the second display interface (such as...). Figure 11 Connect the power pin of connector J17 in the middle.

[0042] During operation, the user can determine the required operating voltage according to the specifications of the LVDS display to be connected. If 3.3 volts is required, use a jumper cap or other physical device to short-circuit pins 1 and 2 of connector J15; if 5 volts is required, short-circuit pins 3 and 4. By inserting or shorting these physical devices, one of the multiple input terminals can be selected to connect to the output terminal, thus providing a precisely matched and stable operating voltage to the display connected to the second display interface. This purely hardware-based configuration method, independent of software settings, is intuitive and reliable, fundamentally avoiding the risk of display damage due to voltage mismatch, and greatly improving the system's hardware compatibility and operational safety.

[0043] Therefore, this embodiment, through the collaborative design of signal multiplexing circuit and configurable screen power supply module, enables a single embedded motherboard to flexibly adapt to two mainstream displays, MIPI-DSI and LVDS, and can safely provide them with a variety of different operating voltages, achieving a high degree of hardware platform versatility.

[0044] Furthermore, please refer again. Figure 1 The HDMI display interface has a complete circuit structure, capable of providing stable and reliable high-definition video output. The circuit includes: (1) High-speed TMDS signal path: includes three pairs of data signals (HDMI_TX2P / N_PORT, etc.) and one pair of clock signals (HDMI_TXCLKP / N_PORT). Before being sent to connector J12, these signals are all serially passed through dedicated low-capacitance ESD protection devices U19 and U20 to provide electrostatic protection for the main control chip without affecting signal integrity.

[0045] (2) Low-speed control and communication path: This includes the DDC channel (DDC_SCL, DDC_SDA) for reading the EDID information of the display, and the HPD hot-plug detection channel for detecting the connection status of the display device. In the HPD signal path, not only is a pull-down resistor R219 provided to indicate an unconnected state, but a current-limiting resistor R218 is also connected in series before the signal input terminal of the main control chip. This series current-limiting resistor, working in conjunction with the ESD protection diode ED2, forms a two-stage protection system for the HPD signal line, effectively limiting the impact of external abnormal voltage or current surges on the main control chip and improving the reliability of the interface.

[0046] (3) Auxiliary circuit: including a +5V power output circuit for powering the EDID memory of the display device, and a matrix of test points (TP41 to TP53) set on each signal path for easy production testing and fault diagnosis.

[0047] Furthermore, in this embodiment, the aforementioned solution is further refined. The first display interface is specifically implemented as a MIPI-DSI interface, and the second display interface is specifically implemented as an LVDS interface. The power selection interface J15 is specifically implemented as a multi-pin jumper header, and the physical device is a standard jumper cap. The power rails provided on the motherboard for the power selection interface J15 specifically include three voltages: 3.3 volts (VCC3V3_LCD0), 5 volts (VCC5V0_SYS), and 12 volts (VCC12V_DCIN). These three voltage values ​​cover the operating voltage requirements of the vast majority of LVDS displays on the market.

[0048] Please see Figure 2 To achieve complete display and interactive functions, this system also includes a touchscreen interface. The physical carrier of this touchscreen interface is a 6-pin touchscreen connector J14. To ensure the accuracy and reliability of touch detection, this touchscreen interface integrates a power supply noise isolation circuit. This circuit consists of a π-type filter network, specifically: a ferrite bead FB5 is connected in series between the system power supply VCC3V3_TP and the power supply pin of the touchscreen connector J14; simultaneously, capacitors C324 and C325 are connected between the two ends of the ferrite bead FB5 and ground, respectively. High-speed MIPI-DSI signals couple a large amount of high-frequency noise to the system power bus during transmission, and the touch controller has extremely high requirements for power purity. The ferrite bead FB5 utilizes its high impedance characteristic at high frequencies to effectively block this noise from being conducted to the touch controller along the power path. At the same time, capacitors C324 and C325 provide a low-impedance local power bypass for the touch controller, further absorbing residual noise. The design of this power supply noise isolation circuit significantly improves the signal-to-noise ratio of the touch signal by providing a cleaner and more stable power supply to the touch controller, thereby ensuring the accuracy of touch positioning and the smoothness of operation.

[0049] Please see Figure 3 and Figure 8 To achieve precise power-on timing control of the display screen connected to the second display interface (LVDS interface), this system also includes a main logic power control circuit for the second display interface. The core of this circuit is a P-channel MOSFET power switch Q4, connected in series between the system power supply VCC3V3_SYS and a logic power output terminal VCC3V3_LCD0 for powering the display screen connected to the second display interface. The collector of an NPN control transistor Q5 is connected to the control electrode (gate) of the power switch Q4, and its conduction and cutoff are controlled by the enable signal LCD-EN from the main control chip. When LCD-EN is high, Q5 conducts, pulling the gate potential of Q4 low, thus turning Q4 on and providing logic power to the display screen.

[0050] The key feature of this circuit is the pull-down resistor R233 connected between the base of the control transistor Q5 and ground to provide a default low-level bias. This design establishes a fail-safe mechanism. During system power-on initialization or software malfunctions, the enable signal output by the main control chip may be in an uncertain high-impedance state. In this case, the pull-down resistor R233 ensures that the base of Q5 is reliably clamped to a low level, thus keeping the control transistor Q5 off. The off state of Q5 keeps the gate of Q4 high through the pull-up resistor R229, thereby keeping the power switch Q4 off. This design provides a clear "default off" state for the power control path, preventing accidental power-on due to floating control signals at the hardware level, effectively avoiding electrical shocks to the display screen, and enhancing the overall reliability of the system.

[0051] Furthermore, please refer again. Figure 8 To further optimize the performance of the main logic power control circuit, a capacitor C329 is connected in parallel between the gate and source of the power switch Q4. This capacitor C329, together with the pull-up resistor R229 connected to the gate, forms an RC network. When the control transistor Q5 is turned on, the presence of capacitor C329 prevents the gate voltage of the power switch Q4 from jumping instantaneously, instead causing it to smoothly decrease according to the discharge curve of the RC circuit. This mechanism smooths out the turn-on speed of the power switch. The display module exhibits a large capacitive load upon power-on. If the power switch turns on too quickly, a charging current with a very large peak value, i.e., a surge current, will be generated. This RC network significantly reduces the peak value of the surge current and broadens its duration by slowing down the turn-on speed of the switch, thereby effectively suppressing the surge current generated when powering on the display connected to the second display interface. This not only protects the stability of the main system power supply but also reduces the electrical impact on the power switch itself.

[0052] Please see Figure 3 and Figure 7To drive the TFT-LCD display screen normally, this system also includes an onboard TFT bias power supply generation circuit. The core of this circuit is an integrated power management chip, U23. The circuit contains a single-inductor boost converter composed of the internal circuitry of U23, inductor L12, and diode D30. This converter generates a first positive bias voltage, AVDD-LCD. The unique feature of this circuit is that it also includes a first charge pump circuit (composed of D31, C343, and C345) and a second charge pump circuit (composed of D33, C347, and C348). Both charge pump circuits reuse a high-frequency switching node LX within the boost converter to generate a second positive bias voltage, VGH-LCD, higher than the first positive bias voltage, and a negative bias voltage, VGL-LCD, respectively. This highly integrated topology uses only one core boost circuit to generate three key bias voltages, saving hardware costs and board space.

[0053] To ensure the reliability of the bias power supply, comprehensive protection measures are designed into the circuit of this embodiment. A current-limiting resistor R251 for soft-start is connected in series in the output path of the second positive bias voltage VGH-LCD. This resistor, together with the load-side capacitor, forms an RC network, ensuring that the VGH-LCD voltage builds up smoothly and avoiding voltage surges to the TFT gate. Furthermore, Zener diodes D32 and D34 are connected in parallel at the respective output terminals of the second positive bias voltage VGH-LCD and the negative bias voltage VGL-LCD to provide overvoltage or undervoltage clamping protection. When the output voltage attempts to exceed its safe operating range due to abnormal fluctuations, the corresponding Zener diode will break down, clamping the voltage to a preset safe value, thus providing final hardware-level electrical protection for the display panel.

[0054] Please see Figure 3 and Figure 6 This system also integrates a complete LED backlight driver circuit for illuminating the display screen's backlight. The core of this circuit is a constant current driver chip U22 used to drive the LED backlight. To precisely control the current flowing through the LEDs, a current sampling network is incorporated into the circuit, connected to the feedback pin FB of the constant current driver chip. This current sampling network consists of at least two precision resistors (R240 and R243) connected in parallel. When the backlight driver circuit is operating, the total return current flows through this parallel resistor network. The purpose of this parallel structure design is to distribute the total current flowing through the network, reducing the current flowing through each resistor, thereby reducing the power stress on individual resistors and achieving a more even heat distribution. This design not only improves the long-term reliability of the circuit under high power loads but also optimizes the PCB's thermal management performance by dispersing heat sources.

[0055] Furthermore, please refer again. Figure 6To achieve high-quality backlight brightness adjustment, the LED backlight driving circuit also includes an analog dimming conversion circuit. This circuit consists of an RC low-pass filter composed of resistor R245 and capacitor C338. This RC low-pass filter converts the PWM dimming signal LCD1_BL_PWM4 from the main control chip into a stable DC voltage. The PWM dimming signal is a digital signal with a variable pulse width, whose duty cycle is proportional to the desired brightness level. After integration processing by the RC low-pass filter, this digital pulse signal is converted into a smooth DC voltage with an amplitude proportional to the PWM duty cycle.

[0056] The stable DC voltage is injected into the feedback pin FB of the constant current driver chip U22 through the injection resistor R246. The constant current driver chip internally adjusts the output current by comparing the difference between the voltage at the feedback pin and an internal reference voltage. By injecting this DC voltage, the chip's feedback reference is dynamically adjusted, making the current flowing through the LED backlight linearly related to this DC voltage value. This design smoothly changes the constant DC current flowing through the LED backlight by adjusting the feedback reference, achieving noiseless analog dimming. Compared to digital dimming methods that directly use PWM signals to switch the LED, this solution ensures that the LED always operates in a stable DC state, fundamentally eliminating inductor howling and ceramic capacitor vibration noise that may be caused by rapid current switching, while also ensuring the consistency of the LED's spectral characteristics at different brightness levels.

[0057] Please see Figure 11 and Figure 13 To ensure compatibility with backlight modules operating at different logic levels and to achieve precise timing control, this system also includes an adaptive level-shifting backlight control interface. The core of this interface is a dual-channel level-shifting chip, U21. The chip's A-side reference voltage VCCA is connected to the motherboard's 3.3V logic power supply VCC3V3_LCD0, and its B-side reference voltage VCCB is connected to the 5V system power supply VCC5V0_SYS. Its input terminals (A1, A2) receive backlight control signals (LCD-BL-EN and LCD0_BL_PWM0) from the main control chip, operating in the first voltage domain (3.3V). Its output terminals (B1, B2) output backlight control signals operating in the second voltage domain (5V) with the same logic state, ultimately providing them to the external backlight module via connector J18.

[0058] The key design feature of this interface lies in its output enable control circuit. This circuit consists of a pull-up resistor R227 connected between the power supply VCC3V3_LCD0 in the first voltage domain and the output enable pin OE of the level conversion chip. This pull-up resistor provides a hardware default high level for the output enable pin, ensuring that during system power-up and main control chip initialization, as long as the 3.3V power supply is established, the level conversion channel is enabled by default, avoiding output uncertainty caused by a floating OE pin. Simultaneously, this pull-up resistor design allows the main control chip to actively pull the output enable pin low for software gating. A GPIO pin of the main control chip can be connected to the OE pin, disabling the level conversion chip's output at any time by outputting a low level. This structure combines the hardware's default safe state with fine-grained timing control in software, enabling the system to precisely control the backlight signal output timing at the software level, thus achieving a flicker-free power-on / off experience and quickly cutting off backlight control when system anomalies are detected, improving the overall reliability of the system.

[0059] In addition, combined Figure 14 , Figure 15 and Figure 16 As shown, this embodiment also provides a display self-adaptation method based on the above-mentioned multi-screen compatible embedded motherboard circuit system, enabling the system of this embodiment to adapt to and drive displays with different interface standards and power supply specifications through the coordinated work of hardware pre-configuration and software self-configuration. The following uses the example of switching the system from adapting to a MIPI-DSI display to adapting to an LVDS display to illustrate the specific steps of this method: The first step is hardware-level adaptation. This step is performed with the motherboard powered off. First, determine the required logic operating voltage according to the specifications of the display screen to be connected, which conforms to the second display standard (LVDS standard). Then, select a matching operating voltage for the power pins of the second display interface (LVDS interface) by plugging and unplugging or shorting the physical components (jump caps) on the power selection interface J15. Specifically, if the display screen requires a 5-volt operating voltage, use jump caps to short the two pins on connector J15 that are connected to the 5-volt power rail and the VCC_LVDS output network, respectively. After completing this physical configuration, connect the LVDS display screen's data cable to the LVDS interface (J17 or J34) on the motherboard.

[0060] The second step is software-level adaptation. This step is achieved by modifying the device tree file in the operating system. Developers need to locate the device tree file (with the suffix .dts or .dtsi) corresponding to the motherboard hardware in the embedded operating system's source code. In this file, the controller node corresponding to the second display interface (LVDS interface) is set to enabled (status = "okay"), while the controller node corresponding to the first display interface (MIPI-DSI interface) is set to disabled (status = "disabled"). The purpose of this operation is to instruct the operating system kernel on how to configure the pin multiplexing function of the main control chip at startup. In addition, detailed parameters matching the connected LVDS display need to be filled into the enabled LVDS controller node, including resolution, video timing parameters, and backlight control pin definitions. After completing the modifications, the kernel and device tree are recompiled to generate new system firmware and burned to the motherboard.

[0061] The third step is system startup and self-adaptation. The embedded motherboard circuit system is powered on and started. The system bootloader loads the kernel and the modified device tree file. During kernel initialization, the pin control subsystem parses the configuration in the device tree and configures the corresponding set of multiplexed signal pins of the main control chip to the second operating mode (LVDS mode). Subsequently, the kernel loads the corresponding LVDS display driver according to the configuration in the device tree file. This driver initializes the LVDS display controller inside the main control chip according to the parameters defined in the device tree and begins outputting video signals through the LVDS interface to light up the display screen. At this point, the entire self-adaptation process is complete.

[0062] Preferably, please refer to Figure 3 , Figure 4 and Figure 11 In this embodiment, to adapt to display modules with different backlight control logics, a hardware abstraction layer is designed on the backlight control circuit. Specifically, selectively mountable 0-ohm resistors R234 and R236 are connected in series in the paths of the pulse width modulation brightness adjustment signal (LED_PWM) and the backlight enable signal (CABC_EN) connected to the display connector J34. This design allows for flexible connection or disconnection of one or both control signals during the production assembly stage, depending on the specific specifications of the selected screen material, by selectively mounting or not mounting these two resistors. By using different mounting combinations of these two resistors, the same motherboard hardware can seamlessly adapt to various heterogeneous backlight control schemes, such as those requiring only PWM dimming, only an enable switch, or both, significantly enhancing the reusability of the hardware platform.

[0063] Preferably, please refer to Figure 3 and Figure 5 In this embodiment, to maximize the integrity of high-speed signals within a limited PCB space, the system employs a hybrid topology for ESD protection of the LVDS interface. Specifically, for the four pairs of core differential signals LVDS0_D1 to LVDS0_D3 and LVDS0_CLK, integrated ESD protection arrays ED14 and ED15 with low capacitance and high channel consistency are used. For the LVDS0_D0 differential signal pair, two discrete TVS diodes D48 and D49 with smaller package sizes are used. This asymmetrical design aims to provide layout flexibility, allowing discrete components to be compactly placed in the optimal physical location of the signal traces, thereby minimizing the signal stumps introduced by the protection devices and effectively avoiding signal reflection and impedance mismatch problems that may be caused by layout constraints. It is an optimization scheme that prioritizes the overall signal integrity of the system.

[0064] Preferably, please refer to Figure 3 and Figure 9 In this embodiment, the system also includes several auxiliary circuits to improve display quality and hardware compatibility. 1. To ensure reliable initialization of the display screen, a hardware power-on reset circuit consisting of pull-up resistor R228 and capacitor C331 is integrated. This circuit is independent of the processor software state and can automatically generate a defined low-level reset pulse on the LCD-RST signal line when power is established. 2. To ensure compatibility with displays of different physical scanning directions, a hardware-configurable scanning direction control circuit is designed. By selectively mounting resistors R253 / R256 and R254 / R257, the L / R (left / right scan) and U / D (up / down scan) control pins can be configured to high or low levels without software modification. 3. To guarantee display quality, a highly stable reference generation circuit is designed for the screen common electrode voltage VCOM. This circuit consists of high-precision resistors R247 and R248 and energy storage capacitor C340, providing an accurate initial voltage reference and effectively suppressing dynamic load fluctuations.

[0065] Preferably, please refer to Figure 2 , Figure 3 and Figure 10In this embodiment, to maximize compatibility with touchscreen modules from different sources, the system designs a parallel, selectable touch panel interface scheme. Specifically, a 6-pin FPC connector J19 has signal definitions completely consistent with the aforementioned touchscreen connector J14. In terms of circuit routing, all signal pins of J19 (including I2C bus, interrupt, and reset signals) are connected in parallel with their corresponding signal pins of J14. This design allows the motherboard to be physically compatible with touchscreen modules of at least two different FPC specifications. During actual assembly, depending on the purchased materials, the FPC can be selectively inserted into either J19 or J14, while the other remains unused. This binary hardware redundancy design significantly enhances the product's supply chain resilience.

[0066] Preferably, please refer to Figure 11 and Figure 12 In this embodiment, to enhance the system's intelligence and operational reliability, the LVDS interface connector J17 is designed as an integrated intelligent display panel control interface. In addition to the high-speed LVDS data channel, this interface integrates an I2C communication bus (SDA / SCL), enabling the main control system to read the EDID information inside the screen and thus automatically configure display parameters. Simultaneously, this interface integrates a series of control signals such as panel reset (RST) and backlight control (BL / BEN), providing a hardware path for advanced power management in the main system. Furthermore, multiple ground pins of this connector are interspersed among the high-speed signal pins, forming an effective ground shield and providing a low-impedance return path for high-speed differential signals, physically ensuring signal integrity and anti-interference capabilities.

[0067] Preferably, to further improve the power integrity and operational reliability of the system, the auxiliary circuit design in this embodiment also includes the following optimization schemes. Please refer to... Figure 6 At the boost output of the LED backlight driver circuit, a multi-stage parallel output filter capacitor network is employed. This network consists of multiple capacitors (C332 to C336) with different capacitance values ​​and packages connected in parallel. Compared to conventional designs using a single large-capacity capacitor, this parallel capacitor array significantly reduces the total equivalent series inductance (ESL), thereby providing a lower impedance path over a wider frequency band and more effectively filtering out high-frequency ripple and noise generated by the switching operation of the boost converter. This design provides a cleaner and more stable DC power supply for the LED backlight string, helping to extend LED lifespan and reduce electromagnetic interference (EMI).

[0068] Preferably, please refer to again. Figure 2 and Figure 10This system employs differentiated power integrity schemes, each with its own emphasis, for the two parallel touch panel interfaces (J14 and J19). For the J14 interface, a π-type filter network focusing on high-frequency noise isolation is used; while for the J19 interface, a large-capacity 4.7 μF decoupling capacitor C337 is placed near its power input pin. This large-capacity capacitor primarily serves to meet the instantaneous high current demands generated by the touch controller during high-frequency scanning or rapid internal logic state transitions, effectively suppressing power bus voltage drops caused by current surges by providing a local charge storage pool. This power scheme, offering different optimization directions for redundant interfaces with identical functions, reflects a deep consideration and adaptive design of the subtle differences in the electrical characteristics of different peripheral modules.

[0069] Preferably, please refer to Figure 4 and Figure 7 This system integrates further optimized circuitry for display control logic and image quality assurance. 1. Regarding backlight control, in addition to supporting standard PWM dimming and enable signals, this system also provides support for Content Adaptive Backlight Control (CABC) via pin 37 (CABC_EN) of connector J34. This hardware path allows the motherboard to work collaboratively with advanced display modules supporting CABC technology, dynamically adjusting the backlight intensity based on the real-time brightness of the displayed content, thereby achieving significant power savings while ensuring visual quality. 2. Regarding image quality assurance, the precision voltage divider network (R247, R248) in the TFT bias power supply generation circuit, used to generate the common electrode voltage VCOM, has its input taken from the first positive bias voltage AVDD-LCD. This design establishes an inherent proportional relationship between the VCOM voltage and the AVDD-LCD voltage. When the AVDD-LCD experiences slight fluctuations due to load changes, the VCOM voltage fluctuates proportionally, thereby maintaining the stability of the core voltage difference required to drive the liquid crystal. This effectively suppresses color shift and display crosstalk that may be caused by such fluctuations, ensuring color fidelity under various operating conditions.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-screen compatible embedded motherboard circuit system, characterized in that, include: One main control chip; A display interface module, the display interface module including at least one first display interface and at least one second display interface, the first display interface and the second display interface being used to connect to a display screen conforming to a first display standard and a second display standard, respectively; Among them, a set of reusable signal pins of the main control chip are electrically connected to the signal terminals of the first display interface and the second display interface simultaneously. The set of reusable signal pins is configured to selectively operate in a first working mode or a second working mode in response to software configuration, so as to output display signals that conform to the first display standard or the second display standard respectively, thereby directly driving the first display interface or the second display interface. It also includes a configurable screen power supply module, which includes: At least two power rails, each carrying a different voltage value; A power selection interface, wherein multiple input terminals of the power selection interface are electrically connected to the at least two power rails respectively, and its output terminal is electrically connected to a power pin of the second display interface; The power selection interface is used to select one of the plurality of input terminals to be connected to the output terminal by plugging or shorting physical devices, so as to provide the required operating voltage to the display screen connected to the second display interface.

2. The multi-screen compatible embedded motherboard circuit system according to claim 1, characterized in that, The first display interface is a MIPI-DSI interface, and the second display interface is an LVDS interface; the power selection interface is a multi-pin jumper header, and the physical device is a jumper cap; the at least two power rails include at least two of the following: 3.3V, 5V, and 12V power rails.

3. The multi-screen compatible embedded motherboard circuit system according to claim 2, characterized in that, The system also includes a touchscreen interface, which includes: Touchscreen connector; The power supply noise isolation circuit includes a π-type filter network, which consists of a ferrite bead connected in series between a system power supply and the power supply pin of the touch screen connector, and two capacitors located between the two ends of the ferrite bead and ground, respectively, to suppress the transmission of power supply noise generated by the high-speed digital signal of the display interface module to the touch screen connector.

4. The multi-screen compatible embedded motherboard circuit system according to claim 2, characterized in that, The system also includes a main logic power control circuit for the second display interface, the main logic power control circuit comprising: A power switching transistor is connected in series between a system power supply and a logic power output terminal for powering the display screen connected to the second display interface; The control transistor is turned on and off by an enable signal from the main control chip, and the output terminal of the control transistor is connected to the control terminal of the power switch transistor. A pull-down resistor is connected between the base of the control transistor and ground to provide a default low-level bias, ensuring that the control transistor remains in the off state when the enable signal is in a high-impedance state, thereby keeping the power switch transistor in the off state.

5. The multi-screen compatible embedded motherboard circuit system according to claim 4, characterized in that, A capacitor is connected in parallel between the control electrode and the source electrode of the power switch transistor. This capacitor, together with the pull-up resistor connected to the control electrode, forms an RC network to smooth the turn-on speed of the power switch transistor, thereby suppressing the surge current generated when the display screen connected to the second display interface is powered on.

6. The multi-screen compatible embedded motherboard circuit system according to claim 2, characterized in that, The system also includes a TFT bias power supply generation circuit, which includes: A single-inductor boost converter is used to generate a first positive bias voltage; The first charge pump circuit and the second charge pump circuit both reuse a high-frequency switching node inside the boost converter to generate a second positive bias voltage higher than the first positive bias voltage and a negative bias voltage, respectively. In the output path of the second positive bias voltage, a current-limiting resistor for soft-start is connected in series; and Zener diodes for overvoltage or undervoltage clamping protection are connected in parallel at the respective output terminals of the second positive bias voltage and the negative bias voltage.

7. The multi-screen compatible embedded motherboard circuit system according to claim 2, characterized in that, The system also includes an LED backlight driving circuit, which includes: A constant current driver chip used to drive LED backlighting; A current sampling network is connected to the feedback pin of the constant current drive chip. The current sampling network consists of at least two precision resistors connected in parallel to distribute the total current flowing through the network, thereby reducing the power stress of a single resistor and achieving a balanced heat distribution.

8. The multi-screen compatible embedded motherboard circuit system according to claim 7, characterized in that, The LED backlight driving circuit also includes an analog dimming conversion circuit, which includes: An RC low-pass filter, consisting of resistors and capacitors, is used to convert the PWM dimming signal from the main control chip into a stable DC voltage. The stable DC voltage is injected into the feedback pin of the constant current drive chip, and the constant DC current flowing through the LED backlight is smoothly changed by adjusting the feedback reference to achieve noiseless analog dimming.

9. The multi-screen compatible embedded motherboard circuit system according to claim 2, characterized in that, The system also includes an adaptive level shifting backlight control interface, which includes: The level conversion chip receives a backlight control signal operating in the first voltage domain from the main control chip at its input terminal, and outputs a backlight control signal operating in the second voltage domain at its output terminal. An output enable control circuit includes a pull-up resistor connected between the power supply in the first voltage domain and the output enable pin of the level conversion chip. The pull-up resistor provides a hardware default high level for the output enable pin and allows the main control chip to actively pull the output enable pin low to achieve software gating.

10. A display self-adaptation method for a multi-screen compatible embedded motherboard circuit system, applied to the embedded motherboard circuit system as described in any one of claims 1 to 9, characterized in that, Includes the following steps: Based on the specifications of the display screen to be connected that conforms to the second display standard, a matching operating voltage is selected for the power pins of the second display interface by plugging or shorting physical components on the power selection interface. By modifying the device tree file in the operating system, the state of the controller node corresponding to the second display interface is set to enabled, while the state of the controller node corresponding to the first display interface is set to disabled. Power on and start the embedded motherboard circuit system so that the system kernel configures the group of multiplexable signal pins of the main control chip to the second working mode according to the configuration of the device tree file, and loads the corresponding driver to light up the display screen.

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