High-speed low-power-consumption comparator

Abstract

The invention discloses a low-power-consumption high-speed two-stage dynamic comparator for an analog-to-digital converter, relates to the technical field of integrated circuits, and aims to solve the problems that a traditional dynamic comparator is high in power consumption, limited in speed and uncontrollable in balance between offset voltage and performance. The comparator comprises a two-stage dynamic structure of a pre-amplification stage and a latch stage, wherein the pre-amplification stage takes a PMOS transistor as an input tube and is matched with an NMOS switching tube and a PMOS active load tube to realize preliminary amplification of an input differential signal; the latch stage adopts a PMOS latch structure instead of a traditional NMOS latch structure. And through two paths of delay controllable clock signals (clkb1 and clkb2), the latch stage is controlled to be activated in a delayed manner after the preamplifier stage works for a preset time, and meanwhile, a current source of the preamplifier stage is closed when the latch stage is activated. By adjusting latch level delay time, offset voltage, power consumption and speed can be flexibly balanced, performance requirements of different analog-to-digital converters are met, and the analog-to-digital converter is suitable for scenes such as portable equipment, communication systems and the like with high requirements on energy efficiency and speed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a high-speed, low-power comparator. Background Technology

[0002] In the field of analog and mixed-signal integrated circuits, comparators, as key building blocks for analog-to-digital signal conversion, directly determine the accuracy and efficiency of the entire system. They are widely used in core circuits such as high-speed analog-to-digital converters, memory-sensor amplifiers, and data receiving interfaces. With the rapid development of the Internet of Things, wearable devices, and mobile communication technologies, unprecedented stringent requirements have been placed on integrated circuits for the coordinated optimization of high speed and low power consumption. As a critical node in the signal chain, high-speed, low-power comparators have become a current research hotspot and challenge.

[0003] Traditional high-speed comparator architectures primarily rely on latch-type structures with preamplifier stages. This structure uses a preamplifier to initially amplify the weak input differential signal, overcoming random offset voltage caused by mismatch in subsequent latches and effectively isolating the input signal from switching noise (i.e., kickback noise) generated during the latch regeneration stage. However, this architecture faces a fundamental contradiction in pursuing high speed: the preamplifier itself needs sufficient gain and bandwidth to ensure response speed and suppress offset, but this typically consumes a large static bias current, leading to a significant increase in power consumption, and the additional cascade delay it introduces becomes a bottleneck for improving the overall comparator speed. Furthermore, to achieve high input impedance and low offset, the preamplifier often uses differential pair transistor loads, whose static power consumption persists throughout the entire comparator cycle, resulting in significant energy waste in intermittently operating systems (such as successive approximation ADCs).

[0004] In recent years, researchers have proposed numerous improvement schemes to achieve a better trade-off between speed, power consumption, accuracy, and noise. For example, they have employed offset storage techniques, introduced charge-pumped input structures to improve gain, or designed pipelined comparator strategies that interleave multi-stage dynamic amplifiers and latches. However, these techniques often come at the cost of increased circuit complexity, clock phase overhead, or placement and routing difficulties. Furthermore, as semiconductor process nodes continue to evolve towards the nanoscale, supply voltages are constantly decreasing, posing a series of avalanche challenges to comparator design: at low voltages, the intrinsic gain of transistors decreases, leading to performance degradation in the amplification stage; the signal swing shrinks, making the comparator less tolerant to noise and offset; and the short-channel effect of transistors exacerbates process variations and instability in performance.

[0005] Therefore, the current state of the technology clearly demonstrates that developing an innovative comparator solution that can fundamentally optimize speed and power consumption synergistically without significantly increasing circuit complexity or relying on expensive calibration techniques, while also possessing good offset characteristics, low kickback noise, and strong robustness to advanced low-voltage processes, has become an urgent technical challenge for the industry. This patented invention aims to provide a novel circuit architecture and operating method to overcome the performance bottlenecks of existing technologies, precisely against this backdrop. Summary of the Invention

[0006] This invention proposes a high-speed, low-power comparator.

[0007] This invention proposes a high-speed, low-power comparator, specifically comprising: a first-stage preamplifier stage and a second-stage latch stage; using a PMOS transistor as the input transistor, paired with an NMOS switch and a PMOS active load transistor. A clock signal clk controls the switching transistor to turn on / off, realizing the operation and shutdown of the preamplifier stage; the PMOS input transistor, with its superior matching, helps reduce offset voltage; innovatively using a PMOS latch structure instead of a traditional NMOS latch; delayed activation of the latch stage is achieved through two delay-controllable clock signals, clkb1 and clkb2; the preamplifier stage first operates for a preset time to amplify the input signal, then the latch stage starts, and simultaneously the preamplifier stage current source is turned off, reducing redundant power consumption.

[0008] The low power consumption in the preamplifier stage allows us to design the input transistors (PMOS transistors M3 and M4) to be large enough to achieve high preamplifier gain without worrying about the high power consumption in the first stage. Due to the high gain in the preamplifier stage, the delay in the latch stage is shortened. Furthermore, the common-mode voltage at the preamplifier output node is sufficiently low at the start of latch stage operation to strongly activate the input PMOS transistors M10 and M11 in the latch stage. Therefore, the comparator speed is increased without the cost of power consumption or speed reduction. The proposed comparator achieves the advantages of low power consumption and high speed at an acceptable bias voltage.

[0009] In the first-stage preamplifier, the gate of NMOS transistor M1 is connected to the clock signal clk, the source is grounded, and the drain is connected to the drain of PMOS transistor M3; the gate of NMOS transistor M2 is connected to the clock signal clk, the source is grounded, and the drain is connected to the drain of PMOS transistor M4; the gate of PMOS transistor M3 is connected to the differential input Vin+, the drain is connected to the drain of NMOS transistor M1, and is also connected to the gate of PMOS transistor M10 at node O1-, and the source is connected to the drain of M5; the gate of PMOS transistor M4 is connected to the differential input Vin-, the drain is connected to the drain of M2, and is also connected to the gate of PMOS transistor M11 at node O1+, and the source is connected to the drain of M5; the gate of PMOS transistor M5 is connected to the clock signal clkb1, the source is connected to the power supply Vdd, and the drain is connected to the drains of PMOS transistors M3 and M4.

[0010] In the second latching stage, the gate of NMOS transistor M6 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out-. It is also connected to the drain of PMOS transistors M10, M13, M9, and M8. The gate of NMOS transistor M7 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out+. It is also connected to the drain of PMOS transistors M11, M8, M12, and M9. The gate of NMOS transistor M8 is connected to node Out+, its source is grounded, and its drain is connected to node Out-. The gate of NMOS transistor M9 is connected to node Out-, its source is grounded, and its drain is connected to node O. ut+; PMOS transistor M10's gate is connected to node O1-, its source is connected to the drain of PMOS transistor M12, and its drain is connected to node Out-; PMOS transistor M11's gate is connected to node O1+, its source is connected to the drain of PMOS transistor M13, and its drain is connected to node Out+; PMOS transistor M12's gate is connected to node Out+, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M10; PMOS transistor M13's gate is connected to node Out-, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M11; PMOS transistor M14's gate is connected to clock signal clkb2, its source is connected to power supply Vdd, and its drain is connected to the sources of PMOS transistors M12 and M13.

[0011] The present invention discloses a high-speed, low-power comparator, the main features of which are: 1. The delay line controller generates clkb1 and clkb2 clock signals to realize latch stage delay activation. This solves the problem that the delay in traditional circuits depends on the preamplifier stage output charging to the NMOS threshold voltage, which is uncontrollable and affected by the input common-mode voltage. The delay can be adjusted according to the requirements to balance offset, speed and power consumption.

[0012] 2. At the start of the latch stage operation, the common-mode voltage at the output node of the preamplifier is low enough to strongly activate the input PMOS transistors of the latch stage; therefore, the comparator speed is increased without the cost of power consumption or speed reduction.

[0013] 3. It can be expanded into an NMOS preamplifier and latch stage structure, sacrificing some offset voltage for higher speed, and adapting to different performance requirements. At the same time, the proposed comparator is robust to overlapping control signals, because overlapping signals only slightly affect power consumption and do not affect accuracy. Attached Figure Description

[0014] Figure 1 The diagram shows the proposed high-speed, low-power comparator structure.

[0015] Figure 2 The proposed clock control timing diagram for a high-speed, low-power comparator is shown.

[0016] Figure 3 The waveform shown is the typical output voltage waveform of the proposed comparator.

[0017] Figure 4 The relationship between the offset voltage of the proposed comparator and the latch stage delay is given. Detailed Implementation

[0018] The specific embodiments of the present invention are described below with reference to specific examples.

[0019] The proposed circuit is as follows Figure 1 As shown. The PMOS latch is used for the second stage of the comparator. The delay of the second stage is determined by... Figure 2 Clock mode control. The reset phase is the same as that of a conventional circuit.

[0020] In the first-stage preamplifier, the gate of NMOS transistor M1 is connected to the clock signal clk, the source is grounded, and the drain is connected to the drain of PMOS transistor M3; the gate of NMOS transistor M2 is connected to the clock signal clk, the source is grounded, and the drain is connected to the drain of PMOS transistor M4; the gate of PMOS transistor M3 is connected to the differential input Vin+, the drain is connected to the drain of NMOS transistor M1, and is also connected to the gate of PMOS transistor M10 at node O1-, and the source is connected to the drain of M5; the gate of PMOS transistor M4 is connected to the differential input Vin-, the drain is connected to the drain of M2, and is also connected to the gate of PMOS transistor M11 at node O1+, and the source is connected to the drain of M5; the gate of PMOS transistor M5 is connected to the clock signal clkb1, the source is connected to the power supply Vdd, and the drain is connected to the drains of PMOS transistors M3 and M4.

[0021] In the second latching stage, the gate of NMOS transistor M6 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out-. It is also connected to the drain of PMOS transistors M10, M13, M9, and M8. The gate of NMOS transistor M7 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out+. It is also connected to the drain of PMOS transistors M11, M8, M12, and M9. The gate of NMOS transistor M8 is connected to node Out+, its source is grounded, and its drain is connected to node Out-. The gate of NMOS transistor M9 is connected to node Out-, its source is grounded, and its drain is connected to node O. ut+; PMOS transistor M10's gate is connected to node O1-, its source is connected to the drain of PMOS transistor M12, and its drain is connected to node Out-; PMOS transistor M11's gate is connected to node O1+, its source is connected to the drain of PMOS transistor M13, and its drain is connected to node Out+; PMOS transistor M12's gate is connected to node Out+, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M10; PMOS transistor M13's gate is connected to node Out-, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M11; PMOS transistor M14's gate is connected to clock signal clkb2, its source is connected to power supply Vdd, and its drain is connected to the sources of PMOS transistors M12 and M13.

[0022] During the large-scale prevention phase, the preamplifier stage amplifies the input differential signal within a predetermined time. Then, the latch stage is activated to amplify its input differential signal, while the current source (M5) of the first stage is turned off to reduce its power consumption, which is the primary source of total power consumption. The typical output voltage waveform of the proposed comparator is shown below. Figure 3 As shown. The control signal is implemented using a delay-line based controller. The relationship between the offset voltage of the proposed comparator and the latch stage delay is as follows. Figure 4 As shown, by adjusting the latch stage delay, the relationship between comparator speed and offset voltage can be balanced.

[0023] This paper proposes a low-power, high-speed two-stage dynamic comparator, the core of which lies in a controlled time-sharing mechanism. During the evaluation phase, the first-stage preamplifier is activated first to amplify the small input differential signal. Subsequently, after a pre-set delay, the second-stage latch is activated to complete the high-speed decision. Simultaneously, the first-stage preamplifier is immediately turned off to cut off its main power source. This "amplify first, then latch, then immediately turn off the preceding stage" operating mode, combined with the use of better-matched PMOS input transistors in both stages, enables the comparator to achieve the advantages of reduced power consumption and increased speed while maintaining a low offset voltage.

[0024] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-speed, low-power comparator, characterized in that, The structure adopts a first-stage preamplifier stage and a second-stage latch stage; In the first-stage preamplifier, the gate of NMOS transistor M1 is connected to the clock signal clk, its source is grounded, and its drain is connected to the drain of PMOS transistor M3; the gate of NMOS transistor M2 is connected to the clock signal clk, its source is grounded, and its drain is connected to the drain of PMOS transistor M4; the gate of PMOS transistor M3 is connected to the differential input Vin+, its drain is connected to the drain of NMOS transistor M1, and is also connected to the gate of PMOS transistor M10 at node O1-, and its source is connected to the drain of M5; the gate of PMOS transistor M4 is connected to the differential input Vin-, its drain is connected to the drain of M2, and is also connected to the gate of PMOS transistor M11 at node O1+, and its source is connected to the drain of M5; the gate of PMOS transistor M5 is connected to the clock signal clkb1, its source is connected to the power supply Vdd, and its drain is connected to the drains of PMOS transistors M3 and M4. In the second latching stage, the gate of NMOS transistor M6 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out-. It is also connected to the drain of PMOS transistors M10, M13, M9, and M8. The gate of NMOS transistor M7 is connected to the clock signal clk, its source is grounded, and its drain is connected to node Out+. It is also connected to the drain of PMOS transistors M11, M8, M12, and M9. The gate of NMOS transistor M8 is connected to node Out+, its source is grounded, and its drain is connected to node Out-. The gate of NMOS transistor M9 is connected to node Out-, its source is grounded, and its drain is connected to node O. ut+; PMOS transistor M10's gate is connected to node O1-, its source is connected to the drain of PMOS transistor M12, and its drain is connected to node Out-; PMOS transistor M11's gate is connected to node O1+, its source is connected to the drain of PMOS transistor M13, and its drain is connected to node Out+; PMOS transistor M12's gate is connected to node Out+, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M10; PMOS transistor M13's gate is connected to node Out-, its source is connected to the drain of PMOS transistor M14, and its drain is connected to the source of PMOS transistor M11; PMOS transistor M14's gate is connected to clock signal clkb2, its source is connected to power supply Vdd, and its drain is connected to the sources of PMOS transistors M12 and M13.

2. The high-speed, low-power comparator according to claim 1, characterized in that, PMOS transistors M3 and M4 are used as input transistors, paired with NMOS switches M1 and M2 and PMOS active load transistor M5; the clock signal clk controls the switching transistors to turn on / off, realizing the operation and stop of the preamplifier stage; the PMOS input transistors reduce the offset voltage due to their better matching.

3. A high-speed, low-power comparator according to claim 1, characterized in that, It uses a PMOS latch structure instead of a traditional NMOS latch; the latch stage is activated by delay through two clock signals clkb1 and clkb2 with controllable delay; the preamplifier stage first works for a preset time to amplify the input signal, and then the latch stage starts up. At the same time, the current source of the preamplifier stage is turned off to reduce redundant power consumption.

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