Framework and layout method for connecting chip with DDR (Double Data Rate) based on positive and negative pasting

Abstract

According to the framework and the layout method for connecting the chip with the DDR based on the positive and negative pasting, punching is carried out at the central sites of the four PINs which are adjacent to one another on the DDR particles or within the allowable deviation range deviating from the central sites, and punching is carried out according to the adjacent relation, so that high-density integration of punching on the DDR particles is guaranteed firstly; and all devices are connected through the punched holes, so that integration of the devices on the PCB is indirectly facilitated. Moreover, the DDR particle PIN and the chip PIN which are in contact with the same via hole have the same network attribute, so that non-interference among different networks can be realized only by adjusting the position of the via hole, and the quality of communication between the chip and the DDR particle is ensured. And the chip PINs and the DDR particle PINs, which have the same network attribute, are not short-circuited, so that the distance between the via holes can be unlimited, and high-density integration of a PCB (Printed Circuit Board) device can be realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to an architecture and layout method for connecting a main chip to DDR based on reversible bonding. Background Technology

[0002] In recent years, technological advancements in the industry have demanded increasingly smaller PCB (printed circuit board) areas, with more and more integrated devices (such as chips) and smaller spacing between chips, leading to increased density. To meet the design requirements of low-cost, high-density PCBs, the layout and wiring space for chips and DDR (memory chips) is gradually decreasing. Therefore, achieving low-cost, high-density wiring and layout within a limited PCB size is particularly important.

[0003] In existing methods, a reverse-mount design exists between the chip and the DDR chip, but placement and interconnection are typically achieved through blind vias. This method requires multiple lamination and electroplating processes, resulting in complex design, long lead times, and high costs. Another existing method places the DDR chips on the periphery of the chip on the same side, using through-holes or deep microvias for placement and interconnection. However, this method results in low device density and is generally not applicable to PCBs with very limited dimensions. Summary of the Invention

[0004] This application aims to achieve high-density, low-cost layout of chips and DDR particles on a PCB board, and provides an architecture and layout method for connecting DDR based on reverse-mounted chips.

[0005] To achieve this objective, the following technical solution is adopted in this application: A layout method for connecting DDR chips based on reversible mounting is provided, the steps of which include: S1, place the chip and DDR chip on the first and second sides of the PCB board respectively, with the first and second sides facing each other; S2, fan-out holes are made on the DDR chip; S3, determine whether the chip pin projected onto the fan-out punched area is in contact with the DDR via punched in the punched area. If so, the network attributes of the chip pins and the network attributes of the DDR vias they contact are defined to be the same; If not, mark the chip pins as having undefined network attributes.

[0006] Preferably, the layout method for connecting DDR chips based on reversible bonding further includes the following steps: S4 determines whether the DDR vias achieve non-interference between different networks. If so, the DDR via is marked as drilling qualified; If not, proceed to step S5 or jump to step S6; S5, adjust the position of the DDR via, and then return to step S4.

[0007] Preferably, step S6 includes the following steps: S61, filter out the network attributes closest to the DDR via that are power network or ground network and propose to change the DDR via; S62, the interconnection method is adjusted to change the type of the DDR via to a blind via, or the DDR via with a power network attribute is directly connected with a metal surface layer.

[0008] Preferably, the second surface is located within the projection area of ​​the first surface.

[0009] Preferably, the second side is the back side of the PCB board, and the first side is the front side of the same PCB board.

[0010] Preferably, in step S2, the method for fan-out drilling of the DDR chip is as follows: A hole is drilled at the center point of four adjacent pins on the DDR chip, or within the allowable deviation range from the center point. The drilled hole is defined as a DDR via.

[0011] Preferably, the network attributes include one or more of a power network, a ground network, and a signal network.

[0012] Preferably, the DDR chip includes LPDDR5.

[0013] This application also provides an architecture for connecting DDR chips based on reversible bonding, wherein the chip and DDR chip are placed on the first and second sides of the PCB board, respectively, and the first and second sides are arranged opposite to each other; the chip pins contact the DDR vias punched on the DDR chip; the network attributes of the chip pins are the same as the network attributes of the DDR vias they are connected to.

[0014] Preferably, when the first DDR via causes network interference, the type of the second DDR via closest to the first DDR via is adjusted to be a blind via, or the first DDR via with a power network attribute is directly connected with a metal surface layer. The DDR via is drilled at the center of four adjacent pins on the DDR chip or within the allowable deviation range from the center.

[0015] This application has the following beneficial effects: There are no restrictions on the spacing between vias with the same network attributes because when the chip pins and DDR vias share the same network, they will not short-circuit, thus eliminating the need for pre-defined via spacing. Furthermore, by drilling vias at the center point of four adjacent pins on the DDR chip, or within the allowable deviation range from that center point, this adjacent drilling arrangement ensures high-density integration of the vias on the DDR chip. Connecting various components through these vias indirectly facilitates component integration on the PCB board. Moreover, since the DDR chip pins contacting the same via and the chip pins share the same network attributes, interference between different networks can be prevented simply by adjusting the via position, ensuring high-quality communication between the chip and the DDR chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram illustrating the implementation steps of the layout method for connecting DDR chips based on reversible mounting provided in this application; Figure 2 This is an example diagram showing the positional relationship between the pins of a chip mounted on the same PCB board from both sides and the pins of a DDR chip. Figure 3 This is an example diagram of vias punched on DDR chips; Figure 4 This is an example diagram of pin and via connections defined as a signal network or ground network; Figure 5 These are example diagrams of signal networks, ground networks, and power networks; Figure 6 This is an example diagram showing how to change DDR vias to blind vias or connect them directly with a metal surface layer; Figure 7 This is an example diagram illustrating the final implementation of the front-to-back mounting and routing scheme for DDR chips and dies; Figure 8 Yes Figure 7 Example diagram after connecting to the power network; Figure 9 This is an example diagram showing that the via channel is too narrow in some areas; Figure 10 This is an example diagram showing the layout of filter capacitors around the DDR chip. Detailed Implementation

[0018] The technical solution of this application will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this application. To better illustrate the embodiments of this application, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0020] In the accompanying drawings of the embodiments of this application, the same or similar reference numerals correspond to the same or similar components. In the description of this application, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] In the description of this application, unless otherwise expressly specified and limited, the term "connection" or similar designation indicating a connection between components should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] In this application embodiment, the high-density device layout of the PCB board first adopts the method of front and back mounting of chips and DDR chips, and then achieves low-cost signal interconnection through innovative wiring method, thereby realizing the high-density and low-cost layout of chips and DDR chips on the PCB board.

[0023] The following uses LPDDR5 chips (fifth-generation low-power double data rate memory) as an example to illustrate the architecture and layout method of DDR chip connection based on reversible mounting provided in this implementation. Because LPDDR5 chips are relatively large, with a chip pitch of approximately 0.65mm, as long as the LPDDR5 chips can achieve high-density chip layout and low-cost signal communication on the PCB board, other DDR chips can theoretically also achieve high-density, low-cost layout on the same PCB board using the same method.

[0024] The layout method for connecting DDR chips based on reversible mounting provided in this application, such as... Figure 1 As shown, it includes the following steps: S1, place the chip and DDR chip on the first and second sides of the PCB board respectively, with the first and second sides facing each other; preferably, the first side is the front side of the PCB board, the second side is the back side of the PCB board, and the second side is located within the projection area of ​​the first side. Figure 2 The black solid circles in the image represent the pins of the chip, while the gray solid circles represent the pins of the DDR chip. S2 involves fan-out drilling on the DDR chip, using the following method: A DDR via is defined as a hole drilled at the center point of four adjacent pins on a DDR chip, or within the allowable deviation range from that center point. Figure 3 In the diagram, the gray circles represent DDR vias, and the black circles represent chip pins. The center points of the four pins are calculated using existing methods such as the centroid method, and will not be explained in detail here.

[0025] S3, determine whether the chip pin projected onto the fan-out punch area is in contact with the DDR via punched in that punch area. If so, then the network attributes of the chip pins are defined to be the same as the network attributes of the contacting DDR vias; If not, mark the chip pin; In this application, network attributes include power network, ground network, and signal network. Figure 5 The gray solid circles in the diagram represent signal networks, while the black solid circles indicated by the arrows represent power or ground networks. There are no restrictions on the spacing between vias with the same network attribute because when chip pins and DDR vias share the same network, they will not short-circuit, thus eliminating the need for pre-defined via spacing. Furthermore, by drilling vias at the center point of four adjacent pins on the DDR chip, or within the allowable deviation range from that center point, this adjacent drilling arrangement ensures high-density integration of the vias on the DDR chip. Connecting various components through these vias indirectly facilitates component integration on the PCB. Moreover, since DDR chip pins contacting the same via and chip pins share the same network attribute, interference between different networks can be prevented simply by adjusting the via position, ensuring high-quality communication between the chip and the DDR chip.

[0026] S4 determines whether the DDR vias achieve non-interference between different networks. If so, mark the DDR via as successfully drilled; If not, proceed to step S5 or jump to step S6; S5, adjust the position of the DDR via, and then return to step S4.

[0027] The method for determining whether interference occurs between different networks is an existing method and will not be described in detail.

[0028] In step S5, the preferred method for adjusting the DDR via position is: Randomly select a position within the allowable positional deviation range from the original position of the DDR via as the adjusted DDR via position.

[0029] Preferably, step S6 includes the following steps: S61, filter out another DDR via whose network attribute is power network or ground network that is closest to the DDR via, and define it as the DDR via whose interconnection method is to be changed; S62, Adjust the interconnection method to change the type of DDR via to blind via, or directly connect the DDR via with the power network attribute using a copper surface layer.

[0030] For example, Figure 6 In the diagram, the via type represented by numbers 17-18 or 16-18 is changed to a blind via. Alternatively, DDR vias with network attributes of power network can be directly connected using a copper surface layer. Figure 6 Large black connected area (100).

[0031] Through the above steps, an example diagram of the front-to-back mounting layout and routing of DDR chips and PCBs on the same PCB board is shown below. Figure 7 As shown. At this point, the power network is also connected via vias, eliminating the need for additional wiring layers. The power network (preferably copper) is as follows: Figure 8 As indicated by reference numeral 200 in the attached diagram. Inner layer routing space can be used to connect power networks. If a local channel is too narrow, try adjusting the via for optimization, such as... Figure 9 At point 'a', if the copper strip width is insufficient, the via can be moved down slightly to increase the copper strip width. Power networks typically require filter capacitors, which are preferably evenly distributed around the DDR chips, on the same side of the PCB as the DDR chips, and preferably on the back side. For example... Figure 10 The filter capacitor 300 is positioned around the DDR chip.

[0032] It should be stated that the above-described specific embodiments are merely preferred embodiments and technical principles applied in this application. Those skilled in the art should understand that various modifications, equivalent substitutions, and variations can be made to this application. However, such variations, as long as they do not depart from the spirit of this application, should be within the scope of protection of this application. Furthermore, some terminology used in this application's specification and claims is not limiting but merely for ease of description.

Claims

1. A layout method for DDR based on reversible chip bonding, characterized in that the steps include: include: S1, place the chip and DDR chip on the first and second sides of the PCB board respectively, with the first and second sides facing each other; S2, fan-out holes are made on the DDR chip; S3, determine whether the chip pin projected onto the fan-out punched area is in contact with the DDR via punched in the punched area. If so, the network attributes of the chip pins and the network attributes of the DDR vias they contact are defined to be the same; If not, mark the chip pins as having undefined network attributes.

2. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, It also includes the following steps: S4 determines whether the DDR vias achieve non-interference between different networks. If so, the DDR via is marked as drilling qualified; If not, proceed to step S5 or jump to step S6; S5, adjust the position of the DDR via, and then return to step S4.

3. The layout method for DDR chip interconnection based on reversible bonding according to claim 2, characterized in that, Step S6 includes the following steps: S61, filter out the network attributes closest to the DDR via that are power network or ground network and propose to change the DDR via; S62, the interconnection method is adjusted to change the type of the DDR via to a blind via, or the DDR via with a power network attribute is directly connected with a metal surface layer.

4. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, The second surface is located within the projection area of ​​the first surface.

5. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, The second side is the back side of the PCB board, and the first side is the front side of the same PCB board.

6. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, In step S2, the method for fan-out drilling of the DDR chip is as follows: A hole is drilled at the center point of four adjacent pins on the DDR chip, or within the allowable deviation range from the center point. The drilled hole is defined as a DDR via.

7. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, The network attributes include one or more of the following: power network, ground network, and signal network.

8. The layout method for DDR chip interconnection based on reversible bonding according to claim 1, characterized in that, The DDR chips include LPDDR5.

9. An architecture for connecting DDR chips based on reversible bonding, characterized in that, The chip and DDR chip are placed on the first and second sides of the PCB board, respectively, with the first and second sides facing each other; the chip pins are in contact with the DDR vias punched on the DDR chip; the network attributes of the chip pins are the same as the network attributes of the DDR vias they are connected to.

10. The architecture for connecting DDR chips based on reversible bonding according to claim 9, characterized in that, When network interference occurs in the first DDR via, adjust the type of the second DDR via closest to the first DDR via to a blind via, or directly connect the first DDR via with a metal surface layer if the network attribute is a power network. The DDR via is drilled at the center of four adjacent pins on the DDR chip or within the allowable deviation range from the center.

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