Semiconductor element stack structure
By using large-sized first substrate vias and small-sized second substrate vias in wafer or chip stack structures, the problems of the number of front-side wiring layers and occupied area are solved, thereby simplifying circuit design and improving signal transmission efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-05
AI Technical Summary
In wafer stacking or chip stacking structures, the number of winding layers on the front side of the substrate and the area occupied by the substrate vias are constantly increasing, which leads to increased circuit design complexity and makes it difficult to optimize the area occupied by the substrate vias.
A large-sized first substrate via is used to penetrate the substrate, and a small-sized second substrate via is used to connect the semiconductor device to the redistribution layer, reducing the number of winding layers and the area occupied on the front side of the substrate. At the same time, multiple second substrate vias and the back redistribution layer are used for power and signal transmission.
It effectively reduces the number of winding layers and the area occupied on the front side of the substrate, improves the warp control flexibility of the wafer/chip, and achieves efficient power and signal transmission.
Smart Images
Figure CN121985579A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure, and more particularly to a semiconductor element stacking structure. Background Technology
[0002] Currently, in wafer or chip stacked structures, the number of routing layers on the front side of the substrate is constantly increasing, thus increasing the complexity of circuit design. Furthermore, in wafer or chip stacked structures, power and / or signal transmission is often achieved through-substrate vias (TSVs). Therefore, reducing the footprint of TSVs remains a continuous goal. Summary of the Invention
[0003] The present invention provides a semiconductor device stacking structure that can reduce the number of winding layers on the front side of the substrate and the area occupied by substrate vias.
[0004] This invention proposes a semiconductor device stacking structure, comprising multiple first semiconductor device structures stacked together. Each first semiconductor device structure includes a substrate, multiple semiconductor devices, a redistribution layer (RDL), a first substrate via, and multiple second substrate vias. The substrate includes a front side and a back side. The multiple semiconductor devices are located on the front side of the substrate. The redistribution layer is located on the back side of the substrate. The first substrate vias penetrate the substrate. The first substrate vias are electrically connected to the redistribution layer. The multiple second substrate vias penetrate the substrate. Each second substrate via is located directly below a corresponding semiconductor device. Each second substrate via is electrically connected to the corresponding semiconductor device and the redistribution layer. The size of each first substrate via is larger than the size of each second substrate via.
[0005] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the plurality of first semiconductor element structures may be a plurality of semiconductor wafers.
[0006] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the plurality of first semiconductor element structures may be a plurality of semiconductor chips.
[0007] According to one embodiment of the present invention, in the above-described semiconductor element stacking structure, the first substrate via is not located directly below the plurality of semiconductor elements.
[0008] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the overall height of the first substrate via may be greater than the overall height of each second substrate via.
[0009] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the volume of the first substrate via can be larger than the volume of each second substrate via.
[0010] According to one embodiment of the present invention, in the above-described semiconductor element stacking structure, the volume of the first substrate via can be 10 to 1000 times the volume of each second substrate via.
[0011] According to one embodiment of the present invention, in the above-described semiconductor element stack structure, each first semiconductor element structure may further include a dielectric structure. The dielectric structure is located on the front side of the substrate. Multiple semiconductor elements are located within the dielectric structure.
[0012] According to an embodiment of the present invention, in the above-described semiconductor element stack structure, the first substrate via can extend into the dielectric structure.
[0013] According to an embodiment of the present invention, in the above-described semiconductor element stack structure, each first semiconductor element structure may further include a dielectric structure. The dielectric structure is located on the back side of the substrate. A redistribution layer is located within the dielectric structure.
[0014] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the first substrate via and a plurality of second substrate vias can extend into the dielectric structure.
[0015] According to one embodiment of the present invention, in the above-described semiconductor element stacking structure, two adjacent first semiconductor element structures can be joined together.
[0016] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the bonding method for two adjacent first semiconductor element structures can be bump bonding.
[0017] According to an embodiment of the present invention, in the above-mentioned semiconductor element stacking structure, the bonding method of two adjacent first semiconductor element structures can be a hybrid bonding method.
[0018] According to one embodiment of the present invention, the above-described semiconductor device stack structure may include a plurality of first substrate vias and a plurality of redistribution layers. Each first substrate via is electrically connected to a corresponding redistribution layer.
[0019] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, a plurality of first substrate vias may be located between a plurality of second substrate vias.
[0020] According to one embodiment of the present invention, the above-described semiconductor element stacking structure may further include a second semiconductor element structure. A plurality of first semiconductor element structures may be stacked on the second semiconductor element structure.
[0021] According to one embodiment of the present invention, in the above-described semiconductor element stacking structure, the second semiconductor element structure may be a semiconductor wafer.
[0022] According to one embodiment of the present invention, in the above-described semiconductor element stacking structure, the second semiconductor element structure may be a semiconductor chip.
[0023] According to an embodiment of the present invention, in the above-described semiconductor element stacking structure, the one of the plurality of first semiconductor element structures closest to the second semiconductor element structure may be bonded to the second semiconductor element structure.
[0024] Based on the above, in the semiconductor device stacking structure proposed in this invention, multiple second substrate vias penetrate the substrate. Each second substrate via is located directly beneath its corresponding semiconductor device. Each second substrate via is electrically connected to the corresponding semiconductor device and the redistribution layer. The size of the first substrate via is larger than the size of each second substrate via, meaning the second substrate vias can have a smaller size. Therefore, the number of winding layers on the front side of the substrate and the area occupied by the substrate vias can be reduced, and greater flexibility is provided for wafer / chip warpage control. Furthermore, power and / or signals can be transmitted to multiple semiconductor devices through the multiple second substrate vias and the redistribution layer located on the back side of the substrate.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figure 1 This is a cross-sectional view of a semiconductor element stacking structure according to some embodiments of the present invention;
[0027] Figure 2 This is a cross-sectional view of a semiconductor element stacking structure according to other embodiments of the present invention.
[0028] Symbol Explanation
[0029] 10, 20: Semiconductor device stacking structure
[0030] 100, 100A, 100B, 122: Semiconductor device structures
[0031] 102, 124: Base
[0032] 104, 126: Semiconductor components
[0033] 106: Rewire Layer
[0034] 108, 110: Substrate perforation
[0035] 112, 114, 128: Dielectric structure
[0036] 116, 130: Intrawire structure
[0037] 118, 120, 132: Connecting pads
[0038] 134, 136: Connecting terminals
[0039] H1, H2: Overall height
[0040] S1, S3: Front
[0041] S2, S4: Back side Detailed Implementation
[0042] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation.
[0043] Figure 1 This is a cross-sectional view of a semiconductor element stack structure according to some embodiments of the present invention.
[0044] Please refer to Figure 1 The semiconductor element stack structure 10 includes a plurality of semiconductor element structures 100 stacked together. Furthermore, the number of semiconductor element structures 100 is not limited to the number shown in the figures; as long as there are multiple semiconductor element structures 100, they fall within the scope of this invention. In some embodiments, the plurality of semiconductor element structures 100 may be multiple semiconductor wafers or multiple semiconductor chips. Each semiconductor element structure 100 includes a substrate 102, a plurality of semiconductor elements 104, a redistribution layer 106, a substrate via 108, and a plurality of substrate vias 110. Furthermore, the number of semiconductor elements 104 and the number of substrate vias 110 are not limited to the numbers shown in the figures; as long as the number of semiconductor elements 104 and the number of substrate vias 110 are both multiple, they fall within the scope of this invention. The substrate 102 includes a front side S1 and a back side S2. In some embodiments, the substrate 102 may be a semiconductor substrate, such as a silicon substrate.
[0045] Multiple semiconductor elements 104 are located on the front side S1 of the substrate 102. In some embodiments, the semiconductor elements 104 may be active (active) elements, passive (passive) elements, or a combination thereof. In some embodiments, the semiconductor elements 104 may be memory (e.g., dynamic random access memory, DRAM), transistors, capacitors, resistors, or a combination thereof. In some embodiments, the multiple semiconductor elements 104 in the same semiconductor element structure 100 may be the same element or different elements. In some embodiments, the multiple semiconductor elements 104 in different semiconductor element structures 100 may be the same element or different elements. In some embodiments, the layout design of the multiple semiconductor elements 104 in different semiconductor element structures 100 may be the same or different. In this embodiment, the layout design of the multiple semiconductor elements 104 in semiconductor element structure 100A may be the same as the layout design of the multiple semiconductor elements 104 in semiconductor element structure 100B, but the present invention is not limited thereto. In other embodiments, the layout design of the plurality of semiconductor elements 104 in semiconductor element structure 100A may be different from the layout design of the plurality of semiconductor elements 104 in semiconductor element structure 100B.
[0046] In some embodiments, each semiconductor element structure 100 may further include a dielectric structure 112. The dielectric structure 112 is located on the front side S1 of the substrate 102. A plurality of semiconductor elements 104 are located in the dielectric structure 112. In some embodiments, the material of the dielectric structure 112 is, for example, silicon oxide, silicon nitride, or a combination thereof.
[0047] The redistribution layer 106 is located on the back side S2 of the substrate 102. The redistribution layer 106 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the redistribution layer 106 is, for example, copper, tantalum, tantalum nitride, or a combination thereof.
[0048] In some embodiments, each semiconductor element structure 100 may further include a dielectric structure 114. The dielectric structure 114 is located on the back side S2 of the substrate 102. A redistribution layer 106 is located within the dielectric structure 114. In some embodiments, the material of the dielectric structure 114 is, for example, silicon oxide, silicon nitride, or a combination thereof.
[0049] A substrate via 108 penetrates the substrate 102. The substrate via 108 is electrically connected to the redistribution layer 106. In some embodiments, the semiconductor device stack structure 10 may include a plurality of substrate vias 108 and a plurality of redistribution layers 106. Each substrate via 108 may be electrically connected to a corresponding redistribution layer 106. In some embodiments, the substrate via 108 is not located directly beneath the plurality of semiconductor devices 104. In some embodiments, the substrate via 108 may extend into the dielectric structure 112. In some embodiments, the substrate via 108 may extend into the dielectric structure 114. In some embodiments, the material of the substrate via 108 is, for example, copper, tantalum, tantalum nitride, or a combination thereof.
[0050] Multiple substrate vias 110 penetrate the substrate 102. Each substrate via 110 is located directly beneath a corresponding semiconductor element 104. Each substrate via 110 is electrically connected to the corresponding semiconductor element 104 and the redistribution layer 106. In some embodiments, the substrate via 110 may be directly connected to an electrode (not shown) in the semiconductor element 104. In some embodiments, the substrate via 110 may be electrically connected to the semiconductor element 104 via an interconnect structure (not shown). In some embodiments, the multiple substrate vias 110 may extend into a dielectric structure 114. In some embodiments, multiple substrate vias 108 may be located between the multiple substrate vias 110. In some embodiments, the material of the substrate via 110 is, for example, copper, tantalum, tantalum nitride, or a combination thereof.
[0051] The size of the substrate perforation 108 is larger than the size of each substrate perforation 110. In some embodiments, the overall height H1 of the substrate perforation 108 may be greater than the overall height H2 of each substrate perforation 110. In some embodiments, the volume of the substrate perforation 108 may be greater than the volume of each substrate perforation 110. In some embodiments, the volume of the substrate perforation 108 may be 10 to 1000 times the volume of each substrate perforation 110.
[0052] In some embodiments, each semiconductor element structure 100 may further include a plurality of interconnect structures 116, a plurality of pads 118, and a plurality of pads 120. Each interconnect structure 116 is electrically connected to a corresponding substrate via 108 or a corresponding semiconductor element 104. In some embodiments, the material of the interconnect structure 116 is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. The plurality of pads 118 are located in the dielectric layer 112. In some embodiments, the interconnect structure 116 may be electrically connected to the corresponding pad 118 via other interconnect structures (not shown). In some embodiments, the material of the pad 118 is, for example, a conductive material such as aluminum. The plurality of pads 120 are located in the dielectric layer 114. The redistribution layer 106 may be electrically connected to the corresponding pad 120 via interconnect structures (not shown). In some embodiments, the material of the pad 120 is, for example, a conductive material such as aluminum.
[0053] In some embodiments, the semiconductor device stack structure 10 may further include a semiconductor device structure 122. Multiple semiconductor device structures 100 may be stacked on the semiconductor device structure 122. In some embodiments, the semiconductor device structure 122 may be a semiconductor wafer or a semiconductor chip.
[0054] The semiconductor device structure 122 includes a substrate 124, a plurality of semiconductor devices 126, a dielectric structure 128, a plurality of interconnect structures 130, and a plurality of pads 132. The substrate 124 includes a front side S3 and a back side S4. In some embodiments, the substrate 124 may be a semiconductor substrate, such as a silicon substrate.
[0055] Multiple semiconductor elements 126 are located on the front side S3 of the substrate 124. In some embodiments, the semiconductor elements 126 may be active elements, passive elements, or a combination thereof. In some embodiments, the semiconductor elements 126 may be memory (e.g., dynamic random access memory), transistors, capacitors, resistors, or a combination thereof. In some embodiments, the multiple semiconductor elements 126 in the semiconductor element structure 122 may be the same or different elements.
[0056] The dielectric structure 128 is located on the front side S3 of the substrate 124. A plurality of semiconductor elements 126 may be located in the dielectric structure 128. In some embodiments, the material of the dielectric structure 128 is, for example, silicon oxide, silicon nitride, or a combination thereof.
[0057] Multiple interconnect structures 130 are located within the dielectric structure 128. Semiconductor elements 126 can be electrically connected to corresponding interconnect structures 130. In some embodiments, the material of the interconnect structure 130 is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof.
[0058] Multiple pads 132 are located within the dielectric structure 128. Interconnect structures 130 can be electrically connected to corresponding pads 132 via other interconnect structures (not shown). In some embodiments, the pads 132 are made of a conductive material such as aluminum.
[0059] In some embodiments, two adjacent semiconductor element structures 100 may be joined together. In this embodiment, the joining method of two adjacent semiconductor element structures 100 may be a bump joining method, but the present invention is not limited thereto. In some embodiments, the semiconductor element stack structure 10 may further include a connection terminal 134. For example, the connection terminal 134 is located between the pad 118 of one of the two adjacent semiconductor element structures 100 (e.g., semiconductor element structure 100A) and the pad 120 of the other of the two adjacent semiconductor element structures 100 (e.g., semiconductor element structure 100B), and is electrically connected to the pad 118 of one of the two adjacent semiconductor element structures 100 (e.g., semiconductor element structure 100A) and the pad 120 of the other of the two adjacent semiconductor element structures 100 (e.g., semiconductor element structure 100B), thereby allowing the two adjacent semiconductor element structures 100 to be joined together. In some embodiments, the connection terminal 134 may be a bump (e.g., a solder ball), but the present invention is not limited thereto.
[0060] In some embodiments, the semiconductor element structure 100 closest to semiconductor element structure 122 may be bonded to semiconductor element structure 122. For example, semiconductor element structure 100A may be bonded to semiconductor element structure 122. In this embodiment, the bonding method between semiconductor element structure 100A and semiconductor element structure 122 may be a bump bonding method, but the invention is not limited thereto. For example, the semiconductor element stack structure 10 may also include a connection terminal 136. The connection terminal 136 is located between and electrically connected to pads 120 and 132, thereby allowing semiconductor element structure 100A and semiconductor element structure 122 to be bonded to each other. In some embodiments, the connection terminal 136 may be a bump (e.g., a solder ball), but the invention is not limited thereto.
[0061] As can be seen from the above embodiments, in the semiconductor device stack structure 10, a plurality of substrate vias 110 penetrate the substrate 102. Each substrate via 110 is located directly below the corresponding semiconductor device 104. Each substrate via 110 is electrically connected to the corresponding semiconductor device 104 and the redistribution layer 106. The size of the substrate via 108 is larger than the size of each substrate via 110, that is, the substrate via 110 can have a smaller size. Therefore, the number of winding layers on the front side S1 of the substrate 102 and the area occupied by the substrate vias can be reduced, and the warpage control of the wafer / chip is more flexible. In addition, power and / or signals can be transmitted to the plurality of semiconductor devices 104 through the plurality of substrate vias 110 and the redistribution layer 106 located on the back side S2 of the substrate 102.
[0062] Figure 2 This is a cross-sectional view of a semiconductor element stack structure according to other embodiments of the present invention.
[0063] Please refer to Figure 1 and Figure 2 , Figure 2 Semiconductor element stacking structure 20 and Figure 1 The differences in the semiconductor element stacking structure 10 are as follows. Please refer to... Figure 2 In the semiconductor device stack structure 20, the bonding method for two adjacent semiconductor device structures 100 (e.g., semiconductor device structure 100A and semiconductor device structure 100B) can be a hybrid bonding method. In the semiconductor device stack structure 20, pads 118 and 120 can be used as bonding pads. For example, in the semiconductor device stack structure 20, pad 118 of semiconductor device structure 100A can be bonded to pad 120 of semiconductor device structure 100B, and dielectric structure 112 of semiconductor device structure 100A can be bonded to dielectric structure 114 of semiconductor device structure 100B, thereby allowing semiconductor device structures 100A and 100B to be bonded to each other. In the semiconductor device stack structure 20, the materials of pads 118 and 120 used for hybrid bonding are, for example, copper, tantalum, tantalum nitride, or combinations thereof.
[0064] In the semiconductor device stack structure 20, the bonding method between semiconductor device structure 100A and semiconductor device structure 122 can be a hybrid bonding method. In the semiconductor device stack structure 20, pads 120 and 132 can be used as bonding pads. For example, in the semiconductor device stack structure 20, pad 120 of semiconductor device structure 100A can be bonded to pad 132 of semiconductor device structure 122, and dielectric structure 114 of semiconductor device structure 100A can be bonded to dielectric structure 128 of semiconductor device structure 122, thereby bonding semiconductor device structure 100A and semiconductor device structure 122 to each other. In the semiconductor device stack structure 20, the materials of pads 120 and 132 used for hybrid bonding are, for example, copper, tantalum, tantalum nitride, or combinations thereof.
[0065] In addition, Figure 1 Semiconductor element stacking structure 10 and Figure 2 In the semiconductor element stack structure 20, the same or similar components are represented by the same symbols and their descriptions are omitted.
[0066] As can be seen from the above embodiments, in the semiconductor device stack structure 20, a plurality of substrate vias 110 penetrate the substrate 102. Each substrate via 110 is located directly below the corresponding semiconductor device 104. Each substrate via 110 is electrically connected to the corresponding semiconductor device 104 and the redistribution layer 106. The size of the substrate via 108 is larger than the size of each substrate via 110, that is, the substrate via 110 can have a smaller size. Therefore, the number of winding layers on the front side S1 of the substrate 102 and the area occupied by the substrate vias can be reduced, and the warpage control of the wafer / chip is more flexible. In addition, power and / or signals can be transmitted to the plurality of semiconductor devices 104 through the plurality of substrate vias 110 and the redistribution layer 106 located on the back side S2 of the substrate 102.
[0067] In summary, the semiconductor device stacking structure of the above embodiments includes a plurality of first semiconductor device structures stacked together. Each first semiconductor device structure includes a substrate, a plurality of semiconductor devices, a redistribution layer, a first substrate via, and a plurality of second substrate vias. The substrate includes a front side and a back side. The plurality of semiconductor devices are located on the front side of the substrate. The redistribution layer is located on the back side of the substrate. The first substrate via penetrates the substrate. The first substrate via is electrically connected to the redistribution layer. The plurality of second substrate vias penetrate the substrate. Each second substrate via is located directly below the corresponding semiconductor device. Each second substrate via is electrically connected to the corresponding semiconductor device and the redistribution layer. The size of the first substrate via is larger than the size of each second substrate via, that is, the second substrate vias can have a smaller size. Therefore, the number of winding layers on the front side of the substrate and the area occupied by the substrate vias can be reduced, and the wafer / chip warpage control is more flexible. In addition, power and / or signals can be transmitted to the plurality of semiconductor devices through the plurality of second substrate vias and the redistribution layer located on the back side of the substrate.
[0068] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A semiconductor device stacking structure, comprising: A plurality of first semiconductor element structures stacked together, wherein each of the first semiconductor element structures comprises: The base, including the front and back sides; Multiple semiconductor elements are located on the front side of the substrate; A redistribution layer is located on the back side of the substrate; A first substrate via penetrates the substrate and is electrically connected to the redistribution layer; and Multiple second substrate vias penetrate the substrate, wherein each second substrate via is located directly beneath a corresponding semiconductor element and is electrically connected to the corresponding semiconductor element and the redistribution layer. The size of the first substrate perforation is larger than the size of each of the second substrate perforations.
2. The semiconductor element stacking structure of claim 1, wherein the plurality of first semiconductor element structures comprises a plurality of semiconductor wafers.
3. The semiconductor element stacking structure as claimed in claim 1, wherein the plurality of first semiconductor element structures comprise a plurality of semiconductor chips.
4. The semiconductor element stacking structure of claim 1, wherein the first substrate via is not located directly beneath the plurality of semiconductor elements.
5. The semiconductor device stacking structure of claim 1, wherein the overall height of the first substrate via is greater than the overall height of each of the second substrate vias.
6. The semiconductor device stacking structure of claim 1, wherein the volume of the first substrate via is greater than the volume of each of the second substrate vias.
7. The semiconductor device stacking structure of claim 1, wherein the volume of the first substrate via is 10 to 1000 times the volume of each of the second substrate vias.
8. The semiconductor element stacking structure of claim 1, wherein each of the first semiconductor element structures further comprises: A dielectric structure is located on the front side of the substrate, wherein a plurality of the semiconductor elements are located within the dielectric structure.
9. The semiconductor element stack structure of claim 8, wherein the first substrate via extends into the dielectric structure.
10. The semiconductor element stacking structure of claim 1, wherein each of the first semiconductor element structures further comprises: A dielectric structure is located on the back side of the substrate, wherein the redistribution layer is located within the dielectric structure.
11. The semiconductor device stack structure of claim 10, wherein the first substrate via and a plurality of second substrate vias extend into the dielectric structure.
12. The semiconductor element stacking structure of claim 1, wherein two adjacent first semiconductor element structures are joined to each other.
13. The semiconductor element stacking structure of claim 12, wherein the bonding method of two adjacent first semiconductor element structures includes bump bonding.
14. The semiconductor element stacking structure of claim 12, wherein the bonding method of two adjacent first semiconductor element structures includes hybrid bonding.
15. The semiconductor device stack structure of claim 1, comprising a plurality of first substrate vias and a plurality of redistribution layers, wherein each of the first substrate vias is electrically connected to a corresponding redistribution layer.
16. The semiconductor device stacking structure of claim 15, wherein a plurality of the first substrate vias are located between a plurality of the second substrate vias.
17. The semiconductor device stacking structure as claimed in claim 1, further comprising: A second semiconductor element structure, wherein a plurality of the first semiconductor element structures are stacked on the second semiconductor element structure.
18. The semiconductor element stacking structure of claim 17, wherein the second semiconductor element structure comprises a semiconductor wafer.
19. The semiconductor element stacking structure of claim 17, wherein the second semiconductor element structure comprises a semiconductor chip.
20. The semiconductor element stack structure of claim 17, wherein the one of the plurality of first semiconductor element structures closest to the second semiconductor element structure is bonded to the second semiconductor element structure.