Silicon adapter plate applied to radio frequency microsystem and preparation method of silicon adapter plate

Abstract

The invention provides a silicon adapter plate applied to a radio frequency microsystem and a preparation method thereof, and the method comprises the steps: sequentially forming a plurality of Damascus wiring layers and a plurality of organic medium wiring layers on a silicon substrate through employing a Damascus wiring technology and a PI wiring technology; therefore, the silicon adapter plate can realize high-density integration that the depth-to-width ratio of the TSV blind holes is not less than 10: 1 and the number of wiring layers is 8, the thermal stability and the high-frequency performance of a system are remarkably improved, and a better process platform support is provided for a radio frequency-digital integrated microsystem. Due to the superfine line width and line distance of the second interconnection structure in the Damascus wiring layer, the bottleneck of high-density signal interconnection can be effectively solved, and the transmission power consumption is greatly reduced; due to the existence of the organic medium wiring layer, the problem of large radio frequency loss of a single Damascus wiring layer can be solved, in addition, by adjusting the thickness of the organic medium wiring layer, regulation and control of warping of the adapter plate can be further achieved, and the preparation process is simple, easy to implement and low in manufacturing cost.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic packaging technology, and relates to a silicon adapter board for use in radio frequency microsystems and its preparation method. Background Technology

[0002] Addressing the urgent need for miniaturized, highly integrated, and multifunctional radio frequency (RF) front-ends in fields such as radar, electronic warfare equipment systems, and 5G communications, RF microsystem integration can achieve a high degree of integration of functional modules at the micro-nano scale, making it a key direction for the development of modern electronic information systems.

[0003] Currently, RF microsystem integration mainly employs damascene or organic dielectric layer wiring processes on adapter boards to fabricate multilayer wiring layers. Damask wiring achieves multilayer interconnection through copper-filled trenches and vias, offering advantages such as high density and low resistance, but faces challenges including aspect ratio limitations, high process complexity, and insufficient thermal stability. Organic dielectric layer wiring, on the other hand, uses photosensitive materials such as polyimide (PI), featuring low dielectric constant and low loss, but it has limitations in high-frequency performance and integration density. With the development of more complex RF-digital integrated microsystems, single damascene or organic dielectric layer wiring processes can no longer meet the requirements of high-density integration, interference immunity, large bandwidth, and low power consumption in RF microsystems.

[0004] Furthermore, when integrating Damascus wiring technology and organic dielectric layer wiring technology heterogeneously, high-density integration is not possible due to the aspect ratio of traditional TSV (Through Silicon Via) technology. Moreover, the number of wiring layers in a single process is generally 4-6 layers, which cannot support the needs of more complex RF-digital integrated microsystems. Existing adapter board process production lines can only be used for semiconductor front-end process (FEOL) or semiconductor back-end packaging process (BEOL), resulting in a lack of "mid-end" process capabilities and an inability to effectively integrate multi-functional modules. In addition, as the integration density increases, thermal expansion coefficient mismatch occurs, and traditional heat dissipation solutions are unable to meet the heat dissipation requirements of high-power RF devices, affecting system reliability and performance. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a silicon interposer board and its fabrication method for use in radio frequency microsystems, to solve the series of problems encountered in heterogeneous integration using damascene wiring technology and organic dielectric layer wiring technology in the prior art. To achieve the above and other related objectives, this invention provides a method for fabricating a silicon interposer board for use in radio frequency microsystems, comprising the following steps:

[0006] A silicon substrate is provided, the silicon substrate having a front side and a back side disposed opposite to each other, and a plurality of TSV blind vias are formed by etching on the front side of the silicon substrate;

[0007] An insulating barrier layer and a first seed layer are sequentially formed on the sidewall and bottom of the TSV blind via. Metal is filled in the TSV blind via to form a first interconnect structure. The first interconnect structure is planarized to make the first interconnect structure flush with the front side of the substrate.

[0008] A damascus wiring layer is formed on the front side of the silicon substrate using a damascus process. The damascus wiring layer includes multiple inorganic dielectric layers and a second interconnect structure located in the inorganic dielectric layers. The second interconnect structure is electrically connected to the first interconnect structure.

[0009] An organic dielectric wiring layer is formed on the damascus wiring layer using a PI wiring process. The organic dielectric wiring layer includes multiple organic dielectric layers and a third interconnect structure located in the organic dielectric layers. The third interconnect structure is electrically connected to the second interconnect structure.

[0010] A UBM layer is formed on the third interconnect structure, and the UBM layer is electrically connected to the third interconnect structure.

[0011] Optionally, the density of the second interconnect structure and the density of the third interconnect structure are both 25% to 50%.

[0012] Optionally, the aspect ratio of the TSV blind hole is ≥10:1.

[0013] Optionally, the number of inorganic dielectric layers is 1 to 5, and the linewidth (S) / line spacing (L) of the second interconnect structure is 0.4μm / 0.4μm≤S / L≤2μm / 2μm.

[0014] Optionally, the number of organic media layers is 1 to 4, and the thickness of each organic media layer is equal and is 3 to 25 µm.

[0015] Optionally, the linewidth of the third interconnect structure is 2~100µm, the thickness of the third interconnect structure is 2~20µm, and the line spacing of the third interconnect structure is ≤100µm.

[0016] Optionally, the material of the organic dielectric layer is polyimide (PI) or polybenzoxazole (PBO).

[0017] Optionally, the UBM layer is formed by a chemical plating process, wherein the UBM layer is a NiPdAu layer, wherein the thickness of the Ni layer is 1~5µm, the thickness of the Pd layer is 0.1~0.5µm, and the thickness of the Au layer is 0.1~2µm.

[0018] Optionally, the UBM layer is formed by an electroplating process, wherein the UBM layer is a Cu / Ni / SnAg layer, wherein the thickness of the Cu layer is 1~5µm, the thickness of the Ni layer is 0.01~2.5µm, and the thickness of the SnAg layer is 1~5µm.

[0019] The present invention also provides a silicon interposer board for use in radio frequency microsystems, which is prepared by the above-described method for preparing a silicon interposer board for use in radio frequency microsystems, comprising:

[0020] A silicon substrate having a front side and a back side disposed opposite to each other, the silicon substrate including a plurality of TSV blind vias and a first interconnect structure located in the TSV blind vias, the front side of the silicon substrate exposing the surface of the first interconnect structure;

[0021] A damascus wiring layer is located on the front side of the silicon substrate. The damascus wiring layer includes multiple inorganic dielectric layers and a second interconnect structure located in the inorganic dielectric layers. The second interconnect structure is electrically connected to the first interconnect structure.

[0022] An organic dielectric wiring layer is located on the upper surface of the damascus wiring layer. The organic dielectric wiring layer includes multiple organic dielectric layers and a third interconnect structure located in the organic dielectric layers. The third interconnect structure is electrically connected to the second interconnect structure.

[0023] The UBM layer is located on the upper surface of the third interconnect structure and is electrically connected to the third interconnect structure.

[0024] As described above, the silicon interposer board and its fabrication method for RF microsystems of the present invention have the following beneficial effects: A damascus wiring layer and an organic dielectric wiring layer are sequentially formed on a silicon substrate using damascus wiring and PI wiring processes. This allows for high-density integration using the silicon interposer board, achieving a TSV blind via aspect ratio of not less than 10:1 and at least 8 wiring layers, significantly improving the system's thermal stability and high-frequency performance, and providing a superior process platform for RF-digital integrated microsystems. Furthermore, the ultra-fine linewidth and spacing of the second interconnect structure in the damascus wiring layer effectively solves the bottleneck of high-density signal interconnection and significantly reduces transmission power consumption. The presence of the organic dielectric wiring layer overcomes the problem of high RF loss inherent in a single damascus wiring layer. In addition, simulations of the formed silicon interposer board show that adjusting the thickness of the organic dielectric layer can further control the warpage of the interposer board. Attached Figure Description

[0025] Figure 1 A process flow diagram showing the fabrication method of the silicon adapter board of the present invention for use in radio frequency microsystems is shown.

[0026] Figure 2The diagram shows a cross-sectional structure of the TSV blind via formed in a silicon substrate according to the present invention.

[0027] Figure 3 This diagram shows a cross-sectional structure of the present invention after the seed layer is formed in the TSV blind hole.

[0028] Figure 4 The diagram shows a cross-sectional view of the first interconnect structure of the present invention, which excessively covers the TSV blind via and the silicon substrate.

[0029] Figure 5 The diagram shown is a cross-sectional view of the present invention after the first interconnect structure is formed in the TSV blind via.

[0030] Figures 6 to 13 The diagram shows a cross-sectional structure of each step in forming the damascus wiring layer according to the present invention.

[0031] Figures 14 to 20 The diagram shows a cross-sectional structure of each step in forming the organic dielectric wiring layer according to the present invention.

[0032] Figure 21 The diagram shown is a cross-sectional view of the silicon adapter board of the present invention applied to radio frequency microsystems.

[0033] Component designation explanation

[0034] 10. Substrate; 101. Front side; 102. Back side; 103. TSV blind via; 104. First seed layer; 105. First interconnect structure; 15. Inorganic dielectric layer; 151. Barrier layer; 152. Passivation layer; 106. First photoresist layer; 107. First via opening; 108. Second seed layer; 109. Second interconnect structure; 110. Second photoresist layer; 111. Second via opening; 16. Damascus wiring layer; 112. Organic dielectric layer; 114. Third via opening; 115. Third seed layer; 116. Fourth patterned photoresist layer; 117. Third interconnect structure; 18. Organic dielectric wiring layer; 119. UBM layer; S1~S5, Steps. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0038] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0039] Please see Figures 1 to 21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] Example 1

[0041] This embodiment provides a method for fabricating a silicon interposer board for use in radio frequency microsystems, such as... Figure 1 The diagram shown is a process flow chart of the preparation method, which includes the following steps:

[0042] S1: A silicon substrate 10 is provided, the silicon substrate 10 having a front side 101 and a back side 102 disposed opposite to each other, and a plurality of TSV blind vias 103 are formed by etching on the front side 101 of the silicon substrate 10.

[0043] S2: An insulating barrier layer and a first seed layer 104 are sequentially formed on the sidewall and bottom of the TSV blind via 103. Metal is filled in the TSV blind via 103 to form a first interconnect structure 105. The first interconnect structure 105 is planarized so that the first interconnect structure 105 is flush with the front side 101 of the substrate 10.

[0044] S3: A damascus wiring layer 16 is formed on the front side 101 of the silicon substrate 10 using a damascus process. The damascus wiring layer 16 includes multiple inorganic dielectric layers 15 and a second interconnect structure 109 located in the inorganic dielectric layers 15. The second interconnect structure 109 is electrically connected to the first interconnect structure 105.

[0045] S4: An organic dielectric wiring layer 18 is formed on the damascus wiring layer 16 using the PI wiring process. The organic dielectric wiring layer 18 includes multiple organic dielectric layers 112 and a third interconnect structure 117 located in the organic dielectric layers 112. The third interconnect structure 117 is electrically connected to the second interconnect structure 109.

[0046] S5: A UBM layer 119 is formed on the third interconnect structure 117, and the UBM layer 119 is electrically connected to the third interconnect structure 117.

[0047] The following description, in conjunction with the accompanying drawings, further illustrates the fabrication method of the silicon interposer board used in radio frequency microsystems, as follows:

[0048] In step S1, please refer to Figure 2 A silicon substrate 10 is provided, the silicon substrate 10 having a front side 101 and a back side 102 disposed opposite to each other, and a plurality of TSV blind vias 103 are formed by etching on the front side 101 of the silicon substrate 10.

[0049] In this embodiment, the silicon substrate 10 has a front side 101 and a back side 102 disposed opposite to each other. The silicon substrate 10 is a wafer-level substrate 10. The size of the silicon substrate 10 can be 6 inches, 8 inches or 12 inches, and its shape can be circular, square or other arbitrary desired shape. No excessive restrictions are placed on the shape and size of the silicon substrate 10 here.

[0050] Optionally, the thickness of the silicon substrate 10 ranges from 0.5 to 1 mm, and is not limited here. By setting a suitable thickness for the silicon substrate 10, the mechanical strength of the silicon adapter can be guaranteed, and the silicon substrate 10 has a low coefficient of thermal expansion and a high thermal conductivity, thus possessing better thermal stability. In some embodiments, the steps for forming multiple TSV blind vias 103 include: first, determining the aperture size and geometric position of the TSV blind vias 103 to be formed in the silicon substrate 10; second, sequentially forming a hard mask layer on the front side 101 of the silicon substrate 10 and spin-coating a photoresist layer; performing photolithography and development on the photoresist layer to transfer the pattern of the TSV blind vias 103 with the determined aperture size and geometric position onto the hard mask layer; finally, using a deep silicon etching process with the hard mask layer as an etching mask to etch the TSV blind vias 103 in the silicon substrate 10, forming multiple TSV blind vias 103 arranged in an array in the silicon substrate 10; and then removing the hard mask layer by an etching process.

[0051] Specifically, in this embodiment, the thickness of the silicon substrate 10 is 725 μm, and the aspect ratio of the TSV blind via 103 is ≥10:1. For example, the diameter of the TSV blind via 103 can be 10 μm, and the depth of the TSV blind via 103 can be 100 μm, that is, the aspect ratio of the TSV blind via 103 is 10:1.

[0052] In step S2, please refer to Figures 3 to 5 An insulating barrier layer (not shown in the figure) and a first seed layer 104 are sequentially formed on the sidewall and bottom of the TSV blind via 103. Metal is filled in the TSV blind via 103 to form a first interconnect structure 105. The first interconnect structure 105 is planarized so that the first interconnect structure 105 is flush with the front side 101 of the substrate 10.

[0053] In this embodiment, the insulating barrier layer is made of one or more combinations of polycrystalline silicon, monocrystalline silicon, or silicon oxide. The insulating barrier layer can be formed using thermal oxidation or chemical vapor deposition processes. The insulating barrier layer is used to prevent material interdiffusion and mixing between the subsequently formed first seed layer 104 and first interconnect structure 105 and the silicon substrate 10. The formed insulating barrier layer covers the front side 101 of the silicon substrate 10, the sidewalls of the TSV blind via 103, and the bottom.

[0054] In this embodiment, the first seed layer 104 comprises one or more layers of metal. The metal forming the first seed layer 104 is at least one or a combination of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, or nickel. The first seed layer 104 can be formed using physical vapor deposition or chemical vapor deposition processes. Figure 3As shown, the first seed layer 104 formed covers the front side 101 of the silicon substrate 10, the sidewalls and bottom of the TSV blind via 103, and an insulating barrier layer is also formed between the seed layer 104 and the silicon substrate 10.

[0055] In this embodiment, metal is filled into the first seed layer 104 within the TSV blind via 103 to form a structure as described above. Figure 4 The first interconnect structure 105 is shown; and when the first interconnect structure 105 excessively covers the TSV blind via 103 and the front side 101 of the silicon substrate 10, as shown... Figure 5 As shown, a planarization process is also required to remove the redundant first interconnect structure 105.

[0056] Optionally, the material of the first interconnect structure 105 includes one of copper, aluminum, nickel, gold, silver, and titanium. The first interconnect structure 105 can be formed by a process such as electroplating deposition.

[0057] Optionally, the planarization process may include a combination of one or more processes such as grinding, chemical mechanical polishing, dry polishing, etching, and cutting. After the planarization process, the top of the first interconnect structure 105 is flush with the front side 101 of the substrate 10, and there is no obvious metal residue on the front side 101 of the substrate 10.

[0058] In step S3, please refer to Figures 6 to 13 A damascus wiring layer 16 is formed on the front side 101 of the silicon substrate 10 using a damascus process. The damascus wiring layer 16 includes multiple inorganic dielectric layers 15 and a second interconnect structure 109 located in the inorganic dielectric layers 15. The second interconnect structure 109 is electrically connected to the first interconnect structure 105.

[0059] Optionally, the inorganic dielectric layer 15 can be a non-photosensitive insulating dielectric layer or a photosensitive insulating dielectric layer. Specifically, when the inorganic dielectric layer 15 is a non-photosensitive insulating dielectric layer, the first via opening 107 can be formed by dry etching.

[0060] In this embodiment, the inorganic dielectric layer 15 includes a barrier layer 151 and a passivation layer 152 stacked together. The material of the passivation layer 151 includes one of silicon nitride and silicon oxynitride, and the material of the barrier layer 152 includes metal compounds of Ta and Ti such as TiN or TaN.

[0061] In this embodiment, the damask wiring layer 16 includes an inorganic dielectric layer 15 as an example. The process steps of the damask wiring layer 16 are as follows: First, as Figure 6As shown, an inorganic dielectric layer 15 is formed on the front side 101 of the silicon substrate 10 using physical vapor deposition and chemical vapor deposition methods. The inorganic dielectric layer 15 includes a barrier layer 151 and a passivation layer 152 stacked together, and a first photoresist layer 106 is formed on the passivation layer 152. Then, as... Figure 7 As shown, the first photoresist layer 106 undergoes a first exposure and development process to pattern the first photoresist layer 106, opening the area to be formed of the first via opening 107 and covering the area outside the first via opening 107. The inorganic dielectric layer 15 is then etched using a dry etching method to form the first via opening 107. The bottom of the first via opening 107 exposes the first interconnect structure 105, and the width of the first via opening 107 is greater than the width of the TSV blind via 103. The first photoresist layer is then removed. Then, as... Figure 8 As shown, an insulating barrier layer and a second seed layer 108 are sequentially formed on the sidewall and bottom of the first through-hole opening 107 and on the passivation layer 152 using physical vapor deposition or chemical vapor deposition processes, as follows: Figure 9 As shown, a metal material is deposited on the second seed layer 108 in the first through-hole opening 107 through an electroplating process to overfill the first through-hole opening 107. Excess metal material on the surface of the inorganic dielectric layer 15 is removed by a chemical mechanical polishing process, so that the surface of the metal material filling the first through-hole opening 107 is substantially flush with the surface of the passivation layer 152. Further, as... Figure 10 As shown, an inorganic dielectric layer 15 is further formed on the passivation layer 152 by chemical vapor deposition, and a second photoresist layer 110 is formed on the inorganic dielectric layer 15, as follows. Figure 11 As shown, the second photoresist layer 110 undergoes a second exposure and development process to achieve patterning of the second photoresist layer 110, forming the second via opening 111, as shown. Figure 12 As shown, an insulating barrier layer Ta and a seed layer Cu are sequentially formed on the sidewall, bottom, and top of the second via opening 111 using physical vapor deposition or chemical vapor deposition. A metal material is deposited on the Cu seed layer in the second via opening 111 by electroplating to overfill the second via opening 111. An excess second interconnect structure 109 located on the surface of the inorganic dielectric layer 15 is removed by chemical mechanical polishing, so that the surface of the second via opening 111 is substantially flush with the surface of the second interconnect structure 109.

[0062] Since the bottom of the first through-hole opening 107 exposes the first interconnect structure 104, an electrical connection is formed between the subsequently formed second interconnect structure 109 and the first interconnect structure 105.

[0063] In some embodiments, the metallic material deposited on the second seed layer 108, inside the first through-hole opening 107, and inside the second through-hole opening 111 includes copper.

[0064] Optionally, the number of layers in the damascus wiring layer 16 can be 1 to 5. For example, the number of layers in the damascus wiring layer 16 can be 1, 2, 3, 4, or 5. Specifically, as shown in the example... Figure 13 As shown, the above-described process steps for the damascus wiring layer 16 can be repeated to prepare a damascus wiring layer 16 comprising a multilayer inorganic dielectric layer 15 and a second interconnect structure 109 located in the inorganic dielectric layer.

[0065] In one embodiment, the linewidth of the second interconnect structure 109 is 0.2~2µm. For example, the linewidth of the second interconnect structure 109 is 0.2µm, 1µm, 1.8µm or 2µm. The density of the second interconnect structure 109 is 25%~50%. That is, for a single-layer damask wiring layer 16, the density of the second interconnect structure 109 can be 25%~50% of the total density of the damask wiring layer 16. When the damask wiring layer 16 includes multiple inorganic dielectric layers 15 and the second interconnect structure 109 located in the inorganic dielectric layers, the density of the second interconnect structure 109 in each inorganic dielectric layer 15 can be the same or different.

[0066] In one embodiment, the linewidth (S) / line spacing (L) of the second interconnect structure 109 is 0.4μm / 0.4μm≤S / L≤2μm / 2μm. The closer the S / L of the second interconnect structure 109 is to 0.4µm / 0.4µm, the denser the distribution of the second interconnect structure 109; the closer the S / L of the second interconnect structure 109 is to 2µm / 2µm, the sparser the distribution of the second interconnect structure 109. Specifically, in actual design, the sparse regions of the second interconnect structure 109 should be distributed as much as possible in the middle region of the silicon substrate 10 to reduce stress generated during packaging; and the second interconnect structure 109 with a large linewidth and high density should be avoided in areas prone to warping, such as the boundaries of the silicon substrate 10.

[0067] In step S4, please refer to Figures 14 to 21 An organic dielectric wiring layer 18 is formed on the damascus wiring layer 16 using a PI wiring process. The organic dielectric wiring layer 18 includes multiple organic dielectric layers 112 and a third interconnect structure 117 located in the organic dielectric layers 112. The third interconnect structure 117 is electrically connected to the second interconnect structure 109.

[0068] Optionally, the organic dielectric layer is a photosensitive insulating dielectric layer, including one of polyimide (PI) or polybenzoxazole (PBO).

[0069] In this embodiment, the organic dielectric wiring layer 18 includes an organic dielectric layer 112 as an example. The process steps of the organic dielectric wiring layer 18 are as follows: First, as Figure 14 As shown, an organic dielectric layer 112 is formed on the front side 101 of the damask wiring layer 16 by coating, and the organic dielectric layer is exposed and developed to achieve patterning, opening up the area where the third via opening 114 needs to be formed, thus forming the third via opening 114. The bottom of the third via opening 114 exposes the second interconnect structure 109 in the damask wiring layer 16. A stable structure is formed by high-temperature curing, and then, as... Figure 16 As shown, a third seed layer 115 is formed in the third through-hole opening 114 using a sputtering process, wherein the third seed layer 115 simultaneously covers the organic dielectric layer 112, and further, as... Figure 17 As shown, photoresist is coated again on the third seed layer 115 and exposed and developed to form a fourth patterned photoresist layer 116, opening up the area where the third interconnect structure 117 needs to be formed; then, as... Figure 18 As shown, a metal material is deposited in the third through-hole opening 114 and on the third seed layer 115 on the organic dielectric layer 112 through an electroplating process to form a structure as shown. Figure 18 The third interconnection structure 117 shown; as Figure 19 As shown, the fourth patterned photoresist layer 116 is removed, and the third seed layer 115 below the fourth patterned photoresist layer 116 is etched away.

[0070] Since the bottom of the third through-hole opening 114 exposes the second interconnect structure 109, an electrical connection is formed between the subsequently formed third interconnect structure 117 and the second interconnect structure 109.

[0071] In some embodiments, the metallic material deposited on the third seed layer 115 includes titanium and copper.

[0072] Optionally, the number of organic dielectric layers 112 is 1 to 4, and the thickness of each organic dielectric layer 112 is equal and ranges from 3 to 25 µm. For example, the number of organic dielectric layers 112 can be 1, 2, 3, or 4, and the thickness of each organic dielectric layer 112 can be 5 µm, 13 µm, or 20 µm. Specifically, for example... Figure 20 As shown, the PI wiring process can be repeated to fabricate an organic dielectric wiring layer 18 comprising a multilayer organic dielectric layer 112 and a third interconnect structure 117 located in the organic dielectric layer 112.

[0073] In one embodiment, the linewidth of the third interconnect structure 117 is 2~100µm, and the thickness of the third interconnect structure 117 is 2~20µm. For example, the linewidth of the third interconnect structure 117 is 2µm, 10µm, 50µm, or 100µm. The thickness of the third interconnect structure 117 is 2~20µm, that is, the thickness of the copper layer located on the seed layer 114 is 2~20µm, for example, it can be 2µm, 10µm, 15µm, or 20µm. The density of the third interconnect structure 117 is 25%~50%, that is, for a single organic dielectric wiring layer 18, the density of the third interconnect structure 117 can be 25%~50% of the total density of the organic dielectric wiring layer 18. When the organic dielectric wiring layer 18 is multi-layered, the density of the third interconnect structure 117 in each organic dielectric wiring layer 18 can be the same or different.

[0074] In one embodiment, the line spacing of the third interconnect structure 117 is ≤100μm. The smaller the line spacing of the third interconnect structure 117, the denser the distribution of the third interconnect structure 117. The larger the line spacing of the third interconnect structure 117, the sparser the distribution of the third interconnect structure 117. Specifically, the line spacing of the third interconnect structure 117 can be reasonably selected according to actual design needs.

[0075] Furthermore, in another embodiment, when the sparse distribution of the third interconnect structure 117 leads to high stress, the stress generated during packaging can be reduced by adding a dummy filling structure in the organic dielectric layer 112 to connect the third interconnect structure 117 together.

[0076] In step S5, please refer to Figure 21 A UBM layer 119 is formed on the third interconnect structure 117, and the UBM layer 119 is electrically connected to the third interconnect structure 117.

[0077] Specifically, in this embodiment, the UBM layer 119 is a NiPdAu layer, and the UBM layer 119 is electrically connected to the third interconnect structure 117. The NiPdAu layer is fabricated by chemical plating. The thickness of the Ni layer in the NiPdAu layer is 1~5µm, the thickness of the Pd layer is 0.1~0.5µm, and the thickness of the Au layer is 0.1~2µm.

[0078] In another embodiment, the UBM layer 119 is a Cu / Ni / SnAg layer, and the UBM layer 119 is electrically connected to the third interconnect structure 117. The Cu / Ni / SnAg layer is fabricated by an electroplating process. The thickness of the Cu layer in the Cu / Ni / SnAg layer is 1~5µm, the thickness of the Ni layer is 0.01~2.5µm, and the thickness of the SnAg layer is 1~5µm.

[0079] Example 2

[0080] This embodiment also provides a silicon adapter board for use in radio frequency microsystems. The silicon adapter board for use in radio frequency microsystems can be prepared by the above-described method for preparing silicon adapter boards for use in radio frequency microsystems, but is not limited thereto. In this embodiment, the silicon adapter board for use in radio frequency microsystems is directly prepared by the above-described preparation process. Therefore, the preparation process, materials, structure, etc. of the silicon adapter board for use in radio frequency microsystems can be referred to the above-described method for preparing silicon adapter boards for use in radio frequency microsystems, and will not be described in detail here.

[0081] like Figure 21 As shown, the silicon adapter board used in the radio frequency microsystem in this embodiment includes:

[0082] A silicon substrate 10 has a front side 101 and a back side 102 disposed opposite to each other. The silicon substrate 10 includes a plurality of TSV blind vias 103 and a first interconnect structure 105 located in the TSV blind vias 103. The front side 101 of the silicon substrate 10 exposes the surface of the first interconnect structure 105.

[0083] The damascus wiring layer 16 is located on the front side 101 of the silicon substrate 10. The damascus wiring layer 16 includes a multilayer inorganic dielectric layer 15 and a second interconnect structure 109 located in the inorganic dielectric layer 15. The second interconnect structure 109 is electrically connected to the first interconnect structure 105.

[0084] An organic dielectric wiring layer 18 is located on the upper surface of the damascus wiring layer 16. The organic dielectric wiring layer 18 includes multiple organic dielectric layers 112 and a third interconnect structure 117 located in the organic dielectric layers 112. The third interconnect structure 117 is electrically connected to the second interconnect structure 109.

[0085] UBM layer 119 is located on the upper surface of the third interconnect structure 117 and is electrically connected to the third interconnect structure 117.

[0086] By controlling the relevant parameters in the silicon substrate 10, TSV blind via 103, damask wiring layer 16 and organic dielectric wiring layer 18 in this embodiment, the silicon adapter board finally formed for use in radio frequency microsystems is simulated. During the simulation, the simulation temperature is gradually cooled from 200 ℃ to 0 ℃.

[0087] In this embodiment, when the thickness of the silicon substrate 10 is 725 μm, the thickness of the TSV blind via 102 is 100 μm, the number of damascus wiring layers 16 is 5 with a total thickness of 8.5 μm, and the number of organic dielectric wiring layers 18 is 3 with a total thickness of 39 μm, a simulation of a silicon adapter board applied to a radio frequency microsystem is performed. The simulation calculation shows that the maximum edge displacement of the silicon adapter board is 1.9 mm. However, when the thickness of a single organic dielectric wiring layer 18 is changed, making the total thickness of the organic dielectric wiring layer 18 15 μm, the simulation of the silicon adapter board applied to the radio frequency microsystem is performed... A second simulation was performed, and the maximum displacement of the silicon interposer's edge was calculated to be 1.1 mm. The above results show that changing the thickness of the organic dielectric wiring layer 18 can significantly alleviate the warping phenomenon of the interposer. When the thickness of a single layer of the organic dielectric wiring layer 18 was changed again, so that the total thickness of the organic dielectric wiring layer 18 was 30 μm, the silicon interposer applied to the RF microsystem was simulated again. The maximum displacement of the silicon interposer's edge was calculated to be 1.5 mm. That is, by adjusting the thickness of the organic dielectric wiring layer 18, the warping of the interposer can be controlled.

[0088] In summary, the silicon interposer board and its fabrication method for RF microsystems of the present invention, by sequentially forming multiple damascus wiring layers and multiple organic dielectric wiring layers on a silicon substrate using damascus wiring and PI wiring processes, enables the silicon interposer board to achieve high-density integration with a TSV blind via aspect ratio of not less than 10:1 and 8 wiring layers, significantly improving the system's thermal stability and high-frequency performance, and providing a better process platform support for RF-digital integrated microsystems. Furthermore, the ultra-fine linewidth and spacing of the second interconnect structure in the damascus wiring layer effectively solves the bottleneck of high-density signal interconnection and significantly reduces transmission power consumption; while the presence of the organic dielectric wiring layer overcomes the problem of high RF loss inherent in a single damascus wiring layer. In addition, by adjusting the thickness of the organic dielectric wiring layer, the warpage of the interposer board can be further controlled, and the fabrication process is relatively simple, easy to implement, and has low manufacturing costs.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon adapter board for use in radio frequency microsystems, characterized in that, Includes the following steps: A silicon substrate is provided, the silicon substrate having a front side and a back side disposed opposite to each other, and a plurality of TSV blind vias are formed by etching on the front side of the silicon substrate; An insulating barrier layer and a first seed layer are sequentially formed on the sidewall and bottom of the TSV blind via. Metal is filled in the TSV blind via to form a first interconnect structure. The first interconnect structure is planarized to make the first interconnect structure flush with the front side of the substrate. A damascus wiring layer is formed on the front side of the silicon substrate using a damascus process. The damascus wiring layer includes multiple inorganic dielectric layers and a second interconnect structure located in the inorganic dielectric layers. The second interconnect structure is electrically connected to the first interconnect structure. An organic dielectric wiring layer is formed on the damascus wiring layer using a PI wiring process. The organic dielectric wiring layer includes multiple organic dielectric layers and a third interconnect structure located in the organic dielectric layers. The third interconnect structure is electrically connected to the second interconnect structure. A UBM layer is formed on the third interconnect structure, and the UBM layer is electrically connected to the third interconnect structure.

2. The method for fabricating a silicon adapter board for use in radio frequency microsystems according to claim 1, characterized in that: The density of the second interconnect structure and the density of the third interconnect structure are both 25% to 50%.

3. The method for fabricating a silicon adapter board for use in radio frequency microsystems according to claim 1, characterized in that: The aspect ratio of the TSV blind hole is ≥10:

1.

4. The method for fabricating a silicon interposer board for use in radio frequency microsystems according to claim 1, characterized in that: The number of inorganic dielectric layers is 1 to 5, and the linewidth (S) / line spacing (L) of the second interconnect structure is 0.4μm / 0.4μm≤S / L≤2μm / 2μm.

5. The method for fabricating a silicon interposer board for use in radio frequency microsystems according to claim 1, characterized in that: The number of organic media layers is 1 to 4, and the thickness of each organic media layer is equal and ranges from 3 to 25 µm.

6. The method for fabricating a silicon interposer board for use in radio frequency microsystems according to claim 1, characterized in that: The linewidth of the third interconnect structure is 2~100µm, the thickness of the third interconnect structure is 2~20µm, and the line spacing of the third interconnect structure is ≤100µm.

7. The method for fabricating a silicon interposer board for use in radio frequency microsystems according to claim 1, characterized in that: The organic media layer is made of polyimide (PI) or polybenzoxazole (PBO).

8. The method for fabricating a silicon interposer board for use in radio frequency microsystems according to claim 1, characterized in that: The UBM layer is formed by chemical plating, and the UBM layer is a NiPdAu layer, wherein the thickness of the Ni layer is 1~5µm, the thickness of the Pd layer is 0.1~0.5µm, and the thickness of the Au layer is 0.1~2µm.

9. The method for fabricating a silicon adapter board for use in radio frequency microsystems according to claim 1, characterized in that: The UBM layer is formed by an electroplating process. The UBM layer is a Cu / Ni / SnAg layer, wherein the thickness of the Cu layer is 1~5µm, the thickness of the Ni layer is 0.01~2.5µm, and the thickness of the SnAg layer is 1~5µm.

10. A silicon adapter board for use in radio frequency microsystems, characterized in that, The silicon interposer board used in the radio frequency microsystem is prepared by the method for preparing a silicon interposer board for the radio frequency microsystem as described in any one of claims 1 to 9, comprising: A silicon substrate having a front side and a back side disposed opposite to each other, the silicon substrate including a plurality of TSV blind vias and a first interconnect structure located in the TSV blind vias, the front side of the silicon substrate exposing the surface of the first interconnect structure; A damascus wiring layer is located on the front side of the silicon substrate. The damascus wiring layer includes multiple inorganic dielectric layers and a second interconnect structure located in the inorganic dielectric layers. The second interconnect structure is electrically connected to the first interconnect structure. An organic dielectric wiring layer is located on the upper surface of the damascus wiring layer. The organic dielectric wiring layer includes multiple organic dielectric layers and a third interconnect structure located in the organic dielectric layers. The third interconnect structure is electrically connected to the second interconnect structure. The UBM layer is located on the upper surface of the third interconnect structure and is electrically connected to the third interconnect structure.

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