Semiconductor structure preparation method and semiconductor structure

Abstract

The invention relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate of which the top surface is covered with a first lamination; after at least one through hole penetrating through the first lamination layer is formed, a first conductive structure with the top surface lower than the top surface of the dielectric lamination layer is formed in the through hole, and part of the dielectric lamination layer is transversely etched and removed to obtain a groove exposing the whole top surface of the first conductive structure; after the first sacrificial layer is removed, a second barrier layer at least covering the side wall of the groove is formed; after the groove is filled with a second sacrificial layer, forming a second lamination layer covering the second sacrificial layer; a T-shaped groove which penetrates through the second lamination layer and is narrow in bottom and wide in top is formed; after the second sacrificial layer is removed, a target groove is obtained; and after a third barrier layer covering the inner surface of the target groove is formed, a target conductive structure is formed in the target groove. At least the problem of electrical failure caused by metal atom migration can be prevented.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the rapid development of semiconductor technology, the market has increasingly higher requirements for the integration, performance and reliability of integrated circuits, which has led to a continuous increase in the number of stacked film layers and the complexity of the structure inside the chip. Back-end interconnect technology is becoming more and more important in the chip manufacturing field.

[0003] In advanced manufacturing processes, the critical dimensions of patterns are getting smaller and smaller, the dielectric constant of interlayer dielectric materials is getting lower and lower, the porosity is getting higher and higher, and the structure is also more loose. This leads to an increase in the resistance of the interconnect structure, and even open circuits and short circuits, causing the entire chip to fail. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure fabrication method and semiconductor structure to address the problems in the background art mentioned above. This method can at least utilize a barrier layer to fully surround the target conductive structure, preventing electrical failures caused by metal atom migration, reducing the impedance of the target conductive structure, and reducing the probability of open circuits or short circuits.

[0005] According to various embodiments of this disclosure, a first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided with a first stacked layer on its top surface, the first stacked layer including a dielectric stacked layer and a first sacrificial layer stacked sequentially in a direction away from the substrate;

[0007] After forming at least one through hole through the first stack, a first conductive structure is formed in the through hole with its top surface lower than the top surface of the dielectric stack. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer.

[0008] Laterally etch and remove part of the dielectric stack to obtain a groove that exposes the entire top surface of the first conductive structure. The critical dimensions of the groove are related to the critical dimensions of the first conductive structure.

[0009] After removing the first sacrificial layer, a second barrier layer is formed that at least covers the sidewalls of the groove;

[0010] After the groove is filled with the second sacrificial layer, a second stack covering the second sacrificial layer is formed;

[0011] A T-shaped groove is formed that runs through the second stack and is narrower at the bottom and wider at the top. The bottom surface of the T-shaped groove is located inside the top surface of the second sacrificial layer.

[0012] After removing the second sacrificial layer, the target trench is obtained;

[0013] After forming a third barrier layer covering the inner surface of the target trench, a target conductive structure is formed inside the target trench.

[0014] The semiconductor structure fabrication method in the above embodiments involves forming at least one via penetrating the first stacked layer, followed by forming a first conductive structure within the via with its top surface lower than the top surface of the dielectric stack. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer, forming a first conductive layer surrounded by the first barrier layer on its bottom surface and outer sidewall. The first sacrificial layer protects the dielectric stack, preventing damage during via etching and avoiding uncontrollable depth of subsequent grooves that could affect the thickness / height of the target conductive structure within the groove. Then, based on the desired lateral etching depth, a portion of the dielectric stack is laterally etched and removed to obtain a groove exposing the entire top surface of the first conductive structure. The critical dimensions of the groove are related to the critical dimensions of the first conductive structure, ensuring not only that the groove exposes the entire top surface of the first conductive structure but also preventing an increase in the probability of current leakage paths between adjacent interconnect structures due to excessively large groove critical dimensions. The lateral etching depth is related to the lateral etching rate and etching time; the lateral etching depth can be precisely controlled by controlling the etching time. After removing the first sacrificial layer, a second barrier layer is formed, at least covering the sidewalls of the groove. The groove is then filled with the second sacrificial layer, which defines the shape and size of the bridging portion. Next, a second stack is formed, covering the second sacrificial layer. The number of film layers and the material of each layer in the second stack can correspond to the same number of film layers and the same material as the first stack, reducing the complexity and cost of the fabrication process. A T-shaped groove, narrower at the bottom and wider at the top, is formed, penetrating the second stack. The bottom surface of the T-shaped groove is inside the top surface of the second sacrificial layer. After removing the second sacrificial layer, the target trench is obtained. The target trench includes a connected T-shaped groove and a recess. After forming a third barrier layer covering the inner surface of the target trench, a target conductive structure is formed within the target trench. The portion of the target conductive structure located within the groove constitutes a bridging section. The critical dimension of the bridging section is larger than and related to the critical dimension of the first conductive structure. This not only avoids interconnection open circuits or short circuits due to the bottom critical dimension of the target conductive structure being too small, but also reduces the impedance of the target conductive structure. Since the outer wall and bottom surface of the first conductive layer are covered with a first barrier layer, and the outer wall of the target conductive structure is covered with a second barrier layer and a third barrier layer, the target conductive structure is completely surrounded by barrier layers, preventing electrical failures caused by metal atom migration and improving the yield and reliability of the interconnection structure.

[0015] In some embodiments, the second stack and the first stack have the same number of film layers; in the film layer ordering along the direction away from the substrate, the same film layer number in the first stack and the second stack corresponds to the same material. This reduces the complexity and cost of the fabrication process.

[0016] In some embodiments, the first stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first sacrificial layer sequentially stacked along a first direction away from the top surface of the substrate; lateral etching and removal of a portion of the dielectric stack includes: lateral etching and removal of a portion of the second dielectric layer and a portion of the third dielectric layer to obtain a groove exposing the entire top surface of the first conductive structure, wherein the ratio of the critical dimension of the groove to the critical dimension of the first conductive structure is R, R ∈ [1.05, 1.1]. The first sacrificial layer can protect the third dielectric layer from damage during the etching process to form vias. The depth of the lateral etching is related to the lateral etching rate and etching time, and the lateral etching depth can be precisely controlled by controlling the etching time. The thickness / height of the bridging portion within the groove can be precisely controlled by controlling the lateral etching rate, etching time, and the thickness / height of the third dielectric layer. The ratio of the critical dimension of the groove to the critical dimension of the first conductive structure is R, where R ∈ [1.05, 1.1]. This avoids the critical dimension of the groove being too large, which would increase the probability of current leakage paths between adjacent interconnect structures fabricated subsequently; and avoids the critical dimension of the groove being too small, which would increase the impedance of the target conductive structure.

[0017] In some embodiments, a second barrier layer covers the sidewalls of the groove, a second sacrificial layer covers the entire top surface of the first conductive structure exposed by the groove, and a second sacrificial layer covers a portion of the dielectric stack exposed by the groove.

[0018] In some embodiments, the second barrier layer covers the sidewalls of the groove, the second barrier layer covers the entire top surface of the first conductive structure exposed by the groove, and the second barrier layer covers a portion of the dielectric stack exposed by the groove.

[0019] In some embodiments, the first sacrificial layer includes a metal barrier layer. The metal barrier layer can protect the dielectric stack from damage during etching to form vias, and prevent subsequent uncontrollable trench depth from affecting the thickness / height of the target conductive structure within the trench.

[0020] In some embodiments, the second sacrificial layer comprises α-carbon and / or fluorinated amorphous carbon, which facilitates the removal of the second sacrificial layer using an ashing process, thereby reducing the complexity and cost of the preparation process.

[0021] In some embodiments, the second sacrificial layer includes a target carbon layer; removing the second sacrificial layer includes treating and removing the target carbon layer with a target gas containing ozone.

[0022] In some embodiments, the first dielectric layer includes a nitrogen-doped carbide film; forming at least one via through the first stack includes: dry etching the first stack to obtain an initial via through the first sacrificial layer, the third dielectric layer, and the second dielectric layer; and etching the nitrogen-doped carbide film through the initial via to obtain the via. The nitrogen-doped carbide film can effectively suppress the diffusion of metal atoms from the interconnect structure to the dielectric layer, thereby improving device performance and reliability.

[0023] In some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following target process steps: the semiconductor structure fabrication method as described in any of the foregoing embodiments; planarizing a second stack to obtain a target conductive structure whose top surface is flush with the top surface of the remaining second stack.

[0024] In some embodiments, the target process steps are repeated a preset number of times. The preset number of times the target process steps are repeated can be set according to the specific requirements of the conductive plugs for the height / thickness of the interconnect structure in a particular application scenario.

[0025] In some embodiments, a third aspect of this disclosure provides a semiconductor structure fabricated using the semiconductor structure fabrication method described in any of the foregoing embodiments. The semiconductor structure includes a substrate, a dielectric stack, and a second stack. The top surface of the substrate is covered by the dielectric stack, and the dielectric stack includes at least one via penetrating the dielectric stack. The via includes a first conductive structure whose top surface is lower than the top surface of the dielectric stack. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer. The dielectric stack includes a groove exposing the entire top surface of the first conductive structure, and the critical dimension of the groove is related to the critical dimension of the first conductive structure. The sidewall of the groove is covered by a second barrier layer. The second stack is located on the top surface of the dielectric stack and includes a T-shaped groove that penetrates the second stack and communicates with the groove. The T-shaped groove is narrower at the bottom and wider at the top, and the bottom surface of the T-shaped groove is located inside the groove. The T-shaped groove and the groove together constitute a target trench. The inner surface of the target trench is covered by a third barrier layer, and the target trench includes a target conductive structure.

[0026] The unexpected technical effects that can be produced by the embodiments of this disclosure include:

[0027] The first sacrificial layer protects the dielectric stack, preventing damage during via etching and ensuring uncontrollable depth of subsequent trenches that could affect the thickness / height of the target conductive structure within the trench. Then, based on the desired lateral etching depth, a portion of the dielectric stack is etched and removed laterally, resulting in a trench exposing the entire top surface of the first conductive structure. The critical dimensions of the trench are related to the critical dimensions of the first conductive structure, ensuring not only complete exposure of the top surface but also preventing an increase in the probability of current leakage paths between adjacent interconnect structures due to excessively large trench critical dimensions. The lateral etching depth is related to the lateral etching rate and etching time, allowing for precise control of the lateral etching depth by controlling the etching time. After removing the first sacrificial layer, a second barrier layer is formed, at least covering the trench sidewalls. The trench is then filled with the second sacrificial layer, which defines the shape and size of the bridging portion. Subsequently, a second stack covering the second sacrificial layer is formed. The number of layers and the material of each layer in the second stack can correspond to the same number of layers and the material of each layer in the first stack, reducing the complexity and cost of the fabrication process. The target trench includes interconnected T-grooves and recesses. After a third barrier layer is formed covering the inner surface of the target trench, a target conductive structure is formed within the target trench. The portion of the target conductive structure located within the recess constitutes a bridging portion. The critical dimension of the bridging portion is larger than and related to the critical dimension of the first conductive structure. This not only avoids interconnection open circuits or short circuits due to the bottom critical dimension of the target conductive structure being too small, but also reduces the impedance of the target conductive structure. Since the outer walls and bottom surface of the first conductive layer are covered by the first barrier layer, and the outer walls of the target conductive structure are covered by the second and third barrier layers, the target conductive structure is completely surrounded by barrier layers, preventing electrical failures caused by metal atom migration and improving the yield and reliability of the interconnect structure. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 The diagram shown is a flowchart illustrating a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0030] Figure 2 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming the first stack in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0031] Figure 3The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a patterned mask layer on the first stack in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0032] Figure 4 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a through-hole in step S20 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0033] Figure 5 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a conductive material in step S20 of a semiconductor structure preparation method provided in an embodiment of this disclosure.

[0034] Figure 6 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming the first conductive structure in step S20 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0035] Figure 7 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a groove in step S30 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0036] Figure 8 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after removing the first sacrificial layer in step S40 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0037] Figure 9a The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first photoresist material layer on a second stack in step S50 of a semiconductor structure fabrication method provided in an embodiment of this disclosure; wherein, the second barrier layer covers the sidewalls and bottom surface of the groove.

[0038] Figure 9b The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first photoresist material layer on a second stack in step S50 of a semiconductor structure fabrication method provided in an embodiment of this disclosure; wherein the second barrier layer only covers the sidewalls of the groove.

[0039] Figure 10 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second photoresist material layer on a second stack in step S50 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0040] Figure 11The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a T-groove in the second stack in step S60 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0041] Figure 12 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after removing the second sacrificial layer in step S70 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0042] Figure 13 The diagram shown is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the target conductive structure in step S80 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0043] Explanation of reference numerals in the attached figures:

[0044] 101. Substrate; 10. Dielectric stack; 11. First dielectric layer; 12. Second dielectric layer; 13. Third dielectric layer; 14. First sacrificial layer; 15. First barrier layer; 16. First conductive structure; 201. Via; 30. Groove; 17. Second barrier layer; 18. Second sacrificial layer; 20. Second stack; 50. T-groove; MT. Target trench; 21. First dielectric layer; 22. Second dielectric layer; 23. Third dielectric layer; 24. Third sacrificial layer; 31. Fourth sacrificial layer; 32. First photoresist layer; 33. Second photoresist layer; PR1. First photoresist layer; T0. First pattern; 41. Third photoresist layer; 42. Fourth photoresist layer; PR2. Second photoresist layer; 60. Target conductive structure; 61. Third barrier layer; 62. Bridging portion. Detailed Implementation

[0045] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0049] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0052] In the embodiments of this disclosure, "stacked" or "layered structure" can refer to one or more layers.

[0053] Please see Figure 1 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising: steps S10-S80, wherein:

[0054] Step S10: Provide a substrate with a first stacked layer on its top surface, the first stacked layer including a dielectric stacked layer and a first sacrificial layer stacked sequentially along the direction away from the substrate;

[0055] Step S20: After forming at least one through hole through the first stack, a first conductive structure with its top surface lower than the top surface of the dielectric stack is formed in the through hole. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer.

[0056] Step S30: Laterally etch and remove part of the dielectric stack to obtain a groove that exposes the entire top surface of the first conductive structure. The critical dimensions of the groove are related to the critical dimensions of the first conductive structure.

[0057] Step S40: After removing the first sacrificial layer, a second barrier layer is formed that at least covers the sidewalls of the groove;

[0058] Step S50: After filling the groove with the second sacrificial layer, a second stack covering the second sacrificial layer is formed;

[0059] Step S60: Form a T-shaped groove that penetrates the second stack and is narrower at the bottom and wider at the top, with the bottom surface of the T-shaped groove located inside the top surface of the second sacrificial layer;

[0060] Step S70: After removing the second sacrificial layer, the target trench is obtained;

[0061] Step S80: After forming a third barrier layer covering the inner surface of the target trench, a target conductive structure is formed inside the target trench.

[0062] Please continue reading. Figure 1 After forming at least one via penetrating the first stack, a first conductive structure is formed within the via with its top surface lower than the top surface of the dielectric stack. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer, forming a first conductive layer surrounded by the first barrier layer on its bottom surface and outer sidewall. The first sacrificial layer protects the dielectric stack, preventing damage during via etching and avoiding uncontrollable depth of subsequent grooves that could affect the thickness / height of the target conductive structure within the groove. Then, according to the required lateral etching depth, a portion of the dielectric stack is laterally etched and removed to obtain a groove exposing the entire top surface of the first conductive structure. The critical dimension of the groove is related to the critical dimension of the first conductive structure, ensuring not only that the groove exposes the entire top surface of the first conductive structure but also preventing an increase in the probability of current leakage paths between adjacent interconnect structures due to excessively large groove critical dimensions. The lateral etching depth is related to the lateral etching rate and etching time, and the lateral etching depth can be precisely controlled by controlling the etching time. After removing the first sacrificial layer, a second barrier layer is formed, at least covering the sidewalls of the groove. The groove is then filled with the second sacrificial layer, which defines the shape and size of the bridging portion. Next, a second stack is formed, covering the second sacrificial layer. The number of film layers and the material of each layer in the second stack can correspond to the same number of film layers and the same material as the first stack, reducing the complexity and cost of the fabrication process. A T-shaped groove, narrower at the bottom and wider at the top, is formed, penetrating the second stack. The bottom surface of the T-shaped groove is inside the top surface of the second sacrificial layer. After removing the second sacrificial layer, the target trench is obtained. The target trench includes a connected T-shaped groove and a recess. After forming a third barrier layer covering the inner surface of the target trench, a target conductive structure is formed within the target trench. The portion of the target conductive structure located within the groove constitutes a bridging section. The critical dimension of the bridging section is larger than and related to the critical dimension of the first conductive structure. This not only avoids interconnection open circuits or short circuits due to the bottom critical dimension of the target conductive structure being too small, but also reduces the impedance of the target conductive structure. Since the outer wall and bottom surface of the first conductive layer are covered with a first barrier layer, and the outer wall of the target conductive structure is covered with a second barrier layer and a third barrier layer, the target conductive structure is completely surrounded by barrier layers, preventing electrical failures caused by metal atom migration and improving the yield and reliability of the interconnection structure.

[0063] In some embodiments, the substrate provided in step S10 may be made of materials including, but not limited to, semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate is a semiconductor structure that provides mechanical support and electrical properties for fabricating the semiconductor structure. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art can select the type of substrate based on the type of transistors formed on the substrate; therefore, the type of substrate should not limit the scope of this disclosure.

[0064] Please refer to Figure 2 In some embodiments, a series of layers are sequentially formed on the top surface of the substrate in a direction away from the substrate: NDC film (nitrogen-doped carbide film), SICO film (silicon carbide oxide film), TEOS film (tetraethyl orthosilicate film), TIN film (titanium nitride film), SION film (silicon oxynitride film), OX film (silicon oxide film), BARC layer (bottom anti-reflective coating), and PR layer (photoresist layer). It should be noted that this is only an illustrative example illustrating the specific implementation principle of this embodiment. In different embodiments, the film materials can be equivalently replaced, or the film thickness can be modified as needed to meet the actual requirements of different application scenarios.

[0065] Please continue to refer to this. Figure 2 In some embodiments, the PR layer and BARC layer are etched based on the first photomask to obtain a first pattern (not shown) that is spaced apart along a direction parallel to the top surface of the substrate.

[0066] Please refer to Figure 3 In some embodiments, the SION film and TIN film are further etched using the first pattern as a mask to obtain first openings (not shown) spaced apart along a direction parallel to the top surface of the substrate.

[0067] Please refer to Figure 4 In some embodiments, the TEOS film, SICO film, and NDC film are further etched using the first opening as a mask to obtain vias (not shown) spaced apart along a direction parallel to the top surface of the substrate.

[0068] Please refer to Figure 5 In some embodiments, after forming a first conductive layer covering the inner surface of the via and the top surface of the TIN film, a conductive material (not shown) is formed to fill the via.

[0069] Please refer to Figure 6In some embodiments, in step S10, a substrate 101 with a first stacked layer covering its top surface is provided. The first stacked layer includes a dielectric stacked layer 10 and a first sacrificial layer 14 sequentially stacked along a direction away from the substrate 101. In step S20, after forming at least one through-hole 201 penetrating the first stacked layer, a first conductive structure 16 with its top surface lower than the top surface of the dielectric stacked layer 10 is formed within the through-hole 201. The first conductive structure 16 includes a first conductive layer and a first barrier layer 15 covering the outer sidewall and bottom surface of the first conductive layer. The material of the first barrier layer 15 may include, but is not limited to, at least one of titanium nitride, cobalt, platinum, and titanium-tungsten layers.

[0070] For example, please continue to refer to Figures 5-6 The first stack includes a first dielectric layer 11, a second dielectric layer 12, a third dielectric layer 13, and a first sacrificial layer 14, sequentially stacked along a first direction away from the top surface of the substrate 101; the first dielectric layer 11, the second dielectric layer 12, and the third dielectric layer 13 together constitute the dielectric stack 10. The first dielectric layer 11 may include an NDC film, the second dielectric layer 12 may include a SiCO film, the third dielectric layer 13 may include a TEOS film, and the first sacrificial layer 14 may include a metal barrier layer, such as a TIN film. The metal barrier layer can protect the dielectric stack 10, preventing damage to the dielectric stack 10 during etching to form the via 201, and preventing the uncontrollable depth of the subsequent groove 30 from affecting the thickness / height of the target conductive structure 60 within the groove 30.

[0071] For example, please continue to refer to Figures 5-6 It can be done in the flattening process Figure 5 After the conductive material is etched, the conductive material is etched back to obtain a first conductive structure 16 with its top surface lower than the top surface of the dielectric stack 10. The conductive material retained in the via 201 is used to form the first conductive structure 16.

[0072] For example, please continue to refer to Figure 6 The first dielectric layer 11 includes a nitrogen-doped carbide film; forming at least one via 201 penetrating the first stack includes: dry etching the first stack to obtain an initial via penetrating the first sacrificial layer 14, the third dielectric layer 13, and the second dielectric layer 12; and etching the nitrogen-doped carbide film through the initial via to obtain the via 201. The nitrogen-doped carbide film can effectively suppress the diffusion of metal atoms from the interconnect structure to the dielectric layer, thereby improving device performance and reliability.

[0073] Please refer to Figure 7 In some embodiments, step S30, lateral etching and removal of a portion of the dielectric stack 10, includes:

[0074] Laterally etch and remove part of the second dielectric layer 12 and part of the third dielectric layer 13 to obtain a groove 30 that exposes the entire top surface of the first conductive structure 16. The ratio of the critical dimension of the groove 30 to the critical dimension of the first conductive structure 16 is R, where R ∈ [1.05, 1.1].

[0075] For example, please continue to refer to Figure 7 The first sacrificial layer 14 protects the third dielectric layer 13, preventing damage during the etching process to form the via 201. The depth of the lateral etching is related to the lateral etching rate and etching time, and the lateral etching depth can be precisely controlled by controlling the etching time. The thickness / height of the bridging portion within the groove 30 can be precisely controlled by controlling the lateral etching rate, etching time, and the thickness / height of the third dielectric layer 13. The ratio of the critical dimension of the groove 30 to the critical dimension of the first conductive structure 16 is R, where R ∈ [1.05, 1.1]. For example, R can be 1.05, 1.07, 1.09, or 1.1. This avoids the critical dimension of the groove 30 being too large, which would increase the probability of current leakage paths between subsequently fabricated adjacent interconnect structures; and avoids the critical dimension of the groove 30 being too small, which would increase the impedance of the target conductive structure 60.

[0076] Please refer to Figure 8 In some embodiments, in step S40, a dry etching process can be used to remove the first sacrificial layer 14.

[0077] Please refer to Figure 9a In some embodiments, after removing the first sacrificial layer 14 in step S40, a second barrier layer 17 covering at least the sidewalls of the groove 30 can be formed by a deposition process; the material of the second barrier layer 17 may include, but is not limited to, at least one of titanium nitride layer, cobalt layer, platinum layer and titanium tungsten layer.

[0078] Please continue to refer to this. Figure 9a In some embodiments, in step S50, the second sacrificial layer 18 is filled into the groove 30, and after planarization, a second sacrificial layer 18 with its top surface flush with the top surface of the third dielectric layer 13 is obtained.

[0079] Please continue to refer to this. Figure 9a In some embodiments, in step S50, a second stack 20 covering the second sacrificial layer 18 is formed. The second sacrificial layer 18 may include α-carbon and / or fluorinated amorphous carbon, which facilitates the removal of the second sacrificial layer 18 by an ashing process, reducing the complexity and cost of the preparation process.

[0080] Please continue to refer to this. Figure 9aIn some embodiments, the second stack 20 includes a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, and a third sacrificial layer 24 sequentially stacked along the direction away from the substrate 101. The number of film layers in the second stack 20 and the first stack can be the same; in the film layer ordering along the direction away from the substrate 101, the same film layer number in the first stack and the second stack 20 corresponds to the same material. This reduces the complexity and cost of the fabrication process.

[0081] Please continue to refer to this. Figure 9a In some embodiments, after the fourth sacrificial layer 31, the first photoresist layer 32, the second photoresist layer 33, and the first photoresist layer PR1 are sequentially formed on the top surface of the second stack 20, the first photoresist layer PR1 is patterned to obtain the patterned first photoresist layer PR1.

[0082] Please continue to refer to this. Figure 9a In some embodiments, the patterned first photoresist material layer PR1 is used as a mask to etch the second photoresist material layer 33 and the first photoresist material layer 32 to obtain a first pattern T0. The first pattern T0 includes a plurality of openings spaced apart along a direction parallel to the top surface of the substrate.

[0083] Please continue to refer to this. Figure 9b In some embodiments, Figure 9b and Figure 9a The difference is that, Figure 9b The second barrier layer 17 located on the bottom surface of the groove 30 was removed by etching. The second barrier layer 17 covers the sidewall of the groove 30, and the second sacrificial layer 18 directly covers the entire top surface of the first conductive structure 16 exposed in the groove 30, and the second sacrificial layer 18 directly covers the exposed portion of the dielectric stack 10 in the groove 30.

[0084] Please refer to Figure 10 In some embodiments, the fourth sacrificial layer 31 is etched further using the first pattern T0 as a mask to obtain a second pattern (not shown). The second pattern includes a plurality of openings that expose portions of the third dielectric layer 23, which are spaced apart along a direction parallel to the top surface of the substrate.

[0085] Please continue to refer to this. Figure 10In some embodiments, a third photoresist layer 41, at least filling the second pattern, can be formed using a deposition process. The third photoresist layer 41 may include an organic dielectric layer (ODL) to reduce the dielectric constant. A fourth photoresist layer 42 is then formed on top of the third photoresist layer 41. The fourth photoresist layer 42 may include a silicon-based hard mask (SHB) layer, used as an anti-reflection layer and etching mask in the photolithography process. A second photoresist layer PR2 is then formed on top of the fourth photoresist layer 42, resulting in an "ODL-SHB-PR" stacked structure to optimize photolithography performance and process tolerance. The second photoresist layer PR2 is patterned to form a third pattern (not shown) within it.

[0086] Please refer to Figure 11 In some embodiments, in step S60, the patterned second photoresist material layer PR2 is used as a mask to etch the second stack 20 to form a T-shaped groove 50 that penetrates the second stack 20 and is narrow at the bottom and wide at the top. The bottom surface of the T-shaped groove 50 is located inside the top surface of the second sacrificial layer 18.

[0087] Please refer to Figure 12 In some embodiments, in step S70, after removing the second sacrificial layer 18, a target trench MT is obtained, which includes interconnected grooves 30 and T-grooves 50.

[0088] Please continue to refer to this. Figure 12 In some embodiments, the second sacrificial layer 18 includes a target carbon layer; removing the second sacrificial layer 18 includes treating and removing the target carbon layer with a target gas containing ozone.

[0089] Please refer to Figure 13 In some embodiments, after forming the third barrier layer 61 covering the inner surface of the target trench MT in step S80, a target conductive structure 60 is formed within the target trench MT. The target conductive structure 60 located within the groove 30 serves to form a bridging portion 62. The target conductive structure 60 located within the T-groove 50 serves to form a conductive interconnect portion (not shown). The orthographic projection of the bottom surface of the conductive interconnect portion onto the top surface of the bridging portion 62 is located within the top surface of the bridging portion 62. The critical dimension of the bridging portion 62 is larger than and associated with the critical dimension of the first conductive structure 16. This not only avoids the interconnection opening or short circuit due to the bottom critical dimension of the target conductive structure 60 being too small, but also reduces the impedance of the target conductive structure 60.

[0090] Figures 10-13 based on Figure 9a If subsequent process steps are performed, Figure 9bContinuing with subsequent process steps will still yield results. Figure 13 The semiconductor structure shown differs in that the second barrier layer 17 covers the sidewalls of the groove 30, the second barrier layer 17 covers the entire top surface of the first conductive structure 16 exposed in the groove 30, and the second barrier layer 17 covers a portion of the dielectric stack 10 exposed in the groove 30.

[0091] In some embodiments, a method for fabricating a semiconductor structure is provided, comprising the following target process steps: the semiconductor structure fabrication method as described in any of the foregoing embodiments; planarizing the second stack 20 to obtain a target conductive structure 60 with its top surface flush with the top surface of the second stack 20; and repeating the target process steps a predetermined number of times.

[0092] For example, please refer to Figure 13 The target process steps may include: the semiconductor structure fabrication method as described in any of the preceding embodiments; planarization and removal of the third sacrificial layer 24 to obtain a target conductive structure 60 with its top surface flush with the top surface of the third dielectric layer 23. The target process steps are repeated a preset number of times. The preset number of times the target process steps are repeated can be set according to the specific requirements of the conductive plugs for the height / thickness of the interconnect structure in a specific application scenario. The target conductive structure 60 includes a first unit 1U, a second unit 1V, and a third unit 2U stacked sequentially along the direction away from the substrate. Repeating the target process steps a preset number of times can yield multiple stacked target conductive structures 60. In different target process steps, the height and / or linewidth of the first unit 1U, the second unit 1V, and the third unit 2U can be set according to requirements to meet the actual process requirements of different application scenarios.

[0093] In some embodiments, a semiconductor structure prepared using the semiconductor structure preparation method described in any of the foregoing embodiments is provided.

[0094] Please continue to refer to this. Figure 13In some embodiments, a semiconductor structure includes a substrate 101, a dielectric stack 10, and a second stack 20; the top surface of the substrate 101 is covered by the dielectric stack 10, and the dielectric stack 10 includes at least one via 201 penetrating the dielectric stack 10; the via 201 includes a first conductive structure 16 whose top surface is lower than the top surface of the dielectric stack 10, the first conductive structure 16 including a first conductive layer and a first barrier layer 15 covering the outer sidewall and bottom surface of the first conductive layer; the dielectric stack 10 includes a recess that exposes the entire top surface of the first conductive structure 16. The key dimensions of the groove 30 are related to the key dimensions of the first conductive structure 16; the sidewalls of the groove 30 are covered with a second barrier layer 17; the second stack 20 is located on the top surface of the dielectric stack 10, and the second stack 20 includes a T-shaped groove 50 that is narrow at the bottom and wide at the top, which penetrates the second stack 20 and connects to the groove 30, and the bottom surface of the T-shaped groove 50 is located inside the groove 30; the T-shaped groove 50 and the groove 30 together constitute the target trench MT, the inner surface of the target trench MT is covered with a third barrier layer 61, and the target trench MT includes the target conductive structure 60.

[0095] Please continue to refer to this. Figures 1-13 The unexpected technical effects that the embodiments of this disclosure can produce include:

[0096] The first sacrificial layer 14 protects the dielectric stack 10, preventing damage during the etching process to form the via 201 and avoiding uncontrollable depth of the subsequent groove 30, which could affect the thickness / height d of the target conductive structure 60 within the groove 30. Then, based on the desired lateral etching depth, a portion of the dielectric stack 10 is etched and removed laterally to obtain the groove 30, exposing the entire top surface of the first conductive structure 16. The critical dimensions of the groove 30 are related to the critical dimensions of the first conductive structure 16, ensuring not only that the groove 30 exposes the entire top surface of the first conductive structure 16 but also preventing an increase in the probability of current leakage paths between adjacent interconnect structures due to excessively large critical dimensions of the groove 30. The lateral etching depth is related to the lateral etching rate and etching time, and the lateral etching depth can be precisely controlled by controlling the etching time. After removing the first sacrificial layer 14, a second barrier layer 17 is formed, at least covering the sidewalls of the groove 30. Then, a second sacrificial layer 18 is filled into the groove 30. The second sacrificial layer 18 defines the shape and size of the bridging portion. Subsequently, a second stack 20 covering the second sacrificial layer 18 is formed. The number of film layers and the material of each film layer in the second stack 20 can correspond to the same number of film layers and the material of each film layer in the first stack, reducing the complexity and cost of the fabrication process. The target trench MT includes a connected T-groove 50 and a groove 30. After forming a third barrier layer 61 covering the inner surface of the target trench MT, a target conductive structure 60 is formed within the target trench MT. The portion of the target conductive structure 60 located within the groove 30 constitutes a bridging portion. The critical dimension of the bridging portion is larger than and related to the critical dimension of the first conductive structure 16. This not only avoids interconnection open circuits or short circuits due to the critical dimension of the bottom of the target conductive structure 60 being too small, but also reduces the impedance of the target conductive structure 60. Since the outer wall and bottom surface of the first conductive layer are covered with the first barrier layer 15, and the outer wall of the target conductive structure 60 is covered with the second barrier layer 17 and the third barrier layer 61, the target conductive structure 60 is completely surrounded by barrier layers, preventing electrical failures caused by metal atom migration and improving the yield and reliability of the interconnection structure.

[0097] In some embodiments, an electronic device is provided, including the semiconductor structure of any embodiment of this disclosure.

[0098] The aforementioned electronic devices include, but are not limited to, suitable types of electronic products such as consumer electronics, home electronics, automotive electronics, and financial terminals. Consumer electronics include mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include smart locks, televisions, refrigerators, and wearable devices. Automotive electronics include car navigation systems and car DVD players. Financial terminals include ATMs and self-service terminals.

[0099] Please note that, for the sake of brevity, in the structural diagrams given in the embodiments, unless a separate cross-sectional structural diagram is given, structural diagrams from different perspectives related to the inventive points of the embodiments of this disclosure can be referred to each other.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided with a first stacked layer on its top surface, the first stacked layer comprising a dielectric stacked layer and a first sacrificial layer stacked sequentially in a direction away from the substrate; After forming at least one through hole through the first stack, a first conductive structure with its top surface lower than the top surface of the dielectric stack is formed in the through hole. The first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer. Laterally etch and remove part of the dielectric stack to obtain a groove that exposes the entire top surface of the first conductive structure, wherein the critical dimensions of the groove are related to the critical dimensions of the first conductive structure; After removing the first sacrificial layer, a second barrier layer is formed that at least covers the sidewalls of the groove; After the second sacrificial layer is filled into the groove, a second stack covering the second sacrificial layer is formed; A T-shaped groove is formed that runs through the second stack and is narrower at the bottom and wider at the top, with the bottom surface of the T-shaped groove located inside the top surface of the second sacrificial layer; After removing the second sacrificial layer, the target trench is obtained; After forming a third barrier layer covering the inner surface of the target trench, a target conductive structure is formed within the target trench.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, The second stack and the first stack have the same number of film layers; in the film layer ordering along the direction away from the substrate, the same film layer number in the first stack and the second stack corresponds to the same material of the film layer.

3. The semiconductor structure fabrication method according to claim 1, characterized in that, The first stack includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a first sacrificial layer stacked sequentially along a first direction away from the top surface of the substrate; The lateral etching and removal of a portion of the dielectric stack includes: Laterally etch and remove part of the second dielectric layer and part of the third dielectric layer to obtain a groove that exposes the entire top surface of the first conductive structure. The ratio of the critical dimension of the groove to the critical dimension of the first conductive structure is R, where R ∈ [1.05, 1.1].

4. The semiconductor structure fabrication method according to claim 1, characterized in that, The second barrier layer covers the sidewalls of the groove; the second sacrificial layer covers the entire top surface of the first conductive structure exposed by the groove, and the second sacrificial layer covers the exposed portion of the dielectric stack; or The second barrier layer covers the sidewalls of the groove, the second barrier layer covers the entire top surface of the first conductive structure exposed by the groove, and the second barrier layer covers the exposed portion of the dielectric stack.

5. The semiconductor structure fabrication method according to claim 1, characterized in that, Includes at least one of the following features: The first sacrificial layer includes a metal barrier layer; The second sacrificial layer comprises α-carbon and / or fluorinated amorphous carbon.

6. The semiconductor structure fabrication method according to claim 1, characterized in that, The second sacrificial layer includes the target carbon layer; Removing the second sacrificial layer includes: The target carbon layer is treated and removed using a target gas containing ozone.

7. The semiconductor structure fabrication method according to claim 3, characterized in that, The first dielectric layer comprises a nitrogen-doped carbide film; Forming at least one through-hole penetrating the first stack includes: The first stack is dry-etched to obtain an initial hole that penetrates the first sacrificial layer, the third dielectric layer, and the second dielectric layer. The via is obtained by etching the nitrogen-doped carbide film through the initial hole.

8. A method for fabricating a semiconductor structure, characterized in that, The target process steps include the following: The method for fabricating a semiconductor structure as described in any one of claims 1-7; and The second stack is planarized to obtain a target conductive structure whose top surface is flush with the top surface of the remaining second stack.

9. The semiconductor structure fabrication method according to claim 8, characterized in that, The target process steps are repeated a preset number of times.

10. A semiconductor structure, characterized in that, include: A substrate, the top surface of which is covered by a dielectric stack, the dielectric stack including at least one through-hole penetrating the dielectric stack; the through-hole including a first conductive structure whose top surface is lower than the top surface of the dielectric stack, the first conductive structure including a first conductive layer and a first barrier layer covering the outer sidewall and bottom surface of the first conductive layer; the dielectric stack including a groove exposing the entire top surface of the first conductive structure, the critical dimension of the groove being related to the critical dimension of the first conductive structure; the sidewall of the groove being covered by a second barrier layer. The second stack is located on the top surface of the dielectric stack. The second stack includes a T-shaped groove that is narrow at the bottom and wide at the top, which penetrates the second stack and communicates with the groove. The bottom surface of the T-shaped groove is located inside the groove. The T-shaped groove and the groove together form a target trench. The inner surface of the target trench is covered with a third barrier layer. The target trench includes a target conductive structure.

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