Programming enhanced baseboard management controller

Abstract

Techniques for integrating a programmable logic device (PLD) into a baseboard management controller (BMC) are described herein. The program-enhanced BMC is energized by a PLD that is integrated into the program-enhanced BMC and coupled to an internal bus of the program-enhanced BMC. The configuration file is provided to the PLD from immutable BMC hardware in the BMC based at least on the programming-enhanced BMC being energized. The configuration file specifies a configuration of programmable hardware to be programmatically applied to the PLD. Programmable hardware of the PLD is programmed by loading the configuration file, so that the programmable hardware originally presents a peripheral interface defined by the configuration file on an internal bus of the programming-enhanced BMC.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 597,680, filed November 9, 2023, entitled “Programming-Enhanced Baseboard Management Controller”, the entire contents of which are incorporated herein by reference. Background Technology

[0002] A baseboard management controller (BMC) is typically implemented as a discrete component on the motherboard of a computing device, such as a server, to perform system management operations related to the computing device. For example, the BMC can monitor parameters of components (also known as "monitored components") included within the computing device and provide alerts to users (e.g., system administrators) if these parameters exceed established boundaries. Examples of such parameters include temperature, cooling fan speed, power status, and operating system (OS) status.

[0003] Complex programmable logic devices (CPLDs) or field-programmable gate arrays (FPGAs) are typically implemented as another discrete component on the motherboard of a computing device to translate signals from protocols associated with the BMC to protocols associated with the motherboard and the monitored components. This signal translation in this way consumes significant time and resources.

[0004] Traditional discrete BMCs and CPLDs / FPGAs have relatively complex interdependencies. For example, CPLDs / FPGAs rely on BMCs for updates and recovery, and BMCs rely on CPLDs / FPGAs to power on the BMC and perform the aforementioned protocol conversions. BMCs and CPLDs / FPGAs traditionally exhibit incompatible recovery mechanisms, creating weaknesses in computing devices. Furthermore, implementing BMCs and CPLDs / FPGAs as separate discrete components results in relatively high packaging costs and a relatively large footprint on the motherboard. Summary of the Invention

[0005] It may be desirable to integrate programmable logic devices (PLDs) into a BMC. A PLD is an electronic component used to build reconfigurable circuits (e.g., reconfigurable digital circuits). For example, a PLD may have undefined functionality at manufacturing time, and the PLD can subsequently be programmed to have the desired functionality, enabling its use in a circuit. According to this example, programming a PLD can change the connections between its gates to achieve the desired function. Examples of PLDs include, but are not limited to, simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field-programmable gate arrays (FPGAs). Examples of SPLDs include, but are not limited to, programmable array logic (PALs), programmable logic arrays (PLAs), and general-purpose array logic (GALs). By integrating a PLD into a BMC, signal conversion from the BMC's protocol to the protocol of the motherboard on which the BMC is implemented, and to the protocol of the components monitored by the BMC, can be avoided. Integrating a PLD into a BMC allows the PLD to power the BMC even if the PLD's mirror image (e.g., a configuration file defining the PLD's configuration) is corrupted or absent.

[0006] Furthermore, this document describes various methods for integrating PLDs into BMCs. Integrating a PLD into a BMC enables the PLD to natively present a programmable peripheral interface on the BMC's internal bus. A programmable peripheral interface is a peripheral interface created through programming programmable hardware. On one hand, the PLD programs its programmable hardware to provide the programmable peripheral interface. A peripheral interface is an interface that enables interaction (e.g., communication) with peripheral devices. On the other hand, the peripheral interface generated by the PLD enables the BMC to communicate with peripheral devices. Peripheral devices are devices external to the BMC. Examples of peripheral devices include, but are not limited to, sensors, cooling fans, memory, power supply units (PSUs), processing systems, input / output (I / O) devices, root of trust, chassis managers, and rack managers. Examples of sensors include, but are not limited to, thermometers, accelerometers, speed sensors, displacement sensors, and pressure sensors. Examples of memory include, but are not limited to, flash memory and solid-state drives (SSDs). Examples of processing systems include, but are not limited to, central processing units (CPUs) and graphics processing units (GPUs). Examples of I / O devices include, but are not limited to, printed circuit boards (PCAs) and network interface controllers (NICs). A root of trust is an assumed, not derived, authoritative entity on which trust is established. A chassis manager is a system that manages the resources within a computer chassis. A computer chassis is a physical enclosure that stores the hardware components of a computer. A rack manager is a system that manages computer racks. A computer rack is a physical structure on which multiple computer chassis can be mounted simultaneously.

[0007] In the first example method, the programmable enhanced baseboard management controller (BMC) includes immutable BMC hardware, an internal bus, and a programmable logic device (PLD). The immutable BMC hardware is configured to perform system management operations regarding peripheral devices outside the programmable enhanced BMC. The PLD is coupled to the internal bus. The PLD is configured to power on the programmable enhanced BMC. The immutable BMC hardware is configured to provide a configuration file to the PLD, at least based on the programmable enhanced BMC being powered on. The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD. The PLD is also configured to program the programmable hardware of the PLD by loading the configuration file, which causes the programmable hardware to natively present the peripheral interface defined by the configuration file on the internal bus of the programmable enhanced BMC.

[0008] In the second example method, the programmable enhanced BMC is powered by a PLD integrated into and coupled to the internal bus of the programmable enhanced BMC. At least based on the powered programmable enhanced BMC, a configuration file is provided to the PLD from the immutable BMC hardware within the BMC. The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which allows the programmable hardware to natively present the peripheral interface defined by the configuration file on the internal bus of the programmable enhanced BMC.

[0009] In the third example method, the computing system includes memory, a processing system coupled to the memory, and a programmable enhanced BMC. The programmable enhanced BMC includes an internal bus, an immutable peripheral interface coupled to the internal bus, immutable BMC hardware, and a PLD coupled to the internal bus. The immutable BMC hardware is configured to perform system management operations regarding peripheral devices, including memory or the processing system, by providing packets to peripheral devices via the immutable peripheral interface. The PLD is configured to power on the programmable enhanced BMC. The PLD includes programmable hardware. The immutable BMC hardware is also configured to provide a configuration file to the PLD, at least based on the programmable enhanced BMC being powered on. The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD. The PLD is also configured to natively provide a programmable peripheral interface on the internal bus of the programmable enhanced BMC by programming the programmable hardware of the PLD using the configuration file.

[0010] This invention is provided to introduce, in a simplified form, some concepts that will be further described in the following detailed description. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, it should be noted that this invention is not limited to the specific embodiments described in the detailed description and / or other sections of this document. These embodiments presented herein are for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein. Attached Figure Description

[0011] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the invention and, together with the specification, further serve to explain the principles involved and enable those skilled in the art(s) to make and use the disclosed techniques.

[0012] Figure 1 This is a block diagram of an example computing system according to an embodiment.

[0013] Figure 2 A flowchart is depicted illustrating an example method for natively presenting a programmed peripheral interface on the internal bus of a programmable enhanced baseboard management controller (BMC) according to an embodiment.

[0014] Figure 3 This is a block diagram of an example programming enhancement of the BMC according to an embodiment.

[0015] Figure 4 This is a system diagram of an example mobile device according to an embodiment.

[0016] Figure 5 An example computer in which embodiments can be implemented is depicted.

[0017] The features and advantages of the disclosed technology will become more apparent when the following detailed description of the embodiments is taken in conjunction with the accompanying drawings, in which the same reference numerals consistently identify corresponding elements. In the drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost (or more) numerals of the corresponding reference numerals. Detailed Implementation I. Example Implementation

[0018] It may be desirable to integrate programmable logic devices (PLDs) into a BMC. A PLD is an electronic component used to build reconfigurable circuits (e.g., reconfigurable digital circuits). For example, a PLD may have undefined functionality at manufacturing time, and the PLD can subsequently be programmed to have the desired functionality, enabling its use in a circuit. According to this example, programming a PLD can change the connections between its gates to achieve the desired function. Examples of PLDs include, but are not limited to, simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field-programmable gate arrays (FPGAs). Examples of SPLDs include, but are not limited to, programmable array logic (PALs), programmable logic arrays (PLAs), and general-purpose array logic (GALs). By integrating a PLD into a BMC, signal conversion from the BMC's protocol to the protocol of the motherboard on which the BMC is implemented, and to the protocol of the components monitored by the BMC, can be avoided. Integrating a PLD into a BMC allows the PLD to power the BMC even if the PLD's mirror image (e.g., a configuration file defining the PLD's configuration) is corrupted or absent.

[0019] The example embodiments described herein enable the integration of a PLD into a BMC. Integrating a PLD into a BMC allows the PLD to natively present a programmable peripheral interface on the BMC's internal bus. The programmable peripheral interface is created through programming programmable hardware. On one hand, the PLD programs its programmable hardware to provide the programmable peripheral interface. A peripheral interface is an interface that enables interaction (e.g., communication) with peripheral devices. On the other hand, the peripheral interface generated by the PLD enables the BMC to communicate with peripheral devices. Peripheral devices are devices external to the BMC. Examples of peripheral devices include, but are not limited to, sensors, cooling fans, memory, power supply units (PSUs), processing systems, input / output (I / O) devices, roots of trust, chassis managers, and rack managers. Examples of sensors include, but are not limited to, thermometers, accelerometers, velocity sensors, displacement sensors, and pressure sensors. Examples of memory include, but are not limited to, flash memory and solid-state drives (SSDs). Examples of processing systems include, but are not limited to, central processing units (CPUs) and graphics processing units (GPUs). Examples of I / O devices include, but are not limited to, printed circuit boards (PCAs) and network interface controllers (NICs). A root of trust is an authoritative entity to which trust is assumed rather than derived. A chassis manager is a system that manages the resources within a computer chassis. A computer chassis is the physical enclosure that stores the hardware components of a computer. A rack manager is a system that manages computer racks. A computer rack is the physical structure on which multiple computer chassis can be mounted simultaneously.

[0020] The example techniques described herein offer various benefits compared to traditional system management techniques that utilize separate, discrete BMCs and CPLDs / FPGAs on the motherboard. For example, the example techniques eliminate the need to translate signals from the BMC's protocol into protocols monitored by the BMC for the motherboard and components. For example, by utilizing common recovery mechanisms for the BMC and PLDs integrated into the BMC, the example techniques improve the security of computing devices including the BMC. The example techniques can reduce the cost of computing devices by incorporating PLDs into the BMC. For example, incorporating PLDs into the BMC can reduce packaging costs associated with computing devices, such as by eliminating packaging costs associated with separately packaging PLDs from the BMC. The example techniques can reduce the amount of on-board space consumed by the BMC and PLDs on the motherboard by integrating PLDs into the BMC. Integrating PLDs into the BMC eliminates the need for external flash chips and / or PLDs to the BMC (e.g., for protocol conversion purposes). Reducing the amount of on-board space consumed on the motherboard allows for a reduction in motherboard size, which in turn reduces associated costs. For example, integrating the PLD into the BMC can reduce motherboard-related costs by more than 50%.

[0021] The example techniques reduce the amount of time and / or resources (e.g., processor cycles, memory) consumed in performing system management operations related to computing devices. For example, by integrating the PLD into the BMC on the computing device motherboard, the time and resources consumed in performing protocol conversions are avoided. According to this example, by integrating the PLD into the BMC, it is not necessary to convert the BMC's signals from the BMC's protocol to the protocol of the motherboard and components monitored by the BMC in order to perform system management operations. By integrating the PLD into the BMC, the time and resources consumed in recovering the PLD or BMC can be reduced. For example, integrating the PLD into the BMC can avoid recovery failures that would occur if the PLD and BMC were implemented as separate discrete components. Furthermore, the example techniques make it possible to avoid the costs associated with protocol conversions and / or failure recovery. Therefore, the costs associated with performing system management operations and / or recovery according to any of the example techniques described herein can be less than the costs associated with conventional system management and recovery techniques.

[0022] By reducing the time and / or resources consumed in performing system administration and / or recovery operations, the efficiency of the computing system performing these operations is increased. By incorporating the PLD into the BMC, the example technology improves (e.g., enhances) the user experience and efficiency of computing systems that include the BMC. For example, incorporating the PLD into the BMC allows the PLD to natively present a programmable peripheral interface on the BMC's internal bus, which can reduce the amount of time and effort users spend on system administration and recovery operations.

[0023] Figure 1 This is a block diagram of an example computing system 100 according to an embodiment. A computing system is a system that includes a processing system comprising at least one processor capable of manipulating data according to a set of instructions. For example, the computing system may be a server computer, desktop computer, laptop computer, tablet computer, wearable computer such as a smartwatch or head-mounted computer, personal digital assistant, cellular phone, Internet of Things (IoT) device, etc. Figure 1 As shown, the computing system 100 includes a motherboard 102, a programmable enhanced baseboard management controller (BMC) 104, and peripheral devices 106. On one hand, the programmable enhanced BMC 104 is embedded in the motherboard 102. The motherboard 102 includes a processing system capable of communicating with the programmable enhanced BMC 104 and peripheral devices 106. The motherboard (e.g., motherboard 102) is a printed circuit board (PCB) with expansion capabilities, meaning that the motherboard includes expansion interfaces (e.g., slots) where another circuit board can be provided (e.g., inserted). The PCB is a circuit that provides electrical connections between electronic components (e.g., peripheral devices 106) attached to the PCB. Peripheral devices 106 are attached to the motherboard 102. Peripheral devices 106 include any one or more suitable types of devices. For example, peripheral devices 106 may include sensors, cooling fans, memory, power supply units (PSUs), processing systems, and / or input / output (I / O) devices.

[0024] The programmable enhanced BMC 104 includes immutable BMC hardware 108, programmable logic device (PLD) 110, immutable peripheral interface 112, and internal bus 114. The programmable enhanced BMC is a BMC that includes a PLD coupled to the internal bus of the BMC. The immutable BMC hardware 108 is configured to perform system management operations with respect to peripheral device 106. On one hand, the immutable BMC hardware 108 performs system management operations out of band, meaning that the immutable BMC hardware 108 is configured to perform system management operations regardless of whether the computing system 100 is powered on, whether an operating system (OS) is installed on the computing system 100, and whether the OS installed on the computing system 100 is functioning. For example, the immutable BMC hardware 108 can perform system management operations out of band by communicating with peripheral device 106 via (e.g., directly via) the peripheral interfaces in the programmable enhanced BMC 104 (e.g., the programmable peripheral interface 116 and the immutable peripheral interface 112) (e.g., not via motherboard 102). The programmable peripheral interface 116 is discussed in more detail below. On the other hand, the immutable BMC hardware 108 performs system management operations by providing packets to the peripheral device 106 through the programmable peripheral interface 116 and the immutable peripheral interface 112. In the example implementation, the peripheral device 106 includes one or more components (e.g., memory and / or processing systems) incorporated into the motherboard 102. Therefore, the peripheral device 106 does not necessarily need to be outside the motherboard 102, although it is outside the programmable enhanced BMC 104. The immutable BMC hardware 108 is also configured to provide a configuration file to the PLD 110 when powered on, at least based on the programmable enhanced BMC 104. The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD 110.

[0025] PLD 110 is coupled to internal bus 114 and includes programmable hardware. On one hand, PLD 110 (e.g., the programmable hardware therein) operates in a hardware-defined language (HDL) and implements various functions at the circuit level. According to this aspect, PLD 110 performs operations related to any of a variety of tasks, such as sequentially powering on computing system 100 (e.g., initializing the power rails of computing system 100), and / or managing programming-stabilized delays in computing system 100. PLD 110 is configured to power on a programmable-enhanced BMC 104. PLD 110 is also configured to natively provide a programmable peripheral interface 116 on internal bus 114 by programming its programmable hardware using a configuration file received from immutable BMC hardware 108. Therefore, PLD 110 can natively present its programmable hardware as a programmable peripheral interface 116 on internal bus 114. By natively presenting the programmed peripheral interface 116 on the internal bus 114, the programmable hardware enables the programmed peripheral interface 116 to be presented in a manner that allows the immutable BMC hardware 108 to detect (e.g., recognize) the programmed peripheral interface 116 on the internal bus 114, similar to how the immutable BMC hardware 108 detects the immutable peripheral interface 112 on the internal bus 114. On the one hand, the programmed rather than immutable programmed peripheral interface 116 is irrelevant (e.g., irrelevant) to how the immutable BMC hardware 108 interacts with the programmed peripheral interface 116.

[0026] The immutable peripheral interface 112 enables the immutable BMC hardware 108 to perform system management operations on the peripheral device 106 or other devices coupled to the peripheral device 106 by forwarding packets from the immutable BMC hardware 108 to the peripheral device 106.

[0027] Internal bus 114 is configured to transmit information (e.g., packets) to immutable BMC hardware 108, PLD 110 (including programmed peripheral interface 116), and immutable peripheral interface 112, and / or transmit information (e.g., packets) from immutable BMC hardware 108, PLD 110 (including programmed peripheral interface 116), and immutable peripheral interface 112. In one aspect, internal bus 114 is configured to operate according to the Advanced Extensible Interface (AXI) protocol developed by Arm Holding plc.

[0028] On one hand, the programmable enhanced BMC 104 is implemented as a system-on-a-chip (SoC). According to this aspect, the SoC includes an integrated circuit chip, which includes a processor (e.g., a microcontroller, microprocessor, or digital signal processor (DSP)), memory, one or more communication interfaces, and / or other circuitry, and / or one or more embedded firmware to perform its functions.

[0029] On the other hand, the motherboard 102, one or more peripheral devices in the peripheral devices 106, the immutable BMC hardware 108, the programmable logic device 110, the immutable peripheral interface 112, the internal bus 114, and / or the programmable peripheral interface 116 are implemented in hardware logic / circuit. This hardware logic / circuit may include one or more hardware logic components. Examples of hardware logic components include application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and system-on-a-chip (SoCs).

[0030] Figure 2 A flowchart 200 depicts an example method for natively presenting a programmable peripheral interface on the internal bus of a programmable enhanced baseboard management controller (BMC) according to an embodiment. Flowchart 200 can be derived from, for example... Figure 1 The BMC 104, with its enhanced programming capabilities, is used for execution as shown. For illustrative purposes, refer to [reference needed]. Figure 3 The flowchart 200 is described using the programming-enhanced BMC 300 shown. Figure 3 This is a sample implementation of the programmable BMC 104. For example... Figure 3 As shown, the programmable enhanced BMC 300 includes immutable BMC hardware 308, a programmable logic device (PLD) 310, (multiple) immutable peripheral interfaces 312, an internal bus 314, and a storage device 318. Therefore, the PLD 310 is integrated into the programmable enhanced BMC 300. On one hand, the storage device 318 is random access memory (RAM). The immutable BMC hardware 308, PLD 310, (multiple) immutable peripheral interfaces 312, and storage device 318 coupled to the internal bus 314. The PLD 310 includes programmable hardware 320. The programmable hardware 320 includes programmable peripheral interfaces 316. For non-limiting and illustrative purposes, the storage device 318 is shown as storing an initial configuration file 322. Based on the discussion of flowchart 200, further structural and operational embodiments will be apparent to those skilled in the art.

[0031] like Figure 2As shown, the method in flowchart 200 begins at step 202. In step 202, a programmable logic device (PLD) is used to power a programmable baseboard management controller (BMC), which is integrated into the programmable BMC and coupled to the internal bus of the programmable BMC. On one hand, powering the programmable BMC includes removing the programmable BMC from a reset state. According to this aspect, the reset state is a predetermined state that occurs after the power switch of computing device 100 switches from an "off" state to an "on" state and before the power supply of the programmable BMC has asserted "power good" to indicate that the power supply is ready to provide a stable voltage at a power level greater than or equal to a specified (e.g., predetermined) power supply threshold. In the example implementation, PLD 310 powers the programmable BMC 300. For example, PLD 310 can power the programmable BMC 300 by providing a power signal 324 (e.g., an electrical signal) to immutable BMC hardware 308. According to this example, power signal 324 includes the energy to activate immutable BMC hardware 308. In one aspect, power signal 324 enables immutable BMC hardware 308 to operate.

[0032] In an example embodiment, energizing the programmable BMC at step 202 includes a power-on sequence executed by the PLD, wherein the PLD still energizes the programmable BMC even though the initial profile defining the initial configuration to be applied to the PLD during the power-on sequence is corrupted. In an example implementation, PLD 310 executes the power-on sequence, wherein PLD 310 still energizes the programmable BMC 300 even though the initial profile 322 defining the initial configuration to be applied to PLD 310 during the power-on sequence is corrupted.

[0033] In another example embodiment, powering on the programmable BMC at step 202 includes a power-on sequence executed by the PLD, wherein the PLD powers on the programmable BMC even though an initial profile defining the initial configuration to be applied to the PLD during the power-on sequence is inaccessible. In an example implementation, PLD 310 executes a power-on sequence, wherein PLD 310 powers on the programmable BMC 300 even though an initial profile 322 defining the initial configuration to be applied to PLD 310 during the power-on sequence is inaccessible. On one hand, the initial profile 322 does not exist. According to this aspect, storage device 318 does not store the initial profile 322. Further according to this aspect, PLD 310 executes the power-on sequence even though the initial profile 322 does not exist.

[0034] At step 204, a configuration file is provided to the PLD from the immutable BMC hardware within the programmable BMC, at least based on powering on the programmable BMC. The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD. The configuration file can be a mirror of the PLD and / or an update of the PLD. A mirror of the PLD includes software executable by the PLD to programmable hardware of the PLD. An update of the PLD specifies changes to the current configuration of the programmable hardware of the PLD to produce an updated configuration of the programmable hardware. On the one hand, providing the configuration file from the immutable BMC hardware to the PLD at step 204 reduces the amount of time and / or resources (e.g., processor cycles and / or memory) consumed in performing system management operations on a computing device including the programmable BMC. By reducing the amount of time and / or resources consumed, the efficiency of the computing device can be improved. In the example implementation, the immutable BMC hardware 308 is powered on at least based on the programmable BMC 300 to provide configuration file 326 to the PLD 310. According to this implementation, configuration file 326 specifies the configuration of programmable hardware 320 to be programmably applied to PLD 310.

[0035] At step 206, the programmable hardware of the PLD is programmed by loading a configuration file, which causes the programmable hardware to natively present (e.g., instantiate) the peripheral interfaces defined by the configuration file on the internal bus of the programmable enhanced BMC. Therefore, on the one hand, loading the configuration file causes the programmable hardware to natively present the peripheral interfaces on the internal bus of the programmable enhanced BMC. On the other hand, enabling the programmable hardware to natively present the peripheral interfaces defined by the configuration file on the internal bus of the programmable enhanced BMC reduces the cost of the motherboard coupled to the programmable enhanced BMC (and thus the computing device including the programmable enhanced BMC), for example, by eliminating the need to translate signals from the protocol of the programmable enhanced BMC into protocols for the motherboard and(s) of the peripheral devices monitored by the programmable enhanced BMC. On the other hand, enabling the programmable hardware to natively present the peripheral interfaces on the internal bus of the programmable enhanced BMC reduces the amount of time and / or resources (e.g., processor cycles and / or memory) consumed in performing system management operations concerning the computing device including the programmable enhanced BMC. By reducing the amount of time and / or resources consumed, the efficiency of the computing device can be improved.

[0036] In the example implementation, PLD 310 programs the programmable hardware 320 therein by loading configuration file 326. By loading configuration file 326, PLD 310 enables the programmable hardware 320 to natively present the programmed peripheral interface 316 defined by configuration file 326 on internal bus 314. For example, by enabling the programmed peripheral interface 316 to be natively presented on internal bus 314, PLD 310 can enable immutable BMC hardware 308 to handle the programmed peripheral interface 316 in the same way that immutable BMC hardware 308 handles immutable peripheral interfaces(s)312. According to this example, immutable BMC hardware 308 may not be able to determine (e.g., distinguish) whether the programmed peripheral interface 316 is programmed or immutable. In one aspect of the implementation herein, the programmed peripheral interface 316 is the interface between immutable BMC hardware 308 and peripheral devices associated with a specific protocol. Therefore, the programmed peripheral interface 316 can be dedicated to a specific protocol. Examples of protocols that can be associated with peripheral devices include, but are not limited to, the Universal Serial Bus (USB) protocol developed by Compaq Computer Corporation, Digital Equipment Corporation (DEC), International Business Machines Corporation (IBM), Intel Corporation, Microsoft Corporation, NEC Corporation, and Nortel Networks Corporation; the Inter-Integrated Circuit (I2C) protocol developed by Philips Semiconductor (now NXP Semiconductors); the I3C protocol developed by the MIPI Alliance; the PCMCIA protocol (also known as the PC Card Protocol) developed by the Personal Computer Memory Card International Association (PCMCIA); the Serial Peripheral Interface (SPI) protocol developed by Motorola Corporation; the Ethernet protocol developed by Xerox PARC (now Palo Alto Research Center (PARC)); and the High Speed ​​Peripheral Component Interconnect (PCIe) protocol developed by Intel Corporation, Dell Corporation, HP Corporation, and IBM.

[0037] In an example embodiment, loading the configuration file at step 206 includes creating register definitions that define the peripheral interface. In the example implementation, PLD 310 loads configuration file 322 by creating register definitions that define the programmed peripheral interface 316. According to this embodiment, programming the programmable hardware of the PLD at step 206 causes the register definitions to be natively presented on the internal bus of the programmable enhanced BMC to provide the peripheral interface. In the example implementation, PLD 310 programs the programmable hardware 320 to cause the register definitions to be natively presented on the internal bus 314 to provide the programmed peripheral interface 316. On one hand, PLD 310 programs the programmable hardware 320 to have the configuration specified by configuration file 322 by loading configuration file 322. According to this aspect, by programming the programmable hardware 320 in this way, PLD 310 generates register definitions based on the definitions included in configuration file 322. Further according to this aspect, presenting the programmed peripheral interface 316 on the internal bus 314 includes presenting register definitions on the internal bus 314.

[0038] In another example embodiment, programmable hardware programming of the PLD at step 206 causes the operating system (OS) executing on the programmable enhanced BMC to natively detect the peripheral interface. The OS is, in one aspect, a Linux embedded OS. In the example implementation, by programming the programmable hardware 320, the PLD 310 causes the operating system (OS) 328 executing on the programmable enhanced BMC 308 to natively detect the programmed peripheral interface 316.

[0039] In some example embodiments, one or more steps 202, 204, and / or 206 of flowchart 200 are not performed. Furthermore, steps other than or replacing steps 202, 204, and / or 206 may be performed. For example, in an example embodiment, the method of flowchart 200 further includes providing a packet formatted according to a protocol associated with the peripheral interface from immutable BMC hardware to a peripheral device via a peripheral interface. In an example implementation, immutable BMC hardware 308 provides a first packet 330 formatted according to a protocol associated with the programmed peripheral interface 316 to a peripheral device via a programmed peripheral interface 316. In one aspect of this implementation, immutable BMC hardware 308 natively uses a driver associated with the protocol to generate the first packet 330. By natively using the driver associated with the protocol, it means that the immutable BMC hardware 308 uses the driver(s) to generate the first packet 330, similar to how the immutable BMC hardware 308 uses the driver(s) associated with the protocol(s) to generate the second packet 332, where the protocol(s) are associated with the immutable peripheral interface(s) 312. On the one hand, the protocol associated with the programmed rather than immutable peripheral interface is irrelevant to the immutable BMC hardware 108 regarding how it interacts with (e.g., uses) the driver.

[0040] In one aspect of the embodiments herein, packets formatted according to a protocol associated with a peripheral interface are provided from immutable BMC hardware to a peripheral device via the peripheral interface without being converted (e.g., level-shifted or translated) to another protocol during transmission to the peripheral device. In an example implementation, immutable BMC hardware 308 provides a first packet 330 to a peripheral device via a programmed peripheral interface 316, wherein the first packet 330 is not converted to another protocol during transmission to the peripheral device, the other protocol being different from the protocol associated with the programmed peripheral interface 316.

[0041] It will be recognized that the programmable BMC 300 need not include the immutable peripheral interface(s) 312 and / or storage device(s) 318. Furthermore, the programmable BMC 300 may include components other than or replacing the immutable BMC hardware 308, PLD 310, the immutable peripheral interface(s) 312, internal bus 314, and / or storage device(s) 318.

[0042] Figure 4This is a system diagram of an example mobile device 400 including various optional hardware and software components, generally shown as 402. Any component 402 in the mobile device can communicate with any other component, although not all connections are shown for ease of illustration. The mobile device 400 can be any of a variety of computing devices (e.g., cellular phones, smartphones, handheld computers, personal digital assistants (PDAs), etc.) and can allow for two-way wireless communication with one or more mobile communication networks 404 (such as cellular or satellite networks) or with a local area network or wide area network.

[0043] Mobile device 400 includes a processor 410 (e.g., a signal processor, microprocessor, ASIC, or other control and processing logic circuitry) for performing tasks such as signal encoding, data processing, input / output processing, power control, and / or other functions. Operating system 412 can control the allocation and use of component 402 and supports one or more applications 414 (also known as "applications"). Applications 414 may include general mobile computing applications (e.g., email applications, calendars, contact managers, web browsers, messaging applications) and any other computing applications (e.g., word processing applications, mapping applications, media player applications).

[0044] The mobile device 400 includes a programmable enhanced baseboard management controller (BMC) 492, which can be configured similarly to the one referenced above. Figure 1 The described programming enhancements to BMC 104 and / or the above references Figure 3 The described method of programming enhancement for operating the BMC 300.

[0045] Mobile device 400 includes memory 420. Memory 420 may include non-removable memory 422 and / or removable memory 424. Non-removable memory 422 may include random access memory (RAM), read-only memory (ROM), flash memory, hard disk, or other known memory storage technologies. Removable memory 424 may include flash memory or a Subscriber Identity Module (SIM) card (which is well known in the Global System for Mobile Communications (GSM)) or other well-known memory storage technologies (such as "smart cards"). Memory 420 may store data and / or code for running operating system 412 and applications 414. Example data may include web pages, text, images, sound files, video data, or other datasets to be sent to or received from one or more network servers or other devices via one or more wired or wireless networks. Memory 420 may store user identifiers (such as International Mobile Subscriber Identity (IMSI)) and device identifiers (such as International Mobile Equipment Identity (IMEI)). Such identifiers may be sent to network servers to identify users and devices.

[0046] Mobile device 400 may support one or more input devices 430, such as touchscreen 432, microphone 434, camera 436, physical keyboard 438, and / or trackball 440, and one or more output devices 450, such as speaker 452 and display 454. Touchscreens such as touchscreen 432 can detect input in different ways. For example, a capacitive touchscreen detects touch input when an object (e.g., a fingertip) twists or interrupts the current flowing through its surface. As another example, a touchscreen can use an optical sensor to detect touch input when a beam of light from an optical sensor is interrupted. Physical contact with the screen surface is not necessary for some inputs to be detected by a touchscreen. For example, touchscreen 432 may support finger hover detection using capacitive sensing, as is well known. Other detection techniques may be used, including camera-based detection and ultrasound-based detection. To achieve finger hovering, the user's finger is typically positioned within a predetermined interval above the touchscreen, such as between 0.1 and 0.25 inches, or between 0.25 and 0.5 inches, or between 0.5 and 0.75 inches, or between 0.75 and 1 inch, or between 1 and 1.5 inches, etc.

[0047] Other possible output devices (not shown) may include piezoelectric or other tactile output devices. Some devices may provide more than one input / output function. For example, touchscreen 432 and display 454 may be combined in a single input / output device. Input device 430 may include a natural user interface (NUI). NUI is any interface technology that enables users to interact with a device in a “natural” way, free from the artificial constraints imposed by input devices such as mice, keyboards, and remote controls. Examples of NUI methods include methods that rely on speech recognition, touch, and stylus recognition, gesture recognition both on and near the screen, air gestures, head and eye tracking, speech and talking, vision, touch, gestures, and machine intelligence. Other examples of NUI include motion pose detection using accelerometers / gyroscopes, facial recognition, 3D displays, head, eye and gaze tracking, immersive augmented reality, and virtual reality systems, all of which provide a more natural interface, as well as technologies for sensing brain activity using electric field sensing electrodes (EEG and related methods). Therefore, in a specific example, the operating system 412 or application 414 may include speech recognition software as part of a voice control interface that allows users to operate the mobile device 400 via voice commands. Furthermore, the mobile device 400 may include input devices and software that allow user interaction via spatial gestures, such as detecting and interpreting gestures to provide input to gaming applications.

[0048] Multiple wireless modems 470 may be coupled to multiple antennas (not shown) and may support bidirectional communication between processor 410 and external devices, as is well known in the art. Multiple modems 470 are generally shown and may include a cellular modem 476 for communicating with mobile communication network 404 and / or other radio-based modems (e.g., Bluetooth® 474 and / or Wi-Fi 472). At least one of the multiple wireless modems 470 is typically configured to communicate with one or more cellular networks, such as a GSM network for data and voice communication within a single cellular network, between cellular networks, or between a mobile device and the Public Switched Telephone Network (PSTN).

[0049] The mobile device 400 may also include at least one input / output port 480, a power supply 482, a satellite navigation system receiver 484 (e.g., a Global Positioning System (GPS) receiver), an accelerometer 486, and / or a physical connector 490, which may be a Universal Serial Bus (USB) port, an IEEE 1394 (FireWire) port, and / or an RS-232 port. The components 402 described are not essential or do not include all components; as those skilled in the art will recognize, any component can be removed and other components can be added.

[0050] Although some operations of the disclosed methods have been described in a specific order for ease of presentation, it should be understood that this descriptive approach includes rearrangement unless the specific language used herein requires a particular order. For example, operations described sequentially may be rearranged or performed concurrently in certain situations. Furthermore, for simplicity, the accompanying figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods. II. Further discussion of some example embodiments

[0051] (A1) Example Programming Enhanced Baseboard Management Controller (BMC) Figure 1 104; Figure 3 300; Figure 4 ,492) includes: immutable BMC hardware ( Figure 1 108; Figure 3 ,308), internal bus ( Figure 1 ,114; Figure 3 ,314), and programmable logic devices (PLDs) Figure 1 110; Figure 3 (310). Immutable BMC hardware is configured to perform peripheral device operations outside the BMC with regard to programming enhancements ( Figure 1 The system management operation is 106). The PLD is coupled to the internal bus. The PLD is configured to power on the programmable enhanced BMC (106). Figure 2 (202). The immutable BMC hardware is configured to at least provide power to the PLD based on a programmable enhanced BMC. Figure 2 ,204) configuration file ( Figure 3 ,326). The configuration file specifies the programmable hardware to be programmatically applied to the PLD ( Figure 3 The PLD is configured as 320. The PLD is also configured to have its programmable hardware programmed by loading a configuration file. Figure 2 ,206), which allows programmable hardware to present a peripheral interface ( Figure 1 ,116; Figure 3 ,316), which is natively defined by the internal bus-based configuration file of the programmably enhanced BMC.

[0052] (A2) In the example programmable BMC of A1, the PLD is configured to power on the programmable BMC even though the initial profile is corrupted, which defines the initial configuration to be applied to the PLD before the programmable BMC is powered on.

[0053] (A3) In any of the example programming-enhanced BMCs in A1 to A2, the PLD is configured to power on the programming-enhanced BMC even though the PLD cannot access the initial configuration file, which defines the initial configuration to be applied to the PLD before the programming-enhanced BMC is powered on.

[0054] (A4) In any of the example programming enhancements of A1 to A3, the immutable BMC hardware is configured to provide packets via a peripheral interface, the packets being formatted according to a protocol associated with the peripheral interface.

[0055] (A5) In any of the example programming enhancements of A1 to A4, the immutable BMC hardware is configured to provide packets formatted according to the protocol without the packets being converted to another protocol.

[0056] (A6) In any of the example programmable enhanced BMCs in A1 to A5, the PLD is configured to load a configuration file by creating a register definition that defines the peripheral interface; and the programmable hardware is configured to natively present the register definition on the internal bus of the programmable enhanced BMC to provide the peripheral interface.

[0057] (A7) In any of the example programming-enhanced BMCs in A1 to A6, the PLD enables the operating system (OS) running on the programming-enhanced BMC to natively detect peripheral interfaces by loading a configuration file.

[0058] (B1) Example methods include using a programmable logic device (PLD) Figure 1 110; Figure 3 ,310) for programmable enhanced board management controller (BMC) ( Figure 1 104; Figure 3 300; Figure 4 ,492) Power on, Programmable Logic Device (PLD) ( Figure 1 110; Figure 3 (310) is integrated into the programmable enhanced BMC and coupled to the internal bus of the programmable enhanced BMC ( Figure 1 ,114; Figure 3 The method also includes at least a programmably enhanced BMC being powered on, from the immutable BMC hardware in the BMC ( , 314). Figure 1 108; Figure 3 ,308) provides ( to PLD) Figure 2 ,204) configuration file ( Figure 3 ,326). The configuration file specifies the programmable hardware to be programmatically applied to the PLD ( Figure 3 The method also includes configuring the PLD's programmable hardware by loading a configuration file (320). Figure 2 ,206), which allows programmable hardware to natively present peripheral interfaces ( Figure 1 ,116; Figure 3 ,316), which is defined by a configuration file on the internal bus of the programmably enhanced BMC.

[0059] (B2) In the example method of B1, energizing the programmable enhanced BMC includes: the PLD performing a power-on sequence, wherein the PLD still energizes the programmable enhanced BMC despite the initial profile being corrupted, the initial profile defining the initial configuration to be applied to the PLD during the power-on sequence.

[0060] (B3) In any of the example methods in B1 to B2, energizing the programmable enhanced BMC includes: the PLD performing a power-on sequence, wherein the PLD is still energized in the programmable enhanced BMC, the initial configuration file defining the initial configuration to be applied to the PLD during the power-on sequence, even though the initial configuration file is not accessible.

[0061] (B4) In any of the example methods of B1 to B3, the method further includes: providing packets formatted according to the protocol associated with the peripheral interface from the immutable BMC hardware to the peripheral device via the peripheral interface.

[0062] (B5) In any of the example methods of B1 to B4, providing packets includes: providing packets formatted according to the protocol associated with the peripheral interface from immutable BMC hardware to the peripheral device via the peripheral interface, provided that the packets are not converted to another protocol during transmission to the peripheral device.

[0063] (B6) In any of the example methods in B1 to B5, loading the configuration file includes: loading the configuration file by creating a register definition that defines the peripheral interface; and wherein programmable hardware programming of the PLD causes the register definition to be natively presented on the internal bus of the programmable enhanced BMC to provide the peripheral interface.

[0064] (B7) In any of the example methods of B1 to B6, the programmable hardware programming of the PLD enables the operating system (OS) executing on the programmable enhanced BMC to natively detect the peripheral interface.

[0065] (C1) Example computing system ( Figure 1 100; Figure 4 402; Figure 5 ,500) includes memory ( Figure 4 420, 422, 424; Figure 5 ,504), processing systems coupled to memory ( Figure 4 410; Figure 5,502), and a programmable enhanced baseboard management controller (BMC) ( Figure 1 104; Figure 3 300; Figure 4 ,492). Programmable enhanced BMC includes: internal bus ( Figure 1 ,114; Figure 3 ,314), and immutable peripheral interfaces coupled to the internal bus ( Figure 1 ,112; Figure 3 ,312), immutable BMC hardware ( Figure 1 108; Figure 3 ,308), and programmable logic devices (PLDs) Figure 1 110; Figure 3 ,310). The immutable BMC hardware is configured to provide packets to peripheral devices via an immutable peripheral interface ( Figure 3 ,332) to perform actions concerning peripheral devices including memory or processing systems ( Figure 1 The system management operations of the PLD (106) are performed. The PLD is coupled to the internal bus. The PLD is configured to power on the programmable enhanced BMC. The PLD includes programmable hardware ( Figure 3 ,320). The immutable BMC hardware is also configured to at least provide a configuration file to the PLD based on a programmable enhanced BMC being powered on ( Figure 3 , 326). The configuration file specifies the configuration of the programmable hardware to be programmably applied to the PLD. The PLD is also configured to natively provide a programmable peripheral interface on the internal bus of the programmable enhancement BMC by programming the programmable hardware of the PLD using the configuration file. Figure 1 ,116; Figure 3 ,316).

[0066] (C2) In the example computing system of C1, the PLD is configured to execute a power-on sequence in which the PLD is powered on by a programmable enhancement BMC, which defines the initial configuration to be applied to the PLD during the power-on sequence, even though the initial profile is corrupted.

[0067] (C3) In any of the example computing systems in C1 to C2, the PLD is configured to execute a power-on sequence in which the PLD powers on a programmable enhanced BMC, which defines the initial configuration to be applied to the PLD during the power-on sequence, even though the initial configuration file is not accessible.

[0068] (C4) In any of the example computing systems of C1 to C3, the immutable BMC hardware is configured to provide packets formatted according to a protocol associated with the programmed peripheral interface via a programmed peripheral interface.

[0069] (C5) In any of the example computing systems of C1 to C4, the immutable BMC hardware is configured to provide packets formatted according to a protocol without the packets being converted to another protocol.

[0070] (C6) In any of the example computing systems of C1 to C5, the PLD is configured to programmable hardware of the PLD by creating register definitions that define the peripheral interface using a configuration file; and the programmable hardware is configured to natively present the register definitions on the internal bus of the programmable enhanced BMC to provide the programmable peripheral interface.

[0071] (C7) In any of the example computing systems of C1 to C6, the PLD enables the operating system (OS) running on the programmable enhanced BMC to natively detect the programmed peripheral interface. III. Example Computer System

[0072] Figure 5 An example computer 500 in which embodiments can be implemented is depicted. Figure 1 The computing system 100 shown may be implemented using a computer 500, including one or more features and / or alternative features of the computer 500. The computer 500 may be a general-purpose computing device, such as a conventional personal computer, mobile computer, or workstation, or the computer 500 may be a dedicated computing device. The description of the computer 500 provided herein is for illustrative purposes and is not intended to be limiting. As will be known to those skilled in the art, embodiments may be implemented in other types of computer systems.

[0073] like Figure 5 As shown, computer 500 includes processing unit 502, system memory 504, and bus 506 coupling various system components, including system memory 504, to processing unit 502. Bus 506 represents one or more types of bus architectures, including memory bus or memory controller, peripheral bus, accelerated graphics port, and processor or local bus using any of the various bus architectures. System memory 504 includes read-only memory (ROM) 508 and random access memory (RAM) 510. Basic input / output system (BIOS) 512 is stored in ROM 508.

[0074] Computer 500 also includes one or more of the following drives: a hard disk drive 514 for reading and writing to a hard disk, a disk drive 516 for reading and writing to a removable disk 518, and an optical disc drive 520 for reading and writing to a removable optical disc 522 such as a CD-ROM, DVD, ROM, or other optical media. Hard disk drive 514, disk drive 516, and optical disc drive 520 are connected to bus 506 via hard disk drive interface 524, disk drive interface 526, and optical disc drive interface 528, respectively. The drives and their associated computer-readable storage media provide the computer with non-volatile storage of computer-readable instructions, data structures, program modules, and other data. Although hard disks, removable disks, and removable optical discs have been described, other types of computer-readable storage media may also be used to store data, such as flash memory cards, digital video discs, random access memory (RAM), read-only memory (ROM), etc.

[0075] Multiple program modules may be stored on a hard disk, magnetic disk, optical disk, ROM, or RAM. These programs include an operating system 530, one or more application programs 532, other program modules 534, and program data 536. Application program 532 or program module 534 may include, for example, computer program logic for implementing one or more (e.g., at least some) of the following as described herein: programmable logic device 110, programmed peripheral interface 116, one or more peripheral devices in peripheral device 106, programmable logic device 310, programmed peripheral interface 316, and / or flowchart 200 (including any steps of flowchart 200).

[0076] Users can input commands and information into computer 500 through input devices such as keyboard 538 and pointing device 540. Other input devices (not shown) may include microphones, joysticks, game controllers, satellite dish antennas, scanners, touchscreens, cameras, accelerometers, gyroscopes, etc. These and other input devices are typically connected to processing unit 502 via serial port interface 542 coupled to bus 506, but may also be connected via other interfaces such as parallel ports, game ports, or Universal Serial Bus (USB).

[0077] Display device 544 (e.g., a monitor) is also connected to bus 506 via an interface such as video adapter 546. In addition to display device 544, computer 500 may include other peripheral output devices (not shown), such as speakers and printers.

[0078] Computer 500 is connected to network 548 (e.g., the Internet) via a network interface or adapter 550, modem 552, or other means for establishing communication on the network. Modem 552 may be internal or external and is connected to bus 506 via serial port interface 542.

[0079] As used herein, the terms "computer program medium" and "computer-readable storage medium" are generally used to refer to media such as a hard disk associated with hard disk drive 514, removable disk drive 518, removable optical disk drive 522, and other media such as flash memory cards, digital video disks, random access memory (RAM), read-only memory (ROM), etc. (e.g., non-transitory media). A computer-readable storage medium is not a signal, such as a carrier signal or a propagating signal. For example, a computer-readable storage medium may not include a signal. Therefore, a computer-readable storage medium itself does not constitute a signal. Such a computer-readable storage medium is distinct from and does not overlap with communication media (excluding communication media). Communication media include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in the signal. As an example, communication media include wireless media such as acoustic, RF, infrared, and other wireless media, as well as wired media. Example embodiments also relate to such communication media.

[0080] As described above, computer programs and modules (including application program 532 and other program modules 534) can be stored on a hard disk, magnetic disk, optical disk, ROM, or RAM. Such computer programs can also be received via network interface 550 or serial port interface 542. When executed or loaded by an application, such computer programs enable computer 500 to implement the features of the embodiments discussed herein. Therefore, such computer programs represent the controller of computer 500.

[0081] The example embodiments also relate to computer program products comprising software (e.g., computer-readable instructions) stored on any computer-usable medium. When executed in one or more data processing devices, such software causes the data processing devices to operate as described herein. Embodiments may employ any computer-usable or computer-readable medium known now or in the future. Examples of computer-readable media include storage devices such as RAM, hard disk drives, floppy disks, CD-ROMs, DVD-ROMs, zip discs, magnetic tapes, magnetic storage devices, optical storage devices, MEMS-based storage devices, nanotechnology-based storage devices, and the like.

[0082] It should be recognized that the disclosed technology is not limited to any particular type of computer or hardware. Certain details of suitable computers and hardware are well known and do not need to be elaborated in this disclosure. IV. Conclusion

[0083] The foregoing detailed description relates to the accompanying drawings illustrating exemplary embodiments of the present disclosure. However, the scope of this disclosure is not limited to these embodiments, but is defined by the appended claims. Therefore, embodiments other than those shown in the drawings, such as modifications of the illustrated embodiments, may still be included in this disclosure.

[0084] References to "an embodiment," "an embodiment," "an example embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is assumed that implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) is within the knowledge of a person skilled in the relevant art(s).

[0085] Descriptors such as “first,” “second,” and “third” are used to refer to some of the elements discussed herein. Such descriptors are used to aid in the discussion of exemplary embodiments and do not indicate the desired order of the referenced elements unless the document makes an affirmative statement that such an order is required.

[0086] Although the subject matter has been described in specific language of structural features and / or actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as examples of implementing the claims, and other equivalent features and actions are intended to be within the scope of the claims.

Claims

1. A programmable enhanced board management controller (BMC) (104, 300, 492), comprising: Immutable BMC hardware (108, 308), which is configured to perform system management operations on peripheral devices (106) outside the programmed enhanced BMC (104, 300, 492); Internal bus (114, 314); and Programmable logic device (PLD) (110, 310) is coupled to the internal bus (114, 314) and the PLD is configured to power on the programmable enhanced BMC (104, 300, 492) (202). The immutable BMC hardware (108, 308) is configured to provide a (204) profile (326) to the PLD (110, 310) at least based on the programming-enhanced BMC (104, 300, 492) being powered on. The profile (326) specifies the configuration of the programmable hardware (320) to be programmably applied to the PLD (110, 310); and The PLD (110, 310) is also configured to program (206) the programmable hardware (320) of the PLD (110, 310) by loading the configuration file (326), such that the programmable hardware (320) natively presents the peripheral interface (116, 316) defined by the configuration file (326) on the internal bus (114, 314) of the programmable enhanced BMC (104, 300, 492).

2. The programmable enhanced BMC of claim 1, wherein the PLD is configured to power on the programmable enhanced BMC even though an initial configuration file is corrupted, the initial configuration file defining an initial configuration to be applied to the PLD before the programmable enhanced BMC is powered on.

3. The programmable enhanced BMC of claim 1, wherein the PLD is configured to power on the programmable enhanced BMC even though the PLD cannot access the initial configuration file, the initial configuration file defining an initial configuration to be applied to the PLD before the programmable enhanced BMC is powered on.

4. The programmable enhanced BMC of claim 1, wherein the immutable BMC hardware is configured to provide packets via the peripheral interface, the packets being formatted according to a protocol associated with the peripheral interface.

5. The programmable enhanced BMC of claim 4, wherein the immutable BMC hardware is configured to provide the packet without converting it to another protocol, the packet being formatted according to the protocol.

6. The programmable enhanced BMC of claim 1, wherein the PLD is configured to load the configuration file by creating register definitions that define the peripheral interface; and The programmable hardware is configured to natively present the register definitions on the internal bus of the programmable enhanced BMC to provide the peripheral interface.

7. The programmable enhanced BMC of claim 1, wherein the PLD causes the operating system (OS) executing on the programmable enhanced BMC to natively detect the peripheral interface by loading the configuration file.

8. A method comprising: A programmable logic device (PLD) (110, 310) powers on a programmable enhanced baseboard management controller (BMC) (104, 300, 492), the PLD (110, 310) being integrated into the programmable enhanced BMC (104, 300, 492) and coupled to the internal bus (114, 314) of the programmable enhanced BMC. At least based on the programming-enhanced BMC (104, 300, 492) being powered on, a (204) configuration file (326) is provided from the immutable BMC hardware (108, 308) in the programming-enhanced BMC (104, 300, 492) to the PLD (110, 310), the configuration file (326) specifying the configuration of the programmable hardware (320) to be programmably applied to the PLD (110, 310); and By loading the configuration file (326) to program the programmable hardware (320) of the PLD (110, 310) (206), the programmable hardware (320) natively presents the peripheral interface (116, 316) defined by the configuration file (326) on the internal bus (114, 314) of the programmable enhanced BMC (104, 300, 492).

9. The method of claim 8, wherein energizing the programmed enhanced BMC comprises: The PLD executes a power-on sequence in which, despite the initial configuration file being corrupted, the PLD still powers on the programmed enhancement BMC, the initial configuration file defining the initial configuration to be applied to the PLD during the power-on sequence.

10. The method of claim 8, wherein energizing the programmed enhanced BMC comprises: The PLD executes a power-on sequence in which, although the initial configuration file cannot be accessed during the power-on sequence, the PLD still powers on the programmable enhanced BMC, the initial configuration file defining the initial configuration to be applied to the PLD.

11. The method of claim 8, further comprising: Packets are provided from the immutable BMC hardware to peripheral devices via the peripheral interface, and the packets are formatted according to the protocol associated with the peripheral interface.

12. The method of claim 11, wherein providing the grouping comprises: Without converting the packet to another protocol during transmission to the peripheral device, the packet is provided from the immutable BMC hardware to the peripheral device via the peripheral interface, the packet being formatted according to the protocol associated with the peripheral interface.

13. The method of claim 8, wherein loading the configuration file comprises: The configuration file is loaded by creating register definitions that define the peripheral interface; and The programmable hardware programming of the PLD causes the register definitions to be natively presented on the internal bus of the programmable enhanced BMC to provide the peripheral interface.

14. The method of claim 8, wherein the programmable hardware programming of the PLD causes an operating system (OS) executing on the programmable enhanced BMC to natively detect the peripheral interface.

15. A computing system (100, 402, 500), comprising: Memory (420, 422, 424, 504); Processing systems (410, 502) are coupled to the memory (420, 422, 424, 504). as well as The programmable enhanced board management controller (BMC) (104, 300, 492) includes: Internal bus (114, 314). An immutable peripheral interface (112, 312) is coupled to the internal bus (114, 314). Immutable BMC hardware (108, 308), configured to perform system management operations on a peripheral device (106) by providing packets (332) to the peripheral device (106) via the immutable peripheral interface (112, 312), the peripheral device (106) including the memory (420, 422, 424, 504) or the processing system (410, 502); and A programmable logic device (PLD) (110, 310) is coupled to the internal bus (114, 314), the PLD (110, 310) is configured to power on the programmable enhanced BMC (104, 300, 492), and the PLD (110, 310) includes programmable hardware (320). The immutable BMC hardware (108, 308) is also configured to provide a (204) profile (326) to the PLD (110, 310) at least based on the programmable enhanced BMC (104, 300, 492) being powered on. The profile (326) specifies the configuration of the programmable hardware (320) to be programmably applied to the PLD (110, 310); and The PLDs (110, 310) are also configured to program (206) the programmable hardware (320) of the PLDs (110, 310) using the configuration file (326) to natively provide a programmable peripheral interface (116, 316) on the internal bus (114, 314) of the programmable enhanced BMCs (104, 300, 492).

16. The computing system of claim 15, wherein the PLD is configured to execute a power-on sequence in which the PLD powers the programmed enhancement BMC despite the initial configuration file being corrupted, the initial configuration file defining an initial configuration to be applied to the PLD during the power-on sequence.

17. The computing system of claim 15, wherein the PLD is configured to execute a power-on sequence in which the PLD powers the programmable enhanced BMC, the initial configuration file defining the initial configuration to be applied to the PLD, even though the initial configuration file cannot be accessed during the power-on sequence.

18. The computing system of claim 15, wherein the immutable BMC hardware is configured to provide packets via the programmed peripheral interface, the packets being formatted according to a protocol associated with the programmed peripheral interface.

19. The computing system of claim 18, wherein the immutable BMC hardware is configured to provide the packet without converting it to another protocol, the packet being formatted according to the protocol.

20. The computing system of claim 15, wherein the PLD is configured to program the programmable hardware of the PLD by creating register definitions of the peripheral interface using the configuration file; and The programmable hardware is configured to natively present the register definitions on the internal bus of the programmable enhanced BMC to provide the programmable peripheral interface.

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