Solid-state imaging element, range image imaging apparatus, and control method

Abstract

The solid-state imaging element includes a plurality of pixels, an addition switch, and a pixel driving circuit. Each of the plurality of pixels includes a photoelectric conversion element that generates a charge corresponding to incident light, a charge storage unit that stores the charge, and a reset switch that resets the charge storage unit to a predetermined reset potential supplied from a power supply line. The addition switch is connected in series in two or more stages between a connection line connecting the power supply line side of the reset switch of a predetermined number of pixels and the power supply line. The addition switch is capable of changing a region of the pixel to which the charges accumulated by the charge accumulation unit are added by changing an ON state. The pixel drive circuit changes the on-state of the reset switch and the two or more stages of addition switches in accordance with the region of the pixel to be added.

Description

Technical Field

[0001] This invention relates to solid-state imaging elements, distance imaging devices, and control methods.

[0002] This application claims priority based on Japanese Patent Application No. 2023-177274, filed in Japan on October 13, 2023, the contents of which are incorporated herein by reference. Background Technology

[0003] Distance image capturing devices have been developed that utilize the known speed of light and determine the distance between the measuring device and the object based on the time of flight of light in space (the measuring space) using the time of flight (hereinafter referred to as "TOF") method (for example, see Patent Document 1). In such capturing devices, for example, solid-state imaging elements containing photoelectric conversion elements such as photodiodes are used for capturing images.

[0004] Existing technical documents Patent documents Patent Document 1: Japanese Patent No. 4235729 Summary of the Invention

[0005] The problem that the invention aims to solve However, sometimes the pixels of a solid-state imaging sensor are summed for use. In conventional solid-state imaging sensors, multiple switches are placed within a pixel to sum the pixel values ​​(charges) obtained from photoelectric conversion by multiple photoelectric conversion elements. Therefore, conventional solid-state imaging sensors suffer from the problem of larger pixel sizes. In addition, in conventional solid-state imaging sensors, it is difficult to flexibly change the pixel area where the charge is summed according to the shooting scene.

[0006] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a solid-state imaging element, a distance image imaging device, and a control method that can suppress the increase of pixel size and flexibly change the pixel area where charges are added according to the imaging scene.

[0007] Methods for solving problems To solve the above problems, Embodiment 1 of the present invention relates to a solid-state imaging element, comprising: a plurality of pixels, each having a photoelectric conversion element that generates a charge corresponding to incident light, a charge storage section that stores the charge, and a reset switch that resets the charge storage section to a predetermined reset potential supplied from a power line; an adder switch having two or more stages connected in series between a connecting line connecting a predetermined number of pixels to the power line side of the reset switch and the power line, and capable of changing the region of the pixel where the charge stored in the charge storage section is added by changing the conduction state; and a pixel driving circuit that changes the conduction state of the reset switch and the two or more stages of the adder switch according to the region of the pixel where the addition is performed.

[0008] Alternatively, in embodiment 2 of the present invention, in the solid-state imaging element of embodiment 1, the addition switch of the second level or above is: a first addition switch, disposed between a first connecting line connecting the power line side of the reset switches of N pixels and the power line, configured to add the charge stored by the N charge storage units via the first connecting line and the reset switch, wherein N is an integer greater than or equal to 2; and a second addition switch, disposed between a second connecting line connecting the power line side of the first addition switches of M pixels and the power line, configured to add the additive charge of the region of the N pixels connected by the first connecting line (i.e., the additive pixel region) via the second connecting line and the first addition switch, wherein M is an integer greater than or equal to 2, wherein the pixel driving circuit changes the conduction state of the reset switch, the first addition switch and the second addition switch according to the region of the pixel being added.

[0009] Alternatively, in the solid-state imaging element of the present invention, the additive pixel regions are connected in a linear manner to function as a linear sensor.

[0010] Alternatively, in the solid-state imaging element of the present invention, the first connecting line and the second connecting line are connected in such a way that non-adjacent pixels are added to each other.

[0011] Alternatively, in any of the solid-state imaging elements of embodiments 1 to 4, the pixel is a 4-transistor pixel, which includes a reset transistor as a reset switch, a source follower transistor for converting the charge into an electrical signal, a transfer transistor for transferring the charge to the source follower transistor, and a readout selection transistor for selecting the electrical signal of the pixel.

[0012] Alternatively, in any of the solid-state imaging elements of embodiments 1 to 4, the pixel is a 3-transistor pixel, which includes a reset transistor as a reset switch, a source follower transistor for converting the charge into an electrical signal, and a selection transistor for selecting the readout of the electrical signal of the pixel.

[0013] Alternatively, in any of the solid-state imaging elements of embodiments 1 to 6, the pixel has a plurality of charge storage sections, each of which can be allocated and store charge, and the pixel driving circuit distributes and stores the charge to each of the charge storage sections.

[0014] Alternatively, embodiment 8 of the present invention may include a distance image imaging device comprising: a light source unit that irradiates a light pulse onto a subject; a light receiving unit having a solid-state imaging element as described in any one of embodiments 1 to 7; and a distance image processing unit that controls the pixel driving circuit to cause each of the charge storage units to store charge, and calculates the distance to the subject based on the amount of charge stored in each of the charge storage units.

[0015] Furthermore, embodiment 9 of the present invention is a control method for a solid-state imaging element, the solid-state imaging element comprising: a plurality of pixels, each having a photoelectric conversion element that generates a charge corresponding to incident light, a charge storage section that stores the charge, and a reset switch that resets the charge storage section to a predetermined reset potential supplied from a power line; and an adder switch, wherein two or more stages are connected in series between a connecting line connecting a predetermined number of pixels to the power line side of the reset switch and the power line, and by changing the conduction state, the region of the pixel in which the charge stored in the charge storage section is added can be changed, and the pixel driving circuit changes the conduction state of the reset switch and the two or more stages of the adder switch according to the region of the pixel in which the addition is performed.

[0016] Invention Effects According to the present invention, it is possible to suppress the increase of pixel size and to flexibly change the pixel area where charges are added according to the shooting scene. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating an example of a solid-state imaging element according to the first embodiment.

[0018] Figure 2 This diagram illustrates the switching control of pixel regions in the solid-state imaging element according to the first embodiment.

[0019] Figure 3A This is a timing diagram showing the operation of the first embodiment when performing image capture without addition (individual pixels).

[0020] Figure 3B This is a timing diagram showing the operation of capturing images when performing a ×2 (double addition) of pixels in the first embodiment.

[0021] Figure 3C This is a timing diagram showing the operation of capturing images when performing a 4x pixel addition (4x addition) according to the first embodiment.

[0022] Figure 4A This diagram illustrates the operation of capturing images without addition (individual pixels) in the first embodiment.

[0023] Figure 4B This diagram illustrates the operation of capturing images when performing a ×2 summation (double summation) of pixels according to the first embodiment.

[0024] Figure 4C This diagram illustrates the operation of capturing images when performing a 4x pixel addition (4x addition) according to the first embodiment.

[0025] Figure 5 This is a flowchart illustrating an example of the operation of switching control of pixel regions of the solid-state imaging element in the first embodiment.

[0026] Figure 6A This is a graph showing the sensitivity characteristics of the number of electrons in the solid-state imaging element of the first embodiment.

[0027] Figure 6B This is a graph showing the sensitivity characteristics of the output voltage of the solid-state imaging element according to the first embodiment.

[0028] Figure 7 This is a block diagram illustrating an example of a solid-state imaging element according to the second embodiment.

[0029] Figure 8 This is a block diagram illustrating an example of a solid-state imaging element according to the third embodiment.

[0030] Figure 9 This is a block diagram illustrating an example of a solid-state imaging element according to the fourth embodiment.

[0031] Figure 10 This is a diagram illustrating the switching control of pixel regions of the solid-state imaging element in the fourth embodiment.

[0032] Figure 11 This is a block diagram illustrating an example of a solid-state imaging element according to the fifth embodiment.

[0033] Figure 12 This is a diagram illustrating an example of the Bayer arrangement of RGB pixels in the fifth embodiment.

[0034] Figure 13 This is a block diagram illustrating an example of a solid-state imaging element according to the sixth embodiment.

[0035] Figure 14 This is a block diagram illustrating an example of a solid-state imaging element according to the seventh embodiment.

[0036] Figure 15 This is a block diagram illustrating an example of the distance image camera device according to the eighth embodiment. Detailed Implementation

[0037] Hereinafter, a solid-state imaging element, a distance image imaging device, and a control method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0038] [First Implementation Method] Figure 1 This is a block diagram illustrating an example of the solid-state imaging element 1 according to the first embodiment.

[0039] like Figure 1 As shown, the solid-state imaging element 1 includes a pixel unit 11 and a pixel driving circuit 12.

[0040] The pixel unit 11 includes multiple pixels SG (SG1, SG2, SG3, SG4, ...) and addition switches (addition transistor RS1, addition transistor RS2). In the pixel unit 11, for example, the multiple pixels SG are arranged in a two-dimensional matrix to form a light-receiving area. The pixel unit 11 is configured to add charges in units of (N × M) pixels SG (where N and M are integers greater than or equal to 2). Furthermore, in this embodiment, an example of adding charges in units of (2 × 2) pixels SG with N = 2 and M = 2 will be described.

[0041] A pixel SG is a single pixel. For example, a pixel SG is a 4-transistor pixel. A pixel SG has a photoelectric conversion element PD, a charge storage unit CS, a reset transistor RQ, a source follower transistor SF, a transfer transistor TQ, and a select transistor SQ.

[0042] A photoelectric conversion element (PD) is, for example, an embedded photodiode. The PD performs photoelectric conversion on incident light, generating a charge corresponding to the incident light. The PD has an anode terminal connected to a grounded power supply line and a cathode terminal connected to the source terminal of a transmission transistor (TQ).

[0043] The transfer transistor TQ is turned on (ON state) by the control signal TX. As a result, the transfer transistor TQ stores the charge generated by the photoelectric conversion element PD in the charge storage section CS, and transfers the charge to the source follower transistor SF.

[0044] The charge storage section CS is the section that stores the charge generated by the photoelectric conversion element PD. The charge storage section CS is the floating diffusion section FD.

[0045] The source follower transistor SF is a transistor that converts charge into an electrical signal. The source follower transistor SF outputs an electrical signal (voltage) corresponding to the charge stored in the charge storage section CS to the selection transistor SQ.

[0046] The selector transistor SQ selects the readout of the electrical signal of pixel SG. The selector transistor SQ is turned on (ON state) by the control signal SL. As a result, the selector transistor SQ outputs the pixel value (output signal) to the output line OL.

[0047] The reset transistor RQ (an example of a reset switch) resets the charge storage section CS to a predetermined reset potential supplied from the power supply line VDD. The reset transistor RQ is turned on (ON state) by the control signal RT. Thus, the reset transistor RQ resets the charge storage section CS to the reset potential supplied from the power supply line VDD via the adder switches (adder transistors RS1 and RS2) described later.

[0048] The adder switches (adder transistors RS1 and RS2) are switches with two or more stages connected in series between the connecting lines (connecting lines CL1 and CL2) and the power supply line VDD. The connecting lines (connecting lines CL1 and CL2) connect to the power supply line VDD side of the reset transistors RQ of a predetermined number of pixels SG. In this embodiment, an example of a two-stage adder switch is described. By changing the conduction state, the adder switches (adder transistors RS1 and RS2) can change the region of the pixel SG that adds the charge stored in the charge storage section CS.

[0049] In addition, in this embodiment, the variable pixel SG area is a single pixel SG (not added), a ×2 added area (2 times the added pixel area GA1), and a ×4 added area (4 times the added pixel area GA2).

[0050] Furthermore, in this embodiment, the adder switch with two or more stages is adder transistor RS1 and adder transistor RS2. In other words, adder transistor RS1 and adder transistor RS2 are equivalent to adder switches with two or more stages. Further, in other words, the adder switch with two or more stages includes adder transistor RS1 and adder transistor RS2.

[0051] An adder transistor RS1 (first adder switch) is configured between connection line CL1 (first connection line) and power line VDD. Connection line CL1 (first connection line) connects the power line VDD side of the reset transistors RQ of N (e.g., 2) pixels SG. Adder transistor RS1 has a source terminal connected to connection line CL1, which is connected to the drain terminals of the two reset transistors RQ, and a drain terminal connected to connection line CL2.

[0052] The adder transistor RS1 is configured to add the charges stored in N (e.g., 2) charge storage units CS via the connection line CL1 and the reset transistor RQ. The conduction state of the adder transistor RS1 is changed according to the control signal RTC1.

[0053] An adder transistor RS2 (second adder switch) is configured between connection line CL2 (second connection line) and power line VDD. Connection line CL2 (second connection line) connects the power line VDD side of M (e.g., 2) adder transistors RS1. Adder transistor RS2 has a source terminal connected to connection line CL2, which is connected to the drain terminals of the two adder transistors RS1, and a drain terminal connected to the power line VDD.

[0054] The adder transistor RS2 is configured to add the charge of the adder pixel region GA1 via the connection line CL2 and the adder transistor RS1. The adder pixel region GA1 is the region of N (e.g., 2) pixels SG connected by the connection line CL1. The conduction state of the adder transistor RS2 is changed according to the control signal RTC2.

[0055] In addition, the reset transistor RQ, source follower transistor SF, transfer transistor TQ, select transistor SQ, adder transistor RS1, and adder transistor RS2 are, for example, NMOS transistors.

[0056] The pixel driving circuit 12 changes the conduction state of the reset transistor RQ and the two or more addition switches (adding transistor RS1, adding transistor RS2) according to the region of the pixels SG being added. In addition, the pixel driving circuit 12 controls the transfer of charge to the charge storage section CS of each pixel SG (control of transfer transistor TQ), controls the reset of the charge storage section CS of each pixel SG to the reset potential (control of reset transistor RQ), and controls the selection of each pixel SG (control of selection transistor SQ).

[0057] The pixel driving circuit 12 outputs control signals RT, RTC1, RTC2, TX, and SL.

[0058] Figure 2This diagram illustrates the switching control of the pixel region of the solid-state imaging element 1 in this embodiment.

[0059] like Figure 2 As shown, the pixel driving circuit 12 uses control signals RT, RTC1, and RTC2 to control the switching of pixel regions.

[0060] When performing image capture without addition (for individual pixels SG), the pixel driving circuit 12 controls the control signals RTC1 and RTC2 to be fixed at a High level and outputs a pulse signal to the control signal RT. In this case, the adder transistors RS1 and RS2 are turned on (ON), and the turn-on of the reset transistor RQ is controlled by the pulse signal.

[0061] Furthermore, when the pixel driving circuit 12 performs image capture based on ×2 addition (double addition) on pixel SG, it controls the control signal RT and control signal RTC2 to be fixed in the High state and outputs a pulse signal to control signal RTC1. In this case, reset transistor RQ and adder transistor RS2 are turned on (ON state), and the turn-on of adder transistor RS1 is controlled by the pulse signal.

[0062] Furthermore, when performing pixel SG×4 summation (4x summation) imaging, the pixel driving circuit 12 controls the control signal RT and control signal RTC1 to be fixed in the High state and outputs a pulse signal to the control signal RTC2. In this case, the reset transistor RQ and the adder transistor RS1 are turned on (ON state), and the turn-on of the adder transistor RS2 is controlled by the pulse signal.

[0063] Next, the operation of the solid-state imaging element 1 of this embodiment will be described with reference to the accompanying drawings.

[0064] Figures 3A-3C This is a timing diagram illustrating an example of the switching control of pixel regions in the solid-state imaging element 1 of this embodiment. Additionally, Figures 4A to 4C This diagram illustrates the operation of switching control of the pixel region of the solid-state imaging element 1 in this embodiment.

[0065] Figure 3A It is a timing diagram representing the actions taken when recording without addition (single pixel SG).

[0066] like Figure 3AAs shown, when performing image capture without addition (for individual pixels SG), the pixel driving circuit 12 fixes control signals RTC1 and RTC2 to the High state, sets control signal SL to the High state, and outputs a pulse signal to control signal RT. As a result, each pixel SG is selected, and the charge storage section CS is reset to the potential of the power line VDD.

[0067] Next, the pixel driving circuit 12 outputs a pulse signal to the control signal TX. As a result, the charge obtained by photoelectric conversion by the photoelectric conversion element PD is stored in the charge storage section CS, and the pixel value of the pixel SG is output to the output line OL via the source follower transistor SF and the select transistor SQ.

[0068] In this case, such as Figure 4A As shown, adder transistors RS1 and RS2 are in the ON state, and connecting lines CL1 and CL2 are at the potential of power line VDD (power node). Furthermore, when a pulse signal is output to the control signal RT, the charge storage unit CS is reset to the potential of power line VDD. Additionally, the solid-state imaging element 1 outputs the pixel values ​​of individual pixels SG (pixels SG1, SG2, SG3, and SG4).

[0069] in addition, Figure 3B It is a timing diagram representing the actions taken when performing a 2x pixel summation (2x summation).

[0070] like Figure 3B As shown, when performing image capture with pixel SG×2 addition (double addition), the pixel driving circuit 12 fixes the control signal RT and control signal RTC2 to the High state, sets the control signal SL to the High state, and outputs a pulse signal to the control signal RTC1. As a result, each pixel SG is selected, and the charge storage section CS is reset to the potential of the power line VDD.

[0071] Next, the pixel driving circuit 12 outputs a pulse signal to the control signal TX. As a result, the charge obtained by photoelectric conversion by the photoelectric conversion element PD is added in the two pixels SG and stored in the charge storage section CS. The pixel value of the pixel SG is then output to the output line OL via the source follower transistor SF and the select transistor SQ.

[0072] In this case, such as Figure 4BAs shown, the reset transistor RQ and the adder transistor RS2 are in the ON state. After reset, the adder transistor RS1 becomes the OFF state. Therefore, the connection line CL1 becomes a floating node (determined node). Then, when a pulse signal is output to the control signal TX, the charge accumulation sections CS of the two pixels SG are added together through the connection line CL1. The solid-state imaging element 1 outputs the pixel value of the sum of the two pixels SG (the sum of pixel SG1 and pixel SG2, and the sum of pixel SG3 and pixel SG4).

[0073] in addition, Figure 3C It is a timing diagram representing the actions taken when performing a 4x4 pixel summation (4x summation).

[0074] like Figure 3C As shown, when performing image capture with pixel SG×4 addition (4x addition), the pixel driving circuit 12 fixes the control signal RT and control signal RTC1 to the High state, sets the control signal SL to the High state, and outputs a pulse signal to the control signal RTC2. As a result, each pixel SG is selected, and the charge storage section CS is reset to the potential of the power line VDD.

[0075] Next, the pixel driving circuit 12 outputs a pulse signal to the control signal TX. As a result, the charge obtained by photoelectric conversion by the photoelectric conversion element PD is added in the four pixels SG and stored in the charge storage section CS. The pixel value of the pixel SG is then output to the output line OL via the source follower transistor SF and the select transistor SQ.

[0076] In this case, such as Figure 4C As shown, the reset transistor RQ and the adder transistor RS1 are in the ON state. After reset, the adder transistor RS2 becomes in the OFF state. Therefore, connection lines CL1 and CL2 become floating nodes (determined nodes). Furthermore, when a pulse signal is output to the control signal TX, the charge accumulation sections CS of the four pixels SG are added together through connection lines CL1 and CL2. The solid-state imaging element 1 outputs the pixel value of the sum of the four pixels SG (the sum of pixel SG1, pixel SG2, pixel SG3, and pixel SG4).

[0077] Next, refer to Figure 5 The control processing of the pixel driving circuit 12 in this embodiment will be described.

[0078] Figure 5 This is a flowchart illustrating an example of the operation of switching control of the pixel region of the solid-state imaging element 1 in this embodiment.

[0079] like Figure 5As shown, the pixel driving circuit 12 first determines whether a single pixel (pixel SG) is used (step S101). If a single pixel (pixel SG) is used (step S101: Yes), the pixel driving circuit 12 causes the process to proceed to step S102. Otherwise, if a single pixel (pixel SG) is not used (step S101: No), the pixel driving circuit 12 causes the process to proceed to step S103.

[0080] In step S102, the pixel driving circuit 12 fixes control signals RTC1 and RTC2 to high and performs pulse control on the control signal RT. After the processing in step S102, the pixel driving circuit 12 ends the processing of the pixel region switching control.

[0081] In step S103, the pixel driving circuit 12 determines whether to use ×2 addition. If ×2 addition is used (step S103: Yes), the pixel driving circuit 12 causes the process to proceed to step S104. Otherwise, if ×2 addition is not used (step S103: No), the pixel driving circuit 12 causes the process to proceed to step S105.

[0082] In step S104, the pixel driving circuit 12 fixes the control signal RT and the control signal RTC2 to high, and performs pulse control on the control signal RTC1. After the processing in step S104, the pixel driving circuit 12 ends the processing of the pixel region switching control.

[0083] In step S105, the pixel driving circuit 12 determines whether to use ×4 addition. If ×4 addition is used (step S105: Yes), the pixel driving circuit 12 causes the process to proceed to step S106. Otherwise, if ×4 addition is not used (step S105: No), the pixel driving circuit 12 terminates the pixel region switching control process.

[0084] In step S106, the pixel driving circuit 12 fixes the control signal RT and the control signal RTC1 to high, and performs pulse control on the control signal RTC2. After the processing in step S106, the pixel driving circuit 12 ends the processing of the pixel region switching control.

[0085] Next, refer to Figure 6A and Figure 6B The effect of charge addition on the solid-state imaging element 1 in this embodiment will be explained.

[0086] Figure 6A as well as Figure 6B This is a diagram illustrating the effect of charge addition on the solid-state imaging element 1 in this embodiment.

[0087] Figure 6AThe graph shown illustrates the sensitivity characteristics of the number of electrons in the solid-state imaging element 1 of this embodiment.

[0088] exist Figure 6A In the diagram, the horizontal axis represents illuminance or exposure time, and the vertical axis represents the number of output electrons.

[0089] Additionally, waveform W1 represents the sensitivity characteristics when dealing with a single pixel (SG), waveform W2 represents the sensitivity characteristics when multiplied by 2, and waveform W3 represents the sensitivity characteristics when multiplied by 4.

[0090] like Figure 6A As shown, the slope of waveform W2 when ×2 is added is twice the slope of waveform W1 when a single pixel (pixel SG) is added, and the slope of waveform W3 when ×4 is added is four times the slope of waveform W1 when a single pixel (pixel SG) is added. That is, the sensitivity characteristic of the number of electrons when ×2 is added is twice that when a single pixel (pixel SG) is added, and the sensitivity characteristic of the number of electrons when ×4 is added is four times that when a single pixel (pixel SG) is added.

[0091] Thus, in the solid-state imaging element 1 of this embodiment, the detection sensitivity can be improved by using ×2 addition or ×4 addition.

[0092] also, Figure 6B The graph shown illustrates the sensitivity characteristics of the output voltage of the solid-state imaging element 1 in this embodiment.

[0093] exist Figure 6B In the diagram, the horizontal axis represents illuminance or exposure time, and the vertical axis represents output voltage.

[0094] Furthermore, waveform W4 represents the sensitivity characteristics when a single pixel (pixel SG) is added ×2 and when ×4 is added. That is, in the solid-state imaging element 1 of this embodiment, the slopes are the same when a single pixel (pixel SG) is added ×2 and when ×4 is added.

[0095] Thus, in the solid-state imaging element 1 of this embodiment, the sensitivity based on the number of electrons increases, but the sensitivity based on the output voltage remains unchanged when the number of individual pixels (SG), the number of electrons is increased by 2 times and 4 times, respectively, so the output voltage remains unchanged. That is, even when the number of electrons increases by 2 times and 4 times, the capacity of the floating diffusion section FD (charge storage section CS) also increases by 2 times and 4 times, respectively. In other words, in the solid-state imaging element 1 of this embodiment, saturation is not easily achieved even when the number of electrons is increased by 4. Therefore, in the solid-state imaging element 1 of this embodiment, the influence of noise can be reduced, and the S / N ratio (signal-to-noise ratio) based on the number of electrons can be improved.

[0096] As explained above, the solid-state imaging element 1 of this embodiment is a solid-state imaging element 1 having multiple pixels SG, and includes adder switches (adder transistors RS1 and RS2) and a pixel driving circuit 12. Each pixel SG has a photoelectric conversion element PD that generates a charge corresponding to the incident light, a charge storage section CS that stores the charge, and a reset transistor RQ (reset switch) that resets the charge storage section CS to a predetermined reset potential supplied from the power line VDD. The adder switches (adder transistors RS1 and RS2) are two or more stages of adder switches connected in series between the power line VDD and the connection lines (connection lines CL1 and CL2) connecting the reset transistors RQ of a predetermined number of pixels SG to the power line VDD. By changing the conduction state, the area of ​​the pixel SG where the charge stored in the charge storage section CS is added can be changed. The pixel driving circuit 12 changes the conduction state of the reset transistor RQ and the two or more stages of adder switches (adder transistors RS1 and RS2) according to the area of ​​the pixel SG where the addition is performed.

[0097] Therefore, the solid-state imaging element 1 of this embodiment, through its simple configuration of connecting two or more stages of adder switches (adder transistor RS1, adder transistor RS2) in series between the reset transistor RQ and the power line VDD, can suppress the increase in pixel size while performing charge addition. Furthermore, by changing the conduction states of the two or more stages of series-connected adder switches (adder transistor RS1, adder transistor RS2) and the reset transistor RQ, the solid-state imaging element 1 of this embodiment can flexibly change the pixel area where charge is added according to the imaging scene. Therefore, the solid-state imaging element 1 of this embodiment can suppress the increase in pixel size and can flexibly change the pixel area where charge is added according to the imaging scene.

[0098] Furthermore, as shown in Figure 6 above, and Figure 6B As explained, the solid-state imaging element 1 of this embodiment can improve detection sensitivity and reduce the influence of noise by using ×2 addition or ×4 addition. This improves the S / N ratio (signal-to-noise ratio) based on the number of electrons.

[0099] In this embodiment, the adder switches of level 2 or higher are adder transistor RS1 (first adder switch) and adder transistor RS2 (second adder switch). Adder transistor RS1 (first adder switch) is positioned between a first connection line connecting the power supply lines VDD of N (e.g., 2) pixel SG reset transistors RQ and the power supply line VDD, and is configured to add the charges stored in the N charge storage sections CS via connection line CL1 (first connection line) and reset transistors RQ (where N is an integer of 2 or more). Adder transistor RS2 (second adder switch) is positioned between connection line CL2 (second connection line) connecting the power supply lines VDD of M (e.g., 2) adder transistors RS1 and the power supply line VDD, and is configured to add the additive charges of the region GA1 of the N pixel SGs connected by connection line CL1 via connection line CL2 and adder transistor RS1 (where M is an integer of 2 or more). The pixel driving circuit 12 changes the conduction state of the reset transistor RQ, the adder transistor RS1, and the adder transistor RS2 according to the region of the pixel SG to be added.

[0100] Therefore, the solid-state imaging element 1 of this embodiment can be switched to use as any one of the following: a single pixel SG, N pixels SG (e.g., 2 pixels SG: ×2 added together), or (N×M) pixels SG (2×2=4 pixels SG: ×4 added together). Thus, the solid-state imaging element 1 of this embodiment can flexibly change the pixel area where charges are added according to the imaging scene.

[0101] In addition, in this embodiment, the pixel SG is a 4-transistor pixel having a reset transistor RQ that acts as a reset switch, a source follower transistor SF that converts charge into an electrical signal, a transfer transistor TQ that transfers charge to the source follower transistor SF, and a selection transistor SQ that reads out the electrical signal of the pixel SG.

[0102] Therefore, the solid-state imaging element 1 of this embodiment can use 4-transistor pixels, and the pixel area can be flexibly changed by adding charges according to the imaging scene. In addition, the solid-state imaging element 1 of this embodiment can achieve charge addition without changing the composition of the pixel SG by adding an addition switch (addition transistor RS1, addition transistor RS2).

[0103] Furthermore, the control method of this embodiment is a control method for a solid-state imaging element 1 having multiple pixels SG. Each pixel SG has a photoelectric conversion element PD that generates charge corresponding to incident light, a charge storage section CS that stores charge, and a reset transistor RQ that resets the charge storage section CS to a predetermined reset potential supplied from the power line VDD. The solid-state imaging element 1 has adder switches (adder transistors RS1 and RS2). These adder switches are connected in series with the power line VDD between two or more stages of connecting lines (connecting lines CL1 and CL2) that connect the power line VDD side of the reset transistors RQ of a predetermined number of pixels SG. By changing the conduction state, the area of ​​the pixel SG where the charge stored in the charge storage section CS is added can be changed. In this control method, the pixel driving circuit 12 changes the conduction state of the reset transistor RQ and the two or more stages of adder switches (adder transistors RS1 and RS2) according to the area of ​​the pixel SG where the addition is performed.

[0104] Therefore, the control method of this embodiment has the same effect as the solid-state imaging element 1 described above, which can suppress the increase of pixel size and can flexibly change the pixel area where the charge is added according to the imaging scene.

[0105] [Second Implementation] Next, the solid-state imaging element 1a of the second embodiment will be described with reference to the accompanying drawings.

[0106] In the second embodiment, a variation in which (4×2) pixels SG are applied to the above (N×M) pixels SG will be described.

[0107] Figure 7 This is a block diagram illustrating an example of the solid-state imaging element 1a according to the second embodiment.

[0108] like Figure 7 As shown, the solid-state imaging element 1a includes a pixel section 11a and a pixel driving circuit 12a.

[0109] In the pixel unit 11a, a plurality of pixels SG are arranged in a two-dimensional matrix. The pixel unit 11a includes a plurality of pixels SG and an addition switch (adding transistor RS1, adding transistor RS2).

[0110] In this embodiment, adder transistor RS1 (first adder switch) is configured for each (2×2=4) pixel SG. The drain terminal of the reset transistor RQ for each (2×2=4) pixel SG is connected to the source terminal of adder transistor RS1 via connection line CL1 (first connection line). Through adder transistor RS1 and connection line CL1, the addition of (2×2=4) pixels SG (×4 addition) can be performed.

[0111] Furthermore, adder transistor RS2 (second adder switch) is configured with two adder transistors RS1 (first adder switches) for every two adder transistors. The drain terminals of the two adder transistors RS1 are connected to the source terminals of the adder transistors RS2 via connecting line CL2 (second connecting line). Through adder transistors RS1 and connecting line CL1, and adder transistors RS2 and connecting line CL2, it is possible to add (2×2×2=8) pixels SG (×8 addition).

[0112] In addition, in this embodiment, the variable pixel SG area is a single pixel SG (not added), a ×4 added area (4 times the added pixel area GA1), and a ×8 added area (8 times the added pixel area GA2).

[0113] Pixel driving circuit 12a is a circuit that drives pixel section 11a. The basic functions and control of pixel driving circuit 12a are the same as those of pixel driving circuit 12 described above. Furthermore, in pixel driving circuit 12a, each control signal can be individually controlled via each pixel SG, each adder transistor RS1, and each adder transistor RS2. Pixel driving circuit 12a outputs control signal RT. <n>~RT<n+3> Control signal RTC1 <n>~RTC1<n+1> Control signal RTC2 <n>Control signal TX <n>~TX<n+1> and control signal SL <n>~SL<n+3> (where n is any integer).

[0114] As explained above, this embodiment is a variation in which N of the (N×M) pixels SG are adjacent (2×2=4), and M are 2.

[0115] Therefore, in the solid-state imaging element 1a of this embodiment, it is possible to detect pixel values ​​based on individual pixels SG (non-additive), regions of ×4 addition (additive pixel region GA1 with 4x addition), and regions of ×8 addition (additive pixel region GA2 with 8x addition). The solid-state imaging element 1a of this embodiment achieves the same effect as the solid-state imaging element 1 of the first embodiment described above, and can flexibly switch between individual pixels SG (non-additive), regions of ×4 addition (additive pixel region GA1 with 4x addition), and regions of ×8 addition (additive pixel region GA2 with 8x addition) according to the imaging scene.

[0116] Furthermore, in the above embodiments, an example of (N×M) pixels being (4×2) pixels was described, but this is not a limitation. N and M can be any integer greater than 2, or other values. Additionally, in the above embodiments, an example of N pixels SG being (2×2) pixels SG was described, but this is not a limitation. N pixels SG can also be composed of any two-dimensional matrix such as (2×3) or (4×4).

[0117] [Third Implementation Method] Next, the solid-state imaging element 1b of the third embodiment will be described with reference to the accompanying drawings.

[0118] In the third embodiment, a modified example in which the above-mentioned N pixels SG are composed of linear pixels SG ((1×n) pixels SG) will be described.

[0119] Figure 8 This is a block diagram illustrating an example of the solid-state imaging element 1b according to the third embodiment.

[0120] like Figure 8 As shown, the solid-state imaging element 1b includes a pixel section 11b and a pixel driving circuit 12b.

[0121] In the pixel unit 11b, a plurality of pixels SG are arranged in a two-dimensional matrix. The pixel unit 11b includes a plurality of pixels SG and an addition switch (adding transistor RS1, adding transistor RS2).

[0122] In this embodiment, the adder transistor RS1 (first adder switch) is provided for each of the linear (1×n=n) pixels SG. The drain terminals of the reset transistors RQ of the n pixels SG are connected to the source terminals of the adder transistor RS1 via the connecting line CL1 (first connecting line). Through the adder transistor RS1 and the connecting line CL1, the addition (×n addition) of the (1×n=n) pixels SG can be performed.

[0123] Furthermore, adder transistor RS2 (second adder switch) is configured with two adder transistors RS1 (first adder switches) for every two adder transistors. The drain terminals of the two adder transistors RS1 are connected to the source terminals of the adder transistors RS2 via connecting line CL2 (second connecting line). Through adder transistors RS1 and connecting line CL1, and adder transistors RS2 and connecting line CL2, it is possible to add (1×n×2=2n) pixels SG (×2n addition).

[0124] In this embodiment, the variable pixel SG regions are individual pixel SG (not added), ×n added regions (additive pixel regions GA1 with n times the sum), and ×2n added regions (additive pixel regions GA2 with 2n times the sum). The additive pixel regions GA1 are connected in a linear fashion and function as a linear sensor.

[0125] The pixel driving circuit 12b is a circuit that drives the pixel unit 11b. The basic functions and control of the pixel driving circuit 12b are the same as those of the pixel driving circuit 12 described above. In addition, the pixel driving circuit 12b outputs a control signal RT. <n>Control signal RTC1 <n>Control signal RTC2 <n>Control signal TX <n>and control signal SL <n>(where n is any integer).

[0126] As explained above, in this embodiment, the additive pixel regions GA1 are connected in a linear fashion, functioning as a linear sensor.

[0127] Therefore, the solid-state imaging element 1b of this embodiment can switch between a linear sensor and a region sensor.

[0128] Furthermore, the solid-state imaging element 1b of this embodiment has the same effect as the solid-state imaging element 1 of the first embodiment described above, and can flexibly switch between individual pixels SG (non-additive), linear regions of ×n addition (linear additive pixel regions GA1 of n times addition), and regions of ×2n addition (additive pixel regions GA2 of 2n times addition) according to the imaging scene.

[0129] Furthermore, while the above embodiments illustrate an example of addition along vertical lines, this embodiment is not limited to this. Addition along horizontal lines may also be employed.

[0130] [Fourth Implementation Method] Next, the solid-state imaging element 1c of the fourth embodiment will be described with reference to the accompanying drawings.

[0131] In the fourth embodiment, a modified example in which the above-mentioned adder switch is connected in series in three stages will be described.

[0132] Figure 9 This is a block diagram illustrating an example of the solid-state imaging element 1c according to the fourth embodiment.

[0133] like Figure 9 As shown, the solid-state imaging element 1c includes a pixel unit 11c and a pixel driving circuit 12c.

[0134] Multiple pixels SG are arranged in the pixel unit 11c. The pixel unit 11c includes multiple pixels SG and an adder switch (adder transistor RS1, adder transistor RS2, and adder transistor RS3). In the pixel unit 11c, a three-stage adder switch (adder transistor RS1, adder transistor RS2, and adder transistor RS3) is connected between the drain terminal of the reset transistor RQ of the pixel SG and the power supply line VDD. That is, in this embodiment, the adder switch with two or more stages is adder transistor RS1, adder transistor RS2, and adder transistor RS3. In other words, adder transistor RS1, adder transistor RS2, and adder transistor RS3 are equivalent to an adder switch with two or more stages. Further, the adder switch with two or more stages includes adder transistor RS1, adder transistor RS2, and adder transistor RS3.

[0135] An adder transistor RS1 (first adder switch) is configured between connection line CL1 (first connection line) and power line VDD. Connection line CL1 (first connection line) connects the power line VDD side of the reset transistors RQ of N (e.g., 2) pixels SG. Adder transistor RS1 has a source terminal connected to connection line CL1, which is connected to the drain terminals of the two reset transistors RQ, and a drain terminal connected to connection line CL2.

[0136] Adder transistor RS2 (second adder switch) is configured between connection line CL2 (second connection line) and power line VDD. Connection line CL2 (second connection line) connects the power line VDD side of M (e.g., 2) adder transistors RS1. Adder transistor RS2 has a source terminal connected to connection line CL2, which is connected to the drain terminals of the two adder transistors RS1, and a drain terminal connected to connection line CL3.

[0137] An adder transistor RS3 (third adder switch) is configured between connection line CL3 (third connection line) and power line VDD. Connection line CL3 (third connection line) connects the power line VDD side of L (e.g., 2) adder transistors RS2. Adder transistor RS3 has a source terminal connected to connection line CL3, which is connected to the drain terminals of the two adder transistors RS2, and a drain terminal connected to the power line VDD.

[0138] The adder transistor RS3 is configured to add the summed charges of the adder pixel region GA2 via the connection line CL3 and the adder transistor RS2. The adder pixel region GA2 is a region of (N×M) pixels SG (e.g., 2×2=4) connected by the connection line CL2. The conduction state of the adder transistor RS3 is changed according to the control signal RTC3.

[0139] In addition, the adder transistors RS1, RS2, and RS3 are, for example, NMOS transistors.

[0140] The pixel driving circuit 12c changes the conduction state of the reset transistor RQ and the three-stage addition switches (adding transistor RS1, adding transistor RS2, and adding transistor RS3) according to the region of the pixels SG being added. Furthermore, the pixel driving circuit 12c controls the transfer of charge to the charge storage section CS of each pixel SG (controlled by the transfer transistor TQ), controls the reset of the charge storage section CS of each pixel SG to the reset potential (controlled by the reset transistor RQ), and controls the selection of each pixel SG (controlled by the selection transistor SQ).

[0141] The pixel driving circuit 12c outputs a control signal RT. <n>Control signal RTC1, control signal RTC2, control signal RTC3, control signal TX <n>and control signal SL <n>(where n is any integer).

[0142] Figure 10 This diagram illustrates the switching control of pixel regions in the solid-state imaging element 1c of this embodiment.

[0143] like Figure 10 As shown, the pixel driving circuit 12c uses control signals RT, RTC1, RTC2 and RTC3 to control the switching of pixel regions.

[0144] When the pixel driving circuit 12c is performing image capture without addition (for individual pixels SG), it controls the control signals RTC1, RTC2, and RTC3 to be in the High state and outputs a pulse signal to the control signal RT. In this case, the adder transistors RS1, RS2, and RS3 are in the ON state, and the conduction of the reset transistor RQ is controlled by the pulse signal.

[0145] Furthermore, when performing image capture with pixel SG×2 addition (double addition), the pixel driving circuit 12c controls the control signals RT, RTC2, and RTC3 to be fixed in the High state and outputs a pulse signal to the control signal RTC1. In this case, the reset transistor RQ, adder transistor RS2, and adder transistor RS3 are in the ON state, and the conduction of adder transistor RS1 is controlled by the pulse signal.

[0146] Furthermore, when performing pixel SG×4 addition (4x addition) imaging, the pixel driving circuit 12c controls the control signals RT, RTC1, and RTC3 to be fixed in the High state and outputs a pulse signal to the control signal RTC2. In this case, the reset transistor RQ, adder transistor RS1, and adder transistor RS3 are in the ON state, and the conduction of adder transistor RS2 is controlled by the pulse signal.

[0147] Furthermore, when performing image capture at pixel SG×8 summation (8x summation), the pixel driving circuit 12c controls the control signals RT, RTC1, and RTC2 to be fixed in the High state and outputs a pulse signal to the control signal RTC3. In this case, the reset transistor RQ, adder transistor RS1, and adder transistor RS2 are in the ON state, and the conduction of adder transistor RS3 is controlled by the pulse signal.

[0148] Thus, in the solid-state imaging element 1c of this embodiment, by using the reset transistor RQ of each pixel SG and the three-stage addition switch (addition transistor RS1, addition transistor RS2, and addition transistor RS3), it is possible to detect pixel values ​​based on individual pixel SG (non-addition), regions of ×2 addition (addition pixel region GA1 with 2x addition), regions of ×4 addition (addition pixel region GA2 with 4x addition), and regions of ×8 addition (addition pixel region GA3 with 8x addition). That is, the solid-state imaging element 1c of this embodiment achieves the same effect as the solid-state imaging element 1 of the first embodiment described above, and can flexibly switch between individual pixel SG (non-addition), regions of ×2 addition (addition pixel region GA1 with 2x addition), regions of ×4 addition (addition pixel region GA2 with 4x addition), and regions of ×8 addition (addition pixel region GA3 with 8x addition) according to the imaging scene.

[0149] Furthermore, in this embodiment, an example of an adder switch with three levels is described as an example of two or more levels, but this embodiment is not limited to this. An adder switch with n levels (where n is any integer greater than 2) may also be used.

[0150] [Fifth Implementation Method] Next, the solid-state imaging element 1d of the fifth embodiment will be described with reference to the accompanying drawings.

[0151] In the fifth embodiment, a variation in which the addition of pixels SG is performed by skipping one instead of adding adjacent pixels SG will be described.

[0152] Figure 11 This is a block diagram illustrating an example of the solid-state imaging element 1d according to the fifth embodiment.

[0153] like Figure 11 As shown, the solid-state imaging element 1d includes a pixel section 11d and a pixel driving circuit 12d. Furthermore, the solid-state imaging element 1d is, for example, a color image sensor. The solid-state imaging element 1d is capable of detecting color images.

[0154] In the pixel unit 11d, multiple pixels SG are arranged in a two-dimensional matrix to form a light-receiving area. Furthermore, the multiple pixels SG are arranged in a Bayer arrangement using the three primary colors of light (R (red), G (green), and B (blue)). The pixel unit 11d includes multiple pixels SG and addition switches (addition transistor RS1 and addition transistor RS2).

[0155] In this embodiment, connection line CL1 connects two pixels SG by skipping one and connects to adder transistor RS1. That is, connection line CL1 and connection line CL2 are connected in a way that adds non-adjacent pixels to each other. Thus, connection line CL1 connects pixels of the same primary color among the three primary colors of RGB in a way that adds each other.

[0156] Figure 12 This diagram illustrates an example of the Bayer arrangement of RGB pixels in this embodiment.

[0157] like Figure 12 As shown, the multiple pixels SG of the pixel unit 11d are arranged in such a way that R (red) and G1 (green) are alternately arranged on one line, and G2 (green) and B (blue) are alternately arranged on the next line. In this way, in the Bayer arrangement, the same primary colors are arranged in such a way that one pixel SG is skipped.

[0158] In this embodiment, the connecting line CL1 connects two pixels SG by skipping one, thus enabling the addition of pixels SG with the same primary color (e.g., R (red) and R (red), G1 (green) and G1 (green), G2 (green) and G2 (green), B (blue) and B (blue)). Furthermore, in the pixel unit 11d, it is possible to detect pixel values ​​based on individual pixels SG (without addition), regions where the same color is added ×2, and regions where the same color is added ×4.

[0159] Pixel driving circuit 12d is the circuit that drives pixel unit 11d. The basic function and control of pixel driving circuit 12d are the same as those of pixel driving circuit 12 described above. Furthermore, pixel driving circuit 12d is controlled by adding the same primary colors among R (red), G (green) (G1, G2), and B (blue) together. Pixel driving circuit 12d outputs a control signal RT. <n>Control signal RTC1, control signal RTC2, control signal TX <n>and control signal SL <n>(where n is any integer).

[0160] As described above, in this embodiment, connecting lines CL1 (first connecting line) and CL2 (second connecting line) are connected in such a way that non-adjacent pixels in a plurality of pixels SG are added to each other.

[0161] Therefore, the solid-state imaging element 1d of this embodiment can flexibly switch the addition of non-adjacent pixels to each other.

[0162] In addition, in this embodiment, among the multiple pixels SG, the pixels SG of the three primary colors of light are configured in a Bayer arrangement, and the connecting line CL1 is connected in such a way that the same primary colors in the Bayer arrangement are added to each other.

[0163] Therefore, the solid-state imaging element 1d of this embodiment can add the charges of pixels SG to each other according to the same primary color. Thus, in color image detection, for example, it is possible to flexibly switch between individual pixel SG (no addition), ×2 addition, and ×4 addition. For example, when using ×2 addition and ×4 addition, the solid-state imaging element 1d of this embodiment can improve the detection sensitivity of color images.

[0164] Furthermore, in this embodiment, a Bayer-array color image sensor was used as an example of skipping a single pixel SG, but this embodiment is not limited to this. Skipping a non-color pixel SG can also be implemented. Alternatively, multiple levels (e.g., n levels (where n is any integer greater than 2)) can be skipped instead of one level during addition.

[0165] [Sixth Implementation Method] Next, the solid-state imaging element 1e of the sixth embodiment will be described with reference to the accompanying drawings.

[0166] In the sixth embodiment, a variation in which a 3-transistor pixel is used instead of a 4-transistor pixel (pixel SG) will be described.

[0167] Figure 13 This is a block diagram illustrating an example of the solid-state imaging element 1e according to the sixth embodiment.

[0168] like Figure 13 As shown, the solid-state imaging element 1e includes a pixel section 11e and a pixel driving circuit 12e.

[0169] The pixel unit 11e includes multiple pixels SGa (SGa1, SGa2, SGa3, SGa4, ...) and an addition switch (addition transistor RS1, addition transistor RS2). In the pixel unit 11e, for example, the multiple pixels SGa are arranged in a two-dimensional matrix to form a light-receiving area.

[0170] In addition, besides the change from multiple pixels SG to multiple pixels SGa, the pixel unit 11e is similar to... Figure 1 The pixel portion 11 shown is the same. Therefore, a detailed description of the pixel portion 11e is omitted.

[0171] Pixel SGa is a three-transistor pixel comprising a reset transistor RQ acting as a reset switch, a source follower transistor SF converting charge into an electrical signal, and a selection transistor SQ for reading out the electrical signal that selects pixel SGa. Pixel SGa is identical to pixel SG except that it lacks a transmission transistor TQ. Therefore, a detailed description of pixel SGa is omitted here.

[0172] The pixel driving circuit 12e changes the conduction state of the reset transistor RQ and the two or more addition switches (adding transistor RS1, adding transistor RS2) according to the region of the pixels SGa being added. In addition, the pixel driving circuit 12e controls the reset of the charge storage section CS of each pixel SG to the reset potential (control of the reset transistor RQ) and controls the selection of each pixel SG (control of the selection transistor SQ).

[0173] The pixel driving circuit 12e performs the same control as the pixel driving circuit 12 in the first embodiment, except that it outputs control signals RT, RTC1, RTC2 and SL but does not output control signal TX.

[0174] As explained above, the solid-state imaging element 1e of this embodiment includes a plurality of pixels SGa. Pixel SGa is a 3-transistor pixel that includes a reset transistor RQ that acts as a reset switch, a source follower transistor SF that converts charge into an electrical signal, and a selection transistor SQ that reads out the electrical signal of the pixel SG.

[0175] Therefore, the solid-state imaging element 1e of this embodiment can use 3-transistor pixels, and the pixel area can be flexibly changed by adding charges according to the imaging scene. In addition, the solid-state imaging element 1e of this embodiment can achieve charge addition without changing the composition of the pixel SGa by adding an addition switch (addition transistor RS1, addition transistor RS2).

[0176] Furthermore, in this embodiment, an example of applying a 3-transistor pixel to the first embodiment is described. However, similarly, a 3-transistor pixel can be applied to the second to fifth embodiments.

[0177] [Seventh Implementation Method] Next, the solid-state imaging element 1f of the seventh embodiment will be described with reference to the accompanying drawings.

[0178] In the seventh embodiment, a modified example of multiple TAP (tap) pixels that can be allocated and have charge stored in multiple charge storage sections CS will be described.

[0179] Figure 14 This is a block diagram illustrating an example of the solid-state imaging element 1f according to the seventh embodiment.

[0180] like Figure 14 As shown, the solid-state imaging element 1f includes a pixel unit 11f and a pixel driving circuit 12f.

[0181] The pixel unit 11f includes multiple pixels SGb (SGb1, SGb2, SGb3, SGb4, ...) and addition switches (addition transistor RS11, addition transistor RS12, addition transistor RS21, addition transistor RS22). In the pixel unit 11f, for example, the multiple pixels SGb are arranged in a two-dimensional matrix to form a light-receiving area.

[0182] A pixel SGb has multiple charge storage sections CS (e.g., charge storage section CS1 and charge storage section CS2). A pixel SGb is a pixel that can be allocated and store charge in each charge storage section CS. A pixel SGb has one photoelectric conversion element PD and two element groups. Each element group includes a charge storage section CS, a reset transistor RQ, a source follower transistor SF, a transfer transistor TQ, and a select transistor SQ.

[0183] A photoelectric conversion element (PD) is, for example, an embedded photodiode. The PD performs photoelectric conversion on incident light, generating a charge corresponding to the incident light. The PD has an anode terminal connected to a ground power supply line and a cathode terminal connected to the source terminals of two transmission transistors (TQ1 and TQ2).

[0184] The transfer transistor TQ1 is turned on (ON state) by the control signal TX1. As a result, the transfer transistor TQ1 stores the charge generated by the photoelectric conversion element PD in the charge storage section CS1, and transfers the charge to the source follower transistor SF1.

[0185] The transfer transistor TQ2 is turned on (ON state) by the control signal TX2. As a result, the transfer transistor TQ2 stores the charge generated by the photoelectric conversion element PD in the charge storage section CS2, and transfers the charge to the source follower transistor SF2.

[0186] The charge storage section CS1 is a storage section that distributes and stores the charge generated by the photoelectric conversion element PD. The charge storage section CS1 is the floating diffusion section FD1.

[0187] The charge storage section CS2 is a storage section that distributes and stores the charge generated by the photoelectric conversion element PD. The charge storage section CS2 is the floating diffusion section FD2.

[0188] The source follower transistor SF1 is a transistor that converts charge into an electrical signal. The source follower transistor SF1 outputs an electrical signal (voltage) corresponding to the charge stored in the charge storage section CS1 to the selection transistor SQ1.

[0189] The source follower transistor SF2 is a transistor that converts charge into an electrical signal. The source follower transistor SF2 outputs an electrical signal (voltage) corresponding to the charge stored in the charge storage section CS2 to the selection transistor SQ2.

[0190] The selection transistor SQ1 reads out the electrical signal of the charge storage section CS1 of the selection pixel SGb. The selection transistor SQ1 is turned on (ON state) by the control signal SL1. As a result, the selection transistor SQ1 outputs the pixel value (output signal) to the output line.

[0191] The selection transistor SQ2 reads out the electrical signal of the charge storage section CS2 of the selection pixel SGb. The selection transistor SQ2 is turned on (ON state) by the control signal SL2. As a result, the selection transistor SQ2 outputs the pixel value (output signal) to the output line.

[0192] The reset transistor RQ1 (an example of a reset switch) resets the charge storage section CS1 to a predetermined reset potential supplied from the power supply line VDD. The reset transistor RQ1 is turned on (ON state) by the control signal RT1. Thus, the reset transistor RQ1 resets the charge storage section CS1 to the reset potential supplied from the power supply line VDD via the adder switches (adder transistors RS11 and RS21) described later.

[0193] The reset transistor RQ2 (an example of a reset switch) resets the charge storage section CS2 to the predetermined reset potential supplied from the power supply line VDD. The reset transistor RQ2 is turned on (ON) by the control signal RT2. Thus, the reset transistor RQ2 resets the charge storage section CS2 to the reset potential supplied from the power supply line VDD via the adder switches (adder transistors RS12 and RS22) described later.

[0194] The adder switches (adder transistors RS11 and RS21) are switches with two or more stages connected in series between the connecting lines (connecting lines CL11 and CL21) and the power supply line VDD. The connecting lines (connecting lines CL11 and CL21) connect to the power supply line VDD side of the reset transistor RQ1 of a predetermined number of pixels SGb. In this embodiment, an example of a two-stage adder switch is described. By changing the conduction state, the adder switches (adder transistors RS11 and RS21) can change the area of ​​the pixels SGb that adds the charge stored in the charge storage section CS1.

[0195] The adder switches (adder transistors RS12 and RS22) are switches with two or more stages connected in series between the connecting lines (connecting lines CL12 and CL22) and the power line VDD. The connecting lines (CL12 and CL22) connect to the power line VDD side of the reset transistor RQ2 for a specified number of pixels SGb. By changing the conduction state, the adder switches (RS12 and RS22) can change the area of ​​the pixels SGb that adds the charge stored in the charge storage section CS2.

[0196] In addition, in this embodiment, the variable pixel SGb regions are individual pixel SGb (not added), regions that are added by 2 (additive pixel region GA1 with 2 times the addition), and regions that are added by 4 (additive pixel region GA2 with 4 times the addition). The regions that are added by 2 (additive pixel region GA1 with 2 times the addition) are additive pixel region GA11 and additive pixel region GA12.

[0197] The pixel driving circuit 12f is the circuit that drives the pixel unit 11f. The basic functions and control of the pixel driving circuit 12f are the same as those of the pixel driving circuit 12 described above. In addition, in this embodiment, the pixel SGb has two charge storage units CS (charge storage unit CS1 and charge storage unit CS2), and an additional process of distributing and storing charge to each charge storage unit CS is added.

[0198] The pixel driving circuit 12f outputs control signals RT1, RTC1_1, RTC2_1, TX1 and SL1 for the charge storage unit CS1, and control signals RT2, RTC1_2, RTC2_2, TX2 and SL2 for the charge storage unit CS2.

[0199] As explained above, the solid-state imaging element 1f of this embodiment includes a plurality of pixels SGb. Each pixel SGb includes a plurality of charge storage sections CS (e.g., charge storage section CS1 and charge storage section CS2), and is a pixel (a plurality of TAP pixels) that can be allocated and have charge stored in each charge storage section CS. The pixel driving circuit 12f allocates and stores charge to each charge storage section CS.

[0200] Therefore, the solid-state imaging element 1f of this embodiment can use multiple TAP pixels, and the pixel area can be flexibly changed by adding charges according to the imaging scene. In addition, the solid-state imaging element 1f of this embodiment can achieve charge addition without changing the composition of the pixel SGb by adding an addition switch (addition transistor RS11, addition transistor RS12, addition transistor RS21, addition transistor RS22).

[0201] Furthermore, the above embodiment describes an example where there are two charge storage units CS (2TAP), but this embodiment is not limited to this. This embodiment can also be applied to pixels that distribute charge to three or more charge storage units CS.

[0202] Furthermore, in the above embodiment, an example of distributing the charge generated by the photoelectric conversion element PD was described as an example, but this embodiment is not limited to this. This embodiment can also be applied to pixel structures that also include a gate for discharge.

[0203] Furthermore, in the above embodiments, an example applied to the first embodiment was described as an example, but it is not a limitation. Multiple TAP pixels (e.g., pixels SGb) can also be applied to the second to fifth embodiments.

[0204] [Eighth Implementation Method] Next, the distance image camera device 100 of the eighth embodiment will be described with reference to the accompanying drawings.

[0205] In the eighth embodiment, an example of a camera device (distance image camera device 100) using the solid-state imaging element 1f of the seventh embodiment described above will be described.

[0206] Figure 15 This is a block diagram illustrating an example of the distance image camera device 100 according to the eighth embodiment.

[0207] like Figure 15 As shown, the distance image capturing device 100 includes a light source unit 2, a light receiving unit 3, and a distance image processing unit 4. Additionally, in Figure 15 Also shown is the object, or subject OB, for which the distance is measured using the distance image capturing device 100. Furthermore, in this embodiment, as an example of a distance image capturing element, an example using the solid-state imaging element 1f of the seventh embodiment described above will be explained.

[0208] The light source unit 2 irradiates a light pulse PO onto the subject OB. The light source unit 2, under control from the distance image processing unit 4, irradiates the light pulse PO into the space of the photographic object. In the space of the photographic object, there exists a subject OB, the distance of which is measured in the distance image capturing device 100. The light source unit 2 is, for example, a surface-emitting semiconductor laser module such as a vertical cavity surface emitting laser (VCSEL). The light source unit 2 irradiates the subject OB, for example, with a light pulse PO, which is a structured light composed of a plurality of periodically arranged point lights.

[0209] In addition, the light source unit 2 includes a light source device 21 and a diffuser plate 22.

[0210] The light source device 21 is a laser source that emits a near-infrared wavelength (e.g., a wavelength range of 850 nm to 940 nm). This laser becomes a light pulse PO that irradiates the subject OB. The light source device 21 is, for example, a semiconductor laser light-emitting element. The light source device 21 emits pulsed laser light according to the control from the measurement and control unit 43.

[0211] The diffuser plate 22 is an optical component that diffuses the near-infrared laser emitted by the light source device 21 into a surface wide enough to irradiate the subject OB. The pulsed laser light diffused by the diffuser plate 22 is emitted as a light pulse PO and irradiates the subject OB.

[0212] The light-receiving unit 3 receives the reflected light RL from the light pulse PO reflected by the subject OB and outputs a pixel signal corresponding to the received reflected light RL. The subject OB is the object whose distance is measured in the image capturing device 100. The light-receiving unit 3 includes a lens 31 and a solid-state imaging element 1f.

[0213] Lens 31 is an optical lens that guides the incident reflected light RL towards the solid-state imaging element 1f. Lens 31 directs the incident reflected light RL toward the solid-state imaging element 1f. Thus, lens 31 enables the pixel portion 11f of the light-receiving area of ​​the solid-state imaging element 1f to receive the (incident) reflected light RL.

[0214] The solid-state imaging element 1f is an imaging element used in the distance image capturing device 100. The solid-state imaging element 1f includes a pixel section 11f and a pixel driving circuit 12f. The pixel section 11f has a two-dimensional light-receiving area comprising a plurality of pixels SGb. The pixel driving circuit 12f controls each pixel SGb.

[0215] In the pixel SGb of the pixel unit 11f, as described above, there is a photoelectric conversion element PD, a plurality of charge storage units CS (charge storage unit CS1, charge storage unit CS2) corresponding to the photoelectric conversion element PD, and a constituent element for distributing charge to each charge storage unit CS.

[0216] At a predetermined accumulation timing synchronized with the illumination of the light pulse PO, the pixel driving circuit 12f turns on each of the charge accumulation units CS (charge accumulation units CS1 and CS2) and the transmission transistor TQ respectively. As a result, the pixel driving circuit 12f distributes and accumulates charge to each of the charge accumulation units CS (charge accumulation units CS1 and CS2).

[0217] In addition, as described above, the pixel driving circuit 12f switches pixel regions such as single pixel (pixel SG), ×2 addition, and ×4 addition according to the camera scene (measuring scene).

[0218] The distance image processing unit 4 controls the distance image capturing device 100 to calculate the distance to the subject OB. Based on the amount of charge stored in each of the charge storage units CS, the distance image processing unit 4 measures the distance to the subject OB in the measurement space as the measurement distance.

[0219] In addition, the distance image processing unit 4 includes a timing control unit 41, a distance calculation unit 42, and a measurement control unit 43.

[0220] The timing control unit 41, under the control of the measurement control unit 43, controls the timing of various control signals required for measurement. These control signals include, for example, signals controlling the illumination of the light pulse PO, signals distributing and accumulating reflected light RL in multiple charge accumulation units CS, and signals controlling the number of accumulations per frame. The number of accumulations refers to the number of times the process of distributing and accumulating charge in the charge accumulation units CS is repeated. The number of accumulations is a preset number of distributions within a frame period. The product of this number of accumulations and the accumulation time width is the exposure time. The accumulation time width is the time span during each distribution and charge accumulation process for each charge accumulation unit CS to accumulate charge.

[0221] The distance calculation unit 42 outputs distance information calculated from the pixel signal output from the solid-state imaging element 1f, which is then used to calculate the distance to the subject OB. The distance calculation unit 42 calculates the delay time from the illumination pulse PO to the reception of the reflected light RL based on the amount of charge stored in the multiple charge storage units CS. The distance calculation unit 42 calculates the distance to the subject OB based on the calculated delay time.

[0222] The measurement control unit 43 controls the timing control unit 41. For example, the measurement control unit 43 sets the number of times a frame is accumulated and the accumulation time width, and controls the timing control unit 41 in a manner that captures images according to the set content. That is, the measurement control unit 43 sets the frame period and controls the timing control unit 41 in a manner that captures images according to the set content.

[0223] With this configuration, in the distance image camera device 100, the light receiving unit 3 receives the reflected light RL after the near-infrared light pulse PO irradiated by the light source unit 2 to the subject OB is reflected by the subject OB, and the distance image processing unit 4 outputs distance information (distance image) obtained by measuring the distance to the subject OB.

[0224] As described above, the distance image imaging device 100 of this embodiment includes: a light source unit 2 that irradiates light pulses onto the subject OB; a light receiving unit 3 that has the aforementioned solid-state imaging element 1f; and a distance image processing unit 4. The distance image processing unit 4 controls the pixel driving circuit 12f to cause the charge storage units CS to store charge, and calculates the distance to the subject OB based on the amount of charge stored in the charge storage units CS.

[0225] Therefore, the distance image imaging device 100 of this embodiment achieves the same effect as the solid-state imaging element 1f described above, and can flexibly change the pixel area by adding charges according to the imaging scene. Therefore, the influence of noise can be reduced (and the S / N ratio can be improved).

[0226] Furthermore, the present invention is not limited to the embodiments described above, and modifications can be made without departing from the spirit of the present invention.

[0227] For example, in the embodiments described above, the photoelectric conversion element PD is an example of an embedded photodiode that generates and stores charge by photoelectric conversion of incident light. However, the photoelectric conversion element PD is not limited to this, and its construction can be arbitrary. For example, the photoelectric conversion element PD can be a PN photodiode with a structure that combines P-type and N-type semiconductors, or a PIN photodiode with an I-type semiconductor sandwiched between P-type and N-type semiconductors. The photoelectric conversion element PD is not limited to a photodiode. For example, the photoelectric conversion element PD can also be a grating-type photoelectric conversion element.

[0228] Furthermore, in the embodiments described above, examples were given of pixels SG (SGa, SGb) being any one of a 4-transistor pixel, a 3-transistor pixel, and a plurality of TAP pixels (2TAP pixels). However, pixels SG (SGa, SGb) are not limited to these, and pixels with other configurations may also be used as pixels SG (SGa, SGb). For example, pixels SG (SGa, SGb) may also be configured to include a capacitor in the charge storage section CS.

[0229] Furthermore, in the embodiments described above, examples were given where the reset transistor RQ (RQ1, RQ2), source follower transistor SF (SF1, SF2), transfer transistor TQ (TQ1, TQ2), select transistor SQ (SQ1, SQ2), and adder transistors RS1 to RS3 (RS11, RS12, RS21, RS22) are NMOS transistors. However, these transistors are not limited to this; for example, they could also be other transistors such as PMOS transistors.

[0230] Furthermore, in the eighth embodiment described above, an example of using the solid-state imaging element 1f of the seventh embodiment in the distance image capturing device 100 was given. However, the distance image capturing device 100 is not limited to this, and for example, any of the solid-state imaging elements 1 (1a to 1e) in the first to sixth embodiments may also be used. In addition, the capturing device is not limited to a distance image capturing device, and for example, it may also be applied to the capturing device of a digital camera.

[0231] Furthermore, each component of the aforementioned distance image capturing device 100 or pixel driving circuit 12 (12a-12f) has an internal computer system. Moreover, programs for implementing the functions of each component of the aforementioned distance image capturing device 100 or pixel driving circuit 12 (12a-12f) can be recorded on a computer-readable recording medium, allowing the computer system to read and execute the program recorded on the recording medium, thereby performing the processing in each component of the aforementioned distance image capturing device 100 or pixel driving circuit 12 (12a-12f). Here, "allowing the computer system to read and execute the program recorded on the recording medium" includes installing programs in the computer system. The term "computer system" here includes hardware such as an operating system and peripheral devices.

[0232] Additionally, "computer system" can also include multiple computer devices connected via a network of communication lines, including the Internet, WAN, LAN, and dedicated lines. Furthermore, "computer-readable recording media" refers to removable media such as floppy disks, optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard drives built into a computer system. Thus, the recording medium storing programs can also be a non-transitory recording medium such as a CD-ROM.

[0233] Furthermore, the recording medium also includes internal or external recording media accessible from a distribution server for distributing the program. Alternatively, the program may be divided into multiple parts, downloaded at different time intervals, and distributed via different distribution servers for each component assembly included in the image capture device 100 or pixel drive circuits 12 (12a-12f). Moreover, the "computer-readable recording medium" also includes a medium that retains the program for a certain period of time, such as volatile memory (RAM) within a computer system that acts as a server or client when the program is sent via a network. Additionally, the program described above may be a program used to implement the aforementioned functions. Furthermore, it may be a so-called differential file (differential program) capable of implementing the aforementioned functions through combination with a program already recorded in the computer system.

[0234] Alternatively, some or all of the above functions can be implemented as integrated circuits such as LSI (Large Scale Integration). Each of these functions can be processorized individually, or some or all can be integrated and processorized. Furthermore, the method of integrated circuit implementation is not limited to LSI; it can also be implemented using dedicated circuits or general-purpose processors. Additionally, when advancements in semiconductor technology have led to the development of integrated circuit technologies that replace LSI, integrated circuits based on these technologies can also be used.

[0235] Industrial applicability As explained above, according to the present invention, it is possible to suppress the increase in pixel size and to flexibly change the pixel area where charges are added according to the shooting scene.

[0236] Explanation of reference numerals in the attached figures 1, 1a, 1b, 1c, 1d, 1e, 1f… Solid-state imaging element 2…Light Source Section 3…Light-receiving section 4… Distance Image Processing Unit Pixels 11, 11a, 11b, 11c, 11d, 11e, 11f… Pixel driving circuits 12, 12a, 12b, 12c, 12d, 12e, 12f… 21…Light source device 22…diffuser plate 31…lens 41…Timing Control Department 42…Distance Calculation Unit 43… Measurement and Control Department 100… distance image camera device CL1, CL11, CL12, CL2, CL21, CL22, CL3… connecting wires CS, CS1, CS2… Charge accumulation section FD, FD1, FD2... Floating diffuser section GA1, GA11, GA12, GA2... Additive pixel areas OB…subject OL…output line PD… Photoelectric conversion element PO…light pulse RL…reflected light RQ, RQ1, RQ2… Reset transistors RS1, RS11, RS12, RS2, RS21, RS22, RS3… Adder transistor SG, SG1, SG2, SG3, SG4, SGa, SGa1, SGa2, SGa3, SGa4, SGb, SGa1, SGa2, SGa3, SGa4... pixels SQ, SQ1, SQ2… select transistors SF, SF1, SF2... source follower transistors TQ, TQ1, TQ2… Transmission transistors< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A solid-state imaging element, comprising: Multiple pixels, each having a photoelectric conversion element that generates a charge corresponding to incident light, a charge storage section that stores the charge, and a reset switch that resets the charge storage section to a predetermined reset potential supplied from a power line; An adder switch has two or more levels connected in series between the power line and the power line of the reset switch that connects a specified number of pixels. By changing the conduction state, the area of ​​the pixel that adds the charge stored in the charge storage section can be changed. as well as The pixel driving circuit changes the conduction state of the reset switch and the addition switches of level 2 or higher according to the region of the pixels to be added.

2. The solid-state imaging element according to claim 1, wherein, The addition switch of level 2 or above is: A first adder switch is configured between a first connection line connecting the power line side of the reset switch of N pixels and the power line, and is configured to add the charges stored in the N charge storage units via the first connection line and the reset switch, wherein N is an integer greater than or equal to 2; and The second adder switch is configured between the second connecting line connecting the power lines of the M first adder switches and the power line, and is configured to add the additive charges of the N pixel regions (i.e., the adder pixel regions) connected by the first connecting line via the second connecting line and the first adder switch, where M is an integer greater than or equal to 2. The pixel driving circuit changes the conduction state of the reset switch, the first adder switch, and the second adder switch according to the region of the pixels being added.

3. The solid-state imaging element according to claim 2, wherein, The additive pixel regions are connected in a linear fashion, functioning as a linear sensor.

4. The solid-state imaging element according to claim 2, wherein, The first connecting line and the second connecting line are connected in such a way that non-adjacent pixels are added to each other.

5. The solid-state imaging element according to any one of claims 1 to 4, wherein, The pixel is a 4-transistor pixel, which includes a reset transistor as a reset switch, a source follower transistor for converting the charge into an electrical signal, a transfer transistor for transferring the charge to the source follower transistor, and a readout selection transistor for selecting the electrical signal of the pixel.

6. The solid-state imaging element according to any one of claims 1 to 4, wherein, The pixel is a 3-transistor pixel, which includes a reset transistor as a reset switch, a source follower transistor that converts the charge into an electrical signal, and a selection transistor that selects the readout of the electrical signal of the pixel.

7. The solid-state imaging element according to any one of claims 1 to 4, wherein, The pixel has multiple charge storage sections, and each charge storage section can be allocated and store charge. The pixel driving circuit causes the charge to be distributed and stored in each of the charge storage portions.

8. A distance image camera device, comprising: The light source irradiates the subject with light pulses; The light-receiving part includes the solid-state imaging element as described in claim 7; and The distance image processing unit controls the pixel driving circuit to cause each of the charge storage units to accumulate charge, and calculates the distance to the subject based on the amount of charge accumulated in each of the charge storage units.

9. A control method, which is a control method for a solid-state imaging element. The solid-state imaging element includes: Multiple pixels, each having a photoelectric conversion element that generates a charge corresponding to incident light, a charge storage section that stores the charge, and a reset switch that resets the charge storage section to a predetermined reset potential supplied from a power line; and An adder switch has two or more stages connected in series between the connection line connecting the reset switch of a specified number of pixels and the power line. By changing the conduction state, the region of the pixel that adds the charge stored in the charge storage section can be changed. The pixel driving circuit changes the conduction state of the reset switch and the addition switches of level 2 or above according to the region of the pixels being added.

Images