Semiconductor light-receiving element, optical line terminal device, multivaluated intensity modulation transmission / reception device, digital coherent reception

Abstract

This semiconductor light-receiving element (100) is provided with: an n-type InP substrate (1); an n-type semiconductor layer (2) formed on the n-type InP substrate (1); a multiplication layer (3) which is formed on the n-type semiconductor layer (2), has a layer thickness of 40 nm or more and 170 nm or less, and comprises an InAlAs digital alloy structure in which InAs layers and AlAs layers are alternately laminated; a p-type electric field relaxation layer (4) formed on the multiplication layer (3) and comprising InP or InAlAs; and an InGaAs light absorption layer (5) formed on the p-type electric field relaxation layer (4).

Description

Technical Field

[0001] This disclosure relates to semiconductor light-receiving elements, optical line terminal devices, multi-intensity modulation transceivers, digital coherent receivers, fiber optic wireless systems, SPAD sensor systems, and lidar devices. Background Technology

[0002] With the advancement of digital transformation utilizing digital information, communication networks for exchanging digital information and data centers for accumulating and processing data have seen significant development. Optical communication is used in both communication networks and within data centers. In recent years, optical communication has made remarkable progress in terms of speed and capacity. In the development of optical communication, avalanche photodiodes (APDs) are used as receivers to achieve high receiving sensitivity.

[0003] In access networks connecting optical communication users, Passive Optical Networks (PONs) are the primary mode of operation. PON systems originated with G(E)-PON systems transmitting 1-2 Gbps signals, and it is anticipated that 10G-EPON and XG-PON systems transmitting 10 Gbps signals will increase in the future. Furthermore, the ITU-T (International Telecommunication Union Telecommunication Standardization Sector) is exploring 50G-PON systems as the next generation of high-speed PON systems, and it is expected that 50 Gbps-level transmission will become practical in access networks.

[0004] For the semiconductor light-receiving element (APD) used in a PON system, its structure consists of a light-absorbing layer (InGaAs), an electric field mitigation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). By applying a high electric field of approximately 800 kV / cm to the multiplication layer, electrons and holes generated in the light-absorbing layer are multiplied, i.e., ionized. The function of the electric field mitigation layer is to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light-absorbing layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes is expressed as β.

[0005] In an APD, a higher ratio of electron to hole ionization rates results in less excess noise during multiplication and higher receiver sensitivity. Furthermore, a higher electron-to-hole ionization rate ratio leads to a shorter multiplication time in the multiplication layer, thus resulting in a wider bandwidth.

[0006] The electron-hole ionization ratio k is defined by k = β / α. When electrons are injected into the multiplication layer, the smaller the ionization ratio k, the better the performance of the APD. Compound semiconductor materials such as InAlAs or InP are used as the multiplication layer in APDs for optical communication.

[0007] When InAlAs is chosen as the material for the multiplication layer, the difference in ionization rates between electrons and holes becomes larger compared to InP. Furthermore, in InP, the ionization rate of holes is greater than that of electrons, approximately twice that of electrons. On the other hand, when InAlAs is chosen as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, approximately five times that of holes. Therefore, using InAlAs as the multiplication layer further increases the receiving sensitivity, making InAlAs a more suitable material than InP for the multiplication layer of an APD.

[0008] In PON systems, as mentioned above, APDs, as semiconductor light-receiving elements, require wide response bandwidth and high receiving sensitivity. However, unlike PDs, the doubling time in APDs increases with the doubling rate, leading to bandwidth reduction at high doubling rates. Although APDs with InAlAs-based doubling layers for optical communication have wider bandwidths than APDs made of other semiconductor materials, the bandwidth stops at around 20 GHz when the doubling rate is 6 or higher. In other words, the bandwidth of around 37.5 GHz or higher required for 50G-PON systems is difficult to achieve using existing APDs.

[0009] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0099813

[0010] Non-patent literature 1: Jiyuan Zheng et al., “Digital Alloy In AlAs Avalanche Photodiodes”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 36, NO. 17, SEPTEMBER 1, pp. 3580-3585, 2018

[0011] In 50G-PON systems, the response bandwidth of semiconductor light-emitting elements and semiconductor light-receiving elements, the light output of semiconductor light-emitting elements, and the receiving sensitivity of semiconductor light-receiving elements are all insufficient. Therefore, it is advisable to consider setting a digital bandwidth compensation circuit composed of a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the user side.

[0012] Furthermore, in the optical line terminal (OLT), i.e., the receiving device at the central office side, to compensate for the insufficient receiving sensitivity of semiconductor light-receiving elements, a semiconductor optical amplifier (SOA) is required, or an electro-absorption modulated laser diode (EMD) needs to be integrated into the transmitting side of the ONU to increase optical output. However, the power consumption of DSPs and SOAs is very high, which becomes a factor in cost increases. Therefore, there are concerns that the replacement from existing PON systems to 50G-PON systems will not be able to proceed.

[0013] In addition, in existing PON systems other than next-generation high-speed PON systems, increasing the number of branches of the optical signal output from the OLT is being explored to reduce costs. However, in this case, SOA needs to be integrated into the EML on the transmitting side of the OLT or ONU to increase optical output, which leads to problems such as increased power consumption and cost of the transmitter.

[0014] As mentioned above, in order to compensate for the limitations of semiconductor light-receiving elements in terms of receiving sensitivity and response bandwidth, transceivers that integrate expensive and power-consuming DSPs and SOAs into ONUs or OLTs have been designed. However, problems such as increased power consumption and increased cost still exist. Summary of the Invention

[0015] This disclosure was made to eliminate the aforementioned problems, and its purpose is to obtain a semiconductor light-receiving element with high receiving sensitivity, wide response bandwidth, and low power consumption.

[0016] The semiconductor light-receiving element disclosed herein includes:

[0017] InP substrate;

[0018] An n-type semiconductor layer is formed on the InP substrate described above;

[0019] The multiplication layer is formed on the above-mentioned n-type semiconductor layer, with a thickness of 40 nm or more and 170 nm or less, and is composed of a digital alloy structure;

[0020] A p-type electric field mitigation layer is formed on top of the aforementioned multiplication layer; and

[0021] An InGaAs light-absorbing layer is formed on top of the aforementioned p-type electric field mitigation layer.

[0022] The optical line terminal device disclosed herein includes:

[0023] The aforementioned semiconductor light-receiving element;

[0024] The optical combiner / demultiplexer directs the optical signal onto the aforementioned semiconductor light-receiving element;

[0025] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element;

[0026] A clock data recovery circuit, connected to the aforementioned amplifier circuit, recovers the clock and data from the amplified electrical signal; and

[0027] The forward error correction circuit is connected to the aforementioned clock data recovery circuit to correct errors in the clock and data.

[0028] The multi-value intensity modulation transceiver device disclosed herein includes:

[0029] The aforementioned semiconductor light-receiving element receives light signals modulated by multi-value intensity.

[0030] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element;

[0031] An analog-to-digital converter circuit, connected to the aforementioned amplifier circuit, converts the amplified electrical signal into a digital signal; and

[0032] A digital signal processing circuit is connected to the aforementioned analog-to-digital conversion circuit to process the aforementioned digital signals.

[0033] The fiber optic wireless system disclosed herein has the following features:

[0034] The light source emits analog-modulated light signals;

[0035] The aforementioned semiconductor light-receiving element receives the aforementioned optical signal that has been analog-modulated;

[0036] The transmission path transmits the analog electrical signal output from the aforementioned semiconductor light-receiving element to the antenna; and

[0037] The antenna is connected to the aforementioned transmission path and radiates the aforementioned analog electrical signal as a radio wave signal.

[0038] The digital coherent receiving device disclosed herein includes:

[0039] The aforementioned semiconductor light-receiving element;

[0040] A polarization separator separates the polarization of a polarization-multiplexed optical signal that has been modulated in terms of intensity and phase.

[0041] A 90-degree mixer performs wavelength division and multiplexing on the optical signal output from the aforementioned polarization separator; and

[0042] The digital signal processing circuit is connected to the aforementioned 90-degree mixer to process digital signals.

[0043] The SPAD sensor system disclosed herein includes:

[0044] The SPAD sensor is composed of the aforementioned semiconductor light-receiving element;

[0045] The quenching circuit repeatedly applies voltages above and below the breakdown voltage to the aforementioned SPAD sensor; and

[0046] The optoelectronic measurement circuit measures the electrical signal output from the aforementioned SPAD sensor.

[0047] The lidar device disclosed herein includes:

[0048] The light source emits light in a pulsed pattern;

[0049] The aforementioned semiconductor light-receiving element receives light emitted from the aforementioned light source that is reflected back by the object;

[0050] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor photosensitive element; and

[0051] The ranging circuit calculates the distance based on the electrical signal amplified by the aforementioned amplifier circuit.

[0052] According to the semiconductor light-receiving element disclosed herein, since the multiplication layer is constructed from a digital alloy and the thickness of the multiplication layer is set within a specified range, a semiconductor light-receiving element with high receiving sensitivity and wide response bandwidth can be obtained.

[0053] According to the optical line terminal device, multi-intensity modulation transceiver device, digital coherent receiver device, fiber optic wireless system, SPAD sensor system, and lidar device disclosed herein, since the semiconductor light-receiving element disclosed herein is used as the semiconductor light-receiving element, the device and system can achieve excellent performance. Attached Figure Description

[0054] Figure 1This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0055] Figure 2 This is a cross-sectional view showing the element structure of an end-face incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0056] Figure 3 This is a diagram showing the electric field dependence of the dead zone of electrons in the InAlAs multiplication layer.

[0057] Figures 4A to 4C It is a graph representing the ionization rate of electrons and holes.

[0058] Figure 5 This is a graph showing the ionization ratio and the layer thickness dependence of the tunneling current multiplication layer.

[0059] Figures 6A to 6D This is a graph showing the ionization rate in the multiplication layer and the electric field mitigation layer. Figure 6A This indicates the case of a random alloy structure multiplication layer. Figure 6B This indicates the case of digital alloy construction multiplication layers. Figure 6C This represents the case of a digital alloy multiplication layer where local disorder occurs. Figure 6D It is a graph representing the ionization rate when a thick electric field mitigation layer and a digital alloy multiplication layer are combined.

[0060] Figure 7 This is a diagram showing the structure of a comparative example of an optical line terminal unit (ONU and OLT) for a 50G-PON system.

[0061] Figure 8 This is a diagram showing the structure of the ONU in a 50G-PON system that uses the semiconductor light-receiving element according to Embodiment 1.

[0062] Figure 9 This is a diagram showing the structure of the OLT in a 50G-PON system that uses the semiconductor light-receiving element according to Embodiment 1.

[0063] Figure 10 This is a diagram showing the structure of a 50G-PON system and an OLT / ONU as a comparative example.

[0064] Figure 11 This is a diagram illustrating the structure of the multi-branch 50G-PON system and the OLT / ONU involved in Embodiment 1.

[0065] Figure 12 This is a diagram showing the structure of the 50G-PON system and OLT / ONU involved in Embodiment 1.

[0066] Figure 13 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 2.

[0067] Figure 14 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 2.

[0068] Figure 15 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 3.

[0069] Figure 16 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 4.

[0070] Figure 17 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 5.

[0071] Figure 18 This is a cross-sectional view showing the structure of other elements of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 5.

[0072] Figure 19 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 6.

[0073] Figure 20 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 7.

[0074] Figure 21 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 8.

[0075] Figure 22 This is a diagram showing the structure of the multi-value intensity modulation transceiver device according to Embodiment 9.

[0076] Figure 23A and Figure 23B This is a diagram showing the received waveform of the multi-value intensity modulation transceiver device according to Embodiment 9.

[0077] Figure 24A and Figure 24B This diagram illustrates the operation of the PD during highlight input.

[0078] Figure 25 This diagram illustrates the actions of the APD during highlight input.

[0079] Figure 26 It is a graph representing the residence time of electrons and holes in the various materials that make up the multiplication layer.

[0080] Figure 27 This is a diagram showing the structure of the fiber optic wireless system according to Embodiment 10.

[0081] Figure 28 This is a diagram showing the structure of a fiber optic wireless system as a comparative example.

[0082] Figure 29 This is a diagram showing the structure of the digital coherent receiving device according to Embodiment 11.

[0083] Figure 30A This is a diagram showing the waveforms of a digital coherent receiving device used as a comparative example. Figure 30B This is a diagram showing the waveform of the digital coherent receiving device according to Embodiment 11.

[0084] Figure 31 This is a diagram showing the structure of the SAPD sensor system according to Embodiment 12.

[0085] Figure 32A This is a graph showing the waveforms of the SAPD sensor system used as a comparative example. Figure 32B This is a diagram showing the waveforms of the SAPD sensor system according to Embodiment 12.

[0086] Figure 33 It is a graph showing the difference between the quenching electric field of each structure in the multiplication layer and the electric field of the Geiger mode.

[0087] Figure 34 This is a diagram showing the structure of the lidar device according to Embodiment 13.

[0088] Figure 35A This is a diagram showing the received waveform of the APD of a lidar device used as a comparative example. Figure 35B This is a diagram showing the received waveform of the APD of the lidar device according to Embodiment 13. Detailed Implementation

[0089] Implementation Method 1

[0090] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 1>

[0091] Figure 1 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element 100 according to Embodiment 1. Additionally, Figure 2This is a cross-sectional view showing the element structure of an end-face incident type APD, which is an example of a semiconductor light-receiving element 110 according to Embodiment 1.

[0092] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 1>

[0093] The semiconductor light-receiving element 100 according to Embodiment 1 is formed on an n-type InP substrate 1, with a carrier concentration of 1 to 5 × 10⁻⁶. 18 cm -3 The InAlAs multiplication layer 3 (hereinafter referred to as InAlAs digital alloy construction multiplication layer 3) is composed of an n-type InAlAs buffer layer 2 with a thickness of 0.1–1.0 μm, an InAlAs multiplication layer 3 composed of alternating layers of i-type AlAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm) and i-type InAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm), and a carrier concentration of 0.1–50 × 10⁻⁶. 17 cm -3 The substrate comprises a p-type InP electric field mitigation layer 4 with a thickness of 10–70 nm, an i-type InGaAs light absorption layer 5 with a thickness of 0.1–2.0 μm, an i-type InAlGaAs / InAlAs gradient layer 6, a p-type InP window layer 7 with a thickness of 0.1–3.0 μm, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is sometimes also referred to as an n-type semiconductor layer.

[0094] The semiconductor light-receiving element 110 involved in Embodiment 1 has the same layer structure as the semiconductor light-receiving element 100, but at least on the end face where the incident light 90 is incident, an Fe-doped semi-insulating InP buried layer 20 is also formed.

[0095] The n-type InAlAs buffer layer 2 can be any structure, either random alloy or digital alloy. Silicon (Si) is most suitable as the n-type dopant for the n-type InAlAs buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InAlAs buffer layer 2 to the i-type InAlAs digital alloy multiplication layer 3, which would lead to disorder in the digital alloy structure. Here, disorder refers to the phenomenon where the compositions of the layers in the digital alloy structure mix with each other, resulting in a random alloy structure with an average composition.

[0096] As described above, the InAlAs digital alloy multiplication layer 3 is composed of semiconductor layers stacked alternately in the order of AlAs layers (2 atomic layers thick, approximately 0.6 nm) and InAs layers (2 atomic layers thick, approximately 0.6 nm). However, the thickness of the AlAs and InAs layers can be in the range of more than 2 atomic layers and less than 6 atomic layers, respectively. The reason for setting it to less than 6 atomic layers is that it is desired that the stacked structure of AlAs and InAs layers does not function as a quantum well structure.

[0097] Furthermore, the number of atomic layers in each layer of the InAlAs digital alloy multiplication layer 3 is preferably more than 2 atomic layers and less than 4 atomic layers, with 2 atomic layers being the most suitable. This is because the thinner the atomic layer of each layer, the greater the reduction in ionization ratio k brought about by the digital alloy structure.

[0098] Considering the compatibility with the InAlAs constituting the n-type InAlAs buffer layer 2, it is preferable to increase the thickness of only the first AlAs layer of the InAlAs digital alloy multiplication layer 3 to 3 atomic layers or more. Alternatively, the InAlAs digital alloy multiplication layer 3 can be stacked by alternating InAs layers and AlAs layers in sequence.

[0099] As an example, the InAlAs digital alloy multiplication layer 3 has an i-type conductivity and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 Below. However, the conductivity type of the InAlAs digital alloy multiplication layer 3 can also be a carrier concentration of 5 × 10⁻⁶. 18 cm -3 The following are p-type or n-type.

[0100] To increase the dead space effect in the InAlAs digital alloy multiplication layer 3, the thickness of the InAlAs digital alloy multiplication layer 3 is preferably in the range of 40 nm or more and 170 nm or less. However, considering the typical 20% deviation in layer thickness during the fabrication of the semiconductor light-receiving element 100, the thickness of the InAlAs digital alloy multiplication layer 3 is preferably in the range of 50 nm or more and 140 nm or less.

[0101] In addition to the multiplication layer composed of InAlAs digital alloy structures, InAlGaAs digital alloy structures formed by alternating layers of InAlGa(1-y)As (layer thickness of 2-6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness of 2-6 atomic layers, Al composition ratio Z) can also be used as multiplication layers of this disclosure. Furthermore, digital alloy structures composed of a material system with added antimony (Sb), namely InAlAsSb, can also be used as multiplication layers of this disclosure.

[0102] As described above, the preferred carrier concentration of the p-type InP electric field mitigation layer 4 is 0.1–50 × 10⁻⁶. 17 cm -3 The layer thickness is in the range of 10 nm or more and 70 nm or less. Examples of p-type dopants that can be used as p-type InP electric field mitigation layers 4 include beryllium (Be), zinc (Zn), and carbon (C).

[0103] Furthermore, the electric field mitigation layer does not necessarily have to be composed of p-type InP. That is, the electric field mitigation layer can also be a p-type InAlAs digital alloy structure or a p-type InAlAs random alloy structure. However, if the dopants contained in the p-type InP electric field mitigation layer 4 diffuse into the adjacent InAlAs digital alloy structure multiplication layer 3, the digital alloy structure may become disordered and transform into a random alloy structure of InAlAs. As mentioned above, the InAlAs digital alloy structure multiplication layer 3 is thin, about 100 nm, and therefore has the potential to be significantly affected by disordering due to dopant diffusion. Therefore, in the case of the p-type InP electric field mitigation layer 4, Be, which is difficult to diffuse, is most suitable as the p-type dopant. On the other hand, when p-type InAlAs is used as the constituent material of the electric field mitigation layer, Zn is most suitable as the p-type dopant.

[0104] A layer with a thickness of less than 0.1 μm, composed of InAlGaAs or InGaAsP with a band gap value between the two, is disposed between the p-type InP electric field mitigation layer 4 and the i-type InGaAs light absorption layer 5, thereby preventing the accumulation of electrons and holes at the heterojunction interface. The InGaAs light absorption layer can also be n-type or p-type in terms of conductivity.

[0105] Alternatively, for the same purpose, a layer with a thickness of less than 0.1 μm, composed of InAlGaAs or InGaAsP having an intermediate bandgap value between the i-type InGaAs light-absorbing layer 5 and the p-type InAlAs layer, can be provided between them. The p-type InGaAs contact layer 8 has an outer periphery with an area smaller than that of the multiplication layer.

[0106] exist Figure 1 In one example of the structure of the semiconductor light-receiving element 100 shown, an InAlGaAs / InAlAs gradient layer 6 is formed by repeatedly and alternately stacking two different types of InAlGaAs layers on top of an i-type InGaAs light-absorbing layer 5. The conductivity type of the InAlGaAs / InAlAs gradient layer 6 can also be p-type or n-type. Alternatively, a p-type InAlAs window layer can be used instead of the p-type InP window layer 7.

[0107] <Operating Principle of the Semiconductor Photoreceiving Element According to Embodiment 1>

[0108] The operating principle of the semiconductor light-receiving element 100 according to Embodiment 1 will be explained below.

[0109] If a wide-bandwidth APD of around 37.5GHz or higher can be achieved, then a next-generation high-speed PON system can be realized even without using DSP and SOA. For PDs, which are relatively easy to implement with wide bandwidth, their response bandwidth is limited by:

[0110] (1) RC time constant (R is the resistance of the component, C is the capacitance of the component)

[0111] (2) Carrier travel time (the time that electrons or holes travel in the depletion layer).

[0112] In APD, it is further affected by:

[0113] (3) Limitation on doubling time (the time for electrons and holes to chain-like multiplication within the doubling layer, which increases proportionally to the multiplication rate).

[0114] While the bandwidth of 37.5 GHz can be achieved in PD, a doubling time is required in APD. Therefore, it is difficult to achieve the desired bandwidth if the doubling rate is increased. The doubling time TM is represented by the following equations (1) to (3).

[0115] Doubling time TM = Doubling rate M / GB product (1)

[0116] GB product = 1 / (2πNkτav) (2)

[0117] Right now,

[0118] The doubling time TM = 2πNkMτav (3).

[0119] Here, the GB product is the product of the multiplication rate and the bandwidth, k is the ionization ratio, N is a coefficient that slightly depends on the ionization ratio k, and τav is the average travel time of electrons and holes in the multiplication layer. Therefore, the multiplication time TM can be shortened by reducing the ionization ratio k. In particular, to realize a high-speed PON system, the multiplication time TM needs to be close to zero, that is, the ionization ratio k needs to be close to zero.

[0120] To achieve a zero ionization ratio k, various compound semiconductors have been proposed as materials for the multiplication layer. Furthermore, to further reduce the ionization ratio k, a digital alloy structure (also known as ALSL: Atomic Layer Super Lattice) has been proposed, consisting of alternating layers of different semiconductor compositions stacked at intervals of approximately 1 to 6 atomic layers. However, without structural optimization, it is difficult to achieve a zero ionization ratio k in the digital alloy structure. The digital alloy structure has already been described in Non-Patent Document 1.

[0121] Therefore, in order to reduce the ionization rate ratio k of the digital alloy structure, the inventors fabricated an APD with a digital alloy structure multiplication layer, which uses alternating and repeated stacking of 2-atom-layer InAs and 2-atom-layer AlAs multiplication layers. They analyzed the multiplication characteristics and found that the distance that charge carriers travel in the multiplication layer until ionization occurs is longer than that of an APD with a random alloy structure of InAlAs composed of conventional bulk crystals. This distance traveled by charge carriers in the multiplication layer until ionization is also referred to as the dead space.

[0122] Regarding the length of the dead region (hereinafter referred to as the dead region length), since holes are longer than electrons, in the case of a random alloy structure of InAlAs composed of a typical bulk crystal, if the thickness of the multiplication layer is reduced to about tens of nm, holes cannot be ionized, thus the ionization ratio k decreases. However, when the thickness of the multiplication layer is already reduced to about tens of nm, a higher electric field needs to be applied to the multiplication layer to obtain the desired multiplication rate, thus generating new problems such as an increase in leakage current, such as tunneling current. That is, if the tunneling current increases, the noise generated in the APD will increase. On the other hand, the inventors' analysis found that in the digital alloy structure, the dead region is unusually large compared to the random alloy structure, so even for multiplication layers with a thickness of more than 100 nm, the ionization ratio k is equal to zero (k = 0).

[0123] In other words, the inventors have discovered for the first time that by constructing the multiplication layer of an APD using a digital alloy structure, tunneling current can be suppressed and the ionization ratio k = 0 can be achieved. Specifically, it was found that in the multiplication layer constructed using the digital alloy structure of this disclosure, when the layer thickness is below 170 nm, the ionization ratio k decreases sharply, especially when the layer thickness of the multiplication layer is in the range of 60–130 nm, the dead zone effect is significantly improved. That is to say, the inventors have demonstrated that by applying the multiplication layer constructed using the digital alloy structure of this disclosure, an ionization ratio k = 0, which is impossible to achieve in multiplication layers constructed using random alloy structures or in multiplication layers constructed using thick digital alloy structures, can be achieved. To date, no research institution has reported on the thinning of the multiplication layer of an APD with a digital alloy structure multiplication layer, and the reduction in ionization ratio k is more significant compared to the thinning of the multiplication layer of an APD constructed using existing materials.

[0124] <Method for manufacturing a semiconductor light-receiving element according to Embodiment 1>

[0125] As an example of the semiconductor light-receiving element 100 according to Embodiment 1, the surface-incidence APD can be implemented on an n-type InP substrate 1 using methods such as Metal-Organic Vapor Phase Epitaxy (MOVPE) or Molecular Beam Epitaxy (MBE). Hereinafter, a method for manufacturing the semiconductor light-receiving element 100 according to Embodiment 1 will be described.

[0126] Using the MOVPE or MBE method, crystals with a thickness of 0.1–1 μm and a carrier concentration of 1–5 × 10⁻⁶ are grown on an n-type InP substrate 1. 18 cm -3 n-type InAlAs buffer layer 2.

[0127] An InAlAs digital alloy multiplication layer 3 is crystallized on an n-type InAlAs buffer layer 2. That is, crystals are grown alternately on the n-type InAlAs buffer layer 2 in the order of AlAs layer (2 atomic layers thick, about 0.6 nm) and InAs layer (2 atomic layers thick, about 0.6 nm), thereby forming the InAlAs digital alloy multiplication layer 3.

[0128] On top of the InAlAs digital alloy multiplication layer 3, a crystal growth layer with a thickness of 10 nm or more and 70 nm or less and a carrier concentration of 0.1–50 × 10⁻⁶ is formed. 17 cm -3 p-type InP electric field mitigation layer 4.

[0129] Above the p-type InP electric field mitigation layer 4, an i-type InGaAs light-absorbing layer 5, with a crystal thickness of 0.1 μm or more and 2 μm or less, is sequentially grown; an i-type InAlGaAs / InAlAs graded layer 6, with a thickness of 0.1 μm or more and 3 μm or less, is a p-type InP window layer 7; and a p-type InGaAs contact layer 8. The InAlGaAs / InAlAs graded layer can be either n-type or p-type. Alternatively, a p-type InAlAs window layer can be used instead of the p-type InP window layer 7.

[0130] After crystal growth is completed, a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back side of the n-type InP substrate 1.

[0131] exist Figure 1 In the case of the surface-incident type APD shown, incident light 90 is incident from a direction perpendicular to the i-type InGaAs light-absorbing layer 5. The diameter of the light-receiving part of the APD is in the case of a circle, or the size of the long side is in the case of a rectangle, in the case of a rectangle. A non-reflective coating (not shown) is applied to the incident surface of the APD.

[0132] exist Figure 2 In the case of the end-face incident type APD shown, incident light 90 is incident from a direction parallel to the i-type InGaAs light-absorbing layer 5. From a reliability point of view, the end face portion is covered by an insulating film, an organic film, or a semiconductor layer. Figure 2 In the end-face incident type APD shown, an Fe-doped semi-insulating InP buried layer 20 is formed on the end face. The thickness of the Fe-doped semi-insulating InP buried layer 20 is in the range of 100 nm to 5 μm relative to the incident direction.

[0133] In the APD according to Embodiment 1, Ti and Au are used as electrode materials for the p-type electrode 32. In the APD according to Embodiment 1, the electric field mitigation amount is adjusted so that tunnel breakdown does not occur at a voltage lower than avalanche breakdown. In the APD according to Embodiment 1, the operating voltage is 15V to 90V, and the electric field within the multiplication layer during APD operation is 500kV / cm to 900kV / cm. Furthermore, in the APD according to Embodiment 1, the electric field of the i-type InGaAs light-absorbing layer 5 is set to 300kV / cm or less. The APD according to Embodiment 1 is used in a multiplication rate range of 3 to 30, but when operating in Geiger mode, the multiplication rate is 100 or more.

[0134] <Function of the semiconductor light-receiving element in Implementation Method 1>

[0135] The following is about Figure 1 and Figure 2The function of the APD described in Embodiment 1 will be explained. The inventors discovered that if the multiplication layer is constructed using digital alloys as in Embodiment 1, the dead zone effect, i.e., the reduction effect of the ionization ratio k, is enhanced. Figure 3 This is a graph representing the electric field dependence of the dead zone of electrons in an InAlAs multiplication layer. The inventors analyzed the electron multiplication characteristics in the digital alloy-structured multiplication layer, and the results are as follows: Figure 3 The diagrams clearly demonstrate that the InAlAs digital alloy structured multiplication layer of this disclosure has a longer dead zone compared to existing InAlAs random alloy structured multiplication layers.

[0136] Figures 4A to 4C These are graphs representing the ionization rates of electrons and holes, respectively. Figure 4A This indicates the ionization of electrons. Figure 4B This indicates the ionization of holes. Figure 4C This is a graph showing the ionization rate after thinning the multiplication layer. In existing InAlAs random alloy multiplication layers, such as... Figure 3 As shown in the chart, the dead zone length is about 45nm, so the thickness of the multiplication layer needs to be reduced to about 1.5 times the dead zone (about 70nm). However, if the multiplication layer is reduced to 70nm, the electric field of the multiplication layer becomes higher, and the noise increases with the sharp increase of the tunneling current, making it difficult to obtain an APD with good receiver sensitivity.

[0137] On the other hand, in the InAlAs digital alloy structure multiplication layer 3 of the APD involved in Embodiment 1, such as Figure 3 As shown in the graph, when the reciprocal of the applied electric field is 1.47 × 10⁻⁶, -6 At the cm / V condition, the dead zone length is about 85nm. Therefore, even if the layer thickness of the multiplication layer is about 1.5 times the dead zone thickness (about 130nm), the ionization ratio k can be close to zero. Therefore, in the APD involved in Implementation 1, the influence of tunneling current is small.

[0138] Furthermore, in InAlAs digital alloy multiplication layers, the dead zone exhibits a high dependence on the applied electric field, with the reciprocal of the applied electric field being 1.27 × 10⁻⁶. -6 In the case of cm / V, such as Figure 3 As shown in the chart, the dead zone length is approximately 50 nm, therefore the multiplication layer needs to be thinned to 75 nm. That is, the layer thickness of the InAlAs digital alloy-constructed multiplication layer should be thicker than that of the InAlAs random alloy-constructed multiplication layer.

[0139] Figure 5This is a graph showing the layer thickness dependence of the ionization ratio and tunneling current multiplication layer. The inventors fabricated APDs with InAlAs digital alloy structured multiplication layers and InAlAs random alloy structured multiplication layers, respectively, and measured the ionization ratio k, and combined with... Figure 5 The measurement results from documents 1 and 2 recorded in the document are plotted together. Figure 5 middle.

[0140] in, Figure 5 References 1 and 2 are described below.

[0141] (1) Reference 1

[0142] Yuan Yuan, et al "Temperature dependence of the ionizationcoefficients of InAlAs and AlGaAs digital alloys" pp. 794, Vol. 6,No. 8 / August2018 / Photonics Research

[0143] (2) Reference 2

[0144] Wenyang Wang, et al "Characteristics of thin InAlAs digital alloyavalanche photodiodes" pp. 3841, Vol. 46,No. 16 / 15 August 2021 / Optics Letters

[0145] like Figure 5 As shown, in InAlAs random alloy-structured multiplication layers, the reduction in ionization ratio k due to the dead zone cannot be achieved unless the layer thickness is below 80 nm. On the other hand, if the layer thickness is reduced to below 80 nm, the tunneling current increases sharply, leading to tunnel breakdown. A layer thickness around 60 nm barely balances the reduction in ionization ratio k and the limitation on tunneling current, but the thickness margin is only a few nm, making stable fabrication of APDs extremely difficult. Furthermore, the ionization ratio k is also large, at 0.12. In other words, in existing InAlAs random alloy-structured multiplication layers, it is difficult to apply the reduction in ionization ratio k resulting from thinning to APDs.

[0146] On the other hand, in the InAlAs digital alloy multiplication layer disclosed herein, as the inventors have discovered, due to the large dead zone, therefore... Figure 5As shown, as the multiplication layer gradually thins, the ionization ratio k decreases below 0.1 starting from a thickness of 170 nm. Here, the ionization ratio k is calculated based on the measured value of the multiplication noise and is the minimum ionization ratio within the range of 1 to 10 multiplication rates. With the same ionization ratio k, the layer thickness of the InAlAs digital alloy multiplication layer is more than twice that of the InAlAs random alloy multiplication layer.

[0147] like Figure 5 As shown in the chart, in an APD with a pn junction diameter of 20 μm, if the lower limit of the layer thickness of the multiplication layer with a tunneling current of 1 μA is set to 40 nm, then the layer thickness range of 40 nm to 170 nm is the most suitable range for InAlAs digital alloy construction multiplication layers. The layer thickness within the above range can be fabricated with sufficiently high reproducibility.

[0148] For the layer thickness of the InAlAs digital alloy multiplication layer, which can fully achieve the reduction effect of ionization ratio k through the dead zone effect, the reciprocal of the applied electric field is 1.47 × 10⁻⁶. -6 In the case of cm / V, it is considered to be about twice the dead zone length, therefore, as Figure 3 As shown, given that the dead zone length is 85 nm, twice the dead zone length, i.e., 170 nm, is a suitable value as the upper limit of the layer thickness of the InAlAs digital alloy construction multiplication layer.

[0149] Furthermore, in the construction of InAlAs digital alloy multiplication layers, in order to control the ionization ratio k below 0.05, according to Figure 5 According to the chart, the thickness of the multiplication layer is preferably 150 nm or less. Furthermore, to satisfy the requirements of a tunneling current of 1 μA or less and an ionization ratio k of approximately zero, a thickness of 60 nm or more and 130 nm or less for the multiplication layer is most suitable. When setting a margin of 10 nm for APD fabrication, a thickness of 70 nm or more and 120 nm or less for the multiplication layer is preferred.

[0150] In addition, the length of the dead zone is determined according to Figure 3The dead zone length is preferably 50 nm to 90 nm. The ratio of the dead zone length to the thickness of the multiplication layer is preferably 29% or more, obtained by dividing the minimum dead zone length of 50 nm by the maximum multiplication layer thickness of 170 nm. As the ratio increases, the ionization ratio k decreases, but it cannot exceed 100%. This is because if the ionization ratio k exceeds 100%, multiplication will no longer occur. Therefore, the ratio of the dead zone length to the thickness of the multiplication layer is preferably 29% or more and less than 100%. Furthermore, when an example of a DA-APD with a multiplication layer thickness of 120 nm was fabricated, experiments showed that 42% (= 50 nm / 120 nm) to 75% (= 90 nm / 120 nm) is the most suitable range for the ratio of the dead zone length to the thickness of the multiplication layer.

[0151] The inventors investigated why existing InAlAs random alloy multiplication layers cannot achieve an ionization ratio k=0, but the InAlAs digital alloy multiplication layer disclosed herein can achieve an ionization ratio k=0.

[0152] If the dead zone length of electrons is set as De and the dead zone length of holes is set as Dh, then the conditions for achieving an ionization ratio k = 0 are expressed by the following equations (4) and (5). Among them, equation (4) represents the condition for the difference in dead zone lengths, and equation (5) represents the condition for tunneling current.

[0153] Dhe=Dh―De>0 (4)

[0154] Dh>Tmin (5)

[0155] Here, Dhe is the difference in dead zone length between holes and electrons. Tmin is the minimum layer thickness of the multiplication layer where the tunneling current becomes sufficiently small to not affect the noise level; the thicker the multiplication layer, the lower the tunneling current. Regarding the condition of the dead zone length difference, as follows... Figure 4C As shown, if the thickness of the multiplication layer is below the dead zone length of the hole, the hole will no longer multiply, and the ionization rate ratio k = 0. Therefore, it is set as in the above formula (5).

[0156] In the case of InAlAs random alloy construction of multiplication layers, according to Figure 3 and Figure 5 It can be seen that as the multiplication layer gradually thins, the ionization ratio k begins to decrease at values ​​of De ~ 40 nm and Dh ~ 80 nm. When the pn junction diameter is 20 μm and the tunneling current is set to below 100 nA, the minimum layer thickness Tmin = 90 nm. Therefore, the random alloy structure of InAlAs does not meet the tunneling current condition, and thus the ionization ratio k = 0 cannot be achieved.

[0157] On the other hand, in the case of InAlAs digital alloy construction of the multiplication layer, as the multiplication layer gradually thins, the ionization ratio k begins to decrease at values ​​of De ~ 80 nm and Dh ~ 170 nm. With a pn junction diameter of 20 μm and the tunneling current set to below 100 nA, the minimum layer thickness Tmin = 90 nm. Therefore, there exists a multiplication layer thickness that satisfies the condition of ionization ratio k = 0. Regarding the minimum layer thickness Tmin, it is the same in both InAlAs digital alloy construction and InAlAs random alloy construction of the multiplication layer, since the band gap remains unchanged.

[0158] Specifically, in the case of a random alloy structure, De is approximately 40 nm and Dh is approximately 80 nm. In contrast, the inventors discovered that in the case of a digital alloy structure, De is approximately 80 nm and Dh is approximately 170 nm.

[0159] In the InAlAs digital alloy multiplication layer, the difference in lattice constant between InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm), which constitute the superlattice, is 6.55%, which is very large. Therefore, during the fabrication process, dopants, i.e., impurities, from the electric field mitigation layer may diffuse into the InAlAs digital alloy multiplication layer, resulting in disorder within the multiplication layer.

[0160] Figures 6A to 6D This is a graph showing the ionization rate in the multiplication layer and the electric field mitigation layer. Figure 6A This refers to the case of InAlAs random alloy structure multiplication layers. Figure 6B This refers to the case of InAlAs digital alloy construction of multiplication layers. Figure 6C This represents the case where local disorder occurs in the InAlAs digital alloy structure multiplication layer. Figure 6D This is a graph showing the ionization rate when a thick electric field mitigation layer and an InAlAs digital alloy multiplication layer are combined. (Compared to...) Figure 6A Compared to the InAlAs random alloy structure multiplication layer shown, Figure 6B The InAlAs digital alloy multiplication layer shown has a long dead zone length, but in the InAlAs digital alloy multiplication layer where local disorder occurs due to the diffusion of dopants from the electric field mitigation layer, such as... Figure 6C As shown, the dead zone length becomes shorter.

[0161] To avoid the effects of disorder in the construction of InAlAs digital alloy multiplication layers, the selection of the electric field mitigation layer material, as well as the dopant selection and doping concentration, are important. The impurity diffusion equation is represented by the following equation (6).

[0162] dN / dt = D(d 2 N / d 2x)-F (6)

[0163] In equation (6), N is the impurity concentration, t is time, D is the diffusion constant, x is the position, and F is the external force acting on diffusion. Materials used as the electric field mitigation layer include InP, InAlAs random alloy structures, and InAlAs digital alloy structures. Additionally, p-type dopants used as the electric field mitigation layer include Be and Zn. Considering p-type dopants, a combination of a Be-doped p-type InP electric field mitigation layer and an InAlAs digital alloy multiplication layer is preferred. This is because, in addition to having a small diffusion constant D, Be also forms a potential barrier with the InAlAs digital alloy multiplication layer. This potential barrier is equivalent to F in equation (6).

[0164] In the event of a deviation in the thickness of the electric field mitigation layer, to prevent an increase in the deviation of the electric field mitigation amount (i.e., the product of layer thickness and carrier concentration), the preferred carrier concentration for the electric field mitigation layer is 2 × 10⁻⁶. 18 cm -3 Below. When InAlAs is used as the constituent material of the electric field mitigation layer, Zn doping is most suitable, with a carrier concentration of 2×10⁻⁶. 18 cm -3 The following is most suitable. Furthermore, if the impurity concentration becomes higher than 2 × 10⁻⁶... 18 cm -3 If this increases the amount of inactive impurities, diffusion is more likely to occur; therefore, the carrier concentration must be 5 × 10⁻⁶. 18 cm -3 the following.

[0165] The electric field mitigation amount ΔE is represented by the following equation (7).

[0166] ΔE=W·q·N / ε (7)

[0167] With a constant electric field mitigation amount ΔE, increasing the carrier concentration in the electric field mitigation layer requires reducing the layer thickness inversely proportional to the carrier concentration. Here, W is the layer thickness of the electric field mitigation layer, q is the elementary charge, N is the carrier concentration in the electric field mitigation layer, and ε is the dielectric constant.

[0168] If the carrier concentration N in the electric field mitigation layer becomes 5 × 10 18 cm -3 With a density of approximately 10 nm, the thickness of the electric field mitigation layer becomes approximately 10 nm. To prevent the shortening of the dead zone length due to impurity diffusion into the multiplication layer, the carrier concentration of the electric field mitigation layer is controlled at 5 × 10⁻⁶. 18 cm -3 The following is a summary. Additionally, the electric field mitigation layer requires a thickness of at least 10 nm.

[0169] On the other hand, such as Figure 6D As shown, if the thickness of the electric field mitigation layer is more than 1.5 times the dead zone length of the electric field mitigation layer, then multiplication occurs within the electric field mitigation layer. Figure 3 As shown, in the random alloy structure, the dead zone length is less than 45 nm, therefore the thickness of the random alloy electric field mitigation layer needs to be less than 70 nm. On the other hand, in the InAlAs digital alloy structure, the dead zone length is less than 85 nm, therefore the thickness of the digital alloy electric field mitigation layer needs to be less than 130 nm.

[0170] also, Figures 6A to 6D The lengths of the dead zones shown are the dead zone lengths ( Figure 6A ) < Dead Zone ( Figure 6D ) < Dead Zone ( Figure 6C ) < Dead Zone ( Figure 6B The relationship between ).

[0171] <Effects of the semiconductor light-receiving element according to Embodiment 1>

[0172] First, the first effect of the semiconductor light-receiving element according to Embodiment 1 will be quantitatively explained below.

[0173] If the bandwidth limitation caused by the RC time constant is set as frc, the bandwidth limitation caused by the carrier travel time is set as ftr, and the bandwidth limitation caused by the doubling time is set as fm, then the 3dB bandwidth fc of the existing APD is represented by the following equation (8).

[0174] fc = 1 / ((1 / frc)) 2 + (1 / ftr) 2 + (1 / fm) 2 ) 0.5 (8)

[0175] On the other hand, for the 3dB bandwidth fc of the APD with the InAlAs digital alloy structure multiplication layer involved in Embodiment 1, since the ionization ratio k is close to zero, it can be expressed by the following equation (9) only by the RC time constant and the carrier travel time, according to equations (1), (2) and (3).

[0176] fc = 1 / ((1 / frc)) 2 + (1 / ftr) 2 ) 0.5 (9)

[0177] In equation (9), the carrier travel time ftr is the sum of the travel time in the light absorption layer and the travel time in the multiplication layer.

[0178] The RC time constant is inversely proportional to the sum of the thickness of the light absorption layer and the thickness of the multiplication layer, while it is directly proportional to the travel time. Therefore, equation (9) has a maximum value. That is, it becomes the maximum bandwidth when frc = ftr. If we substitute frc = ftr, then equation (9) is expressed by the following equation (10).

[0179] fc=ftr / √2 (10)

[0180] In addition, the 3dB bandwidth ftr, which is determined by the travel time, is represented by the following equation (11).

[0181] ftr=3.5Vav / (2πWt) (11)

[0182] In equation (11), Vav is the average saturation travel velocity of electrons and holes, and Wt is the sum of the thicknesses of the light-absorbing layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35 × 10⁻⁶. 6 cm / s. Additionally, if the thickness of the multiplication layer is 100 nm and the thickness of the light-absorbing layer is 400 nm, then Wt = 500 nm.

[0183] If Vav = 5.35 × 10 6 Substituting cm / s and Wt = 500nm into equation (11), ftr = 59.6GHz. Furthermore, substituting into equation (10), the 3dB bandwidth of the APD having the InAlAs digital alloy structure multiplication layer according to Embodiment 1 becomes 42.2GHz. Therefore, through the above research, it is clear that the APD having the InAlAs digital alloy structure multiplication layer 3 according to Embodiment 1 can meet the bandwidth requirement of 37.5GHz for a 50G-PON system. In the following description of devices, systems, etc., the APD having the InAlAs digital alloy structure multiplication layer according to this disclosure will be referred to as the DA-APD of this disclosure.

[0184] Figure 7This is a structural diagram showing the optical line termination device (OLT) 250 of a 50G-PON system as a comparative example. The optical line termination device 250 as a comparative example includes: a forward error correction circuit (FEC) 251, a driver amplifier 252, a light source 253, a wavelength division multiplexing (WDM) 254, a digital signal processing circuit (DSP) 255, an analog-to-digital converter (ADC) 256, a burst mode transimpedance amplifier (TIA) 257, and a conventional APD 258.

[0185] Figure 8 This is a structural diagram showing the optical line termination device (OLT) 260 of the 50G-PON system according to Embodiment 1. The optical line termination device 260 includes: FEC 261, driver amplifier 262, light source 263, WDM 264, CDR 265 (Clock Data Recovery: CDR) as a clock data recovery circuit, limiting amplifier 266, burst mode transimpedance amplifier TIA 267, and DA-APD 268 of this disclosure.

[0186] Figure 9 This is a structural diagram showing the optical line termination device (ONU) 270 of the 50G-PON system according to Embodiment 1. The optical line termination device 270 includes: WDM 271, light source 272, driver amplifier 273, FEC 274, DA-APD 275 of this disclosure, TIA 276, limiting amplifier 277, and CDR 278.

[0187] like Figure 7 As shown in the optical line termination device (OLT) 250 of the 50G-PON system as a comparative example, the 50G-PON system as a comparative example requires digital bandwidth compensation, i.e., DSP 255. On the other hand, in the 50G-PON system using the DA-APD of this disclosure, digital bandwidth compensation is not required. As a result, it is possible to omit... Figure 8 The optical line terminal device 260 shown and Figure 9 The DSPs in each structure of the optical line termination device 270 shown can thus reduce power consumption and cost.

[0188] Next, the second effect of the semiconductor light-receiving element according to Embodiment 1 will be explained.

[0189] To achieve multi-branching and SOA omission in PON systems, it is necessary to improve the receiver's SN ratio and increase receiving sensitivity. For example, if one optical demultiplexer is added to increase the number of branches compared to the current situation, the optical quantity will be halved, so the SN ratio needs to be improved by at least 3dB. The SN ratio of a receiver using an APD is expressed by the following equation (12).

[0190] SN ratio = Iph 2 ·M 2 / (2q(Iph+Id)M) 2 ·F·B+4Kb·T·Ft·B / Rt) (12)

[0191] In equation (12), Iph represents the photocurrent of the APD, M represents the multiplication rate, q represents the unit charge, Id represents the multiplied dark current, F represents the excess noise figure of the APD, B represents the bandwidth, Kb represents the Boltzmann constant, T represents the absolute temperature, Ft represents the noise figure of the amplifier, and Rt represents the input resistance. The left-hand side of the denominator represents the shot noise of the APD, and the right-hand side of the denominator represents the thermal noise of the amplifier.

[0192] To simplify equation (12), it is assumed that when Id is much smaller than Iph and the SN ratio is the maximum multiplication rate, the shot noise term of the APD is equal to the thermal noise term of the amplifier. When the thermal noise term of the amplifier is replaced by the shot noise term of the APD, the SN ratio is expressed by the following equation (13).

[0193] SN ratio = Iph / (4q·F·B) (13)

[0194] In addition, the excess noise coefficient F is obtained by the following equation (14).

[0195] F=M(1-(1-k)·((M-1) 2 / M 2 ))) (14)

[0196] As mentioned above, with existing InAlAs random alloyed multiplication layers, it is difficult to achieve thinning to the point of exhibiting a dead zone effect (~70 nm) due to the influence of tunneling current, thus there are no examples of its application in APDs. Therefore, for InAlAs multiplication layers that have not undergone thinning, the ionization ratio k is set to 0.2 for system design. With an ionization ratio k = 0.2 and a multiplication rate of 12x, the excess noise figure F = 3.9.

[0197] On the other hand, in the 50G-PON system according to Embodiment 1, the APD with an InAlAs digital alloy structure as the multiplication layer, namely the DA-APD of this disclosure, is used as a semiconductor photodetector. In the case of the InAlAs digital alloy structure multiplication layer of this disclosure, the dead zone effect functions even when the layer thickness is 100 nm or more, and therefore it can be applied to an APD. In this case, when the ionization ratio k = 0 and the multiplication rate is 12 times, the excess noise figure F = 1.9. Therefore, the excess noise is approximately half that of conventional APDs. As a result, if the DA-APD of this disclosure is applied, the signal-to-noise ratio is improved by 3 dB.

[0198] In a typical 50G-PON system, inserting a single-stage 2-way splitter to increase the number of branches increases the loss by 3dB. Therefore, by using the DA-APD disclosed herein as a semiconductor light-receiving element, it is possible to insert an additional stage of splitter in a 50G-PON system.

[0199] Figure 10 This diagram illustrates the structure of a 50G-PON system 280 as a comparative example, and its OLT / ONU. The OLT of the 50G-PON system 280 includes: FEC251, driver amplifier 252, light source 253, WDM254, DSP255, ADC256, burst-mode transimpedance amplifier TIA257, and the conventional APD258. The ONU of the 50G-PON system 280 includes: FEC251, driver amplifier 252, light source 253, WDM254, DSP255, ADC256, TIA257a, and the conventional APD258.

[0200] Figure 11 This diagram illustrates the structure of the 50G-PON system 282 and the OLT / ONU according to Embodiment 1. The OLT of the 50G-PON system 282 includes: FEC 261, driver amplifier 262, light source 263, WDM 264, DSP 265a, ADC 266a, burst-mode transimpedance amplifier TIA 267, and the DA-APD 268 of this disclosure. The OLT of the 50G-PON system 282 includes: FEC 261, driver amplifier 262, light source 263, WDM 264, DSP 265a, ADC 266a, TIA 267a, and the DA-APD 268 of this disclosure.

[0201] for Figure 10 The 50G-PON system 280 shown as a comparative example has 32 branches. By applying the DA-APD of this disclosure, such as Figure 11As shown in Embodiment 1 of the 50G-PON system 282, the number of branches is doubled to 64, thus enabling a breakthrough improvement. Furthermore, in PON systems other than the 50G-PON system 282, the number of branches can also be doubled, thereby reducing the drive current of the transmitter's laser.

[0202] Figure 12 This diagram illustrates the structure of the 50G-PON system 284 and the OLT / ONU according to Embodiment 1. The OLT of the 50G-PON system 284 includes: a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of this disclosure, a burst-mode transimpedance amplifier TIA 276, a limiting amplifier 277, and a CDR 278. The ONU of the 50G-PON system 284 includes: a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of this disclosure, a TIA 276a, a limiting amplifier 277, and a CDR 278.

[0203] In the 50G-PON system 280, used as a comparative example, SOA was also investigated in the ONU and OLT, which serve as optical line termination devices, to compensate for insufficient sensitivity. However, as... Figure 12 As with the 50G-PON system 284 described in Embodiment 1, an ONU and an OLT can be configured even without using SOA.

[0204] The effects of the semiconductor light-receiving element involved in this disclosure will be further explained.

[0205] The DA-APD disclosed herein has an InAlAs digital alloy multiplication layer. By controlling the thickness of the multiplication layer within a specified range, the ionization rate ratio k becomes zero, thereby making the multiplication time in equation (1) approximately zero. As a result, even with an increase in the multiplication rate, the response bandwidth of the APD does not deteriorate. That is, in the DA-APD of this disclosure, similar to existing PDs, the bandwidth is limited only by the RC time constant and the carrier travel time. Therefore, the wide bandwidth required for 50G-PON systems can be achieved, enabling reception even without DSP-based digital bandwidth compensation.

[0206] Furthermore, if the ionization ratio k is close to zero, excess noise that degrades receiver sensitivity is suppressed, thus eliminating the need for SOA to amplify the optical signal. Moreover, even in PON systems other than 50G-PON systems, more branches can be implemented than before. As a result, lower cost and lower power consumption are achieved in PON systems.

[0207] <Effects of Implementation Method 1>

[0208] As described above, the semiconductor light-receiving element according to Embodiment 1 has a digital alloy structure multiplication layer with a layer thickness controlled within a specified range, thus achieving the effect of obtaining a semiconductor light-receiving element with high reliability, wide bandwidth, and excellent low noise characteristics.

[0209] Implementation Method 2

[0210] Figure 13 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of the semiconductor light-receiving element 120 according to Embodiment 2. Additionally, Figure 14 This is a cross-sectional view showing the element structure of an end-face incident type APD, which is an example of a semiconductor light-receiving element 130 according to Embodiment 2.

[0211] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 2>

[0212] The semiconductor light-receiving element 120 according to Embodiment 2 consists of an n-type InP substrate 1 and carriers sequentially formed on the n-type InP substrate 1 with a carrier concentration of 1 to 5 × 10⁻⁶. 18 cm -3 Furthermore, the InAlAs digital alloy multiplication layer consists of: 2) an n-type InAlAs buffer layer with a thickness of 0.1–1.0 μm; 3) an InAlAs digital alloy multiplication layer composed of alternating layers of i-type AlAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm) and i-type InAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm); and 4) a carrier concentration of 0.1–50 × 10⁻⁶. 17 cm -3 4. A p-type InP electric field mitigation layer with a thickness of 10–70 nm; 5. An i-type InGaAs light-absorbing layer with a thickness of 0.1–2.0 μm; 6. An i-type InAlGaAs / InAlAs graded layer; 7. A layer with a thickness of 0.1–3.0 μm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The following structure comprises an n-type InP window layer 11, a p-type diffusion region 15 disposed within the n-type InP window layer 11, a p-type InGaAs contact layer 8 disposed above the p-type diffusion region 15, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also referred to as an n-type semiconductor layer.

[0213] Figure 14 The semiconductor light-receiving element 130 according to Embodiment 2 shown consists of an Fe-doped semi-insulating InP substrate 1a, an n-type InP conductive layer 2a sequentially formed on the Fe-doped semi-insulating InP substrate 1a, and a carrier concentration of 1 to 5 × 10⁻⁶. 18 cm-3 Furthermore, the InAlAs digital alloy multiplication layer consists of: 2) an n-type InAlAs buffer layer with a thickness of 0.1–1.0 μm; 3) an InAlAs digital alloy multiplication layer composed of alternating layers of i-type AlAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm) and i-type InAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm); and 4) a carrier concentration of 0.1–50 × 10⁻⁶. 17 cm -3 4. A p-type InP electric field mitigation layer with a thickness of 10–70 nm; 5. An i-type InGaAs light-absorbing layer with a thickness of 0.1–2.0 μm; 6. An i-type InAlGaAs / InAlAs graded layer; 7. A layer with a thickness of 0.1–3.0 μm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The following is a configuration consisting of an n-type InP window layer 11, a p-type diffusion region 15 disposed within the n-type InP window layer 11, a p-type InGaAs contact layer 8 disposed above the p-type diffusion region 15, an n-type electrode 31a formed on the surface side of the n-type InP conductive layer 2a, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InP conductive layer 2a may also be composed of n-type InGaAs. Furthermore, the n-type InAlAs buffer layer 2 and the n-type InP conductive layer 2a are also referred to as n-type semiconductor layers.

[0214] The semiconductor light-receiving elements 120 and 130 according to Embodiment 2 differ from the semiconductor light-receiving elements 100 and 110 according to Embodiment 1 in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and a p-type diffusion region 15 is provided in the n-type InP window layer 11. The n-type InP window layer 11 of the semiconductor light-receiving elements 120 and 130 has a thickness of 0.1 μm or more and 3 μm or less, and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 Below. Alternatively, the n-type InP window layer 11 can also use InAlAs, or a stacked structure of InP and InAlAs, to replace InP.

[0215] The p-type diffusion region 15 is formed by selectively diffusing p-type dopants such as Zn locally in either the solid or gas phase. The carrier concentration of the p-type diffusion region 15 is 5 × 10⁻⁶. 17 cm -3 The end of the p-type diffusion region 15 can also be located at a depth up to the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs / InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light-absorbing layer 5. Furthermore, in Figure 13 and Figure 14In the device configuration shown, the p-type diffusion region 15 has a depth reaching the i-type InAlGaAs / InAlAs gradient layer 6. A p-type InGaAs contact layer 8 is disposed above the p-type diffusion region 15.

[0216] exist Figure 13 In the surface-incident type APD shown as an example of a semiconductor light-receiving element 120, an n-type electrode 31 is provided on the back side. On the other hand, in Figure 14 In the surface-incident type APD shown as an example of a semiconductor light-receiving element 130, an n-type electrode 31a is provided on the surface side. That is, in the semiconductor light-receiving element 130, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a. After crystal growth, each semiconductor layer above the n-type InP conductive layer 2a is locally removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2a. In the semiconductor light-receiving element 130, a p-type InP substrate or an n-type InP substrate can also be used instead of the Fe-doped semi-insulating InP substrate 1a.

[0217] <Function of the semiconductor light-receiving element involved in Implementation Method 2>

[0218] exist Figure 1 In the mesa-type structure of the semiconductor light-receiving element 100 shown as an example of the surface-incident type APD according to Embodiment 1, the side portion of the multiplication layer to which the electric field is applied is exposed to the outside, and therefore is prone to deterioration. In particular, when the multiplication layer 3 is constructed using InAlAs digital alloy, each layer of the InAlAs digital alloy multiplication layer 3 is subjected to high strain, and therefore dislocation defects and disorder are prone to occur from the exposed portion toward the inside, which may result in an undesirable situation such as a shortened dead zone length.

[0219] Furthermore, as with the semiconductor light-receiving elements 100 and 110 of Embodiment 1, when a multiplication layer with a thinned InAlAs digital alloy structure is applied, the electric field is tens of times higher than that of the existing InAlAs random alloy structure, which may result in a shorter lifespan as a semiconductor light-receiving element due to the influence of the side surface.

[0220] On the other hand, in such Figure 13 When the p-type diffusion region 15 is provided as in the semiconductor light-receiving element 120 shown, since the portion of the InAlAs digital alloy structure multiplication layer 3 under which an electric field is applied, i.e. the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, the InAlAs digital alloy structure multiplication layer 3, where each layer is a high strain layer, achieves the effect of preventing the deterioration of the dead zone length.

[0221] However, in such Figure 13 In the case where the p-type diffusion region 15 is formed by thermal diffusion, as shown in the semiconductor light-receiving element 120, the heat treatment temperature reaches a high temperature of 400°C or higher during the diffusion process, which easily leads to disordering in the InAlAs digital alloy multiplication layer 3. Furthermore, if Zn diffuses into the n-type InP window layer 11, components with fast diffusion rates and voids generated by Zn diffusion reach the InAlAs digital alloy multiplication layer 3, causing disordering. In particular, if cross-diffusion occurs with the p-type dopant in the p-type InP electric field mitigation layer 4, it may promote disordering in the InAlAs digital alloy multiplication layer 3.

[0222] Therefore, in the semiconductor light-receiving elements 120 and 130 according to Embodiment 2, by using Be-doped p-type InP to the p-type InP electric field mitigation layer 4, the diffusion of Be into the InAlAs digital alloy structure multiplication layer 3 is suppressed, and the intrusion of Zn and voids into the InAlAs digital alloy structure multiplication layer 3 due to mutual diffusion is prevented, thereby achieving the effect of preventing the disordering of the InAlAs digital alloy structure multiplication layer 3.

[0223] Therefore, in the semiconductor light-receiving elements 120 and 130 according to Embodiment 2, even if high-temperature heat treatment is performed in the diffusion process to allow Zn diffusion during the formation of the p-type diffusion region 15, disordering of the InAlAs digital alloy multiplication layer 3 can be prevented, and thus, for example, Figure 6C The dead zone length shown is shortened, while maintaining... Figure 6B The state of having a long dead zone as shown. As a result, in the semiconductor photoreceiving elements 120 and 130 according to Embodiment 2, although Zn diffusion is performed in order to form the p-type diffusion region 15, the ionization ratio k can be kept at approximately zero.

[0224] <Effects of Implementation Method 2>

[0225] According to Embodiment 2, although Zn diffusion is performed during the formation of the element structure to form a p-type diffusion region, the disordering of the InAlAs digital alloy structure multiplication layer can be prevented. Therefore, the ionization ratio k can be kept approximately zero, resulting in a semiconductor light-receiving element with high reliability, wide bandwidth, and excellent low noise characteristics.

[0226] Implementation Method 3

[0227] Figure 15 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element 140 according to Embodiment 3.

[0228] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 3>

[0229] As an example of the semiconductor light-receiving element 140 according to Embodiment 3, the surface incident APD is characterized in that, based on the element structure of the surface incident APD as an example of the semiconductor light-receiving element 120 according to Embodiment 2, a separation groove 17 is further provided along the outer periphery of the p-type diffusion region 15 formed in the n-type InP window layer 11.

[0230] The depth of the separation groove 17 is preferably in the range of 2 μm or more and 5 μm or less. Furthermore, the opening width of the separation groove 17 is preferably in the range of 0.5 μm or more and 100 μm or less. The bottom of the separation groove 17 reaches at least to the InAlAs digital alloy multiplication layer 3. Furthermore, in Figure 15 The diagram shows an example of the separation trench 17 reaching the n-type InAlAs buffer layer 2. The separation trench 17 can be formed by either dry etching or wet etching. However, a method that combines dry etching with excellent depth control to remove the damage layer caused by dry etching is preferred.

[0231] The interior of the separation tank 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18, which is an insulating film composed of an oxide film such as SiN or SiO2. The surface protective film 18 also serves as a non-reflective coating for the light-receiving part. The thickness of the surface protective film 18 is preferably in the range of 50 nm or more and 5000 nm or less. Alternatively, the surface protective film 18 can also be an organic film such as benzocyclobutene (BCB).

[0232] <Function of the semiconductor light-receiving element involved in Implementation Method 3>

[0233] When using an InAlAs digital alloy structure as a multiplication layer, the layers of the InAlAs digital alloy structure are subjected to high strain, making them prone to disorder if external stress is applied. Therefore, as with the semiconductor photoreceiving element 140 according to Embodiment 3, by providing a separation trench 17 along the outer periphery of the p-type diffusion region 15, stress affecting the entire wafer during the manufacturing process can be mitigated. Furthermore, even in the individual semiconductor photoreceiving elements 140, the presence of the separation trench 17 mitigates stress, thus reducing stress concentration at the central light-receiving portion of the semiconductor photoreceiving element 140. Since the InAlAs digital alloy multiplication layer 3 is exposed in the separation trench 17, it is preferable to cover the surface of the separation trench 17 with the aforementioned surface protective film 18. Since a high electric field is not applied to the separation trench 17, it will not become a starting point for degradation.

[0234] As described above, in the semiconductor light-receiving element 140 of Embodiment 3, even if a high-temperature heat treatment is performed during the diffusion process to allow Zn diffusion in order to form the p-type diffusion region 15, disordering of the InAlAs digital alloy multiplication layer 3 can be prevented, and therefore, for example, Figure 6C The dead zone length shown is shortened, while maintaining... Figure 6B This results in a long dead zone, as shown. As a result, even with Zn diffusion during the manufacturing process, the ionization ratio k can be maintained at approximately zero.

[0235] Furthermore, stress is mitigated by the separation groove 17 during the operation of the semiconductor light-receiving element 140, so disorder will not occur even after long-term use of the semiconductor light-receiving element 140. That is, in the semiconductor light-receiving element 140 of Embodiment 3, high reliability such as maintaining wide bandwidth and low noise over a long period of time can be achieved.

[0236] <Effects of Implementation Method 3>

[0237] According to the semiconductor light-receiving element of Embodiment 3, although Zn diffusion is performed to form the p-type diffusion region 15 during the formation of the element structure, the disordering of the InAlAs digital alloy structure multiplication layer can be prevented. Therefore, the ionization ratio k can be kept at approximately zero, and the stress can be mitigated by the presence of the separation groove. Thus, a semiconductor light-receiving element with high reliability, wide bandwidth and excellent low noise characteristics can be obtained.

[0238] Implementation Method 4

[0239] Figure 16 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element 150 according to Embodiment 4.

[0240] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 4>

[0241] As an example of the semiconductor light-receiving element 140 according to Embodiment 3, the surface-incident type APD receives light from the surface side. In contrast, as an example of the semiconductor light-receiving element 150 according to Embodiment 4, the back-incident type APD is characterized by having an opening 33 provided by removing a portion of the n-type electrode 31b on the back side, and incident light onto the n-type InP substrate 1 exposed in the opening 33. That is, an opening 33, which serves as the incident region for the incident light 90, is provided on the back side of the n-type InP substrate 1 opposite to the p-type electrode 32.

[0242] For the back-illuminated APD, which is an example of the semiconductor light-receiving element 150 according to Embodiment 4, similar to the semiconductor light-receiving element 140 according to Embodiment 3, even if a high-temperature heat treatment is performed in the diffusion process to allow Zn diffusion during the formation of the p-type diffusion region 15, the disordering of the InAlAs digital alloy multiplication layer 3 can be prevented, and therefore, for example, as... Figure 6C The dead zone length shown is shortened, while maintaining... Figure 6B The state shown has a long dead zone length.

[0243] Furthermore, compared to a surface-incident APD like semiconductor photodetector 120, a back-incident APD like semiconductor photodetector 150 can form a smaller area of ​​the p-type diffusion region 15, thus further reducing the stress generated during p-type diffusion and further preventing disordering of the InAlAs digital alloy multiplication layer 3. As a result, even though Zn diffusion is performed during the formation of the device structure, disordering of the InAlAs digital alloy multiplication layer 3 can be prevented, thus maintaining the ionization ratio k at approximately zero and further reducing stress. Therefore, a semiconductor photodetector with high reliability, wide bandwidth, and excellent low-noise characteristics can be obtained.

[0244] <Effects of Implementation Method 4>

[0245] According to the semiconductor light-receiving element of Embodiment 4, since the element structure is configured as a back-incident type APD, the area of ​​the p-type diffusion region can be formed smaller compared with the surface-incident type APD. Therefore, the ionization ratio k can be kept at approximately zero, and stress can be further mitigated. Thus, a semiconductor light-receiving element with high reliability, wide bandwidth and excellent low noise characteristics can be obtained.

[0246] Implementation Method 5

[0247] Figure 17 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of the semiconductor light-receiving element 160 according to Embodiment 5. Additionally, Figure 18 This is a cross-sectional view showing the other element configuration of a surface-incident type APD, which is an example of the semiconductor light-receiving element 170 involved in Embodiment 5.

[0248] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 5>

[0249] The semiconductor light-receiving element 160 according to Embodiment 5 is formed on an n-type InP substrate 1, with a carrier concentration of 1 to 5 × 10⁻⁶. 18 cm -3 Furthermore, the InAlAs digital alloy multiplication layer consists of: 2) an n-type InAlAs buffer layer with a thickness of 0.1–1.0 μm; 3) an InAlAs digital alloy multiplication layer composed of alternating layers of i-type AlAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm) and i-type InAs layers (as an example, with a layer thickness of 2 atoms, approximately 0.6 nm); and 4) a carrier concentration of 0.1–50 × 10⁻⁶. 17 cm -3 The substrate comprises a p-type InP electric field mitigation layer 4 with a thickness of 10–70 nm, an i-type InGaAs light-absorbing layer 5 with a thickness of 0.1–2.0 μm, an i-type InAlGaAs / InAlAs gradient layer 6, an n-type InP window layer 11 with a thickness of 0.1–3.0 μm, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also referred to as an n-type semiconductor layer.

[0250] The semiconductor light-receiving element 160 according to Embodiment 5 differs from the semiconductor light-receiving element 100 according to Embodiment 1 in that, in the semiconductor light-receiving element 160, the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed as a mesa, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25. The n-type InP window layer 11 only needs to have a thickness of 50 nm or more, but to avoid prolonging the carrier travel time, a thickness of 200 nm or less is preferred. Furthermore, the conductivity type of the n-type InP window layer 11 can be undoped instead of n-type. In the case of n-type, the carrier concentration is preferably 5.0 × 10⁻⁶. 17 cm -3 the following.

[0251] The method for manufacturing the semiconductor light-receiving element 160 according to Embodiment 5 is characterized in that: a p-type InAlAs conductive layer 25 is crystal-grown on an n-type InP window layer 11 by a method such as MOCVD, and after crystal-growing a p-type InGaAs contact layer 8, a portion of the light-receiving part is left, and the p-type InAlAs conductive layer 25 is removed.

[0252] The thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less. To reduce device resistance, the carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, i.e., 5.0 × 10⁻⁶. 17 cm -3 The above. The p-type InAlAs conductive layer 25 can also be a stacked structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs, to replace p-type InAlAs.

[0253] in addition, Figure 17 The semiconductor light-receiving element 160 shown has an n-type electrode 31 disposed on the back side, and in contrast, in Figure 18 In the semiconductor light-receiving element 170 shown, an n-type electrode 31a is provided on the surface side. That is, in the semiconductor light-receiving element 170, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2a are locally removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2a. A p-type InP substrate or an n-type InP substrate can also be used instead of the Fe-doped semi-insulating InP substrate 1a.

[0254] <Function of the semiconductor light-receiving element according to Embodiment 5>

[0255] The function of the semiconductor light-receiving elements 160 and 170 according to Embodiment 5 will be explained below.

[0256] When forming the p-type InAlAs conductive layer 25 under applied voltage, with Figure 14 Compared to the semiconductor light-receiving element 120 according to Embodiment 2, since it does not undergo a p-type diffusion process accompanied by heat treatment at temperatures above 400°C, it can prevent disordering of the InAlAs digital alloy multiplication layer 3, and therefore will not, for example, Figure 6C The dead zone length shown is shortened, while maintaining... Figure 6B This results in a long dead zone, as shown. As a result, the ionization ratio k can be kept approximately zero.

[0257] <Effects of Implementation Method 5>

[0258] As described above, the semiconductor light-receiving element according to Embodiment 5, similar to the semiconductor light-receiving element according to Embodiment 2, has the region of the multiplication layer directly below the light-receiving portion to which a high electric field is applied separated from the side of the element, thus achieving high reliability. Therefore, a semiconductor light-receiving element with high reliability, wide bandwidth, and excellent low noise characteristics can be obtained.

[0259] Implementation Method 6

[0260] Figure 19 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element 180 according to Embodiment 6.

[0261] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 6>

[0262] As an example of the semiconductor light-receiving element 180 according to Embodiment 6, the surface incident APD is characterized in that, based on the element structure of the surface incident APD as an example of the semiconductor light-receiving element 160 according to Embodiment 5, a separation groove 17 is further provided along the outer periphery of the p-type InAlAs conductive layer 25.

[0263] The depth of the separation groove 17 is preferably in the range of 2 μm or more and 5 μm or less. The opening width of the separation groove 17 is preferably in the range of 0.5 μm or more and 100 μm or less. The bottom of the separation groove 17 reaches at least the InAlAs digital alloy structure multiplication layer 3. Furthermore, in Figure 19 The diagram shows an example of the separation trench 17 reaching the n-type InAlAs buffer layer 2. The separation trench 17 can be formed by either dry etching or wet etching. However, a method that combines dry etching with excellent depth control to remove the damage layer caused by dry etching is preferred.

[0264] The interior of the separation tank 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18, which is an insulating film composed of an oxide film such as SiN or SiO2. The surface protective film 18 also serves as a non-reflective coating for the light-receiving part. The thickness of the surface protective film 18 is preferably in the range of 50 nm or more and 5000 nm or less. Alternatively, the surface protective film 18 can also be an organic film such as BCB.

[0265] <Function of the semiconductor light-receiving element according to embodiment 6>

[0266] When using an InAlAs digital alloy structure as a multiplication layer, the layers of the InAlAs digital alloy structure are subjected to high strain, making them prone to disorder if external stress is applied. Therefore, as with the semiconductor photoreceiving element 180 according to Embodiment 6, a separation trench 17 is provided along the outer periphery of the p-type InAlAs conductive layer 25 to mitigate stress affecting the entire wafer during the manufacturing process. Furthermore, even in the individual semiconductor photoreceiving elements 180, the presence of the separation trench 17 mitigates stress, thus reducing stress concentration at the central light-receiving portion of the semiconductor photoreceiving element 180. Additionally, since the InAlAs digital alloy multiplication layer 3 is exposed in the separation trench 17, it is preferable to cover the surface of the separation trench 17 with the aforementioned surface protective film 18. Since a high electric field is not applied to the separation trench 17, it will not become a starting point for degradation.

[0267] <Effects of Implementation Method 6>

[0268] According to the above, the semiconductor light-receiving element according to Embodiment 6 can alleviate the stress caused by heat treatment in the manufacturing process through the separation groove, thereby preventing the disordering of the digital alloy structure multiplication layer. Therefore, the ionization ratio k can be kept at approximately zero, and the semiconductor light-receiving element with high reliability, wide bandwidth and excellent low noise characteristics can be obtained.

[0269] Implementation Method 7

[0270] Figure 20 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element 190 according to Embodiment 7.

[0271] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 7>

[0272] As an example of the semiconductor light-receiving element 180 involved in Embodiment 6, a surface-incident APD is such as... Figure 19 As shown, light is received from the surface side; in contrast, as... Figure 20 As shown, a back-end incident APD, which is an example of the semiconductor light-receiving element 190 according to Embodiment 7, is characterized by having an opening 33 provided by removing a portion of the n-type electrode 31b on the back side, and having light incident on the n-type InP substrate 1 exposed in the opening 33. That is, an opening 33, which serves as the incident region for incident light 90, is provided on the back side of the n-type InP substrate 1 opposite to the p-type electrode 32.

[0273] For the back-illuminated APD, which is an example of the semiconductor light-receiving element 190 according to Embodiment 7, similar to the semiconductor light-receiving element 180 according to Embodiment 6, the stress caused by heat treatment in the manufacturing process can be alleviated by the separation groove, thus preventing the disordering of the InAlAs digital alloy structure multiplication layer 3, and therefore preventing, for example, Figure 6C The dead zone length shown is shortened, while maintaining... Figure 6B The state shown has a long dead zone length.

[0274] Furthermore, compared to surface-incident APDs, back-incident APDs like the semiconductor photodetector 190 can form a smaller area of ​​the p-type InAlAs conductive layer 25, thus further reducing stress caused by heat treatment during manufacturing processes, and further preventing disordering of the InAlAs digital alloy multiplication layer 3. As a result, even though heat treatment is performed during the formation of the device structure, disordering of the InAlAs digital alloy multiplication layer 3 can be prevented, thus maintaining the ionization ratio k at approximately zero and further reducing stress. Therefore, a semiconductor photodetector with high reliability, wide bandwidth, and excellent low-noise characteristics can be obtained.

[0275] Furthermore, in a back-illuminated APD like the semiconductor light-receiving element 190, compared to a surface-illuminated APD, the area of ​​the mesa-shaped p-type InAlAs conductive layer 25 can be reduced. Therefore, the stress from the mesa portion of the p-type InAlAs conductive layer 25 is less affected, and thus disordering of the InAlAs digital alloy multiplication layer 3 does not occur. Additionally, since stress is also mitigated during the operation of the semiconductor light-receiving element 190, disordering of the InAlAs digital alloy multiplication layer does not occur even after a long period. In other words, the semiconductor light-receiving element 190 according to Embodiment 7 can maintain a wide bandwidth and low noise for a long time.

[0276] <Effects of Implementation Method 7>

[0277] According to the semiconductor light-receiving element of Embodiment 7, since the area of ​​the p-type conductive layer can be formed to be small, the stress generated in the heat treatment process can be further reduced, thus further preventing the disordering of the InAlAs digital alloy structure multiplication layer 3. Therefore, the ionization ratio k can be kept at approximately zero, and the stress can be further reduced. Thus, a semiconductor light-receiving element with high reliability, wide bandwidth and excellent low noise characteristics can be obtained.

[0278] Implementation Method 8

[0279] Figure 21This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element 200 according to Embodiment 8.

[0280] <Component Structure of the Semiconductor Light-Receiving Element According to Embodiment 8>

[0281] The semiconductor light-receiving element 200 according to Embodiment 8 consists of an Fe-doped semi-insulating InP substrate 1a, and carrier concentrations of 1 to 5 × 10⁻⁶ are sequentially formed on the Fe-doped semi-insulating InP substrate 1a. 18 cm -3 Furthermore, the p-type InGaAlAs contact layer 40 has a thickness of 0.1–1 μm and a carrier concentration of 1–5 × 10⁻⁶. 18 cm -3 And a p-type InP conductive layer with a thickness of 0.1–1 μm, 41, p-type or low carrier concentration (5 × 10⁻⁶) 17 cm -3 The following are examples of n-type or i-type InAlGaAs / InAlAs graded layers: 42, i-type InGaAs light-absorbing layers with a thickness of 0.1–2.0 μm; and 43, layers with a thickness of 10–100 nm and a carrier concentration of 1–50 × 10⁻⁶. 17 cm -3 44. A p-type InP electric field mitigation layer; 45. An InAlAs digital alloy multiplication layer composed of alternating layers of i-type AlAs layers (for example, each layer is 2 atomic layers thick, approximately 0.6 nm) and i-type InAs layers (for example, each layer is 2 atomic layers thick, approximately 0.6 nm); 46. An n-type InAlAs electric field adjustment layer with a layer thickness of 10–50 nm; 47. An n-type InP window layer with a layer thickness of 0.1–2 μm; 48. A layer with a layer thickness of 0.1–2 μm and a carrier concentration of 5 × 10⁻⁶. 17 ~8×10 18 cm -3 The n-type InAlAs conductive layer 48 has a thickness of 0.1–2 μm and a carrier concentration of 5 × 10⁻⁶. 17 ~8×10 18 cm -3 The substrate 1a comprises an n-type InGaAs contact layer 49, an n-type electrode 50 formed on the n-type InGaAs contact layer 49, a p-type electrode 51 formed on the p-type InGaAlAs contact layer 40, and a metal film 53 formed on the back side of the Fe-doped semi-insulating InP substrate 1a. The p-type InP conductive layer 41 is also referred to as a p-type semiconductor layer.

[0282] <Method for manufacturing a semiconductor light-receiving element according to Embodiment 8>

[0283] The manufacturing method of the semiconductor light-receiving element 200 according to Embodiment 8 will be described below.

[0284] Using the MOVPE or MBE method, crystals with a carrier concentration of 1–5 × 10⁻⁶ are grown on Fe-doped semi-insulating InP substrates 1a with a layer thickness of 0.1–1 μm. 18 cm -3 The p-type InGaAlAs contact layer 40. Here, an n-type InP substrate can also be used instead of the Fe-doped semi-insulating InP substrate 1a. Alternatively, the p-type InGaAs contact layer 40 can also be p-type InP, p-type InGaAsP, or p-type InGaAs instead of p-type InGaAlAs.

[0285] On top of the p-type InGaAlAs contact layer 40, a crystal with a layer thickness of 0.1–1 μm and a carrier concentration of 1–5 × 10⁻⁶ is grown. 18 cm -3 The p-type InP conductive layer 41. Here, the p-type InP conductive layer 41 can also be a p-type InGaAsP or a p-type InAlGaAs to replace p-type InP.

[0286] Next, an i-type, n-type, or p-type InAlAs layer with a low barrier to holes can also be formed on top of the p-type InP conductive layer 41. Furthermore, in crystal growth, p-type or low carrier concentration (5 × 10⁻⁶) layers can be formed. 17 cm -3 After forming an n-type or i-type InAlGaAs / InAlAs graded layer 42 (as shown below), an i-type InGaAs light-absorbing layer 43 is grown with a crystal thickness of 0.1–2 μm. Alternatively, the i-type InGaAs light-absorbing layer 43 can also have a low carrier concentration (5 × 10⁻⁶). 17 cm -3 The n-type or p-type (hereinafter) is used instead of the i-type. Here, either or both of the p-type InP conductive layer 41 and the n-type InAlGaAs / InAlAs graded layer 42 are not required.

[0287] Next, crystals with a layer thickness of 10–100 nm and a carrier concentration of 1–50 × 10⁻⁶ are grown. 17 cm -3 The p-type InP electric field mitigation layer 44. Examples of p-type dopants for the p-type InP electric field mitigation layer 44 include Be, Zn, and C. The p-type InP electric field mitigation layer 44 does not necessarily have to be p-type InP; it can also be p-type InAlAs or a p-type InAlAs digital alloy structure.

[0288] If the dopant in the p-type InP electric field mitigation layer 44 diffuses into the adjacent InAlAs digital alloy structure multiplication layer 45, the InAlAs digital alloy structure will become disordered and transform into an InAlAs random alloy structure. In particular, since the InAlAs digital alloy structure multiplication layer 45 is thin, around 100 nm, the effect of disordering due to dopant diffusion is significant. Therefore, Be, which is difficult to diffuse, is most suitable as the p-type dopant for the p-type InP electric field mitigation layer 44. On the other hand, when it is a p-type InAlAs electric field mitigation layer, Zn is most suitable as the p-type dopant.

[0289] Alternatively, an InAlGaAs / InAlAs gradient layer with an intermediate bandgap value of 10-100 nm, such as InAlGaAs or InGaAsP, can be disposed between the i-type InGaAs light-absorbing layer 43 and the p-type InP electric field mitigation layer 44.

[0290] An InAlAs digital alloy multiplication layer 45 is crystal-grown on top of a p-type InP electric field mitigation layer 44 as a multiplication layer. The InAlAs digital alloy multiplication layer 45 is composed of semiconductor layers stacked alternately in the order of AlAs layers (2 atomic layers thick, approximately 0.6 nm) and InAs layers (2 atomic layers thick, approximately 0.6 nm), starting from the Fe-doped semi-insulating InP substrate 1a. Alternatively, the InAlAs digital alloy multiplication layer 45 can be formed in the order of InAs layers followed by AlAs layers.

[0291] The number of atomic layers in each layer of the InAlAs digital alloy multiplication layer 45 is preferably more than 2 atomic layers and less than 4 atomic layers, but 2 atomic layers is the most suitable. The reason is that the thinner the atomic layer of each layer, the greater the reduction effect of the ionization ratio k brought about by the digital alloy structure.

[0292] As for the conductivity type of the InAlAs digital alloy multiplication layer 45, type i is listed, and the carrier concentration is listed as 1×10⁻⁶. 17 cm -3 The following. However, it could also be a carrier concentration of 5 × 10⁻⁶. 18 cm -3 The following are p-type or n-type.

[0293] To increase the dead zone effect in the InAlAs digital alloy multiplication layer 45, the thickness of the InAlAs digital alloy multiplication layer 45 is preferably in the range of 40 nm or more and 170 nm or less. However, considering the typical thickness deviation of 20% when fabricating the semiconductor photoreceiving element 190, the thickness of the InAlAs digital alloy multiplication layer 45 is preferably in the range of 50 nm or more and 140 nm or less.

[0294] Next, after growing an n-type InAlAs electric field adjustment layer 46 with a crystal thickness of 10–50 nm, an n-type InP window layer 47 is further grown with a crystal thickness of 0.1–2 μm. Here, the n-type InP window layer 47 also functions as an electric field adjustment layer and an electron propagation layer, but it is not essential. The n-type InAlAs electric field adjustment layer 46 and the n-type InP window layer 47 serve as layers for adjusting the electric field of the outermost surface, and the carrier concentration is preferably 1–500 × 10⁻⁶. 16 cm -3 The range of [the data] is [limited / limited]. By reducing the electric field on the outermost surface, local breakdown is suppressed, thereby improving reliability.

[0295] Above the n-type InP window layer 47, an n-type InAlAs conductive layer 48 is grown as an n-type conductive layer, and an n-type InGaAs contact layer 49 is grown as an n-type contact layer. The thicknesses of the n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 are 0.1–2 μm, and the carrier concentration is 5 × 10⁻⁶. 17 cm -3 ~8×10 18 cm -3 .

[0296] After the crystal growth of the n-type InGaAs contact layer 49, the n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 are etched into a mesa shape to form a first mesa. Then, the outer side of the first mesa is etched to reach the p-type InGaAs contact layer 40, including the first mesa, to form a second mesa. Even if the second mesa does not reach the p-type InGaAs contact layer 40, it is acceptable as long as the i-type InGaAs light-absorbing layer 43 can be electrically separated. The spacing between the first and second mesa is preferably 1 μm or more. Alternatively, the first mesa may be formed after the second mesa.

[0297] The p-type electrode 51 is formed on the p-type InGaAs contact layer 40, and the n-type electrode 50 is formed on the n-type InGaAs contact layer 49. Furthermore, in the case of an n-type semiconductor, the ohmic resistance is an order of magnitude smaller than that of a p-type semiconductor; therefore, it is not necessary to use an n-type InGaAs contact layer 49 with a small band gap, and n-type InP, n-type InGaAlAs, or n-type InGaAsP can also be used. Alternatively, a direct contact can be formed with the n-type InAlAs conductive layer 48.

[0298] Through the above processes, the semiconductor light-receiving element 200 involved in Embodiment 8 is completed.

[0299] <Function and Effect of the Semiconductor Light-Receiving Element According to Embodiment 8>

[0300] The semiconductor light-receiving element 200 according to Embodiment 8 is characterized in that, in the semiconductor light-receiving element 180 according to Embodiment 7, the conductivity type is reversed from n-type to p-type and from p-type to n-type, and the conductivity type on the upper surface side is set to n-type.

[0301] The first function and effect of the semiconductor light-receiving element 200 according to Embodiment 8 will be described below.

[0302] If the InAlAs digital alloy multiplication layer 45 is maintained at high temperatures for a long time during epitaxial crystal growth, it may become disordered and form an InAlAs random alloy structure. In the semiconductor light-receiving element 200 according to Embodiment 8, compared with the semiconductor light-receiving element 190 according to Embodiment 7, the total thickness of each semiconductor layer above the InAlAs digital alloy multiplication layer 45 is thinner, about one-third. That is, in the semiconductor light-receiving element 200 according to Embodiment 8, compared with the semiconductor light-receiving element 190 according to Embodiment 7, the crystal growth time required for epitaxial crystal growth of the remaining semiconductor layers after crystal growth of the InAlAs digital alloy multiplication layer 45 is shorter, about one-third, so it is difficult for the InAlAs digital alloy multiplication layer 45 to become disordered. As a result, it is possible to more reliably achieve a state with a longer dead zone length and an ionization ratio k of zero.

[0303] The second function and effect of the semiconductor light-receiving element 200 according to Embodiment 8 will be explained below.

[0304] The upper electrode, i.e., the surface electrode, of the semiconductor light-receiving element is... Figure 20 The back-incident type APD shown has a p-type electrode 32, in Figure 21 The back-incident APD shown uses an n-type electrode 50. To achieve high speed, the electrode area of ​​the surface-side electrode needs to be further reduced to decrease capacitance. However, if the electrode area of ​​the top-side electrode is reduced, the contact resistance between the electrode and the semiconductor layer increases, thus increasing the RC time constant and causing a narrowing of the response bandwidth.

[0305] In the semiconductor light-receiving element 200 according to Embodiment 8, the upper electrode, i.e., the n-type electrode 50, is in contact with the n-type semiconductor, thus reducing the ohmic resistance to one-tenth compared to contact with the p-type semiconductor. Therefore, the area of ​​the n-type electrode 50 can be reduced, thereby reducing the stress from the electrode and making it difficult for disorder to occur in the InAlAs digital alloy multiplication layer 45. As a result, in the semiconductor light-receiving element 200 according to Embodiment 8, it is easier to achieve a state where the ionization ratio k is zero, thus achieving effects such as reducing the bandwidth correction circuit in the PON system, doubling the number of branches, omitting the SOA, and reducing the operating current of the transmitter's laser.

[0306] <Effects of Implementation Method 8>

[0307] According to the above, the semiconductor light-receiving element according to Embodiment 8, compared with the semiconductor light-receiving element according to Embodiment 7, has a shorter crystal growth time required for epitaxial crystal growth of each semiconductor layer after crystal growth of the InAlAs digital alloy multiplication layer, which is about one-third. Therefore, it is more difficult for disorder to occur in the InAlAs digital alloy multiplication layer, so the dead zone length is longer, and the state of zero ionization ratio k can be achieved more reliably. Furthermore, stress can be further reduced, thus achieving the effect of obtaining a semiconductor light-receiving element with high reliability, wide bandwidth and excellent low noise characteristics.

[0308] Implementation Method 9

[0309] Figure 22 This is a diagram showing the structure of the multi-value intensity modulation transceiver 300 according to Embodiment 9. Additionally, Figure 23A and Figure 23B This is a diagram showing the received waveform of the multi-value intensity modulation transceiver 300 according to Embodiment 9.

[0310] The multi-intensity modulation transceiver 300 is a multi-intensity modulation transceiver using PAM (Pulse Amplitude Modulation). In the transmitting section, the digital signal generated by the DSP 301 is converted from analog to analog in the DAC 302a, amplified in the driver amplifier 303, and used to drive the light source 304, which is composed of a DFB laser or EML, to emit an optical signal into the optical fiber cable 310.

[0311] On the other hand, in the receiving section, the optical signal is incident from the optical fiber cable 310 through the optical system onto the semiconductor light-receiving element of this disclosure, namely DA-APD305, where it is converted into current and multiplied. After being amplified in Linear-TIA306, it is converted into a digital signal in ADC302b and processed by DSP301.

[0312] <Function and Effects of the Multi-Value Intensity Modulation Transceiver Device According to Embodiment 9>

[0313] In the PAM-based multi-level intensity modulation transceiver 300, it is necessary not only to receive binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero), but also, for example, in PAM4 (Pulse Amplitude Modulation-4), to receive four values ​​of light signal intensity with different values. An example of a PAM4 received waveform is shown below. Figure 23A As shown. The quality of the received waveform in PAM4 is determined using an index such as TDECQ (Transmitter Dispersion and Eye Closure Quaternary). TDECQ is calculated using the following equation (15).

[0314] TDECQ (dB) = 10log (OMA / (6·Qt·R)) (15)

[0315] In equation (15), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt depends on the value of SER (Symbol Error Rate) specified by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to become the SER value. TDECQ (dB) is specified, for example, as below 3dB. To reduce TDECQ (dB), the following is required:

[0316] (1) The eye diagrams of all levels have equal openings.

[0317] (2) There is little noise at each level.

[0318] To ensure that the eye diagram openings of the four levels, each composed of different light signal intensities, are equal, the linearity of the semiconductor light-receiving element needs to be excellent. Here, good linearity of the semiconductor light-receiving element means that the photocurrent Iph increases proportionally to the optical input power Pin. That is, even if the optical input power Pin changes, as long as Iph / Pin remains constant, the linearity can be considered good.

[0319] Furthermore, in PAM (Power Amplifier), it's necessary to receive signals ranging from low to high intensity, thus requiring excellent dynamic range. That is, even if the optical input power (Pin) increases, as long as the decrease in Iph / Pin is small, the dynamic range can be considered good. For example... Figure 23B As with the received waveform, if the linearity and dynamic range deteriorate, the eye diagram opening between level 2 and level 3 will be degraded.

[0320] In the case of APD, the following can be cited as reasons for the deterioration of linearity: if the photocurrent increases with the increase of light input, the number of holes and electrons traveling in the multiplication layer and the light absorption layer increases, and the electric field distribution in the multiplication layer and the light absorption layer changes. This phenomenon is called the space charge effect.

[0321] The inventors studied a model of linearity degradation in APD. Figure 24A and Figure 24B This diagram illustrates the operation of the PD during highlight input. For example... Figure 24A As shown, if the light input increases, the photocurrent increases, and the space charge effect comes into play, seemingly causing a voltage drop due to the series resistance, thus reducing the voltage applied to the pn junction. This voltage drop leads to a decrease in the multiplication rate. This is because... Figure 24B The generated electrons and holes affect the electric field distribution. The series resistance Rli that degrades the linearity of the APD is expressed as in equation (16) below.

[0322] Rli=Rsc+Rd+Rlo (16)

[0323] In equation (16), Rsc is the resistance based on the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually tens of Ω, but Rsc is sometimes hundreds of Ω or more.

[0324] It was found that if the time for electrons and holes generated by light absorption to pass through the depletion layer is set as Td, then Rsc is represented by the following equation (17).

[0325] Rsc=W·Td / (2εS) (17)

[0326] In equation (17), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the area of ​​the pn junction.

[0327] Next, we will explain the actions of the APD during highlight input. Figure 25 This is a diagram illustrating the operation of the APD during high-light input. If a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, resulting in the so-called space charge effect. Due to this space charge effect, the multiplication rate of the APD decreases and its linearity deteriorates. As mentioned above, the deterioration of the linearity of the APD is due to the series resistance Rsc, therefore it is necessary to reduce the residence time Td of electrons and holes in the depletion layer. In particular, if the multiplication rate increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is represented by the following equation (18).

[0328] Residence time Tdm = doubling time = 2π·N·k·M·τav (18)

[0329] In equation (18), N is the Emmons coefficient (slightly dependent on the ionization ratio k), M is the multiplication rate, and τav is the travel time in the multiplication layer. The one-way transit time of the carrier across the multiplication layer is subtracted from the residence time Tdm. For ionization ratios k = 0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0–0.001 (InAlAs digital alloy construction), the multiplication rates N are 0.55, 0.83, 1.1, and 2.0, respectively.

[0330] Figure 26 The diagram shows the residence time (Tdm) of electrons and holes in each material constituting the multiplication layer. In the InAlAs digital alloy-constructed multiplication layer, the residence time (Tdm) is significantly reduced. That is, electrons and holes are rapidly expelled from the multiplication layer, thus suppressing the space charge effect within the multiplication layer. As a result, linearity and dynamic range are improved in the InAlAs digital alloy-constructed multiplication layer.

[0331] As a result, although in existing APDs such as Figure 23B The eye diagram openings of PAM4 would be uneven, but in the DA-APD disclosed herein, as... Figure 23A This makes the eye diagram openings more uniform, thus ensuring that TDECQ meets the specified values. Therefore, if the DA-APD of this disclosure is used, even PAM transceivers can use the APD, thereby increasing the transmission distance of optical signals or reducing the drive current of the transmitting laser.

[0332] <Effects of Implementation Method 9>

[0333] As described above, the multi-value intensity modulation transceiver according to Embodiment 9 uses the DA-APD of this disclosure as a semiconductor light receiving element, thus achieving the effect of increasing the transmission distance of optical signals and reducing power consumption.

[0334] Implementation Method 10

[0335] Figure 27 This is a schematic diagram illustrating the structure of the fiber optic wireless system 400 (Radio on fiber: RoF) according to Embodiment 10. Additionally, Figure 28 This is a schematic diagram showing the structure of a fiber optic wireless system 450 as a comparative example. The fiber optic wireless system 400 includes: a light source 401, a transmission path 402 such as a fiber optic cable, a DA-APD 403 of this disclosure, and an antenna 404.

[0336] In the fiber optic wireless system 400 according to Embodiment 10, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., transmission path 402. The transmitted optical amplitude signal is multiplied using the DA-APD 403 of this disclosure and converted into an electrical amplitude signal. The converted electrical amplitude signal is transmitted to an antenna 404 as a radio wave signal.

[0337] The fiber optic wireless system 400 according to Embodiment 10 can efficiently supply signals to an antenna 404 that is spaced apart from the electrical signal source. In addition, since no analog-to-digital or digital-to-analog conversion is performed during transmission, it has the characteristics of simple system structure and low power consumption.

[0338] <The function and effects of the fiber optic wireless system involved in Implementation Method 10>

[0339] exist Figure 28 In the comparative example of the fiber optic wireless system 450 shown, if the signal attenuates during transmission over a fiber optic cable, it cannot be multiplied in the PD406, thus resulting in a problem where sufficient radio wave signal cannot be emitted from the antenna.

[0340] Alternatively, if using an existing APD, then as follows Figure 24A and Figure 24B As shown, when the number of electrons and holes in the multiplication layer increases, the electric field distribution changes, causing the multiplication rate to saturate and making it impossible to ensure the dynamic range. Therefore, not only is it impossible to obtain sufficient electrical signal amplitude, but there are also problems such as analog signal distortion. Consequently, it is difficult to apply existing APDs to fiber optic wireless systems like the comparative example 450.

[0341] On the other hand, in the DA-APD403 of this disclosure used in the fiber optic wireless system 400 according to embodiment 10, such as Figure 26 As shown, due to the short residence time Tdm of electrons and holes in the multiplication layer, changes in the electric field distribution within the multiplication layer are suppressed. As a result, a response with excellent linearity can be obtained over a wide dynamic range. That is, by using the DA-APD403 of this disclosure to multiply the signal, the original signal can be reproduced, and a large current amplitude can be obtained.

[0342] The DA-APD403 disclosed herein can be used with a multiplication rate ranging from 1.2 to 10. However, if the multiplication rate increases, signal distortion occurs; therefore, it is preferable to use it with a multiplication rate ranging from 1.2 to 5. Furthermore, considering the fiber loss and the fact that the quantum efficiency of the APD is not 100% but approximately 80%, a multiplication rate of 2 to 3 is most suitable to compensate for these losses.

[0343] <Effects of Implementation Method 10>

[0344] According to the fiber optic wireless system of Embodiment 10, since the fiber optic wireless system is constructed using the DA-APD of this disclosure, it achieves the effect of outputting strong radio wave signals even when the optical transmission distance is extended.

[0345] Implementation Method 11

[0346] Figure 29 This is a schematic diagram showing the structure of the digital coherent receiving apparatus 500 according to Embodiment 11. The digital coherent receiving apparatus 500 according to Embodiment 11 is characterized by the use of the DA-APD505a of this disclosure.

[0347] In digital coherent communication, optical signals modulated with both phase and intensity are transmitted via polarization multiplexing in an optical fiber. In the digital coherent receiving device 500, firstly, the optical signal input from the optical fiber cable 501 is polarized by a polarization separator 502. After polarization separation, each polarized signal light is incident on 90-degree mixers 503a and 503b, respectively. Meanwhile, the laser light emitted from the semiconductor laser 504 as a local oscillator is separated into two signals that are 90 degrees out of phase.

[0348] The signal light is combined with the laser beam, and the signal light is further separated into orthogonal components (I, Q) and output. Four optical signals, namely four orthogonal I and Q components for each polarization, are incident on four balanced detectors 505. Each balanced detector 505 is formed by connecting two DA-APD505a disclosed herein in series and is configured within 90-degree mixers 503a and 503b. The electrical signals output from the balanced detectors 505 are input to the DSP 506. The digital coherent receiving apparatus 500 according to Embodiment 11 has the above structure.

[0349] <Function of the digital coherent receiving device according to Embodiment 11>

[0350] Figure 30A This is a diagram showing the waveforms of a digital coherent receiving device used as a comparative example. Figure 30B This is a diagram showing the waveform of the digital coherent receiving device according to Embodiment 11.

[0351] In existing balanced detectors, a photodiode (PD) is used as the semiconductor light-receiving element to receive the signal light. However, by using the DA-APD505a disclosed herein, the signal can be multiplied, thus reducing the local oscillator light. Furthermore, if a conventional APD is used, as... Figure 25 As shown, when the number of electrons and holes in the multiplication layer increases, the electric field distribution changes, leading to multiplication rate saturation and an inability to ensure dynamic range. Therefore, not only is it impossible to obtain sufficient electrical signal amplitude, but also problems such as analog signal distortion exist. The result is as follows: Figure 30A As shown, in the comparative example, the interval between waveforms A1 and B1 becomes narrower, and the intensity signal of the constellation waveform is distorted, making it difficult to apply APD.

[0352] On the other hand, in the DA-APD505a disclosed herein, due to... Figure 26 The short residence time (Tdm) of electrons and holes within the multiplication layer suppresses variations in the electric field distribution. The result is as follows: Figure 30B As shown, when using the DA-APD505a of this disclosure, the interval between waveform A and waveform B is widened, resulting in a constellation waveform with excellent linearity over a wide dynamic range. That is, even when the signal is multiplied by the APD, the original signal can be reproduced, and a large current amplitude can be obtained.

[0353] The DA-APD505a disclosed herein can also be used in the range of 1.2 to 10 times. However, if the multiplication rate is too high, the signal will be distorted, so it is preferable to use it in the range of 1.2 to 5 times.

[0354] <Effects of Implementation Method 11>

[0355] According to the above, the digital coherent receiving device according to Embodiment 11, since the DA-APD of this disclosure is used as the semiconductor light-receiving element for receiving optical signals, it achieves the effect of reducing the driving current of the local oscillator light (laser), that is, reducing the power consumption of the digital coherent receiving device.

[0356] Implementation Method 12

[0357] Figure 31 This is a schematic diagram showing the structure of the SPAD (Single Photon Avalanche Diode) sensor system according to Embodiment 12. The SPAD sensor system 600 includes: a photoelectronic measurement circuit 601, a SPAD sensor 602 composed of the DA-APD disclosed herein, and a quenching circuit 603.

[0358] The SPAD sensor system 600 uses the DA-APD disclosed herein. Photons incident on the SPAD sensor system 600 are absorbed in the light-absorbing layer of the SPAD sensor 602, which is composed of the DA-APD of this disclosure, generating electron-hole pairs. The electrons flow into the multiplication layer. An electric field approximately 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

[0359] This state is called Geiger mode. In Geiger mode, electrons reach 10... 6 The effect is multiplied by a factor of two. The generated electrons flow as an electric current and flow into the photoelectron measuring circuit 601. If the current generated by a single photon is known in advance, the number of photons incident on the SPAD sensor system 600 can be counted.

[0360] Figure 32A This is a graph showing the waveforms of the SAPD sensor system used as a comparative example. Figure 32B This is a diagram showing the waveforms of the SAPD sensor system according to Embodiment 12. If an electric field exceeding the avalanche breakdown electric field is continuously applied to the multiplication layer, excess current flows out. Therefore, after detecting a photon, the voltage applied to the SPAD sensor 602 is rapidly reduced, weakening the electric field of the multiplication layer. This operation is called quenching. That is, as... Figure 32A and Figure 32B As shown in the comparison of the multiplication characteristics of the SPAD sensor, the chain multiplication is stopped when the voltage is reduced from B: Geiger mode voltage to A: quench voltage. Then, the voltage is increased from A: quench voltage to B: Geiger mode voltage again, and the sensor becomes capable of receiving incident photons with high sensitivity.

[0361] The quenching circuit 603, which controls the voltage, includes both passive and active circuits. In the passive circuit, if a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in the resistor connected in series with the SPAD sensor 602, resulting in a decrease in the voltage applied to the SPAD sensor 602. In other words, the quenching circuit 603 operates by repeatedly applying voltages above and below the breakdown voltage to the SPAD sensor 602.

[0362] <Function and Effects of the SPAD Sensor System According to Embodiment 12>

[0363] The SPAD sensor system 600 described in Embodiment 12 can not only count photons but also be used as a highly sensitive semiconductor light-receiving element. However, it needs to continuously repeat between the B: Geiger mode voltage and the A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. By reducing the difference between the A: quenching voltage and the B: Geiger mode voltage, the repetition period can be shortened, or the response speed of the SPAD sensor system 600 can be improved.

[0364] In the passive quenching circuit 603, the resistance value connected in series with the SPAD sensor 602 can be reduced, resulting in a faster response speed for the SPAD sensor 602. Furthermore, in the active quenching circuit 603, the voltage amplitude is reduced, thus simplifying the drive circuit and saving power, while also widening the response bandwidth.

[0365] The following explains the effect of using the InAlAs digital alloy structure disclosed herein as a multiplication layer.

[0366] In the InAlAs digital alloy structure multiplication layer disclosed herein, due to... Figure 4A and Figure 6B The dead zone length is long, therefore multiplication does not occur in low electric fields. However, if the electric field is increased, the dead zone length becomes shorter, thus the multiplication rate increases sharply, leading to breakdown. In APDs with random InAlAs alloy multiplication layers and APDs with digital alloy InAlAs multiplication layers having a multiplication layer thickness, if a voltage with a dark current exceeding 10 μA is set as the breakdown voltage, the multiplication rate at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAlAs digital alloy construction multiplication layer of this disclosure, the multiplication rate at 90% of the breakdown voltage is less than 10 times.

[0367] Since the breakdown voltage depends on the component structure, such as the thickness of the light-absorbing layer and the carrier concentration of the electric field mitigation layer, the effect is verified here using the electric field of the multiplication layer, which can be quantified. Specifically, when the reach-through voltage (~12V) is above, the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.

[0368] Figure 33 This is a graph showing the difference between the quenching electric field and the Geiger mode electric field of each constituent material in the multiplication layer. It can be seen that in the InAlAs digital alloy multiplication layer of this disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is very low, at 170 kV / cm. This is significantly lower than that of an InAlAs digital alloy multiplication layer with the same superlattice structure as the InAlAs digital alloy multiplication layer of this disclosure but without thinning, having a layer thickness of over 200 nm. The electric field is 120 kV / cm lower.

[0369] <Effects of Implementation Method 12>

[0370] According to the SPAD sensor system of Embodiment 12, since the DA-APD of this disclosure is used in the SPAD sensor, the difference between the quenching electric field and the Geiger mode electric field, i.e. the applied voltage difference, can be reduced. Therefore, the SPAD sensor system can achieve the effects of improved response bandwidth, simplified quenching circuit, and power saving.

[0371] Implementation Method 13

[0372] Figure 34 This is a diagram showing the structure of the LiDAR (Light Detection and Ranging) device according to Embodiment 13. Figure 35A This is a diagram showing the received waveform of the APD of a lidar device used as a comparative example. Figure 35B This is a diagram showing the received waveform of the APD of the lidar device according to Embodiment 13.

[0373] The lidar device 700 includes: a light source 701, a DA-APD 702 and a TIA 703 disclosed herein, and a ranging circuit 704.

[0374] In the lidar device 700, the distance to the object 705 is calculated by measuring the time it takes for the pulsed light emitted from the light source to return to the semiconductor light-receiving element after illuminating the object 705. The light source 701 uses an LD (Light Detector) or similar device. To detect distant objects, the light intensity of the LD needs to be increased, but for eye safety, there is an upper limit to the amount of light emitted from the LD. Therefore, it is necessary to improve the sensitivity of the semiconductor light-receiving element. Therefore, in the lidar device 700 according to Embodiment 13, the DA-APD 702 of this disclosure is used as the semiconductor light-receiving element with high magnification.

[0375] The detected light pulse is multiplied and converted into a current pulse by the DA-APD702 of this disclosure. Subsequently, it is amplified by the TIA703 and input to the ranging circuit 704, as shown below. Figure 35A and Figure 35B As shown, the arrival time is determined when the intensity of the pulse signal exceeds a preset recognition line. The moment when the light pulse is emitted from the light source 701 is used as a signal input to the ranging circuit 704. The time difference between the two is multiplied by the speed of light and then divided by 2 to calculate the distance to the object 705.

[0376] <The function and effects of the lidar device according to embodiment 13>

[0377] The reflectivity of object 705 is not necessarily high, and the reflection direction is varied, therefore an APD is needed to detect minute light. In existing APDs, such as... Figure 35A As shown, if the voltage is set and activated in a high-multiplication mode, the multiplication time becomes longer, and the current pulse width output from the APD becomes wider. Furthermore, the tunneling current increases, making it difficult to identify the optical pulse.

[0378] On the other hand, in the multiplication layer of the DA-APD702 disclosed herein, even with high multiplication of 20x or more, as described in the explanation of the operation of Embodiment 1, the tunneling current does not increase, thus enabling easy detection of weak light. Furthermore, as... Figure 26 As shown, due to the short residence time in the multiplication layer, therefore... Figure 35B As shown, a current pulse with a high peak intensity can be obtained, resulting in high recognition sensitivity. Consequently, not only can distance measurement of distant objects be achieved, but the light output of the light source can also be reduced, thus saving power and improving eye safety.

[0379] <Effects of Implementation Method 13>

[0380] According to the above, the lidar device according to Embodiment 13 can achieve distance measurement of distant objects by using the DA-APD of this disclosure to receive reflected light from objects, and can save power of the light source, thereby achieving the effect of obtaining a lidar device that is also safe for the eyes.

[0381] This disclosure describes various exemplary implementation methods and embodiments, but the various features, methods, and functions described in one or more embodiments are not limited to the application of a specific implementation method and can be applied to the implementation method alone or in various combinations.

[0382] Therefore, numerous variations, not illustrated, can be conceived within the scope of this disclosure. These include variations, additions, or omissions of at least one constituent element, as well as extraction of at least one constituent element and combination with constituent elements of other embodiments.

[0383] Explanation of reference numerals in the attached figures

[0384] 1…n-type InP substrate; 1a…Fe-doped semi-insulating InP substrate; 2…n-type InAlAs buffer layer; 2a…n-type InP conductive layer; 3, 45…InAlAs digital alloy multiplication layer; 4, 44…p-type InP electric field mitigation layer; 5, 43…i-type InGaAs light absorption layer; 6…i-type InAlGaAs / InAlAs gradient layer; 7…p-type InP window layer; 8…p-type InGaAs contact layer; 11, 47…n-type InP window layer; 15…p-type diffusion region; 17…separation trench; 18…surface protective film; 20…Fe-doped semi-insulating InP buried layer; 25…p-type InAlAs conductive layer; 31, 31a… 31b, 50…n-type electrodes; 32, 51…p-type electrodes; 33…opening; 40…p-type InGaAlAs contact layer; 41…p-type InP conductive layer; 42…n-type InAlGaAs / InAlAs graded layer; 46…n-type InAlAs electric field adjustment layer; 48…n-type InAlAs conductive layer; 49…n-type InGaAs contact layer; 53…metal film; 90…incident light; 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200…semiconductor photoreceiving element; 250, 260, 270…optical line termination device; 251, 261, 274…FEC; 252… 262, 273, 303… Driver amplifiers; 253, 263, 272, 304, 401, 701… Light sources; 254, 264, 271… WDM; 255, 265a, 301, 506… DSP; 256, 266a, 302b… ADC; 258… APD; 257, 267, 276… Burst mode transimpedance amplifiers (TIA); 265, 278… CDR; 266, 277… Limiting amplifiers; 257a, 267a, 276a, 703… TIA; 268, 275, 305, 403, 505a, 702… DA-APD; 280, 282, 284… 50G-PON series System; 302a…DAC; 310, 501…fiber optic cable; 306…Linear-TIA; 400, 450…fiber optic wireless system; 402…transmission path; 404…antenna; 406…PD; 300…multi-value intensity modulation transceiver; 500…digital coherent receiver; 501…fiber optic cable; 502…polarization separator; 503a, 503b…90-degree mixer; 504…semiconductor laser; 505…balance detector; 600…SPAD sensor system; 601…optoelectronic measurement circuit; 602…SPAD sensor; 603…quenching circuit; 700…lidar device; 704…rangement circuit; 705…object.

Claims

1. A semiconductor light-receiving element, characterized in that, have: InP substrate; An n-type semiconductor layer is formed on the InP substrate; A multiplication layer is formed on the n-type semiconductor layer, with a thickness of 40 nm or more and 170 nm or less, and is constructed of digital alloy. A p-type electric field mitigation layer is formed on the multiplication layer; and An InGaAs light-absorbing layer is formed on the p-type electric field mitigation layer.

2. A semiconductor light-receiving element, characterized in that, have: InP substrate; A p-type semiconductor layer is formed on the InP substrate; An InGaAs light-absorbing layer is formed on the p-type semiconductor layer; A p-type electric field mitigation layer is formed on the InGaAs light-absorbing layer; as well as A multiplication layer is formed on the p-type electric field mitigation layer, with a thickness of 40 nm or more and 170 nm or less, and is composed of a digital alloy structure.

3. The semiconductor light-receiving element according to claim 1 or 2, characterized in that, The multiplication layer is composed of a digital alloy structure consisting of alternating layers of InAl and AlAs.

4. The semiconductor light-receiving element according to any one of claims 1 to 3, characterized in that, The thickness of the multiplication layer is greater than 60 nm and less than 130 nm.

5. The semiconductor light-receiving element according to any one of claims 1 to 4, characterized in that, The p-type electric field mitigation layer has a thickness of 10 nm or more and 70 nm or less and is composed of a random alloy structure.

6. The semiconductor light-receiving element according to claim 5, characterized in that, The p-type electric field mitigation layer is composed of InP or InAlAs.

7. The semiconductor light-receiving element according to any one of claims 1 to 4, characterized in that, The p-type electric field mitigation layer has a thickness of 10 nm or more and 130 nm or less and is constructed of digital alloy.

8. The semiconductor light-receiving element according to claim 7, characterized in that, The p-type electric field mitigation layer is composed of an InAlAs digital alloy structure formed by alternating layers of InAs and AlAs.

9. The semiconductor light-receiving element according to any one of claims 1 to 8, characterized in that, The p-type electric field mitigation layer is doped with beryllium or zinc as a p-type impurity.

10. The semiconductor light-receiving element according to claim 1, characterized in that, The n-type semiconductor layer is doped with silicon as an n-type impurity.

11. The semiconductor light-receiving element according to claim 1, characterized in that, An i-type or n-type window layer is formed on the InGaAs light-absorbing layer, a p-type impurity diffusion region is formed within the window layer, and a p-type electrode is disposed on the p-type impurity diffusion region.

12. The semiconductor light-receiving element according to claim 11, characterized in that, The n-type semiconductor layer is an n-type conductive layer, and an n-type electrode is provided at the part of the n-type conductive layer that is partially exposed on the InP substrate.

13. The semiconductor light-receiving element according to claim 12, characterized in that, A separation groove that reaches the n-type conductive layer is provided on the outer periphery of the p-type impurity diffusion region.

14. The semiconductor light-receiving element according to claim 11, characterized in that, A light incident region is provided on the back side of the InP substrate opposite to the p-type electrode.

15. The semiconductor light-receiving element according to claim 1, characterized in that, A p-type contact layer having an outer periphery with an area smaller than that of the multiplication layer is formed on the InGaAs light-absorbing layer, and a p-type electrode is disposed on the p-type contact layer.

16. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that, The dead zone length is greater than 50nm and less than 90nm.

17. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that, The ratio of the dead zone length to the thickness of the multiplication layer is more than 29% and less than 100%.

18. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that, The ionization ratio k is below 0.

1.

19. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that, The multiplication rate at 90% of the breakdown voltage is less than 10 times.

20. An optical line terminal device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 19; The optical combiner / demultiplexer directs the optical signal onto the semiconductor light-receiving element. An amplifier circuit amplifies the electrical signal output from the semiconductor photosensitive element; A clock data recovery circuit, connected to the amplification circuit, recovers the clock and data from the amplified electrical signal; as well as A forward error correction circuit, connected to the clock data recovery circuit, corrects errors in the clock and data.

21. An optical line terminal device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 19; The optical combiner / demultiplexer directs the optical signal onto the semiconductor light-receiving element. An amplifier circuit amplifies the electrical signal output from the semiconductor photosensitive element; An analog-to-digital converter circuit, connected to the amplifier circuit, converts the amplified electrical signal into a digital signal; A digital signal processing circuit, connected to the analog-to-digital conversion circuit, processes the digital signal; as well as A forward error correction circuit is connected to the digital signal processing circuit to correct errors in the digital signal.

22. A fiber optic wireless system, characterized in that, have: The light source emits analog-modulated light signals; The semiconductor light-receiving element according to any one of claims 1 to 19 receives the optical signal modulated by analog. The transmission path transmits the analog electrical signal output from the semiconductor light-receiving element to the antenna; as well as An antenna, connected to the transmission path, radiates the analog electrical signal as a radio wave signal.

23. A multi-value intensity modulation transceiver, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 19 receives a multi-value intensity modulated optical signal; An amplifier circuit amplifies the electrical signal output from the semiconductor light-receiving element; An analog-to-digital converter circuit, connected to the amplifier circuit, converts the amplified electrical signal into a digital signal; as well as A digital signal processing circuit, connected to the analog-to-digital conversion circuit, processes the digital signal.

24. A digital coherent receiving device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 19; A polarization separator separates the polarization of a polarization-multiplexed optical signal that has been modulated in terms of intensity and phase. A 90-degree mixer performs wavelength division and multiplexing on the optical signal output from the polarization separator; and A digital signal processing circuit, connected to the 90-degree mixer, processes digital signals.

25. A SPAD sensor system, characterized in that, have: The SPAD sensor is composed of a semiconductor light-receiving element as described in any one of claims 1 to 19; The quenching circuit repeatedly applies voltages above and below the breakdown voltage to the SPAD sensor; as well as The optoelectronic measurement circuit measures the electrical signal output from the SPAD sensor.

26. A lidar device, characterized in that, have: The light source emits light in a pulsed pattern; The semiconductor light-receiving element according to any one of claims 1 to 19 receives light emitted from the light source that is reflected back by an object; An amplifier circuit amplifies the electrical signal output from the semiconductor light-receiving element; as well as The ranging circuit calculates the distance based on the electrical signal amplified by the amplifier circuit.

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